Network clock synchronization method and device, electronic equipment and storage medium

Abstract

The invention discloses a network clock synchronization method and device, electronic equipment and a storage medium. The method is applied to a target node deployed in a network area, and comprises the steps that network state data corresponding to the target node and a clock synchronization path where the target node is located are acquired, the clock synchronization path is any one of links where the target node is located in a network topology corresponding to the network area, and a plurality of nodes are deployed on the clock synchronization path; the clock synchronization frequency of the target node is adjusted according to the network state data and the clock precision level corresponding to the target node, the target clock synchronization frequency is obtained, and the clock precision level is used for representing the clock synchronization priority corresponding to the target node; acquiring clock errors corresponding to other nodes on the clock synchronization path; and under the target clock synchronization frequency, adjusting the clock precision of the target node based on the clock error to obtain the target clock precision. According to the scheme provided by the embodiment of the invention, the precision of clock synchronization can be improved.

Description

Technical Field

[0001] The present application belongs to the field of communication network technology, and in particular relates to a method, device, electronic device and storage medium for synchronizing a network clock. Background Art

[0002] In the field of communication technology, in order to correctly parse and restore data sent by the sender, the network clock in the communication network needs to be synchronized.

[0003] In related technologies, network clock synchronization typically relies on qualitative parameters (e.g., clock type) to manage clock accuracy. This lacks real-time feedback of quantitative error data, making cumulative error difficult to control and reducing clock synchronization accuracy. Furthermore, related technologies typically employ static configuration to achieve network clock synchronization, which is unable to adapt to dynamic network changes and reduces the stability and accuracy of network clock synchronization. Summary of the Invention

[0004] Embodiments of the present application provide a network clock synchronization method, device, electronic device, and storage medium, which can improve the accuracy of clock synchronization.

[0005] In the first aspect, an embodiment of the present application provides a method for synchronizing a network clock, the method comprising: obtaining network status data corresponding to a target node deployed in a network area, and a clock synchronization path where the target node is located, wherein the clock synchronization path is any one of the links where the target node is located in the network topology corresponding to the network area, and multiple nodes are deployed on the clock synchronization path; adjusting the clock synchronization frequency corresponding to the target node according to the network status data and the clock accuracy level corresponding to the target node to obtain a target clock synchronization frequency, wherein the clock accuracy level is used to characterize the clock synchronization priority corresponding to the target node; obtaining clock errors corresponding to other nodes on the clock synchronization path; and adjusting the clock accuracy of the target node based on the clock error at the target clock synchronization frequency to obtain the target clock accuracy.

[0006] In the second aspect, an embodiment of the present application provides a network clock synchronization device, which includes: a data acquisition module for acquiring network status data corresponding to a target node deployed in a network area, and a clock synchronization path where the target node is located, wherein the clock synchronization path is any one of the links where the target node is located in the network topology corresponding to the network area, and multiple nodes are deployed on the clock synchronization path; a frequency adjustment module for adjusting the clock synchronization frequency corresponding to the target node according to the network status data and the clock accuracy level corresponding to the target node to obtain the target clock synchronization frequency, wherein the clock accuracy level is used to characterize the clock synchronization priority corresponding to the target node; an error acquisition module for acquiring the clock error corresponding to other nodes on the clock synchronization path; an accuracy adjustment module for adjusting the clock accuracy of the target node based on the clock error at the target clock synchronization frequency to obtain the target clock accuracy.

[0007] In a third aspect, an embodiment of the present application provides an electronic device comprising: a processor and a memory storing computer program instructions; when the processor executes the computer program instructions, the network clock synchronization method as described in the first aspect is implemented.

[0008] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having computer program instructions stored thereon. When the computer program instructions are executed by a processor, the method for synchronizing a network clock as described in the first aspect is implemented.

[0009] In a fifth aspect, an embodiment of the present application provides a computer program product. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the network clock synchronization method as described in the first aspect.

[0010] As can be seen from the above, in the embodiment of the present application, the clock synchronization frequency is determined according to the network status data and the clock accuracy level, which can improve the accuracy of clock synchronization, solve the problem in the related art that it is impossible to flexibly adjust according to the actual network status, resulting in the inability to adaptively synchronize resources when the network load changes, thereby affecting the synchronization stability of the clock and reducing the accuracy of clock synchronization, and effectively alleviate it. In addition, in the embodiment of the present application, the clock accuracy level is also taken into account to allow network nodes to work at different clock accuracy levels and adapt to different application requirements, thereby improving the clock accuracy under different application requirements. In addition, in order to improve the synchronization accuracy of the clock accuracy, in the embodiment of the present application, the influence of other nodes on the clock synchronization path on the clock error of the target node is also taken into account. By adjusting the clock accuracy of the target node through other clock errors, the influence of the cumulative error between network clocks on clock synchronization can be reduced, further improving the accuracy of clock synchronization.

[0011] It can be seen that the solution provided in the embodiment of the present application can improve the accuracy of clock synchronization. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0013] Figure 1 is a schematic diagram of a clock synchronization system provided by an embodiment of the present application;

[0014] Figure 2 This is a flowchart of a method for synchronizing a network clock provided by an embodiment of the present application;

[0015] Figure 3 This is an overall flow chart of a network clock synchronization method provided by one embodiment of the present application;

[0016] Figure 4 This is a structural diagram of a network clock synchronization device provided by another embodiment of the present application;

[0017] Figure 5 This is a structural diagram of an electronic device provided in yet another embodiment of the present application. DETAILED DESCRIPTION

[0018] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0019] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0020] For ease of understanding, before explaining the solution provided in this application, the background of the solution provided in this application is first explained.

[0021] A 1588v2 clock is a high-precision clock that uses the IEEE 1588v2 protocol. This protocol manages clock accuracy between devices on a network by defining clock synchronization parameters. Clock accuracy characterizes the accuracy and stability of the time signal provided by the clock source, typically expressed in terms of errors per million clock cycles. The clock source provides a frequency-stable, level-matched square wave clock signal to the pulse generator.

[0022] In related technologies, clock accuracy is usually managed in the following four aspects:

[0023] (1) In terms of synchronization information transmission mechanism, the IEEE 1588v2 protocol relies on parameters such as "clock category" and "clock accuracy" to mainly provide qualitative synchronization status. The clock source device transmits its clock category to each downstream clock device through a synchronization information transmission protocol (for example, Synchronization Status Message (SSM) or Ethernet Synchronization Channel (ESMC). The clock device then adjusts its own synchronization status based on the accuracy of the upstream clock source.

[0024] (2) In terms of clock offset and time error accumulation, in IEEE 1588v2 networks, each node will inevitably generate time errors when synchronizing its clock. As the clock signal is transmitted in the network, these errors will gradually accumulate. In traditional solutions, high-precision devices (for example, G.8273.2 Class C or Class D devices) are usually configured at certain key nodes to reduce transmission errors between nodes. Although high-precision devices can alleviate the problem of cumulative errors to a certain extent, the overall network still has difficulty coping with clock errors caused by complex topologies or traffic fluctuations.

[0025] (3) In terms of fixed node configuration and dynamic feedback, existing IEEE 1588v2 systems generally cannot provide real-time node accuracy feedback. Node accuracy settings are mostly pre-set static parameters that cannot be flexibly adjusted based on actual network conditions. This approach may not be able to adaptively allocate synchronization resources when the network load changes, thereby affecting the clock synchronization stability of some nodes.

[0026] (4) In terms of scalability, although some clock devices can communicate their accuracy levels through synchronization information, existing protocols lack detailed control over the clock accuracy requirements between different clock devices, making it difficult to cope with the complex accuracy requirements under multi-level link transmission. In particular, in high-precision 5G base station synchronization applications, traditional methods cannot meet the strict clock synchronization requirements of specific services.

[0027] Therefore, the IEEE 1588v2 network clock synchronization solution has the following defects:

[0028] (1) Clock accuracy feedback has limitations. Existing solutions primarily evaluate clock source accuracy through qualitative parameters such as “clock type” and “clock accuracy,” but these parameters cannot provide detailed, real-time quantitative accuracy feedback. This qualitative information makes it difficult for downstream clock devices to accurately understand the true accuracy of the received clock, thereby reducing the accuracy of clock synchronization.

[0029] (2) Large cumulative errors. In a communication network, different nodes introduce a certain amount of time error when transmitting clock signals. As the clock signal is transmitted through multiple nodes, the error gradually accumulates. Even with high-precision clock devices (for example, Class C or Class D devices), this cumulative error cannot be completely eliminated. Especially in a multi-hop network environment or under high load conditions, the accumulated error will significantly affect the clock synchronization effect.

[0030] (3) Lack of dynamic control mechanisms. In related technologies, clock synchronization solutions rely on static configurations and cannot be dynamically adjusted according to changes in network conditions. When fluctuations occur in the network (for example, traffic peaks or node changes), the system has difficulty flexibly adjusting clock accuracy, resulting in some nodes being affected in terms of synchronization stability.

[0031] (4) Difficulty meeting high-precision application requirements. Current solutions have limitations in scenarios requiring high precision, especially in 5G, financial transactions, or precision industrial applications, where precision is required to reach the nanosecond level. Existing protocols lack a detailed multi-level precision control mechanism, making it difficult to support these scenarios with strict requirements for clock synchronization.

[0032] To address the problems of the prior art, the embodiments of the present application provide a network clock synchronization method, apparatus, electronic device, and storage medium. In the solution provided in the embodiments of the present application, clock synchronization of an enhanced IEEE 1588v2 network is achieved through dynamic regulation to meet the stringent requirements of high-precision network applications for clock synchronization and address the shortcomings of existing solutions in terms of dynamic adaptability and precision control.

[0033] In one embodiment, the clock synchronization system can be used as the execution subject of the method provided in the embodiment of the present application. Figure 1 As can be seen from the clock synchronization system shown, the clock synchronization system may include a control module 10 , a precision feedback module 20 , a precision control module 30 and a distributed collaboration module 40 .

[0034] For the control module 10, in order to improve the adaptability of the clock synchronization system in a complex network environment, the control module 10 uses artificial intelligence algorithms to monitor and analyze the network status (for example, traffic fluctuations, node changes and load conditions) in real time, predict clock errors, and automatically adjust the clock synchronization frequency of each node based on the current network conditions.

[0035] The accuracy feedback module 20, based on the traditional IEEE 1588v2 protocol, adds a new TLV extension field to convert clock device accuracy information from a simple "clock category" into a specific, quantifiable accuracy value. Each node transmits its clock error in real time and feeds it back to downstream devices in quantified form, enabling accurate clock error information and real-time feedback of quantitative accuracy. This design ensures a refined accuracy feedback mechanism, transitioning from qualitative to quantitative, providing stronger assurance of synchronization accuracy for downstream devices.

[0036] To meet the clock accuracy requirements of different application scenarios, the precision control module 30, in this embodiment of the present application, adds a multi-level precision control protocol to the IEEE 1588v2 protocol to achieve precision grading. By extending the TLV field, each node can operate synchronously at multiple precision levels. Upstream devices can adaptively adjust clock accuracy based on the requirements of downstream devices or applications, achieving adaptive cascaded adjustment of clock accuracy to address different business scenarios.

[0037] The distributed coordination module 40 enables distributed coordination of clock accuracy, enabling each node in the network to communicate with each other and coordinately adjust clock accuracy. This enables bidirectional transmission of clock accuracy and calibration of clock errors, improving the accuracy of clock synchronization. Unlike traditional one-way accuracy transmission, this mechanism implements bidirectional accuracy information exchange, allowing each node to mutually calibrate and optimize accuracy during synchronization, thereby reducing overall system error accumulation.

[0038] The following describes the network clock synchronization method provided by the embodiments of this application. The clock synchronization system may also include a target node, which is the network node where the clock device in the network is located. In some scenarios, the target node may also serve as the execution subject of the method provided by the embodiments of this application. In the embodiments of this application, the entire clock synchronization system is used as the execution subject for the description.

[0039] Figure 2 FIG1 shows a flow chart of a method for synchronizing a network clock according to an embodiment of the present application. Figure 2 As shown, the method includes the following steps S201 to S204:

[0040] Step S201: Acquire network status data corresponding to a target node deployed in a network area and a clock synchronization path where the target node is located.

[0041] In step S201, the target node can be any clock node deployed in the network area, including the node where the clock source device is located or the node where a downstream device of the clock source device is located. The network status data can be the status data of the network area where the target node is located, which can reflect the clock synchronization accuracy between nodes.

[0042] In one example, a clock synchronization system is equipped with sensors and a network monitoring module to collect network status data. This network status data includes transmission delays between nodes, network load, node synchronization errors, and the operating status of each clock device in the system. Specifically, the clock synchronization system uses high-precision sensors and a network monitoring module to collect real-time delay information and network load information from each node in the network. The clock synchronization system continuously monitors the synchronization errors between nodes and calculates the cumulative error. This cumulative error provides a basis for subsequent dynamic control of clock synchronization accuracy and frequency, as well as error calibration. Furthermore, after the sensors and / or network monitoring module collect network status data, the clock synchronization system processes the collected network status data in real time and stores it in the clock synchronization system's central data management module. This processed data can be used to generate a network accuracy requirement analysis, ensuring that the clock synchronization system can adjust clock synchronization accuracy based on the current network status. Furthermore, the clock synchronization system can analyze the network status data to determine the current network accuracy requirements, specifically identifying nodes with high-precision requirements as key points for subsequent control and optimization.

[0043] In step S201, the clock synchronization path is any link in the network topology corresponding to the network area where the target node is located. Multiple nodes are deployed on the clock synchronization path. For example, target node B1 is located on links L1 and L2 in the network topology. The synchronization path corresponding to link L1 is nodes A1-B1-C1-D1. In link L1, clock synchronization is performed in the order of A1-B1-C1-D1. The synchronization path corresponding to link L2 is nodes A2-B1-C2-D1-E1. In link L2, clock synchronization is performed in the order of A2-B1-C2-D1-E1.

[0044] As an example, the clock synchronization system can obtain the network topology corresponding to the network area. During the clock synchronization process, the clock synchronization system can obtain the position of the target node in the network area, and then determine the link where the target node is located based on the position, and determine the clock synchronization path from at least one link based on actual needs.

[0045] Step S202 : adjusting the clock synchronization frequency corresponding to the target node according to the network status data and the clock accuracy level corresponding to the target node to obtain the target clock synchronization frequency.

[0046] In step S202, the clock accuracy level is used to indicate the clock synchronization priority of the target node, in order to meet the clock synchronization accuracy requirements of different application scenarios. For example, in scenarios such as high-frequency financial trading, where clock accuracy is required to be high, a higher clock accuracy level can be set; whereas in scenarios such as monitoring, where clock accuracy is required to be low, a lower clock accuracy level can be set.

[0047] In addition, the corresponding clock synchronization frequencies vary at different clock accuracy levels. For example, in scenarios with higher clock accuracy requirements, setting a more frequent clock synchronization frequency can improve clock synchronization accuracy.

[0048] Step S203: Obtain clock errors corresponding to other nodes on the clock synchronization path.

[0049] In step S203, the other nodes on the clock synchronization path include the upstream node of the target node and the downstream node corresponding to the target node. That is, in the embodiment of the present application, during the clock synchronization process of the target node, not only the impact of the clock error of the upstream node on the clock synchronization accuracy of the target node is taken into account, but also the impact of the clock error of the target node on the clock synchronization accuracy of the downstream node is taken into account. Therefore, the clock accuracy of the target node can be adjusted according to the clock synchronization error corresponding to the entire link, so that each node can calibrate with each other during the synchronization process to improve the overall synchronization accuracy.

[0050] Step S204 : At the target clock synchronization frequency, the clock accuracy of the target node is adjusted based on the clock error to obtain the target clock accuracy.

[0051] In step S204, since the target clock synchronization frequency is determined by the target node's network status data and clock accuracy level, synchronizing the target node's clock at this target clock synchronization frequency can meet the target node's actual needs and improve clock synchronization stability. Furthermore, adjusting the target node's clock accuracy based on the clock errors of upstream and downstream nodes not only improves the target node's clock synchronization accuracy but also enables synchronized updates of the clocks of multiple nodes.

[0052] Based on the scheme defined by the above steps S201 to S204, it can be known that in the embodiment of the present application, the clock synchronization frequency is determined according to the network status data and the clock accuracy level, which can improve the accuracy of clock accuracy synchronization, solve the problem in the related art that it is impossible to flexibly adjust according to the actual network status, resulting in the inability to adaptively synchronize resources when the network load changes, thereby affecting the synchronization stability of the clock and reducing the accuracy of clock synchronization, and effectively alleviate it. In addition, in the embodiment of the present application, the clock accuracy level is also taken into account to allow network nodes to operate at different clock accuracy levels and adapt to different application requirements, thereby improving the clock accuracy under different application requirements. In addition, in order to improve the synchronization accuracy of the clock accuracy, in the embodiment of the present application, the influence of other nodes on the clock synchronization path on the clock error of the target node is also taken into account. By adjusting the clock accuracy of the target node through other clock errors, the influence of the cumulative error between network clocks on clock synchronization can be reduced, further improving the accuracy of clock synchronization.

[0053] It can be seen that the solution provided in the embodiment of the present application can improve the accuracy of clock synchronization.

[0054] The following introduces the implementation process of the method provided in the embodiment of the present application.

[0055] Before synchronizing the network clock of a target node, you need to obtain the clock synchronization path of the target node.

[0056] In some embodiments, the clock synchronization system may determine the link where the target node is located from the links corresponding to the network topology, and obtain at least one candidate clock synchronization path corresponding to the target node. The system then obtains the clock cumulative error and clock cumulative delay corresponding to the at least one candidate clock synchronization path, and determines the clock synchronization path corresponding to the target node from the at least one candidate clock synchronization path based on the clock cumulative error and clock cumulative delay. For example, the candidate clock synchronization path with the smallest clock cumulative error and the shortest clock cumulative delay may be determined as the clock synchronization path for the target node.

[0057] In the above embodiment, the clock cumulative error is the sum of the clock errors of all nodes in the candidate clock synchronization path, and the clock cumulative delay is the sum of the clock delays of all nodes in the candidate clock synchronization path.

[0058] It should be noted that in the embodiment of the present application, the clock synchronization system automatically detects all possible synchronization paths in the network, selects the best path based on the delay stability and error accumulation of each path, and improves the efficiency and accuracy of clock synchronization.

[0059] In addition, in order to solve the problem of abnormality in a single synchronization path causing the clock to be unable to synchronize, in an embodiment of the present application, a redundant mechanism of multi-path synchronization is adopted to ensure that calibration can be achieved through an alternative path when delay fluctuations or failures occur in the main synchronization path.

[0060] Specifically, when the clock synchronization path corresponding to the target node is in an abnormal state, the clock synchronization system determines a backup clock path from at least one candidate clock synchronization path based on the clock cumulative error and the clock cumulative delay; the clock accuracy of the target node is adjusted by the clock error of the node in the backup clock path to obtain the target clock accuracy.

[0061] In the above embodiment, the backup clock path is a path among the at least one candidate clock synchronization path other than the clock synchronization path corresponding to the target node. For example, the backup clock path may be a candidate clock synchronization path among the at least one candidate clock synchronization path that has the smallest cumulative clock error and the smallest cumulative clock delay.

[0062] In this embodiment of the present application, the clock synchronization system uses synchronization signals from both the primary and backup paths for calibration at certain critical nodes, further improving synchronization stability. If a problem occurs on one path, the synchronization signal from the other path can serve as compensation, allowing the node to maintain high accuracy during the failure. In other words, in this embodiment of the present application, the primary synchronization path is prioritized for critical services, while the redundant path is activated when the primary path fluctuates. This approach improves clock synchronization stability.

[0063] After obtaining the network status data of the target node and the clock synchronization path corresponding to the target node, the clock synchronization system needs to determine its corresponding clock synchronization frequency.

[0064] Specifically, the clock synchronization system adjusts the clock synchronization frequency according to the network status data to obtain an initial clock synchronization frequency; then, the initial clock synchronization frequency is adjusted according to the clock accuracy level corresponding to the target node to obtain a target clock synchronization frequency.

[0065] For the initial clock synchronization frequency, the clock synchronization system can predict the network delay corresponding to the target node based on the network status data; when the network delay is greater than the preset delay threshold, the clock synchronization frequency of the target node is increased to obtain the initial clock synchronization frequency.

[0066] It should be noted that in the above embodiment, the network delay corresponding to the target node is predicted by the control module in the clock synchronization system. The above control module can also be deployed in the target node, so that the target node predicts the network delay through the control module, and then determines the initial clock synchronization frequency based on the network delay.

[0067] In an embodiment of the present application, the control module can be driven by AI (Artificial Intelligence) to analyze network status and dynamically adjust clock synchronization frequency and control accuracy based on real-time environmental changes. Because the AI algorithm used in the control module can operate in complex and changing network environments, the control module can determine the initial clock synchronization frequency, thereby achieving real-time optimization of the synchronization strategy and ensuring the accuracy and stability of clock synchronization.

[0068] In one example, the control module can be a time series prediction model based on deep learning, for example, LSTM (Long-Short Term Memory) or GRU (Gated Recurrent Unit), which is suitable for processing time series data and predicting future trends. Since the LSTM model can reduce the gradient vanishing problem when processing time series data, in an embodiment of the present application, an LSTM model is used to train by long-term dependencies on historical data. Before training the LSTM model, the collected network status data (including delay, error accumulation, node load, etc.) is used as the input data source of the LSTM model. Before inputting the LSTM model, it needs to be preprocessed, for example, cleaning, denoising, standardization, etc., to ensure the accuracy and consistency of the training data of the LSTM model, so as to facilitate subsequent model training and prediction. After completing the preprocessing of the model, key indicators such as delay, jitter, error accumulation, etc. can be marked from the historical data, and these labels are used to train the LSTM model so that it can predict future network delay fluctuations and error trends based on the current network status data.

[0069] After the LSTM model is trained, it can be used to predict changes in network latency in real time. The clock synchronization system then generates an adaptive synchronization strategy based on the predicted data (e.g., network latency) output by the LSTM model. For example, if the clock synchronization system predicts that network latency or error may increase in the short term, it will increase the clock synchronization frequency of the target node to reduce the cumulative error caused by jitter. For another example, for nodes under high load, the clock synchronization system can lower the synchronization frequency of non-critical nodes and adjust the clock synchronization frequency up or down based on the clock accuracy level.

[0070] It should be noted that in the embodiments of this application, the output of the LSTM model is not fixed but is continuously adaptively adjusted through a feedback mechanism. For example, the clock synchronization system evaluates the synchronization accuracy after each adjustment and feeds the adjusted results back into the LSTM model as new input, forming a closed-loop control loop. This allows the clock synchronization system to adjust the LSTM model's weights or update strategy based on real-time accuracy feedback data, improving the LSTM model's responsiveness to network fluctuations.

[0071] During dynamic control, the LSTM model also possesses anomaly detection capabilities. By setting specific thresholds, the LSTM model can identify extreme errors or sudden network anomalies. Once an anomaly is detected, the clock synchronization system triggers an automatic recovery mechanism. For example, by prioritizing the target node's clock synchronization frequency, the system can quickly restore accuracy requirements.

[0072] Furthermore, after adjusting the clock synchronization frequency of the target node through the LSTM model to obtain the initial clock synchronization frequency, the clock synchronization system adjusts the initial clock synchronization frequency again according to the clock accuracy level.

[0073] Specifically, the clock synchronization system determines the clock adjustment requirements corresponding to the target node based on the correlation between the clock accuracy level and the accuracy requirement; then, the initial clock synchronization frequency is adjusted according to the clock adjustment requirement to obtain the target clock synchronization frequency corresponding to the target node.

[0074] In the embodiments of this application, a multi-level precision control protocol is used to address the varying requirements for clock synchronization accuracy in different application scenarios. This means that through hierarchical control of synchronization accuracy, synchronization accuracy can be flexibly configured in different scenarios to meet the needs of high-priority nodes while also rationally allocating system resources to ensure synchronization efficiency.

[0075] In the embodiments of the present application, synchronization accuracy can be divided into multiple levels according to the accuracy requirements of different nodes in the network, for example, advanced accuracy level, intermediate accuracy level, and basic accuracy level. Among them, the advanced accuracy level is used for nodes with extremely high accuracy requirements such as 5G base stations and financial high-frequency transactions (error tolerance is within 1 nanosecond); the intermediate accuracy level is suitable for nodes such as industrial automation and edge computing that require higher accuracy but slightly higher error tolerance (error tolerance is between 1-10 nanoseconds); the basic accuracy level is used for nodes with lower accuracy requirements, such as monitoring and low-speed equipment (error tolerance is above 10 nanoseconds).

[0076] By grading the accuracy requirements of each node, the clock synchronization system can reasonably configure the accuracy level according to the actual business needs of each node and optimize resource utilization.

[0077] In an embodiment of the present application, the clock synchronization system can dynamically adjust the synchronization frequency and accuracy according to the real-time status of the network and the node accuracy requirements.

[0078] Specifically, when the network load quantity in the network area is higher than the load quantity threshold, and / or there is a fault in the network equipment in the network area, the clock accuracy level of the target node is compared with the preset level threshold to obtain a comparison result; wherein, when the clock accuracy level of the target node is greater than or equal to the preset level threshold, the initial clock synchronization frequency is increased to obtain the target clock synchronization frequency; when the clock accuracy level of the target node is less than the preset level threshold, the initial clock synchronization frequency is reduced to obtain the target clock synchronization frequency.

[0079] In one example, the clock synchronization system can monitor the accuracy feedback information of each node in the network in real time. If a node reports insufficient accuracy, for example, due to upstream error accumulation or network delay fluctuations, the clock synchronization system will dynamically increase the synchronization frequency of the node.

[0080] In another example, for different accuracy levels, the clock synchronization system allocates more synchronization resources to high-priority nodes. High-precision nodes will receive more frequent synchronization updates, while low-priority nodes receive lower-frequency synchronization signals to balance the system load.

[0081] It should be noted that to ensure that the system can maintain basic synchronization in the event of failure or resource constraints, a degradation mechanism is also introduced in the embodiments of this application. That is, when the network load is too high or a device failure occurs, the clock synchronization system automatically reduces the synchronization accuracy of non-critical nodes to free up resources for high-priority nodes, thereby maintaining overall synchronization stability. When large errors accumulate in high-precision nodes, the clock synchronization system will trigger a cascade adjustment mechanism, transmitting synchronization update instructions to downstream nodes from top to bottom based on node priority. After the key nodes obtain synchronization compensation, the accuracy is synchronized to all relevant nodes to ensure the consistency of the entire system.

[0082] In one example, when a higher-level node detects that the accumulated error exceeds a set threshold, it automatically triggers a cascade adjustment mechanism. Through this cascade adjustment mechanism, the clock synchronization system sends precision update instructions to downstream nodes, ensuring that synchronization accuracy is transmitted and maintained throughout the entire link.

[0083] It should be noted that in this embodiment of the present application, the clock synchronization system can also automatically configure the accuracy level based on the network topology and node requirements. During initialization or topology changes, the clock synchronization system automatically detects the node types and requirements in the network and assigns an initial accuracy level based on pre-set rules. For example, critical business nodes will be automatically assigned a high accuracy level during initial configuration, reducing manual intervention and improving the clock synchronization efficiency of the clock synchronization system.

[0084] After obtaining the target clock synchronization frequency, the clock synchronization system needs to obtain the clock errors corresponding to other nodes on the clock synchronization path. In an embodiment of the present application, the clock synchronization system obtains the clock errors from the target field in the data message sent by each of the other nodes.

[0085] In the above embodiment, the target node communicates with other nodes via a clock synchronization protocol. The protocol includes a target field, which stores the node's clock error. This target field transforms qualitative accuracy information into precise quantitative feedback, ensuring that downstream devices receive specific clock synchronization accuracy values.

[0086] In one example, the TLV field is extended based on the IEEE 1588v2 protocol and a specific data structure is defined for accuracy feedback. This field contains three main information items: the error value of the current clock source, the jitter amplitude, and the timestamp accuracy.

[0087] The error value accurately records the time error of the current clock source in nanoseconds. Each time the synchronization signal is transmitted, the value is remeasured and updated.

[0088] The jitter amplitude is used to record the jitter of the clock source, that is, the stability fluctuation of the clock signal in a short period of time. This information is crucial for precision compensation of downstream devices.

[0089] As for the timestamp accuracy, it can be timestamp information accurate to nanoseconds, so that the downstream device can calibrate the time difference when receiving the signal and reduce error accumulation.

[0090] In an embodiment of the present application, each clock source device measures and updates its own error value and jitter in real time through a built-in high-precision timestamp measurement module. For example, a high-precision oscillator (such as an OCXO or a rubidium oscillator) is used to accurately measure the time difference transmitted to adjacent nodes, and the error calculation is incorporated into the synchronization packet of the transmission protocol, wherein the high-precision signal provided by the oscillator can ensure nanosecond-level error measurement. For another example, within each synchronization cycle, the clock source recalculates the time error and updates the TLV field so that the downstream node receives the accurate value of the current state. Through regular updates, the error value can be guaranteed to be adapted to the network state of the current network.

[0091] To eliminate the basic transmission delay in the network environment, in this embodiment of the application, the actual delay is calculated using two timestamps (the exact time of the sender and the receiver), and correction information is added to the TLV feedback based on the delay value (i.e., the actual delay). This allows downstream devices to accurately understand the actual transmission delay, rather than relying solely on a fixed delay estimate.

[0092] After receiving quantitative feedback data, downstream devices can also dynamically adjust their synchronization strategies based on their own business needs. For example, in financial or high-precision industrial control applications, downstream devices can set a lower error tolerance and use feedback information to adjust the synchronization frequency in real time to meet high-demand scenarios. Specifically, upon detecting that the upstream error value exceeds a set threshold, the device triggers an adaptive synchronization frequency increase to ensure that synchronization accuracy meets the required standards.

[0093] In this embodiment of the present application, the clock synchronization system can also store the accuracy feedback information within each clock cycle in the central control database to facilitate error trend analysis. This historical data can help the system predict error fluctuations and improve the accuracy of AI control.

[0094] After obtaining the clock error, the clock synchronization system uses a distributed coordination mechanism to coordinate the accuracy of multiple nodes in the system to reduce error accumulation and improve overall synchronization accuracy. The distributed coordination mechanism enables each node to calibrate each other during the synchronization process, ensuring consistent accuracy across the entire network.

[0095] In some embodiments, the clock synchronization system determines the weighting coefficients corresponding to other nodes based on the clock accuracy levels corresponding to other nodes; then, the clock errors corresponding to other nodes are weighted averaged according to the weighting coefficients to obtain the total clock error corresponding to the target node; finally, the clock accuracy of the target node is adjusted based on the total clock error to obtain the target clock accuracy.

[0096] It should be noted that in the embodiment of the present application, in order to achieve distributed collaborative calibration, each node not only receives synchronization information from the upstream clock source, but also feeds back its own accuracy status to the upstream node to achieve two-way synchronization of clock accuracy.

[0097] In one example, an additional field is added to the synchronization packets between nodes to record the actual error feedback from the downstream node. During each clock synchronization operation, the error information contained in this field is exchanged between the upstream and downstream nodes, allowing the upstream device to understand the actual synchronization error of the downstream node. After receiving the downstream feedback, the upstream node performs a calibration based on the difference between its local clock and the downstream feedback error. This error calculation enables the upstream node to fine-tune its own synchronization signal, thereby improving the accuracy of clock synchronization with the downstream node.

[0098] In an embodiment of the present application, a collaborative error calibration algorithm may be used to calculate the relative errors between multiple nodes in real time through a mathematical model and adjust each node.

[0099] Specifically, the clock synchronization system uses a weighted error averaging algorithm to calculate the weighted average of errors between multiple nodes. This weighted average is then used to correct each node's local clock, ensuring consistent clock accuracy. The weighting coefficient for weighting the errors between multiple nodes can be determined by node priority. For example, nodes with higher clock accuracy levels receive a larger weighted error.

[0100] For nodes with large errors, the clock synchronization system can make local adjustments using an error compensation factor to bring the node closer to synchronization more quickly. This error compensation factor can be calculated based on historical error data to reduce synchronization delays.

[0101] In an embodiment of the present application, in order to cope with dynamic changes in the network environment, the clock synchronization system can also implement distributed adaptive calibration, and each node adjusts the synchronization frequency and calibration strategy according to the real-time network status.

[0102] Specifically, when a node detects that the cumulative error of the clock exceeds a preset threshold, it automatically triggers a calibration strategy and immediately updates the synchronization frequency to reduce the accumulated error. In an embodiment of the present application, the cumulative error of the clock can be monitored in real time by the control module and adjusted according to network latency and node load. After completing the calibration, each node feeds back the calibration results to the central management module. If the calibration result does not reach the set synchronization accuracy, the clock synchronization system automatically adjusts the parameters and calibrates again to ensure that the final synchronization accuracy meets the requirements.

[0103] To optimize future calibration accuracy, the clock synchronization system stores the results of each distributed calibration in a central database for subsequent data analysis. For example, it uses historical calibration data to establish an error change model to predict the impact of network status on calibration accuracy. For example, based on error trend analysis, it dynamically optimizes the collaborative calibration algorithm to better adapt to different network topologies and node requirements.

[0104] In one embodiment, Figure 3 The overall flow chart of the method provided in the embodiment of the present application is shown in FIG. Figure 3 As shown, the process includes the following steps S301 to S306:

[0105] Step S301, collecting network status data;

[0106] Step S302: The control module predicts the network delay of the target node based on the network status data to adjust the clock synchronization frequency of the target node;

[0107] Step S303: Obtain the clock accuracy level corresponding to the target node to determine the clock adjustment requirement corresponding to the target node;

[0108] Step S304: adjusting the clock synchronization frequency of the target node again according to the clock adjustment requirement to obtain the target clock synchronization frequency;

[0109] Step S305: Obtain the clock errors fed back by the upstream node and the downstream node through the target field in the data message;

[0110] Step S306: performing clock synchronization on the target node according to the target clock synchronization frequency and the clock errors of the upstream and downstream nodes.

[0111] This concludes the introduction to the methods provided in the embodiments of this application.

[0112] Compared with the clock synchronization method in the related art, the solution provided in the embodiment of the present application is improved in at least the following five aspects:

[0113] (1) Quantitative accuracy feedback mechanism. By introducing the TLV extension field in the IEEE 1588v2 protocol data packet, real-time quantitative feedback of clock accuracy is achieved. This mechanism allows each downstream node to obtain the precise error value (e.g., nanosecond error, jitter amplitude) of the upstream node, ensuring the accurate transmission of synchronization signals.

[0114] (2) AI-driven dynamic control. In the embodiments of the present application, a deep learning model (e.g., LSTM or GRU) is used to predict the changing trend of clock accuracy and dynamically adjust the synchronization frequency based on the prediction results. This model can adapt to changes in network status in real time, perform frequency increase, load balancing and other controls, and improve the accuracy of clock synchronization.

[0115] (3) Multi-level precision control protocol. In the embodiments of the present application, a multi-level precision control protocol is designed and implemented to divide synchronization accuracy into multiple levels (e.g., advanced, intermediate, and basic), and dynamically allocate different synchronization accuracies based on the actual business needs of the nodes. This approach allows key nodes to obtain resources first under high load conditions to ensure the efficiency and accuracy of clock synchronization.

[0116] (4) Distributed collaborative calibration mechanism. In the embodiments of this application, bidirectional information transmission and a collaborative error calibration algorithm are used to achieve synchronization accuracy calibration of each node in the distributed network. Through algorithms such as error weighted averaging and compensation factors, each node performs adaptive calibration based on its own errors and those of adjacent nodes during the synchronization process, improving the accuracy consistency of the entire system.

[0117] (5) Redundant Paths and Fault Handling Mechanism. In the embodiments of this application, a multipath redundancy mechanism is introduced into the synchronization network to ensure that critical paths can maintain high synchronization accuracy even when latency fluctuations or failures occur. A path optimization mechanism and an automatic degradation mode are used to handle abnormal situations and dynamic degradation in resource shortages, thereby improving system stability and reliability.

[0118] Through the above five improvements, the solution provided by the embodiment of the present application can at least achieve the following effects:

[0119] (1) Higher synchronization accuracy. This application introduces a quantitative precision feedback mechanism and distributed collaborative calibration to obtain and transmit accurate error values and jitter data in real time. This precision feedback can achieve nanosecond-level error control, while traditional technologies usually only provide limited error feedback and coarse time synchronization, which cannot effectively cope with variable network delays and jitter. This solution significantly improves synchronization accuracy and overall network consistency.

[0120] (2) Dynamic control capability to adapt to complex network environments. This application uses an AI-driven dynamic control module, which can intelligently adjust the synchronization frequency and allocate resources according to the real-time network status. Traditional methods mostly rely on fixed synchronization frequencies and cannot dynamically adapt to delay fluctuations or load changes. This application can use AI to predict error trends and adjust synchronization parameters in real time, thereby improving the system's response speed and synchronization accuracy in complex network environments.

[0121] (3) Multi-level precision control mechanism. This application introduces a multi-level precision control protocol based on the differences in application scenarios, allowing each node in the network to be managed hierarchically with different synchronization accuracies. Existing technologies mostly use single-precision control, which is difficult to meet the different precision requirements of various types of nodes. Multi-level precision control can prioritize nodes with high precision requirements under resource-constrained conditions, optimize resource allocation, and ensure the clock accuracy of critical tasks.

[0122] (4) Fault tolerance of redundant paths. Through redundant paths and a dynamic path selection mechanism, this application can quickly switch to an alternative path when the primary synchronization path fails or the delay fluctuates, ensuring the continuity of clock synchronization. In contrast, the traditional single-path synchronization method is prone to synchronization failure when the path is blocked, and the redundant path mechanism of this application improves the system's fault tolerance and operational stability.

[0123] (5) High adaptability of distributed collaborative calibration. Existing technologies usually rely on centralized clock sources and are susceptible to single point failures. However, this application uses a distributed collaborative calibration mechanism to enable nodes to calibrate each other, feedback errors, and adjust clock parameters, thereby effectively reducing error accumulation and improving the overall synchronization consistency of the system. It is particularly suitable for network scenarios with many nodes and complex topology structures.

[0124] The embodiment of the present application also provides a network clock synchronization device, which is applied to a target node deployed in a network area, such as Figure 4 As shown, the device 400 includes: a data acquisition module 401 , a frequency adjustment module 402 , an error acquisition module 403 and a precision adjustment module 404 .

[0125] Data acquisition module 401 is used to obtain network status data corresponding to a target node deployed in a network area, and a clock synchronization path on which the target node is located. The clock synchronization path is any link on which the target node is located in the network topology corresponding to the network area, and multiple nodes are deployed on the clock synchronization path.

[0126] A frequency adjustment module 402 is configured to adjust the clock synchronization frequency corresponding to the target node according to the network status data and the clock accuracy level corresponding to the target node to obtain a target clock synchronization frequency, wherein the clock accuracy level is used to represent the clock synchronization priority corresponding to the target node;

[0127] The error acquisition module 403 is used to obtain the clock errors corresponding to other nodes on the clock synchronization path;

[0128] The precision adjustment module 404 is configured to adjust the clock precision of the target node based on the clock error at the target clock synchronization frequency to obtain the target clock precision.

[0129] In some embodiments, the frequency adjustment module includes:

[0130] A first adjustment module is used to adjust the clock synchronization frequency according to the network status data to obtain an initial clock synchronization frequency;

[0131] The second adjustment module is used to adjust the initial clock synchronization frequency according to the clock accuracy level corresponding to the target node to obtain the target clock synchronization frequency.

[0132] In some embodiments, the first adjustment module is specifically used to predict the network delay corresponding to the target node based on the network status data; when the network delay is greater than a preset delay threshold, the clock synchronization frequency of the target node is increased to obtain an initial clock synchronization frequency.

[0133] In some embodiments, the second adjustment module is specifically used to determine the clock adjustment requirement corresponding to the target node based on the correlation between the clock accuracy level and the accuracy requirement; and adjust the initial clock synchronization frequency according to the clock adjustment requirement to obtain the target clock synchronization frequency.

[0134] In some embodiments, the second adjustment module is specifically used to compare the clock accuracy level of the target node with a preset level threshold to obtain a comparison result when the network load level in the network area is higher than the load level threshold and / or there is a fault in the network equipment in the network area; when the clock accuracy level of the target node is greater than or equal to the preset level threshold, increase the initial clock synchronization frequency to obtain the target clock synchronization frequency; when the clock accuracy level of the target node is less than the preset level threshold, reduce the initial clock synchronization frequency to obtain the target clock synchronization frequency.

[0135] In some embodiments, data communication is performed between the target node and other nodes through a clock synchronization protocol. A target field is set in the clock synchronization protocol. The target field is used to store the clock error corresponding to the node. The error acquisition module is specifically used to obtain the clock error from the target field in the data message sent by each node in the other nodes.

[0136] In some embodiments, the precision adjustment module is specifically used to determine the weighting coefficients corresponding to other nodes based on the clock precision levels corresponding to other nodes; perform weighted average calculation on the clock errors corresponding to other nodes based on the weighting coefficients to obtain the total clock error corresponding to the target node; and adjust the clock precision of the target node based on the total clock error to obtain the target clock precision.

[0137] In some embodiments, the data acquisition module is specifically used to determine the link where the target node is located from the links corresponding to the network topology, and obtain at least one candidate clock synchronization path corresponding to the target node; obtain the clock cumulative error and clock cumulative delay corresponding to at least one candidate clock synchronization path, wherein the clock cumulative error is the sum of the clock errors of all nodes in the candidate clock synchronization path, and the clock cumulative delay is the sum of the clock delays of all nodes in the candidate clock synchronization path; determine the clock synchronization path corresponding to the target node from at least one candidate clock synchronization path based on the clock cumulative error and the clock cumulative delay.

[0138] In some embodiments, a network clock synchronization device includes: a redundant adjustment module, which is used to determine a backup clock path from at least one candidate clock synchronization path based on the clock cumulative error and the clock cumulative delay when the clock synchronization path corresponding to the target node is in an abnormal state, wherein the backup clock path is a path in at least one candidate clock synchronization path other than the clock synchronization path corresponding to the target node; and adjust the clock accuracy of the target node through the clock error of the node in the backup clock path to obtain the target clock accuracy.

[0139] The network clock synchronization device provided in the embodiment of the present application can implement each process implemented in the aforementioned method embodiment. To avoid repetition, it will not be described here.

[0140] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0141] Figure 5 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application is shown.

[0142] The electronic device may include a processor 501 and a memory 502 storing computer program instructions.

[0143] Specifically, the processor 501 may include a central processing unit (CPU), or an application-specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0144] The memory 502 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 502 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive, or a combination of two or more of these. Where appropriate, the memory 502 may include removable or non-removable (or fixed) media. Where appropriate, the memory 502 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, the memory 502 is a non-volatile solid-state memory.

[0145] The memory may include read-only memory (ROM), random access memory (RAM), magnetic disk storage media devices, optical storage media devices, flash memory devices, electrical, optical or other physical / tangible memory storage devices. Thus, generally, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the method according to an aspect of the present disclosure.

[0146] The processor 501 reads and executes computer program instructions stored in the memory 502 to implement any one of the network clock synchronization methods in the above embodiments.

[0147] In one example, the electronic device may further include a communication interface 503 and a bus 510. Figure 5 As shown, the processor 501, the memory 502, and the communication interface 503 are connected via a bus 510 and communicate with each other.

[0148] The communication interface 503 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0149] Bus 510 comprises hardware, software or both, couples the parts of electronic equipment to each other.For example, and not limitation, bus can comprise accelerated graphics port (AGP) or other graphics bus, enhanced industry standard architecture (EISA) bus, front side bus (FSB), hypertransport (HT) interconnection, industry standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations.In suitable cases, bus 510 can comprise one or more buses.Although the present application embodiment describes and shows specific bus, the application considers any suitable bus or interconnection.

[0150] In addition, in conjunction with the network clock synchronization method in the above embodiments, embodiments of the present application may provide a computer-readable storage medium for implementation. The computer-readable storage medium stores computer program instructions; when the computer program instructions are executed by a processor, any of the network clock synchronization methods in the above embodiments is implemented.

[0151] In addition, in conjunction with the network clock synchronization method in the above embodiments, embodiments of the present application may provide a computer program product for implementation. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes and implements any of the network clock synchronization methods in the above embodiments.

[0152] It should be understood that the present application is not limited to the specific configurations and processes described above and illustrated in the figures. For the sake of brevity, a detailed description of known methods is omitted here. In the above embodiments, several specific steps are described and illustrated as examples. However, the method process of the present application is not limited to the specific steps described and illustrated. Those skilled in the art can make various changes, modifications, and additions, or change the order of the steps after understanding the spirit of the present application.

[0153] The functional modules shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in unit, a function card or the like. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium that can store or transmit information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROMs, flash memories, erasable ROMs (EROMs), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0154] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps. In other words, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0155] Various aspects of the present disclosure have been described above with reference to the flowcharts and / or block diagrams of the network clock synchronization method, apparatus, electronic device, and storage medium according to embodiments of the present disclosure. It should be understood that each block in the flowcharts and / or block diagrams, as well as combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine such that execution of these instructions by the processor of the computer or other programmable data processing device enables the implementation of the functions / actions specified in one or more blocks in the flowcharts and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It should also be understood that each block in the block diagrams and / or flow charts, as well as combinations of blocks in the block diagrams and / or flow charts, can also be implemented by dedicated hardware that performs the specified functions or actions, or by a combination of dedicated hardware and computer instructions.

[0156] The above description is only a specific embodiment of the present application. Those skilled in the art will clearly understand that for the convenience and brevity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the scope of protection of the present application.

Claims

1. A method for synchronizing a network clock, characterized in that: include: Obtaining network status data corresponding to a target node deployed in a network area, and a clock synchronization path on which the target node is located, wherein the clock synchronization path is any one of the links on which the target node is located in a network topology corresponding to the network area, and multiple nodes are deployed on the clock synchronization path; Adjusting a clock synchronization frequency corresponding to the target node according to the network status data and a clock accuracy level corresponding to the target node to obtain a target clock synchronization frequency, wherein the clock accuracy level is used to represent a clock synchronization priority corresponding to the target node; Obtaining clock errors corresponding to other nodes on the clock synchronization path; At the target clock synchronization frequency, the clock accuracy of the target node is adjusted based on the clock error to obtain a target clock accuracy.

2. The method according to claim 1, characterized in that The adjusting the clock synchronization frequency corresponding to the target node according to the network status data and the clock accuracy level corresponding to the target node to obtain the target clock synchronization frequency includes: Adjusting the clock synchronization frequency according to the network status data to obtain an initial clock synchronization frequency; The initial clock synchronization frequency is adjusted according to the clock accuracy level corresponding to the target node to obtain the target clock synchronization frequency.

3. The method according to claim 2, characterized in that The adjusting the clock synchronization frequency according to the network status data to obtain an initial clock synchronization frequency includes: Predicting the network delay corresponding to the target node according to the network status data; When the network delay is greater than a preset delay threshold, the clock synchronization frequency of the target node is increased to obtain the initial clock synchronization frequency.

4. The method according to claim 2, characterized in that The adjusting the initial clock synchronization frequency according to the clock accuracy level corresponding to the target node to obtain the target clock synchronization frequency includes: Determining a clock adjustment requirement corresponding to the target node based on a correlation between the clock accuracy level and the accuracy requirement; The initial clock synchronization frequency is adjusted according to the clock adjustment requirement to obtain the target clock synchronization frequency.

5. The method according to claim 2, characterized in that The adjusting the initial clock synchronization frequency according to the clock accuracy level corresponding to the target node to obtain the target clock synchronization frequency includes: When the network load in the network area is higher than a load threshold, and / or a network device in the network area fails, comparing the clock accuracy level of the target node with a preset level threshold to obtain a comparison result; When the clock accuracy level of the target node is greater than or equal to the preset level threshold, increasing the initial clock synchronization frequency to obtain the target clock synchronization frequency; When the clock accuracy level of the target node is less than the preset level threshold, the initial clock synchronization frequency is reduced to obtain the target clock synchronization frequency.

6. The method according to claim 1, characterized in that The target node communicates data with the other nodes via a clock synchronization protocol, wherein a target field is set in the clock synchronization protocol, and the target field is used to store a clock error corresponding to the node. The obtaining of the clock errors corresponding to the other nodes on the clock synchronization path includes: The clock error is obtained from a target field in a data message sent by each of the other nodes.

7. The method according to claim 6, characterized in that The adjusting the clock accuracy of the target node based on the clock error at the target clock synchronization frequency to obtain the target clock accuracy includes: Determining weighting coefficients corresponding to the other nodes according to clock accuracy levels corresponding to the other nodes; Performing weighted average calculation on the clock errors corresponding to the other nodes according to the weighting coefficient to obtain a total clock error corresponding to the target node; The clock accuracy of the target node is adjusted based on the total clock error to obtain the target clock accuracy.

8. The method according to any one of claims 1 to 7, characterized in that The acquiring the clock synchronization path where the target node is located includes: Determine, from the links corresponding to the network topology, the link where the target node is located, and obtain at least one candidate clock synchronization path corresponding to the target node; Obtaining a clock cumulative error and a clock cumulative delay corresponding to at least one of the candidate clock synchronization paths, wherein the clock cumulative error is the sum of the clock errors of all nodes in the candidate clock synchronization path, and the clock cumulative delay is the sum of the clock delays of all nodes in the candidate clock synchronization path; A clock synchronization path corresponding to the target node is determined from at least one candidate clock synchronization path according to the clock cumulative error and the clock cumulative delay.

9. The method according to claim 8, characterized in that The method further comprises: When the clock synchronization path corresponding to the target node is in an abnormal state, determining a backup clock path from at least one of the candidate clock synchronization paths according to the clock cumulative error and the clock cumulative delay, wherein the backup clock path is a path other than the clock synchronization path corresponding to the target node in at least one of the candidate clock synchronization paths; The clock accuracy of the target node is adjusted according to the clock error of the node in the backup clock path to obtain the target clock accuracy.

10. A network clock synchronization device, characterized in that: include: a data acquisition module, configured to acquire network status data corresponding to a target node deployed in a network area, and a clock synchronization path on which the target node is located, wherein the clock synchronization path is any one of the links on which the target node is located in the network topology corresponding to the network area, and multiple nodes are deployed on the clock synchronization path; a frequency adjustment module, configured to adjust the clock synchronization frequency corresponding to the target node according to the network status data and the clock accuracy level corresponding to the target node to obtain a target clock synchronization frequency, wherein the clock accuracy level is used to represent the clock synchronization priority corresponding to the target node; An error acquisition module, configured to acquire clock errors corresponding to other nodes on the clock synchronization path; The precision adjustment module is used to adjust the clock precision of the target node based on the clock error at the target clock synchronization frequency to obtain the target clock precision.

11. An electronic device, characterized in that: The electronic device includes: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, the network clock synchronization method according to any one of claims 1 to 9 is implemented.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the network clock synchronization method according to any one of claims 1 to 9 is implemented.

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