Clock synchronization system and method, electronic equipment and storage medium
Through the PPS synchronization pulse signal and second time stamp mechanism between master and slave devices, combined with crystal oscillator module and timestamp calibration, high-precision and low-cost clock synchronization are achieved, solving the synchronization problem in resource-constrained environments in the existing technology, and is suitable for multi-device collaborative control and distributed computing.
Patent Information
- Application Number
- CN202510684049.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-26
- Publication Date
- 2025-08-12
AI Technical Summary
The existing clock synchronization solution is difficult to take into account high precision, low cost and system simplification in resource-constrained environments, which limits its application.
Using the PPS synchronization pulse signal and second time stamp mechanism between the master and slave devices, the PPS synchronization pulse signal is sent to the slave device at each full second time stamp through the first clock synchronization module of the master device, and the time stamp alignment is performed by the logic control module, combining the crystal oscillator module and the timestamp calibration module to achieve high-precision synchronization.
It realizes second-level clock synchronization and nanosecond timestamp update between master and slave devices. It has a simple structure, low cost and high synchronization accuracy. It is suitable for multi-device collaborative control and distributed computing scenarios.
Smart Images
Figure CN120474658A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of clock synchronization technology, and in particular to a clock synchronization system, method, electronic device, and storage medium. Background Art
[0002] To achieve collaborative operation among multiple devices, it is often necessary to rely on a unified time base for clock synchronization. Existing clock synchronization solutions include NTP, PTP, GPS, and GPS disciplined clocks. NTP has low accuracy and relies on network servers. Although PTP can achieve nanosecond-level accuracy, it requires a dedicated switch and master clock, making the system complex and costly. GPS clock synchronization is greatly affected by the environment, and each device must be equipped with a receiving module, resulting in high hardware overhead and high cost. GPS disciplined clocks use crystal oscillators to maintain short-term stability and require GPS to calibrate long-term errors. Although they can maintain high synchronization accuracy to a certain extent, they are costly. The above solutions cannot achieve high accuracy, low cost, and system simplification at the same time, which limits their application in resource-constrained environments.
[0003] Therefore, this application proposes a new clock synchronization system. Summary of the Invention
[0004] In view of the above problems, embodiments of the present application provide a clock synchronization system, method, electronic device, and storage medium to overcome the above problems or at least partially solve the above problems.
[0005] According to a first aspect of an embodiment of the present application, a clock synchronization system is provided, comprising: a master device and at least one slave device, wherein the master device comprises a first clock synchronization module and a first logic control module; the slave device comprises a second clock synchronization module and a second logic control module; the first clock synchronization module is communicatively connected to the first logic control module and the second clock synchronization module, respectively; the first logic control module is communicatively connected to the second logic control module, and the second logic control module is communicatively connected to the second clock synchronization module; The first clock synchronization module is configured to send a PPS synchronization pulse signal to the second clock synchronization module at each full second timestamp, and send an interrupt signal to the first logic control module; The first logic control module is configured to, after receiving the interrupt signal, receive a first second timestamp sent by the first clock synchronization module, and send the first second timestamp to the second logic control module; The second clock synchronization module is configured to update the second second timestamp of the second clock synchronization module and clear the second nanosecond timestamp of the second clock synchronization module after receiving the PPS synchronization pulse signal; The second logic control module is configured to align the second second timestamp in the second clock synchronization module with the first second timestamp after receiving the first second timestamp, so as to synchronize the second timestamps between the master device and the slave device.
[0006] Optionally, the first clock synchronization module includes: a first timestamp storage unit, a pulse signal output unit and a second timestamp sending unit; The first timestamp register unit includes a first second counting subunit and a first nanosecond counting subunit; The first nanosecond counting subunit is configured to accumulate first nanosecond timestamps according to a first preset step size when receiving a falling edge of a clock signal, and to clear the accumulated result of the first nanosecond timestamps to zero when the accumulated result reaches a preset nanosecond timestamp; The first second counting subunit is configured to accumulate first second timestamps after the accumulated result of the first nanosecond timestamps reaches the preset nanosecond timestamp; The pulse signal output unit is configured to generate the PPS synchronization pulse signal after the first second timestamp of the first second counting subunit is accumulated by 1, and send the PPS synchronization pulse signal to the second clock synchronization module; The timestamp sending unit is configured to send the generated interrupt signal and the first second timestamp after the first second timestamp is added by 1 to the first logic control module after the first second timestamp of the first second counting subunit is added by 1.
[0007] Optionally, the main device is further provided with a first crystal oscillator module; The first crystal oscillator module is communicatively connected to the first clock synchronization module; The first crystal oscillator module is used to send a clock signal to the first nanosecond counting subunit at a preset frequency, so that the first nanosecond counting subunit accumulates the first nanosecond timestamp according to the first preset step size when receiving the falling edge of the clock signal.
[0008] Optionally, the second clock synchronization module includes: a second timestamp register unit, a pulse signal receiving unit; The second timestamp register unit includes a second second counting subunit and a second nanosecond counting subunit; The pulse signal receiving unit is used to receive the PPS synchronization pulse signal and collect the falling edge of the PPS synchronization pulse signal; The second second counting subunit is used to accumulate the second second timestamp when the pulse signal receiving unit collects the falling edge of the PPS synchronization pulse signal; The second nanosecond counting subunit is used to clear the second nanosecond timestamp when the pulse signal receiving unit collects the falling edge of the PPS synchronization pulse signal, and accumulate the second nanosecond timestamp according to the second preset step size under the drive of the second crystal oscillator module built into the second clock synchronization module.
[0009] Optionally, the second clock synchronization module further includes: a timestamp calibration module; The timestamp calibration module is used to record the second nanosecond timestamps corresponding to multiple continuous PPS synchronization pulse signals, calculate the average value of multiple second nanosecond timestamps to estimate the actual frequency of the second crystal oscillator module, and calibrate the second preset step size according to the actual frequency of the second crystal oscillator module.
[0010] Optionally, the system further includes a host computer, which is communicatively connected to the first logic control module and the second logic control module respectively; The host computer is provided with an Ethernet synchronization communication protocol module, which is used to broadcast the first second timestamp sent by the first logic control module via Ethernet after monitoring the first second timestamp sent by the first logic control module, so that the second logic control module can calibrate the second second timestamp.
[0011] Optionally, there are multiple slave devices, and the system further includes: a multi-channel clock fan-out module; The input end of the multi-channel clock fan-out module is communicatively connected to the output end of the first clock synchronization module of the master device, and the output end of the multi-channel clock fan-out module is communicatively connected to the input end of the second clock synchronization module of each of the slave devices; The multi-channel clock fan-out module is used to transmit the PPS synchronization pulse signal sent by the first clock synchronization module to the second clock synchronization module of each of the slave devices with the same delay.
[0012] In a second aspect of an embodiment of the present application, a clock synchronization method is provided. The method is applied to the clock synchronization system according to the first aspect of the present application, and the method includes: The first clock synchronization module of the master device sends a PPS synchronization pulse signal to the second clock synchronization module of the slave device at each full second timestamp, and sends an interrupt signal to the first logic control module of the master device; After receiving the interrupt signal, the first logic control module receives the first second timestamp output by the first clock synchronization module, and sends the first second timestamp to the second logic control module of the slave device; After receiving the PPS synchronization pulse signal, the second clock synchronization module of the slave device updates its internal second second timestamp and clears its internal second nanosecond timestamp; After receiving the first second timestamp, the second logic control module of the slave device aligns the second second timestamp with the first second timestamp to achieve second timestamp synchronization between the master device and the slave device.
[0013] In a third aspect of an embodiment of the present application, an electronic device is provided, comprising a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the steps of the clock synchronization method as described in the second aspect of the present application.
[0014] In a fourth aspect of an embodiment of the present application, a readable storage medium is provided, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the clock synchronization method described in the second aspect of the present application are implemented.
[0015] Beneficial effects of this application: The present application provides a clock synchronization system, comprising: a master device and at least one slave device, wherein the master device comprises a first clock synchronization module and a first logic control module; the slave device comprises a second clock synchronization module and a second logic control module; the first clock synchronization module is communicatively connected to the first logic control module and the second clock synchronization module, respectively, the first logic control module is communicatively connected to the second logic control module, and the second logic control module is communicatively connected to the second clock synchronization module; the first clock synchronization module is configured to send a PPS synchronization pulse signal to the second clock synchronization module at each full second timestamp, and to send an interrupt signal to the first logic control module; the first logic control module is configured to receive a first second timestamp sent by the first clock synchronization module after receiving the interrupt signal, and send the first second timestamp to the second logic control module; the second clock synchronization module is configured to update a second second timestamp of the second clock synchronization module after receiving the PPS synchronization pulse signal, and clear a second nanosecond timestamp of the second clock synchronization module; and the second logic control module is configured to align the second second timestamp in the second clock synchronization module with the first second timestamp after receiving the first second timestamp, so as to synchronize the second timestamps between the master device and the slave device.
[0016] This application sends PPS synchronization pulse signals and second timestamps to slave devices through the master device, thereby achieving second-level clock synchronization and nanosecond timestamp updates between the master and slave devices. It has a simple structure, low cost, and high synchronization accuracy and stability. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0018] Figure 1 is a schematic diagram of a clock synchronization system provided in an embodiment of the present application; Figure 2 This is a multi-device clock synchronization system provided by an embodiment of the present application; Figure 3 This is a schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0019] The exemplary embodiments of the present application will be described in more detail below in conjunction with the accompanying drawings in the embodiments of the present application. Although the accompanying drawings show exemplary embodiments of the present application, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.
[0020] In a first aspect of the embodiment of the present application, a clock synchronization system is provided, such as Figure 1 As shown, it includes: a master device and at least one slave device, wherein the master device includes a first clock synchronization module and a first logic control module; the slave device includes a second clock synchronization module and a second logic control module; the first clock synchronization module is respectively communicated with the first logic control module and the second clock synchronization module, the first logic control module is communicated with the second logic control module, and the second logic control module is communicated with the second clock synchronization module; The first clock synchronization module is configured to send a PPS synchronization pulse signal to the second clock synchronization module at each full second timestamp, and send an interrupt signal to the first logic control module; The first logic control module is configured to, after receiving the interrupt signal, receive a first second timestamp sent by the first clock synchronization module, and send the first second timestamp to the second logic control module; The second clock synchronization module is configured to update the second second timestamp of the second clock synchronization module after receiving the PPS synchronization pulse signal, and send the first second timestamp to the second logic control module; The second logic control module is configured to align the second second timestamp in the second clock synchronization module with the first second timestamp after receiving the first second timestamp, so as to synchronize the second timestamps between the master device and the slave device.
[0021] In this embodiment, refer to Figure 1 As shown, it includes a master device and at least one slave device. The master device includes a first clock synchronization module and a first logic control module, and the slave device includes a second clock synchronization module and a second logic control module.
[0022] The first clock synchronization module is in communication with the first and second logic control modules, generating a PPS synchronization pulse signal at every full second, sending the PPS synchronization pulse signal to the second clock synchronization module, and simultaneously sending an interrupt signal to the first logic control module. The interrupt signal indicates that the full second has arrived, triggering the acquisition and transmission of the timestamp.
[0023] After receiving the interrupt signal, the first logic control module receives the current first-second timestamp sent by the first clock synchronization module, and sends the first-second timestamp to the second logic control module.
[0024] After receiving the PPS synchronization pulse signal, the second clock synchronization module updates the second second timestamp and nanosecond timestamp maintained by itself to record the new whole second moment and reset the nanosecond timestamp.
[0025] After receiving the first second timestamp from the first logic control module, the second logic control module aligns the local second second timestamp with the first second timestamp to achieve second timestamp synchronization between the master device and the slave device.
[0026] The clock synchronization system described in this application can achieve high-precision second-level time synchronization and nanosecond timestamp correction between master and slave devices without the need for complex network protocols or GPS hardware. It has the advantages of simple structure, low cost, and high synchronization accuracy. It is suitable for the timing consistency requirements in multi-device collaborative control or distributed computing scenarios.
[0027] The clock synchronization system provided by the present application includes a master device and at least one slave device. The master device is provided with a first clock synchronization module and a first logic control module, and the slave device is provided with a second clock synchronization module and a second logic control module. The first clock synchronization module is used to send a PPS synchronization pulse signal to the slave device at each full second timestamp, and send an interrupt signal to the first logic control module. After receiving the interrupt signal, the first logic control module obtains the first second timestamp and sends it to the second logic control module. After receiving the PPS synchronization pulse signal, the slave device updates the local second timestamp and nanosecond timestamp, and the second logic control module aligns the local timestamp with the first second timestamp to achieve second-level time synchronization between the master and slave devices. The present application sends a PPS synchronization pulse signal and a second timestamp to the slave device by the master device, thereby achieving second-level clock synchronization and nanosecond timestamp update between the master and slave devices. It has a simple structure, low cost, and high synchronization accuracy and stability.
[0028] In one embodiment, the first clock synchronization module includes: a first timestamp register unit, a pulse signal output unit, and a second timestamp sending unit; The first timestamp register unit includes a first second counting subunit and a first nanosecond counting subunit; The first nanosecond counting subunit is configured to accumulate first nanosecond timestamps according to a first preset step size when receiving a falling edge of a clock signal, and to clear the accumulated result of the first nanosecond timestamps to zero when the accumulated result reaches a preset nanosecond timestamp; The first second counting subunit is configured to accumulate first second timestamps after the accumulated result of the first nanosecond timestamps reaches the preset nanosecond timestamp; The pulse signal output unit is configured to generate the PPS synchronization pulse signal after the first second timestamp of the first second counting subunit is accumulated by 1, and send the PPS synchronization pulse signal to the second clock synchronization module; The timestamp sending unit is configured to send the generated interrupt signal and the first second timestamp after the first second timestamp is added by 1 to the first logic control module after the first second timestamp of the first second counting subunit is added by 1.
[0029] Continue to refer to Figure 1 The first clock synchronization module is arranged inside the master device, and its structure includes: a timestamp storage unit, a pulse signal output unit and a timestamp sending unit.
[0030] The timestamp register is primarily used to record the current time of the master device, and further comprises a second counter and a nanosecond counter. The nanosecond counter receives clock signals from the system. Each time a falling edge of the clock signal arrives, the nanosecond counter accumulates the nanosecond timestamp according to a first preset step value, for example, accumulating 10 nanoseconds each time. As the clock continues to input, the nanosecond timestamp continues to accumulate. When the accumulated value reaches a set threshold (e.g., 1 billion nanoseconds, corresponding to 1 second), the nanosecond counter automatically resets to zero, triggering the second counter to increment the second timestamp by 1, thereby confirming and advancing the full "1 second."
[0031] The pulse signal output unit automatically generates a standard PPS synchronization pulse signal each time the second counter subunit completes a second timestamp increment operation and outputs this PPS synchronization pulse signal to the connected slave device. This PPS synchronization pulse signal serves as an important indicator of the master device's full second moment. The slave device receives this PPS synchronization pulse signal and uses it to update its local timestamp state, achieving full second alignment between the master and slave devices.
[0032] The timestamp sending unit sends an interrupt signal to the first logic control module in the master device after each full second event, notifying it of the occurrence. Simultaneously, the timestamp sending unit also sends the updated first-second timestamp (i.e., the latest second value) to the first logic control module for subsequent second-time broadcasting or network synchronization operations.
[0033] Through the above structural design, the first clock synchronization module can achieve continuous and stable nanosecond time recording and whole second generation based on the high-frequency clock, and through the PPS synchronization pulse signal and interrupt mechanism, it can efficiently and accurately transmit the current second time to the master control logic and slave devices, effectively supporting the time synchronization requirements of multiple nodes in the system.
[0034] In one embodiment, the main device is further provided with a first crystal oscillator module; The first crystal oscillator module is communicatively connected to the first clock synchronization module; The first crystal oscillator module is used to send a clock signal to the first nanosecond counting subunit at a preset frequency, so that the first nanosecond counting subunit accumulates the first nanosecond timestamp according to the first preset step size when receiving the falling edge of the clock signal.
[0035] Continue to refer to Figure 1 In this embodiment, a first crystal oscillator module is further provided inside the master device for providing a stable clock source for the first clock synchronization module.
[0036] The first crystal oscillator module is communicatively connected to the first clock synchronization module and can periodically output a clock signal at a preset frequency (e.g., 100 MHz). This clock signal is transmitted to the first nanosecond counter subunit in the first timestamp register. This clock signal serves as a time reference to drive the accumulation of nanosecond timestamps.
[0037] Specifically, after receiving the clock signal output by the first crystal oscillator module, the first nanosecond counting subunit detects the falling edge of the signal; each time the falling edge is triggered, the first nanosecond counting subunit increments and accumulates the first nanosecond timestamp according to a first preset step size (for example, 10 nanoseconds). By constant output of the crystal oscillator frequency, combined with a stable falling edge triggering method, the periodicity and consistency of the nanosecond counting process can be guaranteed, thereby providing an accurate time basis for subsequent full-second timestamp generation, PPS synchronization pulse signal output, and interrupt notification. In this application, the first crystal oscillator module adopts temperature compensation or low-jitter design to ensure the short-term stability of its clock frequency, which helps to improve the clock accuracy and synchronization reliability of the entire master device during operation.
[0038] In one embodiment, the second clock synchronization module includes: a second timestamp register unit, a pulse signal receiving unit; The second timestamp register unit includes a second second counting subunit and a second nanosecond counting subunit; The pulse signal receiving unit is used to receive the PPS synchronization pulse signal and collect the falling edge of the PPS synchronization pulse signal; The second second counting subunit is used to accumulate the second second timestamp when the pulse signal receiving unit collects the falling edge of the PPS synchronization pulse signal; The second nanosecond counting subunit is used to clear the second nanosecond timestamp when the pulse signal receiving unit collects the falling edge of the PPS synchronization pulse signal, and accumulate the second nanosecond timestamp according to the second preset step size under the drive of the second crystal oscillator module built into the second clock synchronization module.
[0039] Continue to refer to Figure 1 The second clock synchronization module is provided in the slave device and is used to receive the PPS synchronization pulse signal from the master device and complete the local time update and alignment of the slave device. The second clock synchronization module includes: a second timestamp register unit and a pulse signal receiving unit.
[0040] The second timestamp register unit includes a second second counting subunit and a second nanosecond counting subunit, which are respectively used to record the current second time and nanosecond time of the slave device.
[0041] The pulse signal receiving unit is used to receive the PPS synchronization pulse signal output by the first clock synchronization module of the master device and detect the falling edge of the PPS synchronization pulse signal. The falling edge serves as a flag signal arriving at every full second and is used to trigger the update operation of each time unit in the slave device.
[0042] Specifically, when the pulse signal receiving unit detects the falling edge of the PPS synchronization pulse signal, the second second counting subunit performs a second second timestamp accumulation operation to record the current full second time. At the same time, the second nanosecond counting subunit clears the current second nanosecond timestamp and restarts counting.
[0043] After being cleared, the second nanosecond timestamp continues to operate under the control of the second crystal oscillator module within the second clock synchronization module. This second crystal oscillator module periodically outputs a clock signal at a set frequency (e.g., 100 MHz), driving the second nanosecond counter subunit to accumulate timestamps within each clock cycle according to a second preset step size (e.g., 10 nanosecond increments). This mechanism ensures that the slave device, guided by the master device's PPS synchronization pulse signal, continuously advances its local time based on its own crystal oscillator.
[0044] This embodiment can effectively achieve full-second time alignment between the master and slave devices while maintaining high-precision local time operation of the slave device during the master pulse interval.
[0045] In one embodiment, the second clock synchronization module further includes: a timestamp calibration module; The timestamp calibration module is used to record the second nanosecond timestamps corresponding to multiple continuous PPS synchronization pulse signals, calculate the average value of multiple second nanosecond timestamps to estimate the actual frequency of the second crystal oscillator module, and calibrate the second preset step size according to the actual frequency of the second crystal oscillator module.
[0046] Continue to refer to Figure 1 The second clock synchronization module also includes a timestamp calibration module for dynamically estimating the output frequency of the second crystal oscillator module and calibrating the counting accuracy of the second nanosecond counting subunit based on the estimation result.
[0047] The timestamp calibration module is configured to continuously record the second nanosecond timestamps corresponding to the arrival moments of multiple PPS synchronization pulse signals during the operation of the slave device. Whenever the pulse signal receiving unit of the second clock synchronization module detects a falling edge of the PPS synchronization pulse signal, the count value of the current second nanosecond timestamp is collected and stored.
[0048] By comparing the second-nanosecond timestamp differences between two adjacent PPS synchronization pulses, the time intervals between multiple consecutive pulses are determined. The timestamp calibration module averages these intervals to estimate the actual frequency output by the second crystal oscillator module. Due to slight deviations in actual crystal oscillators, this frequency value is used to dynamically adjust the incrementing step size (i.e., the second preset step size) of the second nanosecond counter subunit to ensure that the slave device's local clock count remains consistent with that of the master device during non-PPS pulse periods.
[0049] In one embodiment, the system further includes a host computer, wherein the host computer is communicatively connected to the first logic control module and the second logic control module respectively; The host computer is provided with an Ethernet synchronization communication protocol module, which is used to broadcast the first second timestamp sent by the first logic control module via Ethernet after monitoring the first second timestamp sent by the first logic control module, so that the second logic control module can calibrate the second second timestamp.
[0050] Continue to refer to Figure 1 The system further includes a host computer for assisting in completing the second-level timestamp synchronization operation between the master and slave devices. The host computer establishes communication connections with the first logic control module in the master device and the second logic control module in the slave device.
[0051] Specifically, the host computer is internally provided with an Ethernet synchronization communication protocol module, which is configured to monitor time synchronization information from the first logic control module at every full second. When the host computer monitors the first second timestamp sent by the first logic control module, it immediately broadcasts the first second timestamp to the second logic control module connected to it via the Ethernet interface.
[0052] After receiving the first-second timestamp, the second logic control module can compare the timestamp with the second-second timestamp recorded in the local second clock synchronization module, and if there is a deviation, calibrate the second-second timestamp according to the received first-second timestamp, thereby achieving high-precision alignment between the master and slave devices at the whole-second level.
[0053] By introducing the host computer and Ethernet broadcast mechanism, after the master device triggers the whole second event, the standard second timestamp can be quickly synchronized to multiple slave devices, effectively solving the problem of inconsistent initial second values caused by different system startup timings, and further improving the time consistency and synchronization efficiency of the entire system in multi-device collaboration scenarios.
[0054] In one embodiment, there are multiple slave devices, and the system further includes: a multi-channel clock fan-out module; The input end of the multi-channel clock fan-out module is communicatively connected to the output end of the first clock synchronization module of the master device, and the output end of the multi-channel clock fan-out module is communicatively connected to the input end of the second clock synchronization module of each of the slave devices; The multi-channel clock fan-out module is used to transmit the PPS synchronization pulse signal sent by the first clock synchronization module to the second clock synchronization module of each of the slave devices with the same delay.
[0055] In this embodiment, refer to Figure 2 The multi-device clock synchronization system shown supports the access of multiple slave devices. To ensure that multiple slave devices can simultaneously receive the PPS synchronization pulse signal output by the master device, the system is also provided with a multi-channel clock fan-out module.
[0056] Among them, the input end of the multi-channel clock fan-out module is communicatively connected to the output end of the first clock synchronization module in the master device, and is used to receive the PPS synchronization pulse signal output by the master device; its output end is communicatively connected to the input end of the second clock synchronization module in multiple slave devices.
[0057] Specifically, the multi-channel clock fan-out module is used to distribute the PPS synchronization pulse signal to the second clock synchronization module of each slave device at the same time using the same physical delay path or electrical delay compensation method each time the master device generates a PPS synchronization pulse signal, ensuring that all slave devices receive the PPS synchronization pulse signal at the same time point.
[0058] This embodiment uses a multi-channel clock fan-out module to effectively avoid time errors caused by wiring path differences or inconsistent electrical delays, ensuring the consistency of synchronous response of each slave device at the whole second, thereby improving the time synchronization accuracy of the entire system and the stability of multi-node collaborative control.
[0059] This application provides a clock synchronization system suitable for high-precision full-second synchronization between multiple devices in a master-slave structure. The system includes: a master device, multiple slave devices, a host computer, and a multi-channel clock fan-out module.
[0060] In this embodiment, the master device includes a first clock synchronization module and a first logic control module, and the slave device includes a second clock synchronization module and a second logic control module.
[0061] The first clock synchronization module includes a first timestamp register unit, a pulse signal output unit, and a timestamp sending unit. The first timestamp register unit further includes a first second counting subunit and a first nanosecond counting subunit. A first crystal oscillator module is communicatively connected to the module as a clock source and is configured to send a clock signal at a fixed frequency to the first nanosecond counting subunit.
[0062] The first nanosecond counter subunit is configured to increment the first nanosecond timestamp by a first preset step size upon each falling edge of the clock signal. When the accumulated first nanosecond timestamp reaches a preset nanosecond value (e.g., 1 billion nanoseconds corresponding to 1 second), the first second counter subunit is triggered to increment the first second timestamp by 1 and reset the first nanosecond timestamp to 0. Subsequently, the pulse signal output unit generates a PPS synchronization pulse signal and sends it to the slave device. Simultaneously, the timestamp transmission unit sends an interrupt signal and the currently accumulated first second timestamp to the first logic control module.
[0063] After receiving the interrupt signal, the first logic control module obtains the first second timestamp from the first clock synchronization module and sends the timestamp to the second logic control module.
[0064] The second clock synchronization module includes a second timestamp register unit and a pulse signal receiving unit, wherein the second timestamp register unit includes a second second counting subunit and a second nanosecond counting subunit, and the second crystal oscillator module is communicatively connected with the second timestamp register unit.
[0065] When the second clock synchronization module receives the falling edge of the PPS synchronization pulse signal through the pulse signal receiving unit, it triggers the second second counting sub-unit to perform the second second timestamp accumulation operation, and at the same time clears the second nanosecond timestamp, and the second crystal oscillator module drives the second nanosecond counting sub-unit to continue accumulating according to the second preset step size.
[0066] After receiving the first second timestamp from the master device, the second logic control module compares the first second timestamp with the local second timestamp and completes second-level time alignment, thereby achieving synchronization between the master and slave devices.
[0067] To further improve the long-term accuracy of the slave device's local clock, the second clock synchronization module also includes a timestamp calibration module. This module records the second nanosecond timestamps of the arrival of multiple consecutive PPS synchronization pulse signals, calculates the time interval between each two adjacent PPS synchronization pulses, and averages these multiple intervals to estimate the actual output frequency of the second crystal oscillator module. Based on this average, the second preset step size is dynamically calibrated, effectively improving the slave device's timing accuracy within the master pulse interval.
[0068] At the system level, a host computer module is also included, communicating with the master device's first logic control module and each slave device's second logic control module. The host computer includes an Ethernet synchronization protocol module, which, upon receiving the first-second timestamp from the master device, broadcasts it to all slave devices via Ethernet. This assists in aligning the second timestamps, particularly when devices have inconsistent power-on times or require remote initialization and synchronization.
[0069] Furthermore, to enable the master device to simultaneously transmit PPS synchronization pulse signals to multiple slave devices, the system also includes a multi-channel clock fan-out module. This module's input is connected to the output of the master device's first clock synchronization module, and its output is connected to multiple slave devices. This module ensures that PPS pulses are transmitted to each slave device along the same delay path, ensuring that multiple devices receive the synchronization signal at the same time, further improving the system's synchronization consistency and real-time performance.
[0070] To sum up, the clock synchronization system provided by this application does not rely on PTP dedicated network equipment or equip each device with a GPS module. Through hardware PPS pulses, Ethernet timestamp broadcast, crystal oscillator drive and frequency calibration mechanisms, it realizes a multi-device second-level time alignment solution with simple structure, low cost, high synchronization accuracy and strong adaptability.
[0071] The clock synchronization system provided by the present application is characterized in that the master device is provided with a first clock synchronization module and a first logic control module, and the slave device is provided with a second clock synchronization module and a second logic control module. The first clock synchronization module is used to send a PPS synchronization pulse signal to the slave device at each full second timestamp, and send an interrupt signal to the first logic control module. After receiving the interrupt signal, the first logic control module obtains the first second timestamp and sends it to the second logic control module. After receiving the PPS synchronization pulse signal, the slave device updates the local second timestamp and nanosecond timestamp, and the second logic control module aligns the local timestamp with the first second timestamp to achieve second-level time synchronization between the master and slave devices. The present application sends a PPS synchronization pulse signal and a second timestamp to the slave device by the master device, thereby achieving second-level clock synchronization and nanosecond timestamp update between the master and slave devices. It has a simple structure, low cost, and high synchronization accuracy and stability.
[0072] Based on the same inventive concept, in a second aspect, the present application provides a clock synchronization method applied to the clock synchronization system described in the first aspect of the present application, the method comprising: Step S101: The first clock synchronization module of the master device sends a PPS synchronization pulse signal to the second clock synchronization module of the slave device at each full second timestamp, and sends an interrupt signal to the first logic control module of the master device; Step S102: After receiving the interrupt signal, the first logic control module receives the first second timestamp output by the first clock synchronization module, and sends the first second timestamp to the second logic control module of the slave device; Step S103, after receiving the PPS synchronization pulse signal, the second clock synchronization module of the slave device updates its internal second second timestamp and clears its internal second nanosecond timestamp; Step S104 : After receiving the first second timestamp, the second logic control module of the slave device aligns the second second timestamp with the first second timestamp to achieve second timestamp synchronization between the master device and the slave device.
[0073] In step S101, the first clock synchronization module of the master device sends a PPS synchronization pulse signal to the second clock synchronization module of the slave device at every full second, and simultaneously sends an interrupt signal to the first logic control module in the master device to indicate that a full second event has arrived.
[0074] In step S102 , after receiving the interrupt signal, the first logic control module obtains the current first second timestamp from the first clock synchronization module and sends the timestamp to the second logic control module of the slave device.
[0075] In step S103, after receiving the PPS synchronization pulse signal, the second clock synchronization module of the slave device immediately updates the second second timestamp recorded internally to mark the start of the current full second, and clears the second nanosecond timestamp recorded internally.
[0076] In step S104, after receiving the first second timestamp sent by the master device, the second logic control module of the slave device aligns and calibrates the local second second timestamp with the first second timestamp, thereby achieving second-level time consistency between the master and slave devices.
[0077] Through the above steps, the system can achieve precise second-level clock synchronization between the master and slave devices without relying on complex network protocols or high-cost hardware.
[0078] Based on the same inventive concept, the third aspect of the embodiment of the present application provides a Figure 3 The electronic device 100 shown includes a processor 120, a memory 110, and a program or instruction stored in the memory 110 and executable on the processor 120. When the program or instruction is executed by the processor, the steps of the clock synchronization method described in the second aspect of the present application are implemented.
[0079] Based on the same inventive concept, the fourth aspect of the embodiment of the present application provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the clock synchronization method described in the second aspect of the present application are implemented.
[0080] Each embodiment in this specification focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referenced to each other.
[0081] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, devices, or computer program products. Therefore, the embodiments of the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0082] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0083] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.
[0084] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.
[0085] Although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.
[0086] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.
[0087] The above is a detailed introduction to the provided clock synchronization system, method, electronic device and storage medium. Specific examples are used in this article to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method of this application and its core idea. At the same time, for general technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on this application.
Claims
1. A clock synchronization system, characterized in that: include: A master device and at least one slave device, wherein the master device includes a first clock synchronization module and a first logic control module; the slave device includes a second clock synchronization module and a second logic control module; the first clock synchronization module is communicatively connected to the first logic control module and the second clock synchronization module respectively, the first logic control module is communicatively connected to the second logic control module, and the second logic control module is communicatively connected to the second clock synchronization module; The first clock synchronization module is configured to send a PPS synchronization pulse signal to the second clock synchronization module at each full second timestamp, and send an interrupt signal to the first logic control module; The first logic control module is configured to, after receiving the interrupt signal, receive a first second timestamp sent by the first clock synchronization module, and send the first second timestamp to the second logic control module; The second clock synchronization module is configured to update the second second timestamp of the second clock synchronization module and clear the second nanosecond timestamp of the second clock synchronization module after receiving the PPS synchronization pulse signal; The second logic control module is configured to align the second second timestamp in the second clock synchronization module with the first second timestamp after receiving the first second timestamp, so as to synchronize the second timestamps between the master device and the slave device.
2. The clock synchronization system according to claim 1, wherein: The first clock synchronization module includes: a first timestamp storage unit, a pulse signal output unit and a second timestamp sending unit; The first timestamp register unit includes a first second counting subunit and a first nanosecond counting subunit; The first nanosecond counting subunit is configured to accumulate first nanosecond timestamps according to a first preset step size when receiving a falling edge of a clock signal, and to clear the accumulated result of the first nanosecond timestamps to zero when the accumulated result reaches a preset nanosecond timestamp; The first second counting subunit is configured to accumulate first second timestamps after the accumulated result of the first nanosecond timestamps reaches the preset nanosecond timestamp; The pulse signal output unit is configured to generate the PPS synchronization pulse signal after the first second timestamp of the first second counting subunit is accumulated by 1, and send the PPS synchronization pulse signal to the second clock synchronization module; The timestamp sending unit is configured to send the generated interrupt signal and the first second timestamp after the first second timestamp is added by 1 to the first logic control module after the first second timestamp of the first second counting subunit is added by 1.
3. The clock synchronization system according to claim 2, wherein: The main device is also provided with a first crystal oscillator module; The first crystal oscillator module is communicatively connected to the first clock synchronization module; The first crystal oscillator module is used to send a clock signal to the first nanosecond counting subunit at a preset frequency, so that the first nanosecond counting subunit accumulates the first nanosecond timestamp according to the first preset step size when receiving the falling edge of the clock signal.
4. The clock synchronization system according to claim 1, wherein: The second clock synchronization module includes: a second timestamp register unit, a pulse signal receiving unit; The second timestamp register unit includes a second second counting subunit and a second nanosecond counting subunit; The pulse signal receiving unit is used to receive the PPS synchronization pulse signal and collect the falling edge of the PPS synchronization pulse signal; The second second counting subunit is used to accumulate the second second timestamp when the pulse signal receiving unit collects the falling edge of the PPS synchronization pulse signal; The second nanosecond counting subunit is used to clear the second nanosecond timestamp when the pulse signal receiving unit collects the falling edge of the PPS synchronization pulse signal, and accumulate the second nanosecond timestamp according to the second preset step size under the drive of the second crystal oscillator module built into the second clock synchronization module.
5. The clock synchronization system according to claim 4, characterized in that: The second clock synchronization module further includes: a timestamp calibration module; The timestamp calibration module is used to record the second nanosecond timestamps corresponding to multiple continuous PPS synchronization pulse signals, calculate the average value of multiple second nanosecond timestamps to estimate the actual frequency of the second crystal oscillator module, and calibrate the second preset step size according to the actual frequency of the second crystal oscillator module.
6. The clock synchronization system according to claim 1, wherein: The system further includes a host computer, which is communicatively connected to the first logic control module and the second logic control module respectively; The host computer is provided with an Ethernet synchronization communication protocol module, which is used to broadcast the first second timestamp sent by the first logic control module via Ethernet after monitoring the first second timestamp sent by the first logic control module, so that the second logic control module can calibrate the second second timestamp.
7. The clock synchronization system according to claim 1, wherein: There are multiple slave devices, and the system further includes: a multi-channel clock fan-out module; The input end of the multi-channel clock fan-out module is communicatively connected to the output end of the first clock synchronization module of the master device, and the output end of the multi-channel clock fan-out module is communicatively connected to the input end of the second clock synchronization module of each of the slave devices; The multi-channel clock fan-out module is used to transmit the PPS synchronization pulse signal sent by the first clock synchronization module to the second clock synchronization module of each of the slave devices with the same delay.
8. A clock synchronization method, characterized in that: The method is applied to the clock synchronization system according to any one of claims 1 to 7, and the method includes: The first clock synchronization module of the master device sends a PPS synchronization pulse signal to the second clock synchronization module of the slave device at each full second timestamp, and sends an interrupt signal to the first logic control module of the master device; After receiving the interrupt signal, the first logic control module receives the first second timestamp output by the first clock synchronization module, and sends the first second timestamp to the second logic control module of the slave device; The second clock synchronization module of the slave device updates its internal second second timestamp after receiving the PPS synchronization pulse signal; After receiving the first second timestamp, the second logic control module of the slave device aligns the second second timestamp with the first second timestamp to achieve second timestamp synchronization between the master device and the slave device.
9. An electronic device, characterized in that: The method comprises a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the steps of the clock synchronization method according to claim 8.
10. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by the processor, the steps of the clock synchronization method according to claim 8 are implemented.