Multistage timing synchronization method, receiving device, electronic equipment, storage medium and chip

Abstract

The invention provides a multistage timing synchronization method, a receiving device, electronic equipment, a storage medium and a chip, and the communication method comprises the steps: determining an initial timing synchronization point according to a received synchronization signal; n channel estimation results are obtained according to the received pilot signals, an ith-level synchronization deviation adjustment value is determined according to the ith channel estimation result in the N channel estimation results, i = 1,..., N, and N is larger than or equal to 1; and adjusting the initial timing synchronization point according to the synchronization deviation adjustment values of all levels to obtain a target timing synchronization point. According to the invention, the accuracy of timing synchronization can be improved, the orthogonality of OFDM subcarriers is ensured, and the communication performance of an OFDM system is enhanced.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a multi-level timing synchronization method, a receiving device, an electronic device, a storage medium and a chip. Background Art

[0002] OFDM (Orthogonal Frequency Division Multiplexing) has technical advantages such as high spectrum resource utilization, strong bandwidth scalability, strong resistance to multipath fading, and flexible spectrum resource allocation. It is an efficient transmission method in wireless communications. OFDM symbols are composed of subcarriers in the frequency domain, and the number of subcarriers determines the number of points in the FFT (Fast Fourier Transformation). Generally, subcarriers are divided into data subcarriers, pilot subcarriers, and null subcarriers. Among them, data subcarriers are used for data transmission; pilot subcarriers are used to eliminate residual phase differences, frequency offset estimation, and channel estimation; null subcarriers are subcarriers that do not send any data and are introduced to reduce interference to adjacent frequency bands.

[0003] While OFDM offers numerous advantages, it places stricter requirements on time synchronization to ensure orthogonality between subcarriers. In OFDM systems, the receiver must detect the start of the OFDM symbol, i.e., the starting point of the FFT window, in order to perform the FFT. Inaccurate time synchronization, such as when the FFT window starting point is too far in advance or too far in advance, will cause symbol timing offset (STO), which can introduce inter-carrier interference (ICI) and inter-symbol interference (ISI), ultimately degrading OFDM system communication quality.

[0004] Inserting a cyclic prefix (CP) into OFDM symbols can, to a certain extent, reduce their sensitivity to STO. Typically, areas where inter-subcarrier interference (ISI) and inter-symbol interference (ISI) are not introduced are called ISI-free regions. For AWGN (Additive White Gaussian Noise) channels, if the FFT window starting point falls within the CP, neither ISI nor ISI is introduced. For fading channels, the ISI-free region is the remaining area after the CP removes multipath.

[0005] For OFDM systems, timing synchronization is mostly based on the strong correlation of preamble signals, such as the Short Training Field (STF) and the Long Training Field (LTF), where STF contains a short training sequence and LTF contains a long training sequence, such as Figure 1 The frame format structure shown in FIG can use the cross-correlation or autocorrelation algorithm to find the maximum energy position as the starting point of the OFDM symbol. However, this implementation method has certain defects: for multipath fading channels, the energy of the first path is not necessarily the path with the strongest energy. Figure 2 As shown, the timing synchronization point obtained using this method will cause the FFT window starting point to be delayed. Furthermore, this implementation may only utilize a portion of the bandwidth and training sequence information, especially in multi-user reception scenarios, resulting in inaccurate timing results. If the channel or CP length corresponding to subsequent OFDM symbols changes, the timing estimated based on the training sequence will also be suboptimal. Summary of the Invention

[0006] In response to the above-mentioned deficiencies in the prior art, the present invention provides a multi-level timing synchronization method, a receiving device, an electronic device, a storage medium and a chip to improve the accuracy of timing synchronization, ensure the orthogonality of OFDM subcarriers, and thereby enhance the communication performance of the OFDM system.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] A first aspect of the present invention provides a multi-level timing synchronization method, comprising:

[0009] Determine the initial timing synchronization point based on the received synchronization signal;

[0010] Obtaining N channel estimation results according to the received pilot signal, and determining an i-th level synchronization deviation adjustment value according to an i-th channel estimation result among the N channel estimation results, where i=1, ..., N, and N≥1;

[0011] The initial timing synchronization point is adjusted according to the synchronization deviation adjustment values of each level to obtain the target timing synchronization point.

[0012] Furthermore, the synchronization signal is a preamble signal;

[0013] The step of determining an initial timing synchronization point according to the received synchronization signal includes:

[0014] Based on the synchronization signal, the initial timing synchronization point is determined by adopting a delayed autocorrelation algorithm, a cross-correlation algorithm, or an algorithm combining cross-correlation and autocorrelation.

[0015] Furthermore, the pilot signal comes from a preamble signal, a signal symbol and / or a data symbol.

[0016] Furthermore, the preamble signal is at least one of L-STF, L-LTF, HE-STF, HE-LTF, VHT-STF, VHT-LTF, HT-STF, HT-LTF, EHT-STF, EHT-LTF, UHR-STF, UHR-LTF, ELR-STF, and ELR-LTF;

[0017] The signal symbol is at least one of L-SIG, RL-SIG, VHT-SIGA, VHT-SIGB, HE-SIGA, HE-SIGB, HT-SIG, U-SIG, EHT-SIG, UHR-SIG, ELR-MARK, and ELR-SIG;

[0018] The data symbol is at least one of L-DATA, HT-DATA, VHT-DATA, HE-DATA, EHT-DATA, UHR-DATA, and ELR-DATA.

[0019] Furthermore, the pilot signal includes a midamble signal.

[0020] Furthermore, the channel estimation result is at least one of PDP, group delay, delay spread, CIR, and CFR.

[0021] Further, determining the i-th level synchronization deviation adjustment value according to the i-th channel estimation result among the N channel estimation results includes:

[0022] According to the i-th channel estimation result, the time point corresponding to the maximum SINR, SIR or SNR is obtained to obtain the i-th level synchronization deviation adjustment value.

[0023] Furthermore, the adjusting the initial timing synchronization point according to the synchronization deviation adjustment values of each level to obtain the target timing synchronization point includes:

[0024] The synchronization deviation adjustment values of each level are added to the initial timing synchronization point to obtain the target timing synchronization point.

[0025] A second aspect of the present invention provides a receiving device, comprising:

[0026] A coarse synchronization module, configured to determine an initial timing synchronization point based on a received synchronization signal;

[0027] A fine synchronization module is used to obtain N channel estimation results based on the received pilot signal, and determine the i-th level synchronization deviation adjustment value based on the i-th channel estimation result among the N channel estimation results, where i = 1, ..., N, N ≥ 1, and then adjust the initial timing synchronization point according to the synchronization deviation adjustment values of each level to obtain the target timing synchronization point.

[0028] A third aspect of the present invention provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the multi-level timing synchronization method as described above when executing the computer program.

[0029] A fourth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the steps of the multi-level timing synchronization method as described above are implemented.

[0030] A fifth aspect of the present invention provides a chip comprising a memory, a processor, and a computer program stored in the memory and capable of running on the processor, wherein the processor implements the steps of the multi-level timing synchronization method as described above when executing the computer program.

[0031] By adopting the above technical solution, the present invention has the following beneficial effects:

[0032] The present invention first determines an initial timing synchronization point based on a received synchronization signal; then, based on a received pilot signal, obtains N channel estimation results and determines an i-th level synchronization deviation adjustment value based on the i-th channel estimation result of the N channel estimation results; finally, the initial timing synchronization point is adjusted based on the synchronization deviation adjustment values of each level to obtain a target timing synchronization point. This reduces performance losses caused by an inaccurate initial timing synchronization point, improves timing synchronization accuracy, ensures orthogonality of OFDM subcarriers, and thus enhances the transmission performance of the OFDM system. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagram of the frame format of a conventional preamble signal;

[0034] Figure 2 Schematic diagram of the power delay spectrum of the multipath channel;

[0035] Figure 3 Flowchart of the multi-stage timing synchronization method in Example 1 of the present invention;

[0036] Figure 4A This is a schematic diagram of the frame format corresponding to the Non-HT signal received in Example 1 of the present invention;

[0037] Figure 4B This is a schematic diagram of the frame format corresponding to the HT signal received in Example 1 of the present invention;

[0038] Figure 4C This is a schematic diagram of the frame format corresponding to the VHT signal received in accordance with embodiment 1 of the present invention;

[0039] Figure 4D This is a schematic diagram of the frame format corresponding to the HE signal received in Example 1 of the present invention;

[0040] Figure 4E This is a schematic diagram of the frame format corresponding to the EHT signal received in Example 1 of the present invention;

[0041] Figure 4F This is a schematic diagram of the frame format corresponding to the UHR signal received in Example 1 of the present invention;

[0042] Figure 4G Schematic diagram of the frame format corresponding to the ELR signal received in Example 1 of the present invention;

[0043] Figure 4H This is a schematic diagram of the frame format corresponding to the HE midamble signal received in Example 1 of the present invention;

[0044] Figure 5 is a schematic block diagram of a receiving device in embodiment 2 of the present invention;

[0045] Figure 6 This is a hardware architecture diagram of the electronic device in Example 3 of the present invention. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0047] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0048] As mentioned earlier, timing synchronization in OFDM systems is often based solely on the strong correlation of pilot signals, using cross-correlation or autocorrelation algorithms to find the location with the highest energy as the starting point of the OFDM symbol. However, in multipath fading channels, multi-user scenarios, or scenarios with fluctuating channels, the timing synchronization position obtained in this way is inaccurate or suboptimal. This approach has little impact on demodulation of low-order modulation schemes, but has a greater impact on high-order modulation schemes.

[0049] In view of this, the present invention provides a multi-level timing synchronization method, a receiving device, an electronic device, a storage medium and a chip.

[0050] Example 1

[0051] This embodiment provides a multi-level timing synchronization method, which is applicable to a receiving device, such as Figure 3 As shown, the method specifically includes the following steps:

[0052] S1, a coarse synchronization step, includes: determining an initial timing synchronization point T0 according to a received synchronization signal.

[0053] In this embodiment, the synchronization signal may be, for example, a preamble signal. As an implementation manner, the preamble signal includes but is not limited to a Legacy-Short Training Field (L-STF) and / or a Legacy-Long Training Field (L-LTF) signal.

[0054] In this embodiment, the specific implementation process of coarse synchronization is as follows: based on the synchronization signal, utilizing the correlation of the synchronization signal itself, such as the correlation of the leading signal L-STF or L-STF, according to the delayed autocorrelation algorithm or the cross-correlation algorithm or the algorithm combining cross-correlation and autocorrelation, the aforementioned initial timing synchronization point T0 is determined based on the maximum energy criterion.

[0055] Among them, since the preamble signal is known to the receiving device, the receiving device can use the known preamble signal to calculate the mutual correlation between the known preamble signal and the received preamble signal to obtain a correlation value used to characterize the size of the correlation between the preamble signal and the received preamble signal.

[0056] S2, a fine synchronization step, specifically includes: S21, obtaining N channel estimation results based on the received pilot signal, and determining the i-th level synchronization deviation adjustment value based on the i-th channel estimation result among the N channel estimation results, where i = 1, ..., N, N ≥ 1; S22, adjusting the initial timing synchronization point according to the synchronization deviation adjustment values of each level to obtain the target timing synchronization point.

[0057] In step S21, the pilot signals used to obtain N channel estimation results can be pilot signals at N time moments, or pilot signals on N time domain resources; the number of pilots can be N or more than N, which is not limited in the present invention.

[0058] In one practicable manner, the pilot signal in step S21 is located in the received preamble signal, signal symbol, and / or data symbol. That is, the pilot signal in step S21 may be one or more pilot signals located in any one type of symbol: the preamble signal, signal symbol, or data symbol; may also be multiple pilot signals located in any two types of symbols; or may also be multiple pilot signals located in all three types of symbols.

[0059] Preferably, the preamble signal includes but is not limited to L-STF, L-LTF, High Efficiency-Short Training Field (HE-STF), High Efficiency-Long Training Field (HE-LTF), Very High Throughput-Short Training Field (VHT-STF), Very High Throughput-Long Training Field (VHT-LTF), High Throughput-Short Training Field (HT-STF), High Throughput-Long Training Field (HT-LTF), Extremely High Throughput-Short Training Field (EHT-STF), Extremely High Throughput-Long Training Field (EHT-LTF), Ultra High Reliability-Short Training Field (Ultra High Reliability-Short Training Field) and Ultra High Reliability-Long Training Field. At least one of the following: Ultra High Reliability-Long Training Field (UHR-STF), Ultra High Reliability-Long Training Field (UHR-LTF), Extended Long Range-Short Training Field (ELR-STF), and Extended Long Range-Long Training Field (ELR-LTF);Signal symbols include but are not limited to Legacy-Signal Field (L-SIG), Repeated Legacy-Signal Field (RL-SIG), Very High Throughput-Signal-A Field (VHT-SIGA), Very High Throughput-Signal-B Field (VHT-SIGB), High Efficiency Signal-A Field (HE-SIGA), High Efficiency Signal-B Field (HE-SIGB), High Throughput-Signal Field (HT-SIG), Universal-Signal Field (U-SIG), Extremely High Throughput-Signal Field (EHT-SIG), Ultra High Reliability Signal Field (UHR-SIG), and Extended Long Range-MARK. At least one of the following: a signal field (ELR-MARK) and an extended long range signal field (ELR-SIG);The data symbols are demodulated or decoded data symbols, including but not limited to at least one of the Legacy-Data Field (L-DATA), High Throughput-Data Field (HT-DATA), Very High Throughput-Data Field (VHT-DATA), High Efficiency-Data Field (HE-DATA), Extremely High Throughput-Data Field (EHT-DATA), Ultra High Reliability-Data Field (UHR-DATA), and Extended Long Range-Data Field (ELR-DATA). ELR may also be referred to as Enhanced Long Range. FIG4 shows the frame formats corresponding to several example received signals.

[0060] In step S21, a preset channel estimation algorithm can be used to obtain the aforementioned channel estimation result, which includes but is not limited to one or more of PDP (Power Delay Profile), group delay, delay spread, CIR (Channel Impulse Response), and CFR (Channel Frequency Response).

[0061] When determining the synchronization deviation adjustment value in step S21, the i-th level synchronization deviation adjustment value T is calculated by obtaining the time point corresponding to the maximum SINR, SIR or SNR according to the i-th channel estimation result. i .

[0062] Among them, SINR is the ratio of signal power to the sum of interference power and noise power, and the formula is: SNR is the ratio of signal power to noise power, and the formula is: SIR is the ratio of signal power to interference power, and the formula is: Where P(n) represents the signal power, I(n) represents the interference power, and σ 2 (n) represents the noise power.

[0063] When the initial timing synchronization point is adjusted in step S22, the synchronization deviation adjustment values of each level are adjusted with respect to the initial timing synchronization point, with positive values indicating an advance and negative values indicating a delay. Specifically, the synchronization deviation adjustment values T i (i=1,…,N) is added to the initial timing synchronization point T0 to obtain the target timing synchronization point T. The specific calculation formula is:

[0064] For example, assuming that two different pilot signals are subsequently received (respectively recorded as the first pilot signal and the second pilot signal, taking the HE frame format as an example, Figure 4D As shown, the first pilot signal is the pilot signal in the preamble signal L-LTF, and the second pilot signal is the pilot signal in the preamble signal HE-LTF), that is, when N=2, the specific process of fine synchronization is as follows:

[0065] First, based on the first pilot signal, a preset channel estimation algorithm is used to obtain the corresponding first channel estimation result, and based on the first channel estimation result, the position corresponding to the maximum SINR or SIR or SNR is obtained based on the SINR or SIR or SNR maximum criterion, and then the first-level synchronization deviation adjustment value T1 is obtained.

[0066] Then, based on the second pilot signal, a preset channel estimation algorithm is used to obtain the corresponding second channel estimation result, and based on the second channel estimation result, the position corresponding to the maximum SINR or SIR or SNR is obtained based on the SINR or SIR or SNR maximum criterion, and then the second-level synchronization deviation adjustment value T2 is obtained.

[0067] Finally, the initial timing synchronization point T0 is adjusted according to the formula T=T0+T1+T2 to obtain the target timing synchronization point T.

[0068] By analogy, when more different pilot signals are received, more channel estimation results can be obtained, and thus more levels of synchronization deviation adjustment values can be obtained to more accurately adjust the initial timing synchronization point.

[0069] This embodiment first determines an initial timing synchronization point based on a received synchronization signal; then, based on a received pilot signal, obtains N channel estimation results and determines an i-th level synchronization deviation adjustment value based on the i-th channel estimation result of the N channel estimation results; finally, the initial timing synchronization point is adjusted based on the synchronization deviation adjustment values of each level to obtain a target timing synchronization point. This reduces performance losses caused by an inaccurate initial timing synchronization point, improves timing synchronization accuracy, ensures orthogonality of OFDM subcarriers, and thus enhances the transmission performance of the OFDM system.

[0070] Preferably, if the OFDM system supports midamble training sequences, the pilot signal in this embodiment includes a midamble signal, such as Figure 4H As shown, the midamble signal is located between data symbols. When the midamble signal is received, the channel estimation result obtained based on the midamble signal can be used to perform timing synchronization correction in the aforementioned fine synchronization step.

[0071] It should be understood that the scope of application of this embodiment is not limited to the Wi-Fi system. Any communication system can use the method of this embodiment as long as there are multi-level pilot signals in the time / frequency domain.

[0072] Example 2

[0073] This embodiment provides a receiving device, such as Figure 5 As shown, the receiving device includes a coarse synchronization module 10 and a fine synchronization module 20 .

[0074] The coarse synchronization module 10 is configured to determine an initial timing synchronization point based on a received synchronization signal. The fine synchronization module 20 is configured to obtain N channel estimation results based on a received pilot signal, and to determine an i-th level synchronization deviation adjustment value based on the i-th channel estimation result of the N channel estimation results, where i = 1, ..., N, and N ≥ 1. The initial timing synchronization point is then adjusted based on the synchronization deviation adjustment values of each level to obtain a target timing synchronization point.

[0075] In one practicable manner, the synchronization signal is a pilot signal;

[0076] The step of determining an initial timing synchronization point according to the received synchronization signal includes:

[0077] Based on the synchronization signal, the initial timing synchronization point is determined by adopting a delayed autocorrelation algorithm, a cross-correlation algorithm, or an algorithm combining cross-correlation and autocorrelation.

[0078] In one implementation, the pilot signal comes from a preamble signal, a signal symbol and / or a data symbol.

[0079] In one implementation, the preamble signal is at least one of L-STF, L-LTF, HE-STF, HE-LTF, VHT-STF, VHT-LTF, HT-STF, HT-LTF, EHT-STF, EHT-LTF, UHR-STF, UHR-LTF, ELR-STF, and ELR-LTF, and may also be a signal or field with other names having similar functions such as synchronization or frame delimiter in a future communication system;

[0080] The signal symbol is at least one of L-SIG, RL-SIG, VHT-SIGA, VHT-SIGB, HE-SIGA, HE-SIGB, HT-SIG, U-SIG, EHT-SIG, UHR-SIG, ELR-MARK, and ELR-SIG, and may also be a signal or field with other names having similar functions to the aforementioned signal symbols in a future communication system;

[0081] The data symbol is at least one of L-DATA, HT-DATA, VHT-DATA, HE-DATA, EHT-DATA, UHR-DATA, and ELR-DATA, and may also be a signal or field with other names having similar functions to the aforementioned data symbols in future communication systems.

[0082] In one implementation, the pilot signal includes a midamble signal.

[0083] In an implementable manner, the channel estimation result is at least one of PDP, group delay, delay spread, CIR, and CFR.

[0084] In one practicable manner, determining the i-th level synchronization deviation adjustment value according to the i-th channel estimation result among the N channel estimation results includes:

[0085] According to the i-th channel estimation result, the time point corresponding to the maximum SINR, SIR or SNR is obtained to obtain the i-th level synchronization deviation adjustment value.

[0086] In one practicable manner, adjusting the initial timing synchronization point according to the synchronization deviation adjustment values of each level to obtain the target timing synchronization point includes:

[0087] The synchronization deviation adjustment values of each level are added to the initial timing synchronization point to obtain the target timing synchronization point.

[0088] In this embodiment, a coarse synchronization module determines an initial timing synchronization point based on a received synchronization signal. A fine synchronization module obtains N channel estimation results based on a received pilot signal, determines an i-th level synchronization deviation adjustment value based on the i-th channel estimation result among the N channel estimation results, and then adjusts the initial timing synchronization point based on the synchronization deviation adjustment values at each level to obtain a target timing synchronization point. This reduces performance losses caused by an inaccurate initial timing synchronization point, improves timing synchronization accuracy, ensures orthogonality of OFDM subcarriers, and enhances the transmission performance of the OFDM system.

[0089] Example 3

[0090] This embodiment provides an electronic device, which can be expressed in the form of a computing device (for example, a server device), including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the steps of the multi-level timing synchronization method provided in Example 1 can be implemented.

[0091] Figure 6 The hardware structure diagram of this embodiment is shown in FIG. Figure 6 As shown, the electronic device 30 specifically includes:

[0092] At least one processor 31, at least one memory 32, and a bus 33 for connecting different system components (including the processor 31 and the memory 32), wherein:

[0093] The bus 33 includes a data bus, an address bus, and a control bus.

[0094] The memory 32 includes a volatile memory, such as a random access memory (RAM) 321 and / or a cache memory 322 , and may further include a read-only memory (ROM) 323 .

[0095] The memory 32 also includes a program / utility 325 having a set (at least one) of program modules 324, such program modules 324 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0096] The processor 31 executes various functional applications and data processing by running the computer program stored in the memory 32, such as the steps of the multi-level timing synchronization method provided in Example 1 of the present invention.

[0097] The electronic device 30 can further communicate with one or more external devices 34 (e.g., a keyboard, pointing device, etc.). Such communication can occur via an input / output (I / O) interface 35. Furthermore, the electronic device 30 can communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 36. The network adapter 36 communicates with other modules of the electronic device 30 via a bus 33. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with the electronic device 30, including but not limited to microcode, device drivers, redundant processors, external disk drive arrays, RAID (RAID) systems, tape drives, and data backup storage systems.

[0098] It should be noted that although several units / modules or sub-units / modules of the electronic device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, depending on the embodiment of the present application, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided and embodied by multiple units / modules.

[0099] Example 4

[0100] This embodiment provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the steps of the multi-level timing synchronization method provided in Embodiment 1 are implemented.

[0101] The readable storage medium may include, but is not limited to, a portable disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0102] In a possible implementation manner, the present invention may also be implemented in the form of a program product, which includes program code. When the program product runs on a terminal device, the program code is used to enable the terminal device to execute the steps of the multi-level timing synchronization method provided in Example 1.

[0103] The program code for executing the present invention may be written in any combination of one or more programming languages, and may be executed entirely on the user device, partially on the user device, as a standalone software package, partially on the user device and partially on a remote device, or entirely on the remote device.

[0104] Example 5

[0105] This embodiment provides a chip, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the multi-level timing synchronization method provided in Embodiment 1 are implemented.

[0106] Although specific embodiments of the present invention have been described above, those skilled in the art will appreciate that these are merely illustrative and that the scope of the present invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, and such changes and modifications are intended to fall within the scope of the present invention.

Claims

1. A multi-level timing synchronization method, characterized in that: include: Determine the initial timing synchronization point based on the received synchronization signal; Obtaining N channel estimation results according to the received pilot signal, and determining an i-th level synchronization deviation adjustment value according to an i-th channel estimation result among the N channel estimation results, where i=1, ..., N, and N≥1; The initial timing synchronization point is adjusted according to the synchronization deviation adjustment values of each level to obtain the target timing synchronization point.

2. The multi-stage timing synchronization method according to claim 1, wherein: The synchronization signal is a leading signal; The step of determining an initial timing synchronization point according to the received synchronization signal includes: Based on the synchronization signal, the initial timing synchronization point is determined by adopting a delayed autocorrelation algorithm, a cross-correlation algorithm, or an algorithm combining cross-correlation and autocorrelation.

3. The multi-stage timing synchronization method according to claim 1, wherein: The pilot signal comes from a preamble signal, a signal symbol and / or a data symbol.

4. The multi-stage timing synchronization method according to claim 3, wherein: The preamble signal is at least one of L-STF, L-LTF, HE-STF, HE-LTF, VHT-STF, VHT-LTF, HT-STF, HT-LTF, EHT-STF, EHT-LTF, UHR-STF, UHR-LTF, ELR-STF, and ELR-LTF; The signal symbol is at least one of L-SIG, RL-SIG, VHT-SIGA, VHT-SIGB, HE-SIGA, HE-SIGB, HT-SIG, U-SIG, EHT-SIG, UHR-SIG, ELR-MARK, and ELR-SIG; The data symbol is at least one of L-DATA, HT-DATA, VHT-DATA, HE-DATA, EHT-DATA, UHR-DATA, and ELR-DATA.

5. The multi-stage timing synchronization method according to claim 1, wherein: The pilot signal includes a midamble signal.

6. The multi-stage timing synchronization method according to claim 1, wherein: The channel estimation result is at least one of PDP, group delay, delay spread, CIR, and CFR.

7. The multi-stage timing synchronization method according to claim 1, wherein: The determining the i-th level synchronization deviation adjustment value according to the i-th channel estimation result among the N channel estimation results includes: According to the i-th channel estimation result, the time point corresponding to the maximum SINR, SIR or SNR is obtained to obtain the i-th level synchronization deviation adjustment value.

8. The multi-stage timing synchronization method according to claim 1, wherein: The adjusting the initial timing synchronization point according to the synchronization deviation adjustment values of each level to obtain the target timing synchronization point includes: The synchronization deviation adjustment values of each level are added to the initial timing synchronization point to obtain the target timing synchronization point.

9. A receiving device, characterized in that: include: A coarse synchronization module, configured to determine an initial timing synchronization point based on a received synchronization signal; A fine synchronization module is used to obtain N channel estimation results based on the received pilot signal, and determine the i-th level synchronization deviation adjustment value based on the i-th channel estimation result among the N channel estimation results, where i = 1, ..., N, N ≥ 1, and then adjust the initial timing synchronization point according to the synchronization deviation adjustment values of each level to obtain the target timing synchronization point.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and capable of running on the processor, characterized in that: When the processor executes the computer program, the steps of the multi-level timing synchronization method according to any one of claims 1 to 8 are implemented.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the multi-level timing synchronization method according to any one of claims 1 to 8 are implemented.

12. A chip, characterized in that: The method comprises a memory, a processor, and a computer program stored in the memory and capable of running on the processor, wherein when the processor executes the computer program, the steps of the multi-level timing synchronization method according to any one of claims 1 to 8 are implemented.

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