Data processing method and device, electronic equipment, storage medium and program product

Abstract

The invention provides a data processing method and device, electronic equipment, a storage medium and a program product. The method comprises the steps that a first data packet is sent to an input queue; determining whether the first data packet satisfies a second condition; in response to the first data packet satisfying the second condition, determining whether the first data packet satisfies a third condition; sending the first data packet to the credit loss queue in response to the fact that the first data packet does not meet the third condition and the credit loss queue meets the first condition; determining whether the first data packet satisfies a fourth condition; sending the first data packet to a first output queue based on the crossbar switch in response to that the first data packet satisfies a fourth condition and satisfies a third condition; thus, under the condition that the first data packet does not meet the third condition, the first data packet is sent to the credit loss queue, subsequent transmission of the second data packet is not affected, and the overall throughput and the response speed of the system are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a data processing method, device, electronic device, storage medium, and program product. Background Art

[0002] In modern digital systems, crossbar switch technology is widely used in various fields. For example, in high-performance computer networks, crossbar switches enable high-speed data exchange between nodes; in data center switches, they manage data transmission between large numbers of servers; and in on-chip networks, crossbar switches handle data flow between different processing units within multi-core processors. Furthermore, in communications systems, crossbar switches are used to efficiently route data packets.

[0003] The crossbar switch uses a credit mechanism for flow control. If the data packets at the front end of the input queue lack credit points, they cannot be sent, which will hinder the normal sending of the data packets at the back end of the input queue, affecting the overall throughput and response speed of the system. Summary of the Invention

[0004] The present disclosure provides a data processing method, device, electronic device, storage medium and program product to at least solve the above technical problems existing in the prior art.

[0005] According to a first aspect of the present disclosure, there is provided a data processing method, comprising:

[0006] Determining whether the input queue corresponding to the first data packet meets a first condition;

[0007] In response to the input queue satisfying the first condition, sending the first data packet to the input queue;

[0008] determining whether the first data packet satisfies a second condition;

[0009] In response to the first data packet satisfying the second condition, determining whether the first data packet satisfies a third condition;

[0010] In response to the first data packet not satisfying a third condition and the credit missing queue satisfying the first condition, sending the first data packet to the credit missing queue;

[0011] determining whether the first data packet satisfies a fourth condition;

[0012] In response to the first data packet satisfying the fourth condition and the third condition, the first data packet is sent to the first output queue based on the crossbar switch.

[0013] In the above solution, after sending the first data packet to the credit loss queue, the method further includes:

[0014] confirming whether the second data packet satisfies the third condition;

[0015] In response to the second data packet satisfying the third condition, sending the second data packet to the second output queue based on the crossbar switch;

[0016] Alternatively, in response to the second output queue not satisfying the third condition, sending the second data packet to the credit missing queue;

[0017] The second data packet is a data packet adjacent to the first data packet and subsequent to the first data packet.

[0018] In the above solution, the method further includes:

[0019] In response to the input queue not satisfying the first condition, repeatedly determining whether the input queue corresponding to the first data packet satisfies the first condition;

[0020] In response to the input queue meeting the first condition, the first data packet is sent to the input queue.

[0021] In the above solution, the method further includes:

[0022] In response to the first data packet not satisfying the second condition, repeatedly determining whether the first data packet satisfies the second condition;

[0023] In response to the first data packet satisfying the second condition, it is confirmed whether the first data packet satisfies a third condition.

[0024] In the above solution, the method further includes:

[0025] In response to the first data packet not satisfying a third condition and the credit-deficient queue not satisfying the first condition, determining whether the first data packet satisfies the third condition or whether the credit-deficient queue satisfies the first condition;

[0026] In response to the first data packet satisfying a third condition, sending the first data packet to the first output queue based on the crossbar switch;

[0027] Alternatively, in response to the first data packet not satisfying the third condition but the credit missing queue satisfying the first condition, the first data packet is sent to the credit missing queue.

[0028] In the above solution, the first condition includes that the queue is not full, and determining whether the input queue corresponding to the first data packet meets the first condition includes:

[0029] Determining whether an input queue of a first host corresponding to sending the first data packet is not full;

[0030] The input queue meeting the first condition includes that the input queue can receive the first data packet; the input queue not meeting the first condition includes that the input queue is full and cannot receive the first data packet.

[0031] In the above solution, the input queue is a first-in-first-out queue, and the second condition includes that the first data packet is the first data packet in the input queue.

[0032] In the above solution, the third condition includes that the credit points of the queue of the input port where the first data packet is located is not zero, and / or the credit points of the first output queue is not zero.

[0033] In the above solution, the credit-deficient queue is a first-in-first-out queue, and the fourth condition includes that the first data packet is the first data packet in the credit-deficient queue.

[0034] In the above solution, the credit loss queue and the input queue are queues corresponding to input ports of the crossbar switch, and are connected to output ports corresponding to the first output queue through the crossbar switch.

[0035] In the above solution, the credit loss queue and the input queue are arbitrated, and if the corresponding input queue meets the third condition, the data packet is transmitted to the corresponding output queue through the crossbar switch.

[0036] In the above solution, before sending the first data packet to the credit loss queue, the method further includes:

[0037] A host identifier of a host that sends the first data packet is added to the first data packet.

[0038] In the above solution, sending the first data packet to the first output queue based on the crossbar switch includes:

[0039] Determine the master credit points and the slave credit points based on the master identifier and the slave identifier included in the first data packet;

[0040] In response to the master credits and the slave credits satisfying a fifth condition, the first data packet is sent to a first output queue corresponding to the slave based on the crossbar switch.

[0041] In the above solution, after the crossbar switch sends the first data packet to the first output queue corresponding to the slave, the method further includes:

[0042] Updating the credit points of the host corresponding to the first data packet;

[0043] Update the credit points of the slave device corresponding to the first data packet.

[0044] According to a second aspect of the present disclosure, there is provided a data processing device, the device comprising:

[0045] an input queue determining unit, configured to determine whether an input queue corresponding to the first data packet satisfies a first condition;

[0046] a first sending unit, configured to send the first data packet to the input queue in response to the input queue satisfying the first condition;

[0047] a first position determining unit, configured to determine whether the first data packet satisfies a second condition;

[0048] a first credit point determination unit, configured to, in response to the first data packet satisfying the second condition, determine whether the first data packet satisfies a third condition;

[0049] a second sending unit, configured to send the first data packet to the credit missing queue in response to the first data packet not satisfying the third condition and the credit missing queue satisfying the first condition;

[0050] a second position determining unit, configured to determine whether the first data packet satisfies a fourth condition;

[0051] The third sending unit is configured to send the first data packet to the first output queue based on the crossbar switch in response to the first data packet satisfying the fourth condition and the third condition.

[0052] In the above solution, the first credit point unit is further used to confirm whether the second data packet meets the third condition;

[0053] The second sending unit is further configured to send the second data packet to the second output queue based on the crossbar switch in response to the second data packet satisfying the third condition;

[0054] Alternatively, the second sending unit is further configured to send the second data packet to the credit loss queue in response to the second output queue not satisfying the third condition;

[0055] The second data packet is a data packet adjacent to the first data packet and subsequent to the first data packet.

[0056] In the above solution, the input queue determination unit is further configured to: in response to the input queue not satisfying the first condition, repeatedly determine whether the input queue corresponding to the first data packet satisfies the first condition;

[0057] The first sending unit is further configured to send the first data packet to the input queue in response to the input queue satisfying the first condition.

[0058] According to a third aspect of the present disclosure, there is provided an electronic device, including:

[0059] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the present disclosure.

[0060] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause the computer to execute the method described in the present disclosure.

[0061] According to a fifth aspect of the present disclosure, a computer program product is provided, comprising a computer program, wherein the computer program implements the method described in the present disclosure when executed by a processor.

[0062] The data processing method disclosed herein determines whether the input queue corresponding to a first data packet satisfies a first condition; in response to the input queue satisfying the first condition, the first data packet is sent to the input queue; determines whether the first data packet satisfies a second condition; in response to the first data packet satisfying the second condition, the first data packet is confirmed to satisfy a third condition; in response to the first data packet not satisfying the third condition and the credit loss queue satisfying the first condition, the first data packet is sent to the credit loss queue; determines whether the first data packet satisfies a fourth condition; in response to the first data packet satisfying the fourth condition and the third condition, the first data packet is sent to the first output queue based on a crossbar switch. In this way, if the first data packet does not satisfy the third condition, the first data packet is sent to the credit loss queue without affecting the subsequent transmission of the second data packet, thereby improving the overall throughput and response speed of the system.

[0063] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings, in which several embodiments of the present disclosure are shown by way of example and not limitation, wherein:

[0065] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[0066] Figure 1 shows a schematic diagram of a crossbar switch in the related art;

[0067] Figure 2 A first optional flow chart of the data processing method provided by an embodiment of the present disclosure is shown;

[0068] Figure 3 A second optional flow chart of the data processing method provided by the embodiment of the present disclosure is shown;

[0069] Figure 4 A third optional flow chart of the data processing method provided by the embodiment of the present disclosure is shown;

[0070] Figure 5 A fourth optional flow chart of the data processing method provided by an embodiment of the present disclosure is shown;

[0071] Figure 6 A fifth optional flow chart of the data processing method provided in an embodiment of the present disclosure is shown;

[0072] Figure 7 A schematic diagram of a crossbar switch provided by an embodiment of the present disclosure is shown;

[0073] Figure 8 An optional structural diagram of a data processing device provided by an embodiment of the present disclosure is shown;

[0074] Figure 9 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0075] To make the purposes, features, and advantages of the present disclosure more apparent and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative work shall fall within the scope of protection of the present disclosure.

[0076] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0077] In the following description, the terms "first\second" are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first\second" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0078] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by those skilled in the art in the art of this disclosure. The terms used in this disclosure are only for the purpose of describing the embodiments of this disclosure and are not intended to limit this disclosure.

[0079] It should be understood that in the various embodiments of the present disclosure, the size of the serial number of each implementation process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.

[0080] Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are explained. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations.

[0081] 1) Cross-switch technology.

[0082] A key technology used in digital circuits and communication systems to connect multiple input and output ports, aiming to achieve flexible and efficient data exchange and routing. By providing a direct connection between each input and each output, a crossbar switch fundamentally avoids the conflicts and bottlenecks caused by shared communication paths. Specifically, a crossbar switch is usually implemented as a two-dimensional switch matrix (i.e., a crossbar matrix), where the rows of the matrix represent input ports and the columns represent output ports, with each intersection having a switch that can be turned on or off. Data from the input port can be directly connected to any output port through these switches, achieving a point-to-point connection. The core of this structure lies in its control logic, which is responsible for managing the status of all switches and dynamically adjusting the connection relationship between inputs and outputs as needed. This control can be based on preset routing rules or dynamically adjusted according to real-time communication needs.

[0083] 2) Input port.

[0084] The input port is the entrance of the crossbar matrix and is responsible for receiving data packets from external devices (such as hosts, network nodes or other switches).

[0085] 3) Output port.

[0086] The output port is the end point of data packet transmission and is responsible for sending data packets from the crossbar matrix to external devices.

[0087] 4) Input queue.

[0088] The input queue is part of an input port and temporarily stores packets received from the input port. This involves buffering packets until they are scheduled for transmission to the output port. It supports flow control and scheduling algorithms (such as credit-based flow control and round-robin scheduling) to prevent packet loss or congestion.

[0089] 5) Output queue.

[0090] The output queue is part of the output port and includes single queue and multiple queues. It is used to buffer and schedule data packets to ensure that they can be transmitted to external devices in sequence and efficiently.

[0091] Crossbar switch technology offers several advantages in practical applications. First, it provides very high bandwidth. Due to the direct connection between inputs and outputs, multiple data streams can be transmitted simultaneously through the crossbar switch without conflict, significantly improving the system's parallel processing capabilities. Second, crossbar switches can significantly reduce data transmission latency. In traditional bus architectures, data must pass through multiple intermediate nodes before reaching its destination, which not only increases transmission time but also the probability of errors. In a crossbar switch, input data can directly reach the target output port, eliminating intermediate links and thus reducing latency. Furthermore, the crossbar switch's structure is highly flexible, allowing the connection between inputs and outputs to be dynamically changed at runtime. This allows the system to flexibly adjust data flow based on actual needs, making it particularly suitable for complex systems that process multiple different types of data streams. Finally, crossbar switches offer excellent scalability. As system requirements increase, the crossbar switch's scale can be expanded by adding more input and output ports without significantly impacting the existing system architecture. This scalability makes crossbar switches particularly suitable for applications that require continuous expansion and upgrades.

[0092] In modern digital systems, crossbar switches are widely used in a variety of fields. For example, in high-performance computer networks, crossbar switches enable high-speed data exchange between nodes; in data center switches, they manage data transmission between large numbers of servers; and in on-chip networks, crossbar switches handle data flow between different processing units within multi-core processors. Furthermore, in communications systems, crossbar switches are used to efficiently route data packets, thereby improving the overall throughput and responsiveness of the communication system.

[0093] Figure 1 FIG. 1 is a schematic diagram of a crossbar switch in the related art.

[0094] like Figure 1As shown in the figure, modern crossbar switch (XBAR) technology consists of three components: an input queue (typically a First-In First-Out (FIFO) queue), a crossbar matrix, and an arbiter. The input queue temporarily stores and sorts data from each input port, ensuring orderly data transmission. The crossbar matrix is the core of the system. Through switches within the matrix, it enables direct connections between any input port and any output port, providing flexible and efficient data routing. The arbiter is responsible for resolving conflicts when multiple input ports simultaneously request the same output port, ensuring good system performance and low latency even under high concurrency conditions. These three components work together to achieve efficient data exchange in complex systems. The entire crossbar switch is flow controlled by a credit mechanism.

[0095] Modern crossbar switches use a credit mechanism for flow control. If the data packet at the front end of the input queue cannot be successfully sent due to lack of credit, it will hinder the normal transmission of data packets at the back end of the queue, affecting the overall throughput and response speed of the system.

[0096] In view of the defects existing in the related technologies, the embodiments of the present disclosure provide a data processing method to solve some or all of the above technical problems.

[0097] Figure 2 A first optional flow chart of the data processing method provided by an embodiment of the present disclosure is shown, and will be explained according to each step.

[0098] Step S201: Determine whether the input queue corresponding to the first data packet meets a first condition.

[0099] In some embodiments, the first data packet includes a data packet that the host needs to send to the slave; the host sends the data packet to the slave based on a cross switch mechanism; when sending, the host first caches the data packet in the input queue corresponding to the host in the input port. The input queue includes data packets from the same host. The input port corresponds to at least one input queue, and each input queue corresponds to a row of the cross matrix; each input queue corresponds to one or more hosts, that is, each input queue stores data packets from one host, or each input queue stores data packets from multiple hosts. In the embodiment of the present disclosure, multiple refers to two or more. The data packets stored in the input queues correspond to different slaves.

[0100] Correspondingly, the cross matrix corresponds to an output port, the output port corresponds to at least one output queue, and each output queue corresponds to a column of the cross matrix; each output queue corresponds to a slave, that is, each output queue stores data packets to be sent to the same slave.

[0101] In some embodiments, the first condition includes being not full, i.e., able to receive and / or store data packets; the input queue meeting the first condition includes being not full and able to receive and / or store data packets; the input queue not meeting the first condition includes being full and unable to receive and / or store data packets. The input queue may be a first-in-first-out queue, corresponding to the input queue of the host that sent the first data packet.

[0102] Step S202: In response to the input queue satisfying the first condition, sending the first data packet to the input queue.

[0103] In some embodiments, in response to the input queue being not full and able to receive and / or store data packets, the first data packet is sent to the input queue. After the data packet queued before the first data packet in the input queue is sent through arbitration by an arbitrator, the arbitrator then determines whether it can be sent to a first output queue. The first output queue is the output queue corresponding to the slave device corresponding to the first data packet. That is, the first data packet is a data packet sent from the master to the slave device.

[0104] Step S203: Determine whether the first data packet meets a second condition.

[0105] In some embodiments, the input queue is a first-in-first-out queue, and the second condition includes being the first data packet in the input queue; the first data packet satisfies the second condition including that the first data packet is the first data packet in the input queue, and after arbitration by the arbitrator, the first data packet is sent out first compared to other data packets in the input queue.

[0106] Step S204: In response to the first data packet satisfying the second condition, confirm whether the first data packet satisfies a third condition.

[0107] In some embodiments, in response to the first data packet being the first data packet of an input queue, determining whether the first data packet satisfies a third condition includes that the input queue corresponding to the first data packet has credit points and / or the first output queue corresponding to the first data packet has credit points.

[0108] In some embodiments, the crossbar switch implements flow control based on a credit mechanism, that is, the receiver allocates credit points to the sender, indicating the amount of data that can be received; the sender sends data packets based on the credit points, and the sender's credit points are reduced by 1 each time a data packet is sent; after the receiver processes the data packet, it returns the credit to the sender, and the sender updates the credit points and continues to send data packets.

[0109] Step S205 : In response to the first data packet not satisfying the third condition and the credit-deficient queue satisfying the first condition, the first data packet is sent to the credit-deficient queue.

[0110] In some embodiments, in response to the input queue corresponding to the first data packet having no credit points and / or the first output queue corresponding to the first data packet having no credit points, that is, the first data packet cannot be sent currently, and the credit missing queue is not full, the first data packet is sent to the credit missing queue.

[0111] The credit-deficient queue and the input queue are queues corresponding to input ports of the crossbar switch and are connected to output ports corresponding to the first output queue via the crossbar switch. The credit-deficient queue is a first-in, first-out queue. When the arbitrator arbitrates the queues corresponding to the input ports, the credit-deficient queue and the input queue participate in the arbitration together. The arbitration may include algorithms such as round-robin and priority scheduling.

[0112] Step S206: Determine whether the first data packet meets a fourth condition.

[0113] In some embodiments, the fourth condition includes being the first data packet in a credit missing queue; the first data packet satisfies the fourth condition, including that the first data packet is the first data packet in the credit missing queue, and after arbitration by the arbitrator, the first data packet is sent first compared to other data packets in the credit missing queue.

[0114] Step S207 : In response to the first data packet satisfying the fourth condition and the third condition, sending the first data packet to the first output queue based on the crossbar switch.

[0115] In some embodiments, in response to the first data packet being the first data packet of a credit-missing queue, and the credit-missing queue corresponding to the first data packet having credit points and / or the first output queue corresponding to the first data packet having credit points, the first data packet is sent to the first output queue based on the crossbar switch.

[0116] In this way, through the data processing method provided by the embodiment of the present disclosure, when the first data packet cannot be sent due to lack of credit points, the first data packet is sent to the credit missing queue of the input port, so that the data packets in the input queue that are behind the first data packet and have credit points can be sent normally, avoiding congestion and improving the overall throughput and response speed of the system.

[0117] Figure 3 A second optional flow chart of the data processing method provided by an embodiment of the present disclosure is shown, and will be explained according to each step.

[0118] In some embodiments, after sending the first data packet to the credit loss queue at step S205, the method further includes:

[0119] Step S301: confirm whether the second data packet meets the third condition.

[0120] In some embodiments, the second data packet includes a data packet in the input queue that is located after the first data packet. The second data packet may be a data packet adjacent to the first data packet or a data packet not adjacent to the first data packet.

[0121] Step S302: In response to the second data packet satisfying the third condition, the second data packet is sent to the second output queue based on the crossbar switch.

[0122] In some embodiments, if the input queue corresponding to the second data packet has credit points and / or the second output queue has credit points, the second data packet is sent to the second output queue via the crossbar switch; the second output queue is the output queue corresponding to the slave receiving the second data packet. The first output queue and the second output queue can be the same or different.

[0123] Step S303: In response to the second data packet not satisfying the third condition and the credit-deficient queue satisfying the first condition, the second data packet is sent to the credit-deficient queue.

[0124] In some embodiments, in response to the input queue corresponding to the second data packet having no credit points and / or the first output queue corresponding to the first data packet having no credit points, that is, the second data packet cannot be sent currently, and the credit missing queue is not full, the second data packet is sent to the credit missing queue.

[0125] The subsequent processing method for the data packets other than the second data packet in the input queue is the same as steps S301 to S303, and the processing method for the second data packet and the data packets other than the second data packet in the credit loss queue is the same as steps S206 to S207, which will not be repeated here.

[0126] In this way, through the data processing method provided by the embodiment of the present disclosure, when the first data packet cannot be sent due to lack of credit points, the first data packet is sent to the credit missing queue of the input port, so that the data packets in the input queue that are behind the first data packet and have credit points can be sent normally, avoiding congestion and improving the overall throughput and response speed of the system.

[0127] Figure 4 A third optional flow chart of the data processing method provided in an embodiment of the present disclosure is shown, and will be explained according to each step.

[0128] Step S401: Determine whether the input queue corresponding to the first data packet meets a first condition.

[0129] In some embodiments, a first data packet is sent by a corresponding host and is destined for a corresponding slave; the first data packet is transmitted based on a cross matrix; confirm whether the input queue corresponding to the host in the input port of the cross matrix meets a first condition; if the input queue does not meet the first condition, repeatedly determine whether the input queue corresponding to the first data packet meets the first condition, that is, repeat step S401; until step S402 is executed in response to the input queue meeting the first condition.

[0130] In some embodiments, if the input queue meets the first condition, step S402 is executed.

[0131] Step S402: Send the first data packet to the input queue.

[0132] In some embodiments, in response to an input queue satisfying a first condition, i.e., the input queue is not full, the first data packet is sent to the input queue, waits for arbitration by an arbitrator in the input queue, and is transmitted to a first output queue based on a crossbar matrix after arbitration. The first output queue is the output queue corresponding to the slave.

[0133] In some embodiments, the input queue is a first-in-first-out queue, and after the first data packet is sent to the input queue, the first data packet is located at the end of the input queue.

[0134] Step S403: Determine whether the first data packet meets a second condition.

[0135] In some embodiments, the first data packet satisfies a second condition, including that the first data packet is the first data packet in the input queue; in response to the first data packet not satisfying the second condition, step S403 is repeated; until the first data packet satisfies the second condition, step S404 is executed.

[0136] Step S404: confirm whether the first data packet meets the third condition.

[0137] In some embodiments, in response to the first data packet being the first data packet in the input queue, it is confirmed whether the input queue corresponding to the first data packet has credit points and / or whether the first output queue corresponding to the first data packet has credit points.

[0138] Specifically, it is determined whether the input queue has sufficient credits to send the first data packet, and / or it is determined whether the first output queue has sufficient credits to receive the first data packet.

[0139] If the first data packet meets the third condition, it means that the input queue has enough credits to send the first data packet, and the first output queue has enough credits to receive the first data packet, and then step S405 is executed.

[0140] If the first data packet does not meet the third condition, it means that the input queue does not have enough credits to send the first data packet, and / or the first output queue does not have enough credits to receive the first data packet, and then step S406 is executed.

[0141] Step S405: Send the first data packet to the first output queue based on the crossbar switch.

[0142] In some embodiments, the input queue has sufficient credit points to send the first data packet, and the first output queue has sufficient credit points to receive the first data packet, then the arbitrator arbitrates all input queues corresponding to the input ports, and in response to the first data packet passing the arbitration, sends the first data packet to the first output queue through the cross switch.

[0143] In some optional embodiments, after sending the first data packet to the first output queue, the method further includes at least one of the following: updating the credit points of the host corresponding to the first data packet; updating the credit points of the slave corresponding to the first data packet.

[0144] Among them, the credit points of the host may include the credit points of the input queue corresponding to the host, that is, the credit points of the input queue corresponding to the host are updated; the credit points of the slave include the credit points of the output queue corresponding to the slave (the first output queue in this embodiment), that is, the credit points of the first output queue corresponding to the slave are updated.

[0145] Step S406: confirm whether the credit-deficient queue meets the first condition.

[0146] In some embodiments, if the credit loss queue is not full, step S407 is executed; if the credit loss queue is full, steps S404 and S406 are repeatedly executed, that is, repeatedly determining whether the first data packet satisfies the third condition, and repeatedly determining whether the credit loss queue satisfies the first condition; until any condition is met, that is, the first data packet satisfies the third condition or the credit loss queue satisfies the first condition; if the first data packet satisfies the third condition, step S405 is executed; if the credit loss queue satisfies the first condition, step S407 is executed.

[0147] Step S407: Send the first data packet to the credit loss queue.

[0148] In some embodiments, the credit missing queue is a first-in-first-out queue, and after the first data packet is sent to the credit missing queue, the first data packet is located at the end of the credit missing queue.

[0149] In some embodiments, the credit-missing queue is a queue corresponding to an input port. Other input queues corresponding to the input port are connected to output ports, including the first output queue, via the crossbar switch. When the arbitrator arbitrates the input queue corresponding to the input port, it also arbitrates the credit-missing queue. That is, data packets in the credit-missing queue, like data packets in the input queue, can be selected and transmitted by the arbitrator.

[0150] In some optional embodiments, after adding the credit-deficient queue, the cross matrix needs to be adjusted to add a row corresponding to the credit-deficient queue.

[0151] In some optional embodiments, a credit counter may be set for the credit-missing queue and credit points may be allocated.

[0152] In a specific implementation, the credit missing queue is an input queue extended in the input port, and is used to store data packets that cannot be sent due to lack of credit points.

[0153] Step S408: Determine whether the first data packet meets the fourth condition.

[0154] In some embodiments, the fourth condition includes being the first data packet in a credit missing queue; the first data packet satisfies the fourth condition, including that the first data packet is the first data packet in the credit missing queue, and after arbitration by the arbitrator, the first data packet is sent first compared to other data packets in the credit missing queue.

[0155] If the first data packet meets the fourth condition, step S409 is executed; if the first data packet does not meet the fourth condition, step S408 is repeated until the first data packet meets the fourth condition.

[0156] Step S409: Determine whether the first data packet meets the third condition.

[0157] In some embodiments, it is determined whether the credit-deficient queue has sufficient credits to send the first data packet, and / or it is determined whether the first output queue has sufficient credits to receive the first data packet.

[0158] If the first data packet meets the third condition, it means that the credit-deficient queue has enough credits to send the first data packet, and the first output queue has enough credits to receive the first data packet, and then step S410 is executed.

[0159] If the first data packet does not meet the third condition, it means that the credit deficiency queue does not have enough credit points to send the first data packet, and / or the first output queue does not have enough credit points to receive the first data packet, and step S409 is repeated until the first data packet meets the third condition, and step S410 is executed.

[0160] Step S410: Send the first data packet to the first output queue based on the crossbar switch.

[0161] In some embodiments, the credit-deficient queue has sufficient credits to send the first data packet, and the first output queue has sufficient credits to receive the first data packet, then the arbitrator arbitrates all input queues corresponding to the input ports, and in response to the first data packet passing the arbitration, sends the first data packet to the first output queue through the cross switch.

[0162] In some optional embodiments, after sending the first data packet to the first output queue, the method further includes at least one of the following: updating the credit points of the host corresponding to the first data packet; updating the credit points of the slave corresponding to the first data packet.

[0163] Among them, the credit points of the host may include the credit points of the input queue corresponding to the host, that is, updating the credit points of the credit missing queue corresponding to the host; the credit points of the slave include the credit points of the output queue corresponding to the slave (the first output queue in this embodiment), that is, updating the credit points of the first output queue corresponding to the slave.

[0164] In this way, through the data processing method provided by the embodiment of the present disclosure, by introducing a credit loss queue, the system can effectively manage data packets when credit is insufficient, transfer them from the regular input queue to the credit loss queue for processing, reduce data packet retention, and improve system efficiency; the credit loss queue and the regular input queue participate in the data exchange of the cross matrix together, even when the credit of the leading data packet is insufficient, the system can continue to process and transmit the subsequent data packets with credit, thereby improving resource utilization and system throughput.

[0165] Figure 5 A fourth optional flow chart of the data processing method provided by an embodiment of the present disclosure is shown, and will be explained according to each part.

[0166] Step S501: Determine whether the input queue corresponding to the first data packet meets a first condition.

[0167] The specific steps of step S501 are the same as those of step S401 and will not be repeated here.

[0168] Step S502: Send the first data packet to the input queue.

[0169] The specific steps of step S502 are the same as those of step S402 and will not be repeated here.

[0170] Step S503: Determine whether the first data packet meets a second condition.

[0171] The specific steps of step S503 are the same as those of step S403 and will not be repeated here.

[0172] Step S504: confirm whether the first data packet meets the third condition.

[0173] The specific steps of step S504 are the same as those of step S404 and will not be repeated here.

[0174] Step S505: Send the first data packet to the first output queue based on the crossbar switch.

[0175] The specific steps of step S505 are the same as those of step S405 and will not be repeated here.

[0176] Step S506: confirm whether the credit-deficient queue meets the first condition.

[0177] The specific steps of step S506 are the same as those of step S406 and will not be repeated here.

[0178] Step S507: Add the host identifier to the first data packet.

[0179] In some embodiments, a host identifier of a host that sends the first data packet is added to the first data packet, and / or a slave identifier of a slave that receives the first data packet is added to the first data packet.

[0180] Step S508: Send the first data packet to the credit loss queue.

[0181] The specific steps of step S508 are the same as those of step S407 and will not be repeated here.

[0182] Step S509: Determine whether the first data packet meets the fourth condition.

[0183] The specific steps of step S509 are the same as those of step S408 and will not be repeated here.

[0184] Step S510: Determine whether the master credits and the slave credits meet the fifth condition.

[0185] In some embodiments, the fifth condition includes that the credit points in the credit counter are not zero, that is, the master credit points are not zero and the slave credit points are not 0, then step S511 is executed.

[0186] In some embodiments, the master credits and the slave credits are determined based on the master identifier and the slave identifier included in the first data packet.

[0187] Specifically, since the credit-missing queue is an input queue extended by the input port, a separate credit counter is no longer set. Instead, a host identifier (such as an ID) is added to the data packet transmitted into the credit-missing queue. The arbitrator obtains the credit counts of the host that sends the first data packet and the slave that receives the first data packet through host identifier and address decoding, and performs arbitration when the credit points of the credit counter support sending the data packet.

[0188] In a specific implementation, the arbitrator accesses the credit counter corresponding to the host based on the host identifier; and / or accesses the credit counter corresponding to the slave based on the slave identifier; in response to the credit counter corresponding to the host having credit points and / or the credit counter corresponding to the slave having credit points, step S511 is executed.

[0189] Among them, the credit counter corresponding to the host has credit points, which may include the input queue corresponding to the host has credit points; the credit counter corresponding to the slave has credit points, which may include the output queue corresponding to the slave (including the first output queue or the second output queue) has credit points.

[0190] In other embodiments, if at least one of the master credits and the slave credits does not satisfy the fifth condition, step S510 is repeated until the master credits and the slave credits satisfy the fifth condition, and step S511 is executed.

[0191] Step S511: Send the first data packet to the first output queue based on the crossbar switch.

[0192] The specific steps of step S511 are the same as those of step S410 and will not be repeated here.

[0193] In this way, through the data processing method provided by the embodiment of the present disclosure, by introducing a credit loss queue, the system can effectively manage data packets with insufficient credit, transfer them from the regular input queue to the credit loss queue for processing, reduce data packet retention, and improve system efficiency; in order to ensure the maximum utilization of the downstream buffer, a credit counter is not set separately for the credit loss queue, and the corresponding credit counter is accessed by setting the host ID bit for the data packet; the credit loss queue participates in the data exchange of the cross matrix together with the regular input queue. Even when the credit of the preceding data packet is insufficient, the system can continue to process and transmit the subsequent data packet with credit, thereby improving resource utilization and system throughput.

[0194] Figure 6FIG. 5 shows a fifth optional flow chart of the data processing method provided in an embodiment of the present disclosure. Figure 7 The cross switch diagram provided by the embodiment of the present disclosure is shown. Figure 6 and Figure 7 Provide explanation.

[0195] like Figure 7 As shown, the disclosed embodiment adds a credit-deficient queue to the output port. The credit-deficient queue is the queue corresponding to the input port and corresponds to the input port of the crossbar matrix. The credit-deficient queue, together with the regular input queues in the system, constitutes the input port of the crossbar matrix and is connected to each output port through the same crossbar matrix. Accordingly, after adding the credit-deficient queue to the input port, the crossbar matrix is adjusted to add a row corresponding to the credit-deficient queue. The credit-deficient queue participates in crossbar matrix arbitration and is arbitrated to the destination slave after being allocated sufficient credits. This ensures that the system can still properly schedule and transmit data packets even when credit is insufficient, avoiding potential congestion and transmission stalls. In the crossbar matrix, the credit-deficient queue has the same status as a regular input queue and has equal access to resources. When the arbitrator arbitrates requests from each input port, data packets in the credit-deficient queue can be selected and transmitted just like data packets in other normal queues. The arbitrator has been expanded to support arbitration for the credit-deficient queue. The arbitrator treats the credit-deficient queue as an equally important input source as other input queues and uses the same arbitration algorithm (such as round-robin or priority scheduling) to determine whether to transmit data packets in the queue.

[0196] In some embodiments, a credit-deficient queue no longer uses a separate credit counter. Instead, a host ID bit is added to the data packets in the credit-deficient queue. The arbiter decodes the host ID bit and the address to obtain the credit counts of the sending master and receiving slave. Arbitration is performed when the credit counter credit values support sending the data packet. The credit-deficient queue adopts a first-in, first-out queue. Data processing based on the credit-deficient queue specifically includes:

[0197] like Figure 6As shown, in response to the input queue corresponding to the slave interface being not full, the first data packet is sent by the host to the input queue corresponding to the corresponding host, and waits for other data packets in the input queue that are ahead of the first data packet to be arbitrated and sent to the slave; when the first data packet arrives at the front end of the input queue, it is checked whether there is enough credit to send, and if so, it is arbitrated by the arbitrator and sent to the slave, otherwise, it is determined whether the credit loss queue is not full, and if so, the first data packet enters the credit loss queue, otherwise, it waits for credit allocation; if the first data packet enters the credit loss queue, it waits for other data packets ahead of the first data packet in the front credit loss queue to be arbitrated and sent to the slave; when the first data packet arrives at the front end of the credit loss queue, it is checked whether there is enough credit to send, and if so, it is arbitrated by the arbitrator and sent to the slave, otherwise, it waits for credit allocation.

[0198] In some embodiments, the data processing method provided by the embodiments of the present disclosure can be applied not only to crossbar switches, but also to other interconnection topologies such as buses and on-chip networks.

[0199] In this way, through the data processing method provided by the embodiment of the present disclosure, a credit deficiency queue is set to participate in the cross matrix arbitration, and after being allocated sufficient credits, it is arbitrated to the destination slave machine, thereby ensuring that the system can still reasonably schedule and transmit data packets in the case of insufficient credit, avoiding potential congestion and transmission stagnation.

[0200] Figure 8 An optional structural diagram of a data processing device provided by an embodiment of the present disclosure is shown, and will be explained according to each part.

[0201] In some embodiments, the data processing device 900 includes an input queue determination unit 901 , a first sending unit 902 , a first position determination unit 903 , a first credit point determination unit 904 , a second sending unit 905 , a second position determination unit 906 and a third sending unit 907 .

[0202] The input queue determination unit 901 is configured to determine whether the input queue corresponding to the first data packet satisfies a first condition;

[0203] The first sending unit 902 is configured to send the first data packet to the input queue in response to the input queue meeting the first condition;

[0204] The first location determining unit 903 is configured to determine whether the first data packet satisfies a second condition;

[0205] the first credit point determination unit 904 is configured to, in response to the first data packet satisfying the second condition, determine whether the first data packet satisfies a third condition;

[0206] The second sending unit 905 is configured to send the first data packet to the credit loss queue in response to the first data packet not satisfying the third condition and the credit loss queue satisfying the first condition;

[0207] The second position determining unit 906 is configured to determine whether the first data packet satisfies a fourth condition;

[0208] The third sending unit 907 is configured to send the first data packet to the first output queue based on the crossbar switch in response to the first data packet satisfying the fourth condition and the third condition.

[0209] The first credit point unit is further configured to confirm whether the second data packet satisfies a third condition;

[0210] The second sending unit 905 is further configured to send the second data packet to the second output queue based on the crossbar switch in response to the second data packet satisfying the third condition;

[0211] Alternatively, the second sending unit 905 is further configured to send the second data packet to the credit loss queue in response to the second output queue not satisfying the third condition;

[0212] The second data packet is a data packet adjacent to the first data packet and subsequent to the first data packet.

[0213] The input queue determining unit 901 is further configured to: in response to the input queue not satisfying the first condition, repeatedly determine whether the input queue corresponding to the first data packet satisfies the first condition;

[0214] The first sending unit 902 is further configured to send the first data packet to the input queue in response to the input queue satisfying the first condition.

[0215] The first position determining unit 903 is further configured to, in response to the first data packet not satisfying the second condition, repeatedly determine whether the first data packet satisfies the second condition;

[0216] In response to the first data packet satisfying the second condition, it is confirmed whether the first data packet satisfies a third condition.

[0217] The first credit point determination unit 904 is further configured to, in response to the first data packet not satisfying the third condition and the credit missing queue not satisfying the first condition, repeatedly determine whether the first data packet satisfies the third condition or whether the credit missing queue satisfies the first condition;

[0218] In response to the first data packet satisfying a third condition, sending the first data packet to the first output queue based on the crossbar switch;

[0219] Alternatively, in response to the first data packet not satisfying the third condition but the credit missing queue satisfying the first condition, the first data packet is sent to the credit missing queue.

[0220] In some embodiments, the first condition includes that the queue is not full, and the input queue determination unit 901 is specifically configured to determine whether the input queue of the first host corresponding to the sending of the first data packet is not full;

[0221] The input queue meeting the first condition includes that the input queue can receive the first data packet; the input queue not meeting the first condition includes that the input queue is full and cannot receive the first data packet.

[0222] In some embodiments, the input queue is a first-in-first-out queue, and the second condition includes the first data packet being the first data packet in the input queue.

[0223] In some embodiments, the third condition includes that the credit points of the queue of the input port where the first data packet is located is not zero, and / or the credit points of the first output queue is not zero.

[0224] In some embodiments, the credit missing queue is a first-in-first-out queue, and the fourth condition includes the first data packet being the first data packet in the credit missing queue.

[0225] In some embodiments, the credit loss queue and the input queue are queues corresponding to input ports of the crossbar switch, and are connected to output ports corresponding to the first output queue through the crossbar switch.

[0226] The third sending unit 907 is specifically configured to arbitrate the credit loss queue and the input queue, and if the corresponding input queue meets the third condition, transmit the data packet to the corresponding output queue through the crossbar switch.

[0227] The second sending unit 905 is further configured to add a host identifier of a host that sends the first data packet to the first data packet before sending the first data packet to the credit loss queue.

[0228] The third sending unit 907 is specifically configured to determine the master credit points and the slave credit points based on the master identifier and the slave identifier included in the first data packet;

[0229] In response to the master credits and the slave credits satisfying a fifth condition, the first data packet is sent to a first output queue corresponding to the slave based on the crossbar switch.

[0230] The third sending unit 907, after sending the first data packet to the first output queue corresponding to the slave device based on the crossbar switch, is further configured to do at least one of the following:

[0231] Updating the credit points of the host corresponding to the first data packet;

[0232] Update the credit points of the slave device corresponding to the first data packet.

[0233] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

[0234] Figure 9 A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are provided as examples only and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0235] like Figure 9 As shown, the electronic device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the electronic device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0236] Multiple components in the electronic device 800 are connected to the I / O interface 805, including an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the electronic device 800 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0237] The computing unit 801 can be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as the data processing method. For example, in some embodiments, the data processing method can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the data processing method described above can be performed. Alternatively, in other embodiments, the computing unit 801 can be configured to perform the data processing method in any other appropriate manner (e.g., by means of firmware).

[0238] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0239] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0240] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0241] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0242] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0243] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact through a communication network. The client-server relationship arises through computer programs running on the respective computers and having a client-server relationship with each other. The server may be a cloud server, a server in a distributed system, or a server integrated with a blockchain.

[0244] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not a limitation herein.

[0245] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0246] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A data processing method, characterized in that: The method comprises: Determining whether the input queue corresponding to the first data packet meets a first condition; In response to the input queue satisfying the first condition, sending the first data packet to the input queue; determining whether the first data packet satisfies a second condition; In response to the first data packet satisfying the second condition, determining whether the first data packet satisfies a third condition; In response to the first data packet not satisfying a third condition and the credit missing queue satisfying the first condition, sending the first data packet to the credit missing queue; determining whether the first data packet satisfies a fourth condition; In response to the first data packet satisfying the fourth condition and the third condition, the first data packet is sent to the first output queue based on the crossbar switch.

2. The method according to claim 1, characterized in that After sending the first data packet to the credit missing queue, the method further includes: confirming whether the second data packet satisfies the third condition; In response to the second data packet satisfying the third condition, sending the second data packet to the second output queue based on the crossbar switch; Alternatively, in response to the second output queue not satisfying the third condition and the credit missing queue satisfying the first condition, sending the second data packet to the credit missing queue; The second data packet is a data packet subsequent to the first data packet.

3. The method according to claim 1, characterized in that The method further comprises: In response to the input queue not satisfying the first condition, repeatedly determining whether the input queue corresponding to the first data packet satisfies the first condition; In response to the input queue meeting the first condition, the first data packet is sent to the input queue.

4. The method according to claim 1, wherein The method further comprises: In response to the first data packet not satisfying the second condition, repeatedly determining whether the first data packet satisfies the second condition; In response to the first data packet satisfying the second condition, it is confirmed whether the first data packet satisfies a third condition.

5. The method according to claim 1, wherein The method further comprises: In response to the first data packet not satisfying a third condition and the credit-deficient queue not satisfying the first condition, repeatedly determining whether the first data packet satisfies the third condition or whether the credit-deficient queue satisfies the first condition; In response to the first data packet satisfying a third condition, sending the first data packet to the first output queue based on the crossbar switch; Alternatively, in response to the first data packet not satisfying the third condition but the credit missing queue satisfying the first condition, the first data packet is sent to the credit missing queue.

6. The method according to claim 1, characterized in that The first condition includes that the queue is not full, and determining whether the input queue corresponding to the first data packet meets the first condition includes: Determining whether an input queue of a first host corresponding to sending the first data packet is not full; The input queue meeting the first condition includes that the input queue can receive the first data packet; the input queue not meeting the first condition includes that the input queue is full and cannot receive the first data packet.

7. The method according to claim 1, characterized in that The input queue is a first-in-first-out queue, and the second condition includes that the first data packet is the first data packet in the input queue.

8. The method according to claim 1, characterized in that The third condition includes that the credit points of the queue of the input port where the first data packet is located is not zero, and / or the credit points of the first output queue is not zero.

9. The method according to claim 1, characterized in that The credit-missing queue is a first-in-first-out queue, and the fourth condition includes that the first data packet is the first data packet in the credit-missing queue.

10. The method according to claim 1, characterized in that The credit loss queue and the input queue are queues corresponding to input ports of the crossbar switch, and are connected to output ports corresponding to the first output queue through the crossbar switch.

11. The method according to claim 1 or 10, characterized in that Arbitration is performed on the credit loss queue and the input queue, and if the corresponding input queue meets a third condition, the data packet is transmitted to the corresponding output queue through the crossbar switch.

12. The method according to claim 1, characterized in that Before sending the first data packet to the credit missing queue, the method further includes: A host identifier of a host that sends the first data packet is added to the first data packet.

13. The method according to claim 12, characterized in that The sending the first data packet to the first output queue based on the crossbar switch includes: Determine the master credit points and the slave credit points based on the master identifier and the slave identifier included in the first data packet; In response to the master credits and the slave credits satisfying a fifth condition, the first data packet is sent to a first output queue corresponding to the slave based on the crossbar switch.

14. The method according to claim 13, characterized in that After sending the first data packet to the first output queue corresponding to the slave device based on the crossbar switch, the method further includes at least one of the following: Updating the credit points of the host corresponding to the first data packet; Update the credit points of the slave device corresponding to the first data packet.

15. A data processing device, characterized in that: The device comprises: an input queue determining unit, configured to determine whether an input queue corresponding to the first data packet satisfies a first condition; a first sending unit, configured to send the first data packet to the input queue in response to the input queue satisfying the first condition; a first position determining unit, configured to determine whether the first data packet satisfies a second condition; a first credit point determination unit, configured to, in response to the first data packet satisfying the second condition, determine whether the first data packet satisfies a third condition; a second sending unit, configured to send the first data packet to the credit missing queue in response to the first data packet not satisfying the third condition and the credit missing queue satisfying the first condition; a second position determining unit, configured to determine whether the first data packet satisfies a fourth condition; The third sending unit is configured to send the first data packet to the first output queue based on the crossbar switch in response to the first data packet satisfying the fourth condition and the third condition.

16. The device according to claim 15, characterized in that The first credit point unit is further configured to confirm whether the second data packet satisfies a third condition; The second sending unit is further configured to send the second data packet to the second output queue based on the crossbar switch in response to the second data packet satisfying the third condition; Alternatively, the second sending unit is further configured to send the second data packet to the credit loss queue in response to the second output queue not satisfying the third condition; The second data packet is a data packet adjacent to the first data packet and subsequent to the first data packet.

17. The device according to claim 15, characterized in that The input queue determining unit is further configured to: in response to the input queue not satisfying the first condition, repeatedly determine whether the input queue corresponding to the first data packet satisfies the first condition; The first sending unit is further configured to send the first data packet to the input queue in response to the input queue satisfying the first condition.

18. An electronic device, characterized in that: include: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method according to any one of claims 1 to 14.

19. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause a computer to execute the method according to any one of claims 1-14.

20. A computer program product, characterized in that The invention comprises a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 14.

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