Remote doping of semiconductor structures, related devices, related systems, and related methods

Abstract

The techniques of the present disclosure generally relate to the field of semiconductor devices. More specifically, the present invention relates to field effect transistors (FETs) and systems and methods for fabricating FETs. The FET includes: a substrate; comprising a channel material; a source electrode and a drain electrode in electrical contact with the channel layer; at least one gate electrode in contact with the gate insulating layer; at least one remote dopant layer in electrical contact with at least a portion of the gate electrode or gate insulating layer; wherein the remote dopant layer comprises at least one boron-containing material; and wherein the remote dopant layer is configured to remotely dope the channel material of the channel layer.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor devices and more particularly to field effect transistors including at least one remote dopant layer comprising at least one boron compound and methods and systems for fabricating the same. Background Art

[0002] Field-effect transistors (FETs) are widely known electronic devices used to control the flow of current in circuits. Conventional transistors typically use various semiconductor materials, such as silicon, which involve relatively thick layers. However, with the increasing miniaturization of electronic devices, there is a growing demand for transistors with new materials and thinner designs that are suitable for the needs of modern electronic devices.

[0003] In recent years, there has been significant interest in using two-dimensional (2D) materials as channel materials for FETs due to their unique electronic properties, such as graphene or transition metal dichalcogenides (TMDCs). For example, channels based on 2D materials are particularly interesting for precisely controlling the flow of current between source and drain electrodes by modulating the voltage / field of the gate electrode.

[0004] However, due to the inherent atomic thickness of 2D materials, one of the main remaining challenges is achieving precise doping at specific regions of the channel to control its electrical properties. Common doping techniques such as ion implantation, chemical treatment, co-deposition, and oxide top layer all result in poor local control, material degradation, and reduced thermal stability. Furthermore, achieving both p-doping and n-doping with the same material using traditional doping techniques is challenging.

[0005] Therefore, there is a need to address the aforementioned challenges of current doping techniques for 2D materials to obtain improved transistors. In particular, this should not compromise the transistor's high stability and threshold voltage. This would be beneficial for the development of commercially relevant and reliable FETs. Summary of the Invention

[0006] This summary is provided to introduce a selection of concepts in a simplified form. These concepts are further described in detail in the detailed description of example embodiments of the present disclosure below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0007] Generally speaking, the technology disclosed herein relates to the field of semiconductor devices, and more specifically to "remote doping" of semiconductor devices. As used herein, remote doping refers to the introduction of a dopant (e.g., a boron compound) into a region of a semiconductor that is physically separated from another region to be doped. Such remote doping devices can improve the electrical performance of field-effect transistors (FETs) while maintaining the basic FET capability of switching between "on" and "off" states in response to a gate voltage or field.

[0008] Thus, in some broad aspects, the present disclosure relates to FETs and methods and systems for manufacturing at least a portion of the FETs. These FETs can be suitable as electronic components for various applications such as central processing units (CPUs) and systems on chip (SoCs). One aspect of the present disclosure relates to a field effect transistor (FET) comprising: a substrate, at least one channel layer comprising a channel material, optionally at least one insulating layer, a source electrode and a drain electrode electrically in contact with the channel layer, at least one gate electrode in contact with the gate insulating layer, at least one remote dopant layer electrically in contact with at least a portion of the gate electrode or the gate insulating layer, wherein the remote dopant layer comprises at least one boron-containing material, and wherein the remote dopant layer is configured to remotely dope the channel material of the channel layer.

[0009] It will be appreciated that although the use of defective oxide layers and the use of remote dopant layers to induce doping have been previously considered, such oxide layers cannot provide the desired local doping with high efficiency and reduced defects. Therefore, the stability and integrity of the FET are compromised. This is in contrast to the present disclosure, in which the remote dopant layer as disclosed herein can provide controlled and localized doping of specific regions of the channel layer comprising the channel material. Without being bound by any particular theory or mode of operation, it is believed that the charged defect states generate a net charge in the remote dopant layer. This net charge generates an electric field that causes band bending in the channel material, thereby controlling the band alignment in the channel region without having to rely on in situ doping. In addition, the remote dopant layer can be configured to provide both p-doping and n-doping, thereby overcoming several challenges of the prior art.

[0010] Another advantage is that the present FET can be configured in various ways, resulting in, for example, single-gate or multi-gate structures, which increases flexibility in FET fabrication. Non-limiting examples of such FET configurations are further described below.

[0011] In certain embodiments, a FET as disclosed herein provides that the boron-containing material may be selected from the group consisting of boron nitride (BN), boron carbide (BC), boron carbonitride (BCN), and mixtures thereof.

[0012] An overview of various other aspects of the technology disclosed herein is provided below, followed by a detailed description of specific embodiments. It should be understood that the above-mentioned objects and advantages are also applicable to various other aspects and features disclosed herein.

[0013] Another aspect of the present disclosure relates to a method for fabricating at least a portion of a FET, comprising the steps of providing a substrate into a reaction chamber, performing one or more cycles, the cycles comprising a boron precursor pulse, wherein at least a portion of the substrate is contacted with at least one boron precursor by introducing the boron precursor into the reaction chamber, wherein as a result of the cycles, at least one remote dopant layer comprising a boron-containing material is formed on the substrate; wherein the substrate comprises at least one channel layer, the at least one channel layer comprising channel material formed before or after forming the remote dopant layer, or a combination thereof; wherein the at least one remote dopant layer is configured to remotely dope the channel material of the channel layer during operation of the FET.

[0014] In other words, the methods disclosed herein generally involve a deposition process in which a remote dopant layer can be gradually grown as a thin film during one or more cycles. This can provide the following advantages: the remote dopant layer can be formed with controlled thickness, reduced defects, and high composition flexibility. Consequently, this results in more reliable doping of localized regions in the channel layer.

[0015] In certain embodiments, methods as disclosed herein provide that at least one channel layer may be formed by providing a substrate to a reaction chamber, performing one or more cycles, the cycles comprising a transition metal precursor pulse, wherein at least a portion of the substrate is contacted with at least one transition metal precursor by introducing the transition metal precursor into the reaction chamber, and a chalcogenide reactant pulse, wherein at least a portion of the substrate is contacted with at least one chalcogenide reactant by introducing the chalcogenide reactant into the reaction chamber, wherein, as a result of the cycles, at least one channel layer comprising a channel material is formed on at least one of the substrate and the remote dopant layer.

[0016] Another aspect of the present disclosure relates to a system for fabricating at least a portion of a field effect transistor, comprising: a reaction chamber constructed and arranged to hold a substrate, a boron precursor container constructed and arranged to contain and evaporate at least one boron precursor, optionally, a reactant gas container and a plasma power supply, a transition metal precursor container constructed and arranged to contain and evaporate at least one transition metal precursor, a chalcogenide reactant container constructed and arranged to contain and evaporate at least one chalcogenide reactant, which is operably connected to the boron precursor container, the transition metal precursor container, and the chalcogenide reactant container, wherein a controller is configured to control the introduction of the boron precursor, the transition metal precursor, and the chalcogenide reactant into the reaction chamber during one or more cycles, wherein, as a result of the cycling, in some embodiments, at least one remote dopant layer comprising a boron compound and at least one channel layer comprising a channel material are formed on the substrate; and wherein the remote dopant layer is configured to remotely dope the channel material included in the channel layer during operation of the field effect transistor.

[0017] In certain embodiments, a system as disclosed herein is configured to fabricate a FET as disclosed herein.

[0018] In certain embodiments, a system as disclosed herein is configured to form at least a portion of a FET by means of a method as disclosed herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] It should be understood that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the sizes of some elements in the drawings may be exaggerated relative to other elements to help improve understanding of the illustrated embodiments of the present disclosure.

[0020] Figure 1 An exemplary embodiment of a single-gate field effect transistor 100 as disclosed herein is schematically illustrated.

[0021] Figure 2 Another exemplary embodiment of a single-gate field effect transistor 200 as disclosed herein is schematically illustrated.

[0022] Figure 3 Another exemplary embodiment of a single-gate field effect transistor 300 as disclosed herein is schematically illustrated.

[0023] Figure 4 An exemplary embodiment of a dual-gate field effect transistor 400 as disclosed herein is schematically illustrated.

[0024] Figure 5 Another exemplary embodiment of a dual-gate field effect transistor 500 as disclosed herein is schematically illustrated.

[0025] Figure 6Another exemplary embodiment of a dual-gate field effect transistor 600 as disclosed herein is schematically illustrated.

[0026] Figure 7 An exemplary embodiment of a three-dimensional (3D) gate field effect transistor 700 as disclosed herein is schematically illustrated.

[0027] Figure 8 Another exemplary embodiment of a three-dimensional (3D) gate field effect transistor 800 as disclosed herein is schematically illustrated.

[0028] Figure 9 Another exemplary embodiment of a three-dimensional (3D) gate field effect transistor 900 as disclosed herein is schematically illustrated.

[0029] Figure 10 An exemplary embodiment of a method for manufacturing at least a portion of a field effect transistor as disclosed herein is schematically illustrated.

[0030] Figure 11 Another exemplary embodiment of a method for manufacturing at least a portion of a field effect transistor as disclosed herein is schematically shown.

[0031] Figure 12 An exemplary embodiment of a system 1200 for fabricating at least a portion of a field effect transistor as disclosed herein is schematically illustrated. DETAILED DESCRIPTION

[0032] Although certain embodiments and examples are disclosed below, those skilled in the art will appreciate that the disclosure extends beyond the specifically disclosed embodiments and / or uses of the disclosure and obvious modifications and equivalents thereof. Accordingly, it is intended that the scope of the disclosure disclosed should not be limited by the specific disclosed embodiments described below.

[0033] In the following detailed description, the technology underlying the present disclosure will be described with reference to different aspects of the present disclosure. It will be readily understood that the various aspects of the present disclosure, as generally described herein and illustrated in the accompanying drawings, may be arranged, replaced, combined, and designed in a wide variety of different configurations, all of which are expressly contemplated and form part of the present disclosure. This description is intended to help the reader more easily understand the technical concepts, but is not intended to limit the scope of the present disclosure. Therefore, the following description is to be considered illustrative in nature, rather than restrictive.

[0034] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment.

[0035] As used herein, the term "comprises" and its variations are synonymous with "includes" and its variations or "contains" and its variations, and are inclusive or open-ended and do not exclude additional, unrecited components, elements, or method steps. When referring to listed components, elements, or method steps, the term "comprises" and its variations also include embodiments "consisting of" the listed components, elements, or method steps. Unless the context clearly dictates otherwise, the singular forms "a," "an," and "the" include both singular and plural referents.

[0036] As used herein, the term "substantially" refers to the complete or nearly complete extent or degree of an action, characteristic, property, state, structure, item, or result. For example, an object that is "substantially" enclosed would mean that the object is completely enclosed or nearly completely enclosed. In some cases, the exact permissible degree of deviation from absolute completeness may depend on the specific context. However, in general, nearly complete will result in having an overall result that is absolutely and completely identical. When used in a negative sense, the use of "substantially" is equally applicable to referring to the complete or nearly complete lack of an action, characteristic, property, state, structure, item, or result.

[0037] As used herein, the term "about" is used to provide flexibility for a numerical value or a range endpoint by specifying that a given value can be "slightly above" or "slightly below" a value or endpoint, depending on the specific context. Unless otherwise indicated, the use of the term "about" with respect to a particular number or numerical range should also be understood to provide support for such numerical term or range without the term "about." For example, the description of "about 30" should be interpreted as providing support not only for values slightly above and slightly below 30, but also for the actual numerical value of 30.

[0038] The numerical ranges described by endpoints include all integers and fractions when appropriate included in the range (e.g., when mentioning the number of elements, 1 to 5 can include 1, 2, 3, 4, and when mentioning, for example, measurement, can also include 1.5, 2, 2.75, and 3.80). The narration of endpoints also includes the endpoint value itself (e.g., 1.0 to 5.0 includes both 1.0 and 5.0). Any numerical range described herein is intended to include all subranges included therein. In addition, unless otherwise stated, the terms first, second, third, etc. in the specification and claims are used to distinguish similar elements, and are not necessarily used to describe order or chronological order. It should be understood that the terms used in this manner are interchangeable where appropriate, and the embodiments of the present disclosure described herein can operate in other sequences different from those described or shown herein.

[0039] Reference throughout this specification to substituents means that one or more hydrogen atoms on the indicated atom in the expression "substituted" is replaced with a selection from the indicated group as detailed below, provided that the normal valency of the indicated atom is not exceeded and that the substitution results in a chemically stable compound, i.e., a compound sufficiently robust to survive isolation from a reaction mixture.

[0040] In this disclosure, "high-k dielectric" refers to a dielectric material having a high relative permittivity. This type of dielectric is characterized by its ability to efficiently store electrical energy, making it particularly valuable for use in electronic devices. High-k dielectrics may include materials that exhibit a high dielectric constant compared to traditional dielectrics such as silicon dioxide. Depending on the specific application, a high-k dielectric may include a single material or a combination of materials, compounds, or alloys known in the art.

[0041] In the present disclosure, "gas" may include materials that are gaseous at normal temperature and pressure (NTP), evaporated solids, and / or evaporated liquids, and may consist of a single gas or a mixture of gases, depending on the context. Gases other than process gases (i.e., gases introduced without passing through a gas distribution assembly, other gas distribution devices, etc.) may be used, for example, to seal the reaction space and may include sealing gases, such as noble gases.

[0042] In some cases, the term "precursor" can refer to a compound that participates in a chemical reaction that produces another compound, particularly a compound that constitutes the membrane matrix or the main skeleton of the membrane. The term "reactant" can be used interchangeably with the term precursor.

[0043] In the present disclosure, the following abbreviations of chemical structures are used: Cp represents cyclopentadienyl, Me represents methyl, Et represents ethyl, n-Pr represents n-propyl, i-Pr represents isopropyl or isopropyl, n-Bu represents n-butyl, and t-Bu represents tert-butyl or tert-butyl.

[0044] In this specification, techniques are described relating to remotely doped transistors comprising at least one channel. Including at least one remote dopant layer comprising at least one boron-containing material into a transistor structure can improve and simultaneously control the electrical performance of such remotely doped transistors.

[0045] Accordingly, various embodiments of the present disclosure relate to a field effect transistor (FET) comprising: a substrate; at least one channel layer comprising a channel material; optionally, at least one insulating layer; a source electrode and a drain electrode electrically contacting the channel layer; at least one gate electrode in contact with the gate insulating layer; at least one remote dopant layer electrically contacting the gate electrode or at least a portion of the gate insulating layer; wherein the remote dopant layer comprises at least one boron-containing material; and wherein the remote dopant layer is configured to remotely dope the channel material of the channel layer.

[0046] In a particular embodiment, the FET includes: a substrate; at least one channel layer comprising a two-dimensional (2D) channel material; optionally, at least one insulating layer; a source electrode and a drain electrode electrically contacting the channel layer; at least one gate electrode in contact with the gate insulating layer; at least one remote dopant layer electrically contacting the gate electrode or at least a portion of the gate insulating layer; wherein the remote dopant layer comprises at least one boron-containing material; and wherein the remote dopant layer is configured to remotely dope the 2D channel material of the channel layer.

[0047] In a particular embodiment, a FET includes: a substrate; at least one channel layer comprising a 2D transition metal dichalcogenide (TMDC) material; optionally, at least one insulating layer; a source electrode and a drain electrode electrically contacting the channel layer; at least one gate electrode in contact with the gate insulating layer; at least one remote dopant layer electrically contacting the gate electrode or at least a portion of the gate insulating layer; wherein the remote dopant layer comprises at least one boron-containing material; and wherein the remote dopant layer is configured to remotely dope the 2D TMDC material of the channel layer.

[0048] A FET as disclosed herein comprises a source electrode and a drain electrode in physical and / or electrical contact with at least one channel layer and at least one gate electrode. The gate electrode is further in contact with a gate insulating layer. The gate insulating layer may comprise at least one insulating material selected from silicon, silicon dioxide, and a high-k dielectric as defined herein.

[0049] In some embodiments, the gate insulating layer may be in electrical contact with the channel layer. In some further embodiments, the gate insulating layer may be disposed between the gate electrode and the channel layer and may be in electrical contact with the gate electrode and the channel layer.

[0050] Thus, in some embodiments, the gate electrode and the corresponding gate insulating layer can be disposed or positioned adjacent to or in physical contact with the channel layer. This configuration allows an external electric field to be applied to the channel (and / or at least one remote dopant layer) to modulate (and / or switch on or off) the current flowing in the channel layer.

[0051] Many alternative geometries, schemes and methods known in the art for electrically connecting or physically orienting source and drain electrodes and / or gate electrodes and / or gate insulation layers relative to the channel layer (e.g., top gate or bottom gate) may be employed as an alternative to or in combination with the embodiments disclosed herein.

[0052] Thus, the FETs disclosed herein can include stacks or structures of various electrodes and layers. "Films" or "layers" referred to herein can be any continuous or discontinuous structure and material, such as materials deposited according to the present technology. For example, films and / or layers can include two-dimensional materials, three-dimensional materials, nanoparticles, or even partial or complete molecular layers or partial or complete atomic layers or clusters of atoms and / or molecules, or layers composed of isolated atoms and / or molecules.

[0053] In some embodiments, a film or layer may include a material or layer having pinholes, which may or may not be continuous.

[0054] One of the core layers in the present disclosure is a channel layer comprising a channel material, the size, chemical, physical and electrical properties of which can be particularly suitable for the purpose of conducting current through the transistor device. Non-limiting examples of suitable channel materials include semiconductor oxides, elemental semiconductors, alloys and / or 2D materials such as graphene and 2D TMDCs. For example, the high carrier mobility and relatively low electrical resistance of 2D TMDC materials can provide a channel layer through which holes or electrons can be conducted with high efficiency.

[0055] The term "2D (channel) material" as used herein may generally refer to a layered atomic structure consisting of approximately a monolayer of atoms, which is suitable for use as a channel material as described herein.

[0056] As used herein, the term "two-dimensional (2D) transition metal dichalcogenides" (TMDCs) generally refers to substantially crystalline materials characterized by a layered atomic structure consisting of approximately a monolayer of transition metal atoms sandwiched or arranged between approximately two layers of chalcogen atoms. In this structure, each transition metal atom is typically covalently bonded to two chalcogen atoms, which can form a hexagonal lattice.

[0057] In some embodiments, the 2D TMDC material may include a transition metal dichalcogenide represented by the general chemical formula MX2, wherein M is a transition metal element selected from Mo, W, Bi, Sb, Ti, Pt, Nb, Re, Ta, Ni, Zr, Hf, V, Ta, and Pd; and wherein X is a chalcogenide selected from S, Se, and Te. Advantageously, a channel including the channel materials described herein can provide improved electronic and mechanical properties. For example, a channel including the disclosed channel materials can be characterized by controlled channel thickness, high charge carrier mobility, low power consumption, and good chemical stability.

[0058] In a particular embodiment, the channel material may include a transition metal dichalcogenide selected from the group consisting of BiS2, BiSe2, BiTe2, MoS2, MoSe2, MoTe2, PtS2, PtSe2, PtTe2, WS2, WSe2, WTe2, PdS2, PdSe2, PdTe2, HfS2, HfSe2, HfTe2, NbS2, NbSe2, NbTe2, ZrS2, ZrSe2, ZrTe2, VS2, VSe2, VTe2, ReS2, ReSe2, ReTe2, NiS2, NiSe2, NiTe2, TaS2, TaSe2, TaTe2, SbS2, SbSe2, SbTe2, TiS2, TiSe2, TiTe2, and mixtures thereof.

[0059] In a particular embodiment, the channel material may include a semiconductor oxide selected from the group consisting of indium tin oxide, indium zinc oxide, gallium zinc oxide, indium oxide, tin oxide, zinc oxide, titanium oxide, gallium oxide, and mixtures thereof.

[0060] In a particular embodiment, the channel material may include an elemental semiconductor selected from the group consisting of Si, Sb, Ge, and combinations thereof.

[0061] In certain embodiments, the channel material may include graphene.

[0062] In a particular embodiment, the channel material may include a chalcogenide alloy, such as Se-Te or Ge-Se-Te.

[0063] In certain embodiments, as provided for in the FETs disclosed herein, at least one channel layer comprising a channel material may have an average thickness of between 0.05 nm and 4.0 nm, or between 0.05 nm and 3.80 nm, or between 0.05 nm and 3.60 nm, or between 0.05 nm and 3.50 nm, or between 0.05 nm and 3.40 nm, or between 0.05 nm and 3.20 nm, or between 0.05 nm and 3.0 nm, or between 0.05 nm and 3.60 nm. Between 0.5 nm and 2.80 nm, or between 0.05 nm and 2.60 nm, preferably between 0.05 nm and 2.50 nm, or between 0.05 nm and 2.40 nm, or between 0.05 nm and 2.20 nm, preferably between 0.05 nm and 2.0 nm, or between 0.05 nm and 1.80 nm, or between 0.05 nm and 1.50 nm, or between 0.05 nm and 1.25 nm, or between 0.05 nm and 1.0 nm.

[0064] In some embodiments, at least one channel layer comprising a channel material may have an average thickness of less than 1.0 nm. Thin channels as disclosed herein provide advantages in that related devices can be further scaled down and characterized by sharp transitions between on and off states of current flow.

[0065] Another core layer of the present disclosure is at least one remote dopant layer that is in electrical contact with at least a portion of a gate electrode or a gate insulating layer. The remote dopant layer as described herein comprises at least one boron-containing material as a dopant material. As will be described later in this disclosure, comprising one or more boron-containing materials can be used to remotely dope at least a portion of a channel material of a channel layer during operation of a field effect transistor.

[0066] In certain embodiments, as provided for in the FETs disclosed herein, the boron-containing material may be selected from the group consisting of boron nitride (BN), boron carbide (BC), boron carbonitride (BCN), and mixtures thereof.

[0067] In some embodiments, the boron nitride (BN) may be amorphous boron nitride (aBN), polycrystalline boron nitride, and / or crystalline boron nitride. Boron-containing materials as disclosed herein can produce remote dopant layers with low dielectric constants and good diffusion resistance, resulting in controlled doping of physical remote layers without sacrificing the stability of the remote dopant film.

[0068] In certain embodiments, as provided for in the FETs disclosed herein, the remote dopant layer can be in electrical contact with at least a portion of the channel layer. This has the advantage that the diffusion of charge carriers can be more easily modulated.

[0069] In certain embodiments, a FET as disclosed herein may further include a spacer layer disposed between the channel layer and the remote dopant layer. As used herein, the spacer layer may include at least one insulating material, wherein the insulating material is typically undoped. The insulating layer may reversibly modulate or even hinder the transfer of holes or electrons between the channel layer and the remote dopant layer. Thus, one function of the spacer layer is to enable and / or improve the ability of the channel layer to "turn off" current by pulling holes or electrons toward the channel layer or driving holes or electrons away from the channel layer in response to application of an appropriate voltage to the gate electrode.

[0070] In certain embodiments, as provided for in the FETs disclosed herein, the spacer layer can be in electrical contact with the channel layer and the remote dopant layer.

[0071] Optionally, the remote dopant layer may further comprise at least one hole transport material and / or at least one electron transport material. The function of the remote dopant layer is to supply additional current carriers (holes or electrons) to the channel and / or spacer layer so as to significantly increase or decrease the conductivity (or current) in the channel layer. Advantageously, a FET having a remote dopant layer of a channel material configured to remotely dope the channel layer can provide controlled and localized doping of the access and contact regions of the FET, which is difficult to achieve in transistors of the prior art.

[0072] The aforementioned components of the FET as described herein are formed or deposited on a supporting but generally non-conductive substrate. As used herein, the term "substrate" may refer to any one or more underlying materials that can be used to form or on which a device, circuit, or membrane can be formed. A "substrate" can be continuous or discontinuous; rigid or flexible; solid or porous; and combinations thereof. The substrate can be in any form, such as a powder, a plate, or a workpiece. A substrate in plate form can include wafers of various shapes and sizes. The substrate can include bulk materials such as silicon (e.g., single crystal silicon), other Group IV materials (e.g., germanium), or other semiconductor materials (e.g., Group II-VI or Group III-V semiconductor materials), and can include one or more layers overlying or underlying the bulk material. In addition, the substrate can include various features, such as recesses, protrusions, etc., formed within or on at least a portion of a layer of the substrate. For example, the substrate can include a bulk semiconductor material and a layer of insulating or (high-k) dielectric material covering at least a portion of the bulk semiconductor material. In specific embodiments, the substrate can include silicon, silicon germanium, silicon oxide, gallium arsenide, gallium nitride, or silicon carbide.

[0073] In some embodiments, a FET as disclosed herein may include at least one insulating layer. The insulating layer may include at least one insulating material, wherein the insulating material may be selected from silicon, silicon oxide, and a high-k dielectric material as defined herein.

[0074] Referring back to the many alternatives and methods for electrically connecting or physically orienting FET components, this disclosure provides some non-limiting exemplary embodiments of some geometries and configurations.

[0075] In certain embodiments, a FET as disclosed herein may further include at least one second remote dopant layer in electrical contact with at least a portion of a gate electrode or gate insulating layer; wherein the gate electrode or gate insulating layer is disposed between the first remote dopant layer and the second remote dopant layer; and wherein the second remote dopant layer includes at least one boron-containing material configured to be used for remotely doping a channel material of a channel layer. The first remote dopant layer and the second remote dopant layer may provide remote doping to different regions of the channel layer. In some embodiments, the first remote dopant layer and the second remote dopant layer may be a continuous or non-continuous structure, thereby providing the ability to pattern, control and / or localize doping of the channel layer. Therefore, the present technology provides high versatility in designing various transistor configurations.

[0076] Figure 1 An exemplary embodiment of a single-gate field-effect transistor 100 of the present disclosure is shown. The single-gate transistor 100 can be formed using deposition methods and / or systems as described herein. In the example shown, the single-gate transistor 100 includes a substrate 111, a channel layer 112 located on the substrate 111, and a gate insulating layer 113, a first spacer layer 119, and a second spacer layer 120 located entirely on the channel layer 112. The gate insulating layer 113 separates the first spacer layer 119 and the second spacer layer 120. The channel layer 112 includes a channel material configured to provide high conductivity, as described herein.

[0077] The transistor 100 further includes a gate electrode 116 on the gate insulating layer 113, a first remote dopant layer 117 on the first spacer layer 119, and a second remote dopant layer 118 on the second spacer layer 120. The gate electrode 116 separates the first remote dopant layer 117 and the second remote dopant layer 118. The first remote dopant layer 117 and the second remote dopant layer 118 each include at least one boron-containing material.

[0078] The transistor 100 further includes a source electrode 114 located at one end of the channel layer 112 adjacent to the first remote dopant layer 117 and a drain electrode 115 located at the other end of the channel layer 112 adjacent to the second remote dopant layer 118 .

[0079] Figure 2Another exemplary embodiment of a single-gate field-effect transistor 200 of the present disclosure is shown. The single-gate transistor 200 can be formed using deposition methods and / or systems as described herein. In the illustrated example, the single-gate transistor 200 includes a substrate 211, an insulating layer 212 located on the substrate 211, and a channel layer 213 located on the insulating layer 212. The channel layer 213 includes a channel material as described herein.

[0080] The transistor 200 further includes a gate insulating layer 214 located on the channel layer 213. The gate insulating layer 214 separates a first spacer layer 220 from a second spacer layer 221, which are also located on the channel layer 213. The transistor 200 further includes a gate electrode 217 located on the gate insulating layer 214. The gate electrode 217 separates a first remote dopant layer 218 located on the first spacer layer 220 from a second remote dopant layer 219 located on the second spacer layer 221. The first remote dopant layer 218 and the second remote dopant layer 219 each include at least one boron-containing material.

[0081] The transistor 200 further includes a source electrode 215 located at one end of the channel layer 213 and adjacent to the first remote dopant layer 218 , and a drain electrode 216 located at an opposite end of the channel layer 213 and adjacent to the second remote dopant layer 219 .

[0082] Figure 3 Another exemplary embodiment of a single-gate field-effect transistor 300 of the present disclosure is shown. The single-gate transistor 300 can be formed using deposition methods and / or systems as described herein. In the illustrated example, the single-gate transistor 300 includes a substrate 311, an insulating layer 312 located on the substrate 311, and a channel layer 313 located on the insulating layer 312. The channel layer 313 includes a channel material as described herein.

[0083] The transistor 300 further includes a gate insulating layer 314 located on the channel layer 313 and a gate electrode 317 located on the gate insulating layer 314. The gate insulating layer 314 and the gate electrode 317 separate a first remote dopant layer 318 and a second remote dopant layer 319, both of which are located on the channel layer 313. The first remote dopant layer 318 and the second remote dopant layer 319 each include at least one boron-containing material.

[0084] The transistor 300 further includes a source electrode 315 located at one end of the channel layer 313 and adjacent to the first remote dopant layer 318 , and a drain electrode 316 located at the other end of the channel layer 313 and adjacent to the second remote dopant layer 319 .

[0085] It should be noted that the FETs described herein are not limited to single-gate structures, but may also include multi-gate devices (i.e., fin field-effect transistors). Multi-gate device designs have the following advantages: they can provide better electrostatic control on one or more channel layers, thereby allowing more precise modulation of the on and off states of the FET. In addition, more precise switching between the on and off states reduces leakage current, resulting in FETs with higher energy efficiency.

[0086] In a particular embodiment, a FET as disclosed herein may further include at least one second gate electrode in contact with the gate insulating layer; wherein at least one channel layer is disposed between the first gate electrode and the second gate electrode; wherein the field effect transistor further includes at least one second remote dopant layer electrically contacting the second gate electrode or at least a portion of the gate insulating layer; and wherein the second remote dopant layer includes at least one boron-containing material configured for remote doping of a channel material of the channel layer.

[0087] Figure 4 An exemplary embodiment of a dual-gate field-effect transistor 400 of the present disclosure is shown. The dual-gate transistor 400 can be formed using deposition methods and / or systems as described herein. In the illustrated example, the dual-gate transistor 400 includes a substrate 411, a second gate electrode 412 located on the substrate 411, a second gate insulating layer 413 located on the second gate electrode 412, and a channel layer 414 located on the second gate insulating layer 413. The channel layer 414 includes a channel material configured to provide high conductivity, as described herein.

[0088] The transistor 400 further includes a first gate insulating layer 415 located on the channel layer 414 and a first gate electrode 418 located on the first gate insulating layer 415. The first gate insulating layer 415 and the first gate electrode 418 separate a first remote dopant layer 419 and a second remote dopant layer 420, both of which are located on the channel layer 414. The first remote dopant layer 419 and the second remote dopant layer 420 each include at least one boron-containing material.

[0089] The transistor 400 further includes a source electrode 416 located at one end of the channel layer 414 and adjacent to the first remote dopant layer 419 , and a drain electrode 417 located at the other end of the channel layer 414 and adjacent to the second remote dopant layer 420 .

[0090] Alternatively, the double-gate transistor 400 may include an insulating layer disposed between the substrate 411 and the second gate electrode 412 .

[0091] Alternatively, the double-gate transistor 400 may include a first spacer layer disposed between the channel layer 414 and the first remote dopant layer 419 and / or a second spacer layer disposed between the channel layer 414 and the second remote dopant layer 420 .

[0092] Figure 5 Another exemplary embodiment of a dual-gate field-effect transistor 500 of the present disclosure is shown. The dual-gate transistor 500 can be formed using deposition methods and / or systems as described herein. In the illustrated example, the dual-gate transistor 500 includes a substrate 511, a second gate electrode 512 located on the substrate 511, and a second gate insulating layer 513 located on the second gate electrode 512.

[0093] The transistor 500 further includes a third remote dopant layer 521 on the second gate insulating layer 513 and a channel layer 514 on the third remote dopant layer 521. The channel layer 514 includes a channel material as described herein.

[0094] Transistor 500 further includes a first gate insulating layer 515 on channel layer 514 and a first gate electrode 518 on first gate insulating layer 515. First gate insulating layer 515 and first gate electrode 518 separate first remote dopant layer 519 and second remote dopant layer 520, both of which are on channel layer 514.

[0095] Transistor 500 also includes a source electrode 516 located on one end of the channel layer 514 and adjacent to the first remote dopant layer 519, and a drain electrode 517 located on the other end of the channel layer 514 and adjacent to the second remote dopant layer 520. The first remote dopant layer 519, the second remote dopant layer 520, and the third remote dopant layer 521 each include at least one boron-containing material.

[0096] Alternatively, the double-gate transistor 500 may include an insulating layer disposed between the substrate 511 and the second gate electrode 512 .

[0097] Optionally, the dual-gate transistor 500 may include a first spacer layer arranged between the channel layer 514 and the first remote dopant layer 519 , a second spacer layer arranged between the channel layer 514 and the second remote dopant layer 520 , and / or a third spacer layer arranged between the third remote dopant layer 521 and the channel layer 514 .

[0098] Figure 6Another exemplary embodiment of a dual-gate field-effect transistor 600 of the present disclosure is shown. The dual-gate transistor 600 can be formed by a deposition method and / or system as described herein. In the illustrated example, the dual-gate transistor 600 includes a substrate 611, a second gate electrode 612 located on the substrate 611, and a second gate insulating layer 613 located on the second gate electrode 612. The second gate insulating layer 613 and the second gate electrode 612 separate a third remote dopant layer 621 and a fourth remote dopant layer 622, both of which are located on the substrate 611.

[0099] The transistor 600 further includes a channel layer 614 on the second gate insulating layer 613, a first gate insulating layer 615 on the channel layer 614, and a first gate electrode 618 on the first gate insulating layer 615. The channel layer 614 includes a channel material as described herein. The first gate insulating layer 615 and the first gate electrode 618 separate a first remote dopant layer 619 and a second remote dopant layer 620, both of which are located on the channel layer 614.

[0100] The transistor 600 further includes a source electrode 616 located at one end of the channel layer 614 and adjacent to the first remote dopant layer 619 , and a drain electrode 617 located at the other end of the channel layer 614 and adjacent to the second remote dopant layer 620 .

[0101] The first remote dopant layer 619 , the second remote dopant layer 620 , the third remote dopant layer 621 , and the fourth remote dopant layer 622 each include at least one boron-containing material as described herein.

[0102] Optionally, the double-gate transistor 600 may include an insulating layer arranged between the substrate 611 and the second gate electrode 612 , an additional insulating layer arranged between the substrate 611 and the third remote dopant layer 621 , and / or an additional insulating layer arranged between the substrate 611 and the fourth remote dopant layer 622 .

[0103] Optionally, the dual-gate transistor 600 may include a first spacer layer arranged between the channel layer 614 and the first remote dopant layer 619, a second spacer layer arranged between the channel layer 614 and the second remote dopant layer 620, a third spacer layer arranged between the channel layer 614 and the third remote dopant layer 621 and the channel layer 614, and / or a fourth spacer layer arranged between the channel layer 614 and the fourth remote dopant layer 622.

[0104] It should be noted that the FETs described herein are not limited to 2D structures, but may also include three-dimensional (3D) stacked structures. Such 3D stacked structures may include multiple gate electrodes surrounding one or more channel regions including channel materials.

[0105] In a particular embodiment, the FET as disclosed herein further includes a plurality of channel layers stacked on top of each other and spatially separated; wherein each channel layer comprises a channel material; wherein the FET further includes a plurality of gate electrodes in contact with a gate insulating layer, wherein at least one gate electrode and gate insulating layer is disposed between every two channel layers; wherein the transistor further includes a plurality of remote dopant layers; wherein at least a portion of each gate electrode or gate insulating layer is electrically in contact with at least one remote dopant layer; and wherein each remote dopant layer comprises at least one boron compound configured for remotely doping the channel material of at least one channel layer.

[0106] Figure 7 Another exemplary embodiment of a 3D field-effect transistor 700 of the present disclosure is shown. The 3D transistor 700 can be formed using deposition methods and / or systems as described herein. In the illustrated example, the 3D transistor 700 includes a substrate 711, a second gate electrode 712 located on the substrate 711, a second gate insulating layer 713 located on the second gate electrode 712, and a first channel layer 714 located on the second gate insulating layer 713. The first channel layer 714 separates a source electrode 716 and a drain electrode 717, both of which are located on the second gate insulating layer 713.

[0107] The transistor 700 further includes a first gate insulating layer 715 located on the first channel layer 714 , a first gate electrode 718 located on the first gate insulating layer 715 , and a third gate insulating layer 719 located on the first gate electrode 718 .

[0108] The first gate insulating layer 715 , the first gate electrode 718 , and the third gate insulating layer 719 separate the first remote dopant layer 727 and the second remote dopant layer 728 , both of which are located on the first channel layer 714 .

[0109] The transistor 700 also includes a second channel layer 720 located on the third gate insulating layer 719, a fourth gate insulating layer 721 located on the second channel layer 720, a third gate electrode 722 located on the fourth gate insulating layer 721, a fifth gate insulating layer 723 located on the third gate electrode 722, and a third channel layer 724 located on the fifth gate insulating layer 723.

[0110] The transistor 700 further includes a sixth gate insulating layer 725 on the third channel layer 724 and a fourth gate electrode 726 on the sixth gate insulating layer 725 ; wherein each channel layer includes a channel material; and wherein each remote dopant layer includes at least one boron-containing material.

[0111] Optionally, the 3D transistor 700 may include an insulating layer disposed between the substrate 711 and the second gate electrode 712 , and / or an additional insulating layer located on the fourth gate electrode 726 .

[0112] Optionally, the 3D transistor 700 may include a first spacer layer disposed between the first channel layer 714 and the first remote dopant layer 727 , and / or a second spacer layer disposed between the first channel layer 714 and the second remote dopant layer 728 .

[0113] Optionally, the 3D transistor 700 may include a third remote dopant layer disposed between the second gate insulating layer 713 and the first channel layer 714 .

[0114] Figure 8 Another exemplary embodiment of a 3D field-effect transistor 800 of the present disclosure is shown. The 3D transistor 800 can be formed using deposition methods and / or systems as described herein. In the illustrated example, the 3D transistor 800 includes a substrate 811, a second gate electrode 812 located on the substrate 811, a second gate insulating layer 813 located on the second gate electrode 812, and a first channel layer 814 located on the second gate insulating layer 813. The first channel layer 814 separates a source electrode 816 and a drain electrode 817 located on the second gate insulating layer 813.

[0115] The transistor 800 further includes a first gate insulating layer 815 located on the first channel layer 814, a first gate electrode 818 located on the first gate insulating layer 815, and a third gate insulating layer 819 located on the first gate electrode 818. The first gate insulating layer 815, the first gate electrode 818, and the third gate insulating layer 819 separate a first remote dopant layer 827 and a second remote dopant layer 828, both of which are located on the first channel layer 814.

[0116] The transistor 800 further includes a second channel layer 820 on the third gate insulating layer 819, a fourth gate insulating layer 821 on the second channel layer 820, a third gate electrode 822 on the fourth gate insulating layer 821, and a fifth gate insulating layer 823 on the third gate electrode 822. The fourth gate insulating layer 821, the third gate electrode 822, and the fifth gate insulating layer 821 separate a third remote dopant layer 829 and a fourth remote dopant layer 830, both of which are located on the second channel layer 820.

[0117] The transistor 800 further includes a third channel layer 824 on the fifth gate insulating layer 823, a sixth gate insulating layer 825 on the third channel layer 824, and a fourth gate electrode 826 on the sixth gate insulating layer 825; wherein each channel layer includes a channel material; and wherein each remote dopant layer includes at least one boron-containing material.

[0118] Optionally, the 3D transistor 800 may include an additional insulating layer disposed between the substrate 811 and the second gate electrode 812 , and / or an additional insulating layer located on the fourth gate electrode 826 .

[0119] Optionally, the 3D transistor 800 may include a first spacer layer arranged between the first channel layer 814 and the first remote dopant layer 827, a second spacer layer arranged between the first channel layer 814 and the second remote dopant layer 828, a third spacer layer arranged between the second channel layer 820 and the third remote dopant layer 829, and / or a fourth spacer layer arranged between the second channel layer 820 and the fourth remote dopant layer 830.

[0120] Optionally, the 3D transistor 800 may include a fifth remote dopant layer disposed between the second gate insulating layer 813 and the first channel layer 814 .

[0121] Figure 9 Another exemplary embodiment of a 3D field-effect transistor 900 of the present disclosure is shown. The 3D transistor 900 can be formed using deposition methods and / or systems as described herein. In the illustrated example, the 3D transistor 900 includes a substrate 911, a second gate electrode 912 located on the substrate 911, a second gate insulating layer 913 located on the second gate electrode 912, and a first channel layer 914 located on the second gate insulating layer 913. The first channel layer 914 separates a source electrode 916 and a drain electrode 917 located on the second gate insulating layer 913.

[0122] The transistor 900 further includes a first gate insulating layer 915 located on the first channel layer 914, a first gate electrode 918 located on the first gate insulating layer 915, and a third gate insulating layer 919 located on the first gate electrode 918. The first gate insulating layer 915, the first gate electrode 918, and the third gate insulating layer 919 separate a first remote dopant layer 927 and a second remote dopant layer 928, both of which are located on the first channel layer 914.

[0123] The transistor 900 further includes a second channel layer 920 located on the third gate insulating layer 919, a fourth gate insulating layer 921 located on the second channel layer 920, a third gate electrode 922 located on the fourth gate insulating layer 921, and a fifth gate insulating layer 923 located on the third gate electrode 922. The fourth gate insulating layer 921, the third gate electrode 922, and the fifth gate insulating layer 923 separate a third remote dopant layer 929 and a fourth remote dopant layer 930, both of which are located on the second channel layer 920.

[0124] The transistor 900 also includes a third channel layer 924 located on the fifth gate insulating layer 923, a sixth gate insulating layer 925 located on the third channel layer 924, and a fourth gate electrode 926 located on the sixth gate insulating layer 925 and separating a fifth remote dopant layer 931 and a sixth remote dopant layer 932 located on the sixth gate insulating layer 925; wherein each channel layer includes a channel material; and wherein each remote dopant layer contains at least one boron-containing material.

[0125] Optionally, the 3D transistor 900 may include an additional insulating layer disposed between the substrate 911 and the second gate electrode 912 , and / or an additional insulating layer located on the fourth gate electrode 926 .

[0126] Optionally, the 3D transistor 900 may include a first spacer layer arranged between the first channel layer 914 and the first remote dopant layer 927, a second spacer layer arranged between the first channel layer 914 and the second remote dopant layer 928, a third spacer layer arranged between the second channel layer 920 and the third remote dopant layer 929, a fourth spacer layer arranged between the second channel layer 920 and the fourth remote dopant layer 930, a fifth spacer layer arranged between the sixth gate insulation layer 925 and the fifth remote dopant layer 931 and / or a sixth spacer layer arranged between the sixth gate insulation layer 925 and the sixth remote dopant layer 932.

[0127] Optionally, the 3D transistor 900 may include a seventh remote dopant layer disposed between the second gate insulating layer 913 and the first channel layer 914 .

[0128] Another aspect of the present disclosure relates to a method for fabricating at least a portion of a field effect transistor (FET), comprising the steps of: a) providing a substrate into a reaction chamber; b) performing one or more cycles, the cycles comprising a boron precursor pulse, wherein at least a portion of the substrate is contacted with at least one boron precursor by introducing the boron precursor into the reaction chamber; wherein, as a result of the cycles, at least one remote dopant layer comprising at least one boron-containing material is formed on the substrate; wherein the substrate comprises at least one channel layer, the at least one channel layer comprising channel material formed before and / or after forming the remote dopant layer, or a combination thereof; wherein the at least one remote dopant layer is configured to remotely dope the channel material of the channel layer during operation of the field effect transistor.

[0129] In certain embodiments, the (remote dopant layer formation) cycle may further comprise a reactant gas pulse, wherein at least a portion of the substrate is contacted with at least one reactant gas, preferably comprising nitrogen, by introducing the reactant gas into the reaction chamber.

[0130] In certain embodiments, the methods as disclosed herein provide that: the substrate may further include a spacer layer; and wherein the spacer layer is disposed between the channel layer and the remote dopant layer.

[0131] In certain embodiments, the method as disclosed herein provides that: the substrate may further include an insulating layer; and wherein the insulating layer is disposed between the channel layer and the substrate.

[0132] In some embodiments, wherein at least one remote dopant layer is formed before at least one channel layer comprising a channel material, the remote dopant layer may be disposed between the substrate and the channel layer comprising the channel material.

[0133] In some embodiments, wherein at least one remote dopant layer is formed after at least one channel layer comprising a channel material, the remote dopant layer may be located on the channel layer comprising the channel material. Optionally, a spacer layer may be disposed between the remote dopant layer and the channel layer comprising the channel material.

[0134] In some embodiments, wherein at least one remote dopant layer is formed before and after forming at least one channel layer comprising a channel material, the remote dopant layer may be disposed between a substrate and the channel layer comprising the channel material, and may be positioned on the channel layer comprising the channel material. Optionally, a spacer layer may be disposed between the remote dopant layer and the channel layer comprising the channel material.

[0135] In certain embodiments, as provided in the methods disclosed herein, the boron-containing material may be selected from the group consisting of boron nitride (BN), boron carbide (BC), boron carbonitride (BCN), and mixtures thereof. In some embodiments, the boron nitride (BN) may be amorphous boron nitride (aBN), polycrystalline boron nitride, and / or crystalline boron nitride. Exemplary methods for depositing boron nitride films are described in U.S. Patent Application No. 17 / 966,660, which is incorporated herein by reference except for any disclaimers and inconsistencies.

[0136] In a particular embodiment, as provided in the methods disclosed herein, at least one channel layer can be formed by: a) providing a substrate to a reaction chamber; b) performing one or more cycles, the cycles comprising: i. a transition metal precursor pulse, wherein at least a portion of the substrate is contacted with at least one transition metal precursor by introducing the transition metal precursor into the reaction chamber; ii. a chalcogenide reactant pulse, wherein at least a portion of the substrate is contacted with at least one chalcogenide reactant by introducing the chalcogenide reactant into the reaction chamber; wherein, as a result of the cycles, at least one channel layer comprising a channel material is formed on the substrate and / or the remote dopant layer, the channel material preferably being a 2D TMDC material.

[0137] In particular, the formation of at least one remote dopant layer comprising at least one boron-containing material and / or at least one channel layer comprising a channel material as described herein can involve a cyclic deposition process, such as an atomic layer deposition (ALD) process or a cyclic chemical vapor deposition (CVD) process. The cyclic deposition method includes one or more cycles.

[0138] In certain embodiments, the method disclosed herein may be an ALD method. In contrast to the sputtering technique commonly used in the prior art to deposit thin films and layers for fabricating various semiconductors and transistors, cyclic deposition processes such as ALD have been found to provide more uniform deposition across the surface of a substrate.

[0139] As used herein, the synonymous terms "deposition" or "cyclic deposition" or "cyclic deposition process" or "cyclic deposition process" refer to the sequential introduction of precursors (and / or reactants) into a reaction chamber to deposit a layer or film on a substrate, and include process techniques such as ALD, CVD, and hybrid cyclic deposition processes including ALD and CVD components. Typically, one deposition cycle can form a film or layer of approximately 0.10 nm. However, the experimental thickness can vary depending on the number and type of cycles and the available reaction sites on the substrate and / or previously deposited layers.

[0140] The term "atomic layer deposition" (ALD) refers to a vapor deposition process in which deposition cycles, typically multiple consecutive deposition cycles, are performed in a process chamber. The term atomic layer deposition as used herein is also intended to include processes designated by related terms such as chemical vapor atomic layer deposition, atomic layer epitaxy (ALE), molecular beam epitaxy (MBE), gas source MBE, organometallic MBE, and chemical beam epitaxy when performed with alternating pulses of precursor / reactant gas and purge gas (e.g., inert carrier gas).

[0141] Typically, for an ALD process, during each cycle, a precursor (e.g., a boron precursor or a transition metal precursor) is introduced into a reaction chamber and chemisorbed onto a deposition surface (e.g., a substrate surface that may include previously deposited material or other material from a previous ALD cycle) and forms a material, e.g., approximately a monolayer or sub-monolayer of material, or several monolayers of material, or multiple monolayers of material that does not readily react with another precursor (i.e., a self-limiting reaction). Thereafter, in some cases, a reactant (e.g., another precursor or reactant gas, such as a chalcogenide reactant or a nitrogen reactant) may be subsequently introduced into the process chamber. The reactant may be capable of further reacting with the precursor. During one or more repetitions, e.g., during each deposition step, a purge step may be utilized to remove any excess precursor from the process chamber and / or remove any excess reactant and / or reaction byproducts from the reaction chamber. Note that in various embodiments as described herein, an ALD process does not necessarily consist of a series of self-limiting surface reactions.

[0142] As used herein, the term "purge" may refer to the process of providing an inert or substantially inert gas to a reaction chamber between two gas pulses that react with each other. For example, a purge, such as with an inert gas (such as a noble gas), may be provided between subsequent pulses to avoid or at least minimize gas phase interactions between precursors and / or reactants.

[0143] In certain embodiments, the methods disclosed herein provide for purging the reaction chamber before and / or after each boron precursor pulse. In certain embodiments, the methods disclosed herein provide for purging the reaction chamber before and / or after each transition metal precursor pulse and chalcogenide reactant pulse.

[0144] Advantageously, the cyclic deposition process disclosed herein can be a thermal deposition process. In other words, in some embodiments, no plasma is used for either pulsing or purging in the cyclic deposition process. In the case of a thermal cyclic deposition process, the duration of the step of providing a boron precursor to the reaction chamber, the duration of the step of providing a transition metal precursor to the reaction chamber, and / or the duration of the step of providing a chalcogenide reactant to the reaction chamber can be relatively long to allow the precursors and / or reactants to react with the surface of the substrate and / or previously deposited layers. For example, the duration can be greater than or equal to 5 seconds, or greater than or equal to 10 seconds, or between approximately 5 seconds and 10 seconds.

[0145] In some embodiments, the cyclic deposition process can employ plasma enhanced deposition techniques. For example, the cyclic deposition process can include a plasma enhanced atomic layer deposition process and / or a plasma enhanced chemical vapor deposition process. In this case, any one of the pulses in the cyclic deposition process can include generating a plasma in the reaction chamber.

[0146] In some embodiments, the methods disclosed herein can be continuous vacuum deposition processes. In the context of a continuous vacuum deposition process, a material is deposited onto a substrate in a reaction chamber without introducing atmospheric air or any interruption that would disrupt the controlled vacuum environment. The process involves maintaining a consistent vacuum pressure within the reaction chamber.

[0147] In certain embodiments, the methods disclosed herein provide that a remote dopant layer can be formed without any intermediate vacuum breaks. In certain embodiments, the methods disclosed herein provide that at least one channel layer and at least one remote dopant layer can be formed in the same reaction chamber without any intermediate vacuum breaks. This has the advantage that the present disclosure avoids the need for repeated evacuation and purging of the reaction chamber, which is common in traditional batch deposition methods.

[0148] In particular embodiments, the method for forming at least one remote dopant layer comprising at least one boron-containing material and / or at least one channel layer comprising a channel material as disclosed herein may include at least 1 cycle, at least 2 cycles, at least 5 cycles, at least 10 cycles, at least 20 cycles, at least 40 cycles, at least 100 cycles, at least 200 cycles, at least 400 cycles, at least 600 cycles, at least 1000 cycles.

[0149] In some embodiments, steps may be repeated for at least 1 cycle to at most 1000 cycles, or at least 2 cycles to at most 100 cycles, or at least 5 cycles to at most 50 cycles.

[0150] In a particular embodiment, as provided by the methods disclosed herein, the remote dopant layer may have an average thickness of between 0.05 nm and 2.0 nm, or between 0.10 nm and 2.0 nm, or between 0.10 nm and 1.75 nm, or between 0.10 nm and 1.50 nm, or between 0.10 nm and 1.25 nm, preferably between 0.10 nm and 1.0 nm, or between 0.20 nm and 1.0 nm, or between 0.25 nm and 1.0 nm.

[0151] In specific embodiments, as provided by the methods disclosed herein: the channel layer may have an average thickness of between 0.05 nm and 2.0 nm, or between 0.10 nm and 2.0 nm, or between 0.10 nm and 1.75 nm, or between 0.10 nm and 1.50 nm, or between 0.10 nm and 1.25 nm, preferably between 0.10 nm and 1.0 nm, or between 0.20 nm and 1.0 nm, or between 0.25 nm and 1.0 nm.

[0152] In some embodiments, at least one remote dopant layer comprising at least one boron-containing material and / or at least one channel layer comprising a channel material can have a growth rate of 0.10 nm or less per cycle of a precursor / reactant gas and a purge gas (e.g., an inert carrier gas). Lower layer thicknesses may be desirable for many electronic applications, including transistors.

[0153] The methods disclosed herein rely on performing one or more cycles to grow at least one thin film remote dopant layer, and in some embodiments, at least one channel layer. Exemplary cycles for forming remote dopant layers are described in U.S. Patent Application No. 17 / 966,660, which is incorporated herein by reference except for any disclaimers and inconsistencies.

[0154] A cycle can include one or more pulses. In some embodiments, at least one pulse involves a self-limiting surface reaction. In some embodiments, all pulses involve self-limiting surface reactions. In the context of the present invention, a self-limiting surface reaction refers to a chemical reaction that automatically stops or slows down once a certain threshold or coverage is reached on the surface, for example, once a complete monolayer or sub-monolayer is formed, the reaction stops by preventing further reaction with additional precursors. In some embodiments, a cycle includes one or more precursor pulses and / or one or more reactant pulses.

[0155] In some embodiments, a cycle for growing a channel layer can include the following pulse sequence: a transition metal precursor pulse and a chalcogenide reactant pulse. In the transition metal precursor pulse, one or more transition metal precursors are provided to the reaction chamber and can be chemisorbed to the substrate (i.e., adhere to atoms or molecules on the surface of the substrate and form chemical bonds therewith). In the chalcogenide reactant pulse, one or more chalcogenide reactants are provided to the reaction chamber and can react with the chemisorbed transition metal to form a channel material or layer on at least a portion of the substrate. The number of cycles of the method disclosed herein determines the total thickness of the deposited channel layer. An advantage of the presently disclosed cyclic deposition process is precise control of the total layer thickness and dopant incorporation.

[0156] Figure 10 An exemplary embodiment of a method as described herein for fabricating at least a portion of a field effect transistor as disclosed herein is described. The method begins after a substrate has been provided to a reaction chamber 1011. A cyclic deposition process includes providing a reactant gas into the reaction chamber in a reactant gas pulse 1012. Optionally, the reaction chamber is purged 1013 after the reactant gas pulse 1012.

[0157] Then, a plasma is formed using the reactant gas 1014, and one or more boron precursors are brought into contact with at least a portion of the substrate with a boron precursor pulse 1015. Optionally, the boron precursor pulse may be followed by a purge of the reaction chamber 1016. The sequence of reactant gas pulse 1012, plasma formation 1014, boron precursor pulse 1015, and optional purges 1013, 1016 may be repeated 1017 any number of times to obtain a desired thickness of the remote dopant layer as disclosed.

[0158] When a remote dopant layer having a desired thickness is formed based on any combination of the aforementioned steps, the method ends 1018. Once the method ends, the substrate may be subjected to additional processes known in the art for forming device structures and / or devices.

[0159] It should be noted that the reactant gas pulse 1012, the formation of the plasma 1014, and the boron precursor pulse 1015 can overlap in a cycle. In addition, the order of each method step (1012 to 1016) within each cycle can be varied. For example, in another exemplary embodiment, a cycle can include the sequential steps of a boron precursor pulse, a reactant gas pulse, and plasma formation.

[0160] Figure 11An exemplary embodiment of a method as described herein for fabricating at least a portion of a field effect transistor as disclosed herein is described. The method begins after a substrate has been provided to a reaction chamber 1111. A cyclic deposition process includes contacting one or more transition metal precursors with at least a portion of the substrate with a transition metal precursor pulse 1112. Optionally, the reaction chamber is purged 1113 after the transition metal precursor pulse 1112. One or more chalcogenide reactants are then provided to the reaction chamber 1114 with a chalcogenide reactant pulse. Optionally, the reaction chamber can be purged 1115 after the chalcogenide reactant pulse.

[0161] The transition metal precursor pulse 1112 , the chalcogenide reactant pulse 1114 , and the optional purges 1113 , 1115 may be repeated 1116 any number of times to obtain a channel layer of the desired thickness.

[0162] When a remote dopant layer having a desired thickness is formed based on any combination of the aforementioned steps, the method ends 1117. Once the method ends, the substrate can be subjected to additional processes known in the art for forming device structures and / or devices.

[0163] It should be noted that the transition metal precursor pulse 1112 and the chalcogenide reactant pulse 1114 can overlap in a cycle. Furthermore, the order of each method step (1112 to 1115) within each cycle can be varied. For example, and in another exemplary embodiment, a cycle can include consecutive steps of a chalcogenide reactant pulse and a transition metal precursor pulse. Thus, the chalcogenide reactant pulse can precede the transition metal precursor pulse.

[0164] In certain embodiments, the methods disclosed herein provide that the boron precursor pulse, transition metal precursor pulse, chalcogenide reactant pulse, and / or reactant gas pulse comprise a plurality of micropulses. As used herein, a "micropulse" is a short period during which one or more boron precursors, one or more transition metal precursors, one or more chalcogenide reactants, and / or one or more reactant gases can be introduced into the reaction chamber. Thus, the methods disclosed herein provide a high degree of flexibility in pulse sequences and lengths, thereby providing a cost-effective and more efficient method than methods disclosed in the prior art.

[0165] In some embodiments, the boron precursor pulse and / or the transition metal precursor pulse may last at least 0.01 s to at most 120 s, or at least 0.01 s to at most 0.1 s, or at least 0.01 s to at most 0.02 s, or at least 0.02 s to at most 0.05 s, or at least 0.05 s to at most 0.1 s, or at least 0.1 s to at most 20 s, or at least 0.1 s to at most 0.2 s, or at least 0.2 s to at most 0.5 s, or at least 0.5 s to at most 1.0 s, or at least 1.0 s to at most 2.0 s, or at least 2.0 s to at most 5.0 s, or at least 5.0 s to at most 10.0 s, or at least 10.0 s to at most 20.0 s.

[0166] In some embodiments, the chalcogenide reactant pulse and / or reactant gas pulse may last at least 0.1 s to at most 20 s, or at least 0.1 s to at most 0.2 s, or at least 0.2 s to at most 0.5 s, or at least 0.5 s to at most 1.0 s, or at least 1.0 s to at most 2.0 s, or at least 2.0 s to at most 5.0 s, or at least 5.0 s to at most 10.0 s, or at least 10.0 s to at most 20.0 s, or at least 20.0 s to at most 120.0 s, or at least 20.0 s to at most 50.0 s, or at least 50.0 s to at most 80.0 s, or at least 80.0 s to at most 120.0 s.

[0167] It should be understood that any two steps and / or pulses and / or micropulses can be separated by a purge. Thus, in some embodiments, a boron precursor pulse and / or a transition metal precursor pulse and a chalcogenide reactant pulse and / or a reactant gas pulse can be separated by a purge. In some embodiments, subsequent cycles are separated by a purge.

[0168] In certain embodiments, the reaction chamber can be purged before and / or after the boron precursor pulse, the transition metal precursor pulse, the chalcogenide reactant pulse, and / or the reactant gas pulse. Purging the reaction chamber before and / or after each precursor pulse and / or reactant pulse has the advantage of removing any residual precursors, reactants, and / or reaction byproducts, thereby avoiding cross-contamination between pulses and producing a film or layer with high purity and few defects.

[0169] In some specific embodiments, one or more channel layers and one or more remote dopant layers can be formed in the same reaction chamber. In some embodiments, one or more channel layers and one or more remote dopant layers can be formed continuously in the same reaction chamber, preferably without any intermediate vacuum break.

[0170] In some specific embodiments, one or more channel layers and one or more remote dopant layers may be formed in separate reaction chambers.

[0171] In the present disclosure, at least one boron-containing material contained in the remote dopant layer is intentionally included to create “charge storage sites” or “charge traps” within the remote dopant layer. These charge storage sites can control the capture and release of charge carriers such as electrons or holes.

[0172] It is demonstrated that one or more boron-containing materials can be used to achieve remote doping of at least a portion of a channel material of a channel layer during operation of a field-effect transistor. In particular, without being limited to a particular theory, a cyclic deposition process as disclosed herein can provide advantages by allowing the stoichiometry of the boron compound to be modulated under specific deposition conditions. This modulation is believed to provide positive or negative (trapped) charge in the remote dopant layer.

[0173] Thus, in some specific embodiments, the boron compound can be a p-type dopant and / or an n-type dopant.

[0174] In some specific embodiments, the remote dopant layer may include one or more trapped charges.

[0175] Various boron precursors may be suitable for use in forming a remote dopant layer comprising at least one boron-containing material.

[0176] In some specific embodiments, the methods disclosed herein may provide that the boron precursor is represented by the following general formula (I):

[0177]

[0178] Among them, R 1 、R 2 、R 3 、R 4 、R 5 、R 6 Each is independently selected from hydrogen, halogen, alkyl, alkenyl and alkoxy.

[0179] The term "halo" or "halogen" as a group or part of a group is generic for fluorine (F), chlorine (Cl), bromine (Br), iodine (I).

[0180] The term "alkyl" as a group or part of a group refers to a group of formula C n H 2n+1 wherein n is a number greater than or equal to 1. The alkyl group may be straight or branched and may be substituted as indicated herein. Typically, the alkyl groups of the present disclosure contain 1 to 20 carbon atoms, preferably 1 to 10 carbon atoms, preferably 1 to 8 carbon atoms, preferably 1 to 6 carbon atoms, and more preferably 1 to 4 carbon atoms. When a subscript is used after a carbon atom herein, the subscript refers to the number of carbon atoms that the named group may contain. For example, the term "C" as a group or part of a group 1-20 "Alkyl" refers to a group having the formula -Cn H 2n+1 wherein n is a number ranging from 1 to 20. Thus, for example, "C 1-8 "Alkyl" includes all straight or branched chain alkyl groups having 1 to 8 carbon atoms, and thus includes methyl, ethyl, n-propyl, isopropyl, butyl and isomers thereof (e.g., n-butyl, isobutyl and tert-butyl); pentyl and isomers thereof, hexyl and isomers thereof, etc. "Substituted alkyl" refers to an alkyl group substituted with one or more substituents (e.g., 1 to 3 substituents, such as 1, 2 or 3 substituents) at any available point of attachment.

[0181] When the suffix "sub" is used in conjunction with an alkyl group, i.e., "alkylene," this is intended to indicate an alkyl group, as defined herein, having two single bonds as points of attachment to other groups. As used herein, the term "alkylene," also known as "alkanediyl," by itself or as part of another substituent, refers to a divalent alkyl group, i.e., having two single bonds for attachment to two other groups. Alkylene groups may be straight or branched and may be substituted as indicated herein. Non-limiting examples of alkylene groups include methylene (-CH2-), ethylene (-CH2-CH2-), methylmethylene (-CH(CH3)-), 1-methyl-ethylene (-CH(CH3)-CH2-), n-propylene (-CH2-CH2-CH2-), 2-methylpropylene (-CH2-CH(CH3)-CH2-), 3-methylpropylene (-CH2-CH2-CH(CH3)-), n-butylene (-CH2-CH2-CH2-CH2-), 2-methylbutylene (-CH2-CH(CH3)-CH2-CH2-CH2-), 4-methylbutylene (-CH2-CH2-CH2-CH(CH3)-), pentylene and its chain isomers, hexylene and its chain isomers.

[0182] The term "alkenyl" as a group or part of a group refers to an unsaturated hydrocarbon group, which may be straight or branched, containing one or more carbon-carbon double bonds. Typically, the alkenyl groups of the present disclosure contain 3 to 20 carbon atoms, preferably 3 to 10 carbon atoms, and preferably 3 to 8 carbon atoms. When a subscript is used after a carbon atom herein, the subscript refers to the number of carbon atoms that the named group may contain. 3-20 Examples of alkenyl groups are ethenyl, 2-propenyl, 2-butenyl, 3-butenyl, 2-pentenyl and isomers thereof, 2-hexenyl and isomers thereof, 2,4-pentadienyl and the like.

[0183] The term "alkoxy", as a group or part of a group, refers to a group having the formula -OR b A group in which R bis an alkyl group as defined above. Non-limiting examples of suitable alkoxy groups include methoxy, ethoxy, propoxy, isopropoxy, butoxy, isobutoxy, sec-butoxy, tert-butoxy, pentyloxy and hexyloxy.

[0184] Where an alkylene group is present, the connection to the molecular structure to which it forms a part may be through a common carbon atom or different carbon atoms. To illustrate this, using the asterisk nomenclature of the present disclosure, a C3 alkylene group may be, for example, *-CH2CH2CH2-*, *-CH(-CH2CH3)-* or *-CH2CH(-CH3)-*.

[0185] In some embodiments, the methods disclosed herein provide that for one or more boron precursors represented by formula (I), the alkyl group is C 1-8 Alkyl, and more specifically C 1-4 More particularly, the alkyl group is a C1, C2, C3, C4, C5, C6, C7 and / or C8 alkyl group.

[0186] In some embodiments, the methods disclosed herein provide that for one or more boron precursors represented by formula (I), the alkenyl group is C 2-8 Alkenyl, and more specifically C 2-4 More particularly, the alkenyl group is a C2, C3, C4, C5, C6, C7 and / or C8 alkenyl group.

[0187] In some embodiments, the methods disclosed herein provide that for one or more boron precursors represented by formula (I), the alkoxy group is C 1-8 Alkoxy, and more precisely C 1-4 More particularly, the alkoxy group is a C1, C2, C3, C4, C5, C6, C7 and / or C8 alkoxy group.

[0188] In some embodiments, the present disclosure provides that R 1 、R 2 、R 3 、R 4 、R 5 、R 6 are each independently selected from hydrogen, halogen, C 1-8 Alkyl, C 2-8 Alkenyl and C 1-8 Alkoxy.

[0189] In some embodiments, the present disclosure provides that R 1 、R 2 、R 3 、R 4 、R 5 、R 6 are each independently selected from hydrogen, halogen, C 1-4Alkyl, C 2-4 Alkenyl and C 1-4 Alkoxy.

[0190] In certain embodiments, methods as disclosed herein provide that the one or more boron precursors may include borazine or a substituted borazine.

[0191] In some specific embodiments, the methods disclosed herein may provide that the boron precursor is selected from the group consisting of: BF3, BCl3, BBr3, BI3, BH3, B2H6, B4H 10 、B5H9、B 10 H 14 and mixtures thereof. In the case where the boron precursor does not contain nitrogen, a reactant gas containing nitrogen may be supplied to the reaction chamber. In some embodiments, the reactant gas may contain NH 3 .

[0192] In various embodiments, a reactant gas comprising one or more of an argon-containing gas and a helium-containing gas may be used during deposition of one or more boron precursors on a surface of a substrate. In various embodiments, the reactant gas may further comprise hydrogen and / or nitrogen. In various embodiments, the reactant gas may comprise at least one of 30-99% argon and / or helium and 1-70% hydrogen. In various embodiments, the reactant gas may comprise at least one of 10-90% argon and 10-90% nitrogen.

[0193] In the present disclosure, one or more transition metal precursors may adhere to and bond to a substrate to initiate the formation of one or more channel layers including a channel material.

[0194] In a particular embodiment, the channel material may include a transition metal dichalcogenide selected from the group consisting of MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, NbS2, NbSe2, NbTe2, VS2, VSe2, VTe2, ReS2, ReTe2, TaS2, TaSe2, TaTe2, and mixtures thereof.

[0195] In certain embodiments, the methods disclosed herein provide that the transition metal precursor may comprise a transition metal in oxidation state +4. Preferably, the transition metal element is selected from the group consisting of at least one of Mo, W, Nb, V, Re, and Ta.

[0196] In certain embodiments, the methods disclosed herein provide that the chalcogenide reactant is selected from the group consisting of H2S, H2S plasma, H2Se, Et2Se, Se2(Si(i-Pr)2)2, [(CH3)3Si]2Se, [(CH3)3Si]2Te, Te[Oi-Pr]4, and mixtures thereof.

[0197] The methods disclosed herein can be performed at different temperatures and / or pressures. In certain embodiments, the methods disclosed herein provide that the substrate can be heated to a temperature of about 80° C. to about 400° C., or about 100° C. to about 400° C., or about 125° C. to about 400° C., preferably about 150° C. to about 400° C., or about 175° C. to about 400° C., preferably about 200° C. to about 400° C., or about 250° C. to about 400° C., or about 300° C. to about 400° C. The temperatures listed can reduce the time required for material deposition, although lower or higher temperatures are still contemplated.

[0198] In certain embodiments, the methods disclosed herein provide that the pressure in the reaction chamber is between about 0.1 Torr and about 100.0 Torr, or between about 0.5 Torr and about 100.0 Torr, or between about 1.0 Torr and about 100.0 Torr, or between about 2.0 Torr and about 100.0 Torr, or between about 5.0 Torr and about 100.0 Torr, or between about 5.0 Torr and about 80.0 Torr, or preferably between about 5.0 Torr and about 50.0 Torr, or between about 10.0 Torr and about 50.0 Torr. The listed pressures can reduce the time required for material deposition, although lower or higher pressures are still contemplated.

[0199] Remote dopant layer and / or channel layer can be formed in any suitable reactor.Therefore, in some embodiments, remote dopant layer and / or channel layer are deposited in a cross-flow reactor.In certain embodiments, remote dopant layer and / or channel layer are deposited in a showerhead reactor.In certain embodiments, remote dopant layer and / or channel layer are deposited in a hot wall reactor.In certain embodiments, remote dopant layer and / or channel layer are deposited in a cold wall reactor.Doing so can advantageously enhance the uniformity and / or repeatability of remote dopant layer and / or channel layer deposition process.

[0200] In some embodiments, after the cyclic deposition process, the substrate is subjected to an annealing step in an environment comprising hydrogen and nitrogen. Suitably, the annealing step may be performed at a temperature of at least 300° C. to at most 600° C. Alternatively, the annealing step may be performed at a temperature of at least 300° C. to at most 1000° C.

[0201] In some embodiments, the boron precursor, transition metal precursor, and / or chalcogenide reactant are provided to the reaction chamber with the aid of a carrier gas. Exemplary carrier gases include nitrogen (N2) and noble gases such as He, Ne, Ar, Xe, or Kr.

[0202] The continuous substrate may extend beyond the boundaries of the processing / reaction chamber where the deposition process occurs. In some processes, the continuous substrate may be moved through the processing chamber, such that the process continues until the end of the substrate is reached. The continuous substrate may be supplied from a continuous substrate feed system to allow for the manufacture and output of the continuous substrate in any suitable form. Non-limiting examples of the continuous substrate may include a sheet or a flexible material. The continuous substrate may also include a carrier or sheet onto which the discontinuous substrate is mounted.

[0203] Another aspect of the present disclosure relates to a system for fabricating at least a portion of a field effect transistor, the system comprising: a reaction chamber constructed and arranged to hold a substrate; a boron precursor container constructed and arranged to contain and evaporate at least one boron precursor; optionally, a reactant gas container and a plasma power source; a transition metal precursor container constructed and arranged to contain and evaporate at least one transition metal precursor; a chalcogenide reactant container constructed and arranged to contain and evaporate at least one chalcogenide reactant; a controller operably connected to the boron precursor container, the transition metal precursor container, and the chalcogenide reactant container; wherein the controller is configured to control the introduction of the boron precursor, the transition metal precursor, and the chalcogenide reactant into the reaction chamber during one or more cycles; wherein, as a result of the cycling, at least one remote dopant layer comprising a boron-containing material and at least one channel layer comprising a channel material are formed on the substrate; and wherein the remote dopant layer is configured to remotely dope the channel material included in the channel layer during operation of the field effect transistor.

[0204] A controller configured to precisely control the introduction of precursor and reactant gases can be particularly beneficial for executing well-controlled chemical reactions that can result in more uniform and reproducible thin films or layers. Furthermore, the controller can adjust flow rates and timing to optimize reaction kinetics, thereby producing desired film properties, such as a specific composition of boron-containing material in a remote dopant layer.

[0205] In some embodiments, the boron precursor, transition metal precursor, optional reactant gas, and / or chalcogenide reactant are provided to the reaction chamber from a temperature-controlled container. In some embodiments, the temperature-controlled container is configured to cool the precursors and / or reactants. In some embodiments, the temperature-controlled container is configured to heat the precursors and / or reactants. In some embodiments, the temperature-controlled container is maintained at a temperature of at least -50°C to at most 20°C, or at a temperature of at least 20°C to at most 250°C, or at least 100°C to at most 200°C.

[0206] In certain embodiments, a system as disclosed herein is configured to fabricate a field effect transistor as disclosed herein.

[0207] In certain embodiments, a system as disclosed herein is configured for forming at least a portion of a field effect transistor by means of a method as disclosed herein.

[0208] Figure 12 Schematically depicted is a system 1200 according to a further exemplary embodiment of the present disclosure. The system 1200 may be used to perform methods as described herein and / or form transistors or device portions as described herein.

[0209] In the illustrated example, system 1200 includes one or more reaction chambers 1202 , a boron precursor gas source 1204 , a transition metal precursor source 1206 , a chalcogenide reactant source 1208 , a purge gas source 1210 , an exhaust 1212 , and a controller 1214 .

[0210] The reaction chamber 1202 can include any suitable reaction chamber, such as an ALD or CVD reaction chamber. Optionally, the system 1200 includes additional gas sources, such as a reactant gas source 1207 and a vacuum power supply 1209.

[0211] Boron precursor gas source 1204 can include a container and one or more boron precursors as described herein, either alone or mixed with one or more carrier gases (e.g., inert gases). Transition metal precursor gas source 1206 can include a container and one or more transition metal precursors as described herein, either alone or mixed with one or more carrier gases. Chalcogenide reactant gas source 1208 can include a container and one or more nitrogen reactants as described herein, either alone or mixed with one or more carrier gases. Purge gas source 1210 can include one or more inert gases, such as N2 or a noble gas, as described herein. System 1200 can include any suitable number of gas sources. Gas sources 1204-1210 can be coupled to reaction chamber 1202 via lines 1216-1222, each of which can include a flow controller, a valve, a heater, etc. Exhaust 1212 can include one or more vacuum pumps.

[0212] Controller 1214 may include electronic circuitry and software to selectively operate valves, manifolds, heaters, pumps, and other components included in system 1200. Such circuitry and components operate to introduce precursor, reactant, and purge gases from respective sources 1204-1210. Controller 1214 may control the timing of gas pulse sequences, the temperature of the substrate and / or reaction chamber, the pressure within the reaction chamber, and various other operations to provide proper operation of system 1200.

[0213] The controller 1214 may include control software to electrically or pneumatically control valves to control the flow of precursors, reactants (e.g., chalcogenide reactants), and purge gases into and out of the reaction chamber 1202. The controller 1214 may include modules that perform certain tasks, such as software or hardware components, such as FPGAs or ASICs. The modules may advantageously be configured to reside on an addressable storage medium of the control system and to execute one or more processes.

[0214] Other configurations of system 1200 are possible, including different numbers and types of precursor and reactant sources and purge gas sources. Furthermore, it should be understood that there are many arrangements of valves, conduits, precursor sources, and purge gas sources that can be used to achieve the goal of selectively feeding gases into reaction chamber 1202. Furthermore, as a schematic representation of the system, many components have been omitted for simplicity of illustration, and such components may include, for example, various valves, manifolds, purifiers, heaters, containers, vents, and / or bypasses.

[0215] During operation of reactor system 1200, a substrate, such as a semiconductor wafer (not shown), is transferred from, for example, a substrate handling system to reaction chamber 1202. Once the substrate is transferred to reaction chamber 1202, one or more gases, such as precursors, reactants, carrier gases, and / or purge gases, are introduced into reaction chamber 1202 from gas sources 1204-1210.

[0216] Furthermore, embodiments of the controller may include a combination of hardware, software, and electronic components or modules, and for purposes of discussion, may be depicted as being primarily implemented in hardware. However, upon reading this detailed description, one of ordinary skill in the art will recognize that, in at least one embodiment, the electronic-based aspects of the present disclosure may be implemented in software (e.g., instructions stored on a non-transitory computer-readable medium) that is executable by one or more processing units (e.g., microprocessors and / or application specific integrated circuits).

[0217] The subject matter of the present disclosure includes all novel and nonobvious combinations and subcombinations of the various processes, systems and configurations, and other features, functions, acts, and / or properties disclosed herein, as well as any and all equivalents thereof.

[0218] The illustrations presented herein are not intended to be actual views of any particular material, structure, or device, but are merely idealized representations used to describe embodiments of the present disclosure.

[0219] The specific embodiments shown and described are illustrative of the present disclosure and its best mode and are not intended to limit the scope of the various aspects and embodiments in any other way. In fact, for the sake of brevity, the conventional manufacturing, connection, preparation and other functional aspects of the system may not be described in detail. In addition, the connecting lines shown in the various figures are intended to represent exemplary functional relationships and / or physical connections between various elements. Many alternative or additional functional relationships or physical connections may exist in actual systems and / or may not exist in some embodiments.

[0220] It should be understood that the configurations and / or methods described herein are exemplary in nature, and these specific embodiments or examples should not be considered restrictive, as many variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. Therefore, the various actions shown may be performed in the order shown, in other orders, or in some cases omitted.

Claims

1. A method for manufacturing at least a portion of a field effect transistor (FET), comprising the steps of: a) providing a substrate into a reaction chamber; b) performing one or more cycles comprising: a boron precursor pulse, wherein at least a portion of the substrate is contacted with at least one boron precursor by introducing the boron precursor into the reaction chamber, and a reactant gas pulse, wherein at least a portion of the substrate is contacted with at least one reactant gas by introducing the reactant gas into the reaction chamber; wherein, as a result of the cycling, at least one remote dopant layer comprising at least one boron-containing material is formed on the substrate; wherein the substrate comprises at least one channel layer, the at least one channel layer comprising a channel material formed before or after forming the remote dopant layer, or a combination thereof; and The remote dopant layer is configured to remotely dope a channel material of the channel layer during operation of the field effect transistor.

2. The method according to claim 1, wherein The boron precursor is represented by the following general formula (I): Among them, R 1 、R 2 、R 3 、R 4 、R 5 、R 6 Each is independently selected from hydrogen, halogen, alkyl, alkenyl and alkoxy.

3. The method according to claim 1, wherein R 1 、R 2 、R 3 、R 4 、R 5 、R 6 are each independently selected from hydrogen, halogen, C 1-8 Alkyl, C 2-8 Alkenyl and C 1-8 Alkoxy.

4. The method according to claim 1, wherein R 1 、R 2 、R 3 、R 4 、R 5 、R 6 are each independently selected from hydrogen, halogen, C 1-4 Alkyl, C 2-4 Alkenyl and C 1-4 Alkoxy.

5. The method according to claim 1, wherein The boron precursor is selected from BF3, BCl3, BBr3, BI3, BH3, B2H6, B4H 10 、B5H9、B 10 H 14 and mixtures thereof.

6. The method according to claim 1, wherein The boron-containing material is selected from boron nitride (BN), boron carbide (BC), boron carbonitride (BCN) and mixtures thereof.

7. The method according to claim 1, wherein The method is an atomic layer deposition (ALD) method.

8. The method according to claim 1, wherein The remote dopant layer is formed without any intermediate vacuum break.

9. The method according to claim 1, wherein The substrate is heated to a temperature of about 80°C to about 400°C.

10. The method according to claim 1, wherein The channel material includes a transition metal dichalcogenide selected from the following: MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, NbS2, NbSe2, NbTe2, VS2, VSe2, VTe2, ReS2, ReSe2, ReTe2, TaS2, TaSe2, TaTe2 and mixtures thereof.

11. The method according to claim 1, wherein The channel material includes graphene.

12. The method according to claim 1, wherein The remote dopant layer has an average thickness between 0.05 nm and 2.0 nm.

13. The method according to claim 1, wherein The at least one channel layer is formed by: a) providing the substrate to the reaction chamber; b) executing one or more loops, each of which includes: i. a transition metal precursor pulse, wherein at least a portion of the substrate is contacted with at least one transition metal precursor by introducing the transition metal precursor into the reaction chamber; ii. a chalcogenide reactant pulse, wherein at least a portion of the substrate is contacted with at least one chalcogenide reactant by introducing the chalcogenide reactant into the reaction chamber; and Wherein, as a result of the cycling, at least one channel layer comprising a channel material is formed on at least one of the substrate and the remote dopant layer.

14. The method according to claim 13, wherein The at least one channel layer and the remote dopant layer are formed in the same reaction chamber without any intermediate vacuum break.

15. The method according to claim 13, wherein The transition metal precursor comprises a transition metal in an oxidation state of +4.

16. The method according to claim 13, wherein: The transition metal precursor includes at least one transition metal element selected from the group consisting of Mo, W, Nb, V, Re, and Ta.

17. The method according to claim 13, wherein: The chalcogenide reactant is selected from H2S, H2S plasma, H2Se, Et2Se, Se2(Si(i-Pr)2)2, [(CH3)3Si]2Se, [(CH3)3Si]2Te and Te[Oi-Pr]4.

18. A system for manufacturing at least a portion of a field effect transistor, comprising: a reaction chamber constructed and arranged to hold a substrate; a boron precursor vessel constructed and arranged to contain and vaporize at least one boron precursor; a transition metal precursor vessel constructed and arranged to contain and vaporize at least one transition metal precursor; a chalcogenide reactant vessel constructed and arranged to contain and vaporize at least one chalcogenide reactant; a controller operably connected to the boron precursor container, the transition metal precursor container, and the chalcogenide reactant container; wherein the controller is configured to control the introduction of the boron precursor, the transition metal precursor, and the chalcogenide reactant into the reaction chamber during one or more cycles; and wherein, as a result of the cycling, at least one remote dopant layer comprising a boron-containing material and at least one channel layer comprising a channel material are formed on the substrate; and wherein the remote dopant layer is configured to remotely dope the channel material included in the channel layer during operation of the field effect transistor.

19. The system according to claim 18, wherein: The system is configured to form at least a portion of a field effect transistor.

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