Pixel device based on half-floating gate, manufacturing method thereof, and image sensor

Abstract

The present invention provides a pixel device based on a semi-floating gate, a manufacturing method thereof, and an image sensor, comprising a deep well and a trench transistor; the active area of ​​the trench transistor is adjacent to the deep well, the source is located on the top surface of the active area, and is separated from the deep well by a semi-floating gate; the drain is located on the top surface of the deep well away from the active area; the semi-floating gate covers part of the surface of the deep well, is partially embedded in the active area, and is separated from the sidewalls of the deep well and the active area by a first oxide layer. The deep well acts as a photodiode, so that when the deep well is exposed to a light source, carriers generate photocurrent, and holes are collected by the semi-floating gate, causing a change in potential, thereby obtaining light information. The pixel device can realize all operations of a single pixel through a single transistor, effectively increasing the pixel's photosensitive area. The manufacturing process of the pixel device is fully compatible with standard CMOS technology, solving the problem of how to manufacture a 1T pixel device with strong light response based on the existing CMOS manufacturing process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a pixel device based on a semi-floating gate, a manufacturing method thereof, and an image sensor. Background Art

[0002] With the widespread adoption of CMOS image sensors (CIS) in fields such as new energy vehicles and smartphones, market demand has grown significantly. This trend is driving demand for image sensors with higher integration, enhanced photosensitivity, and a wider dynamic range. Traditional image sensor pixels typically consist of a photodiode and multiple transistors (such as 3T1P and 4T1P structures). This results in the pixel array occupying a large chip area, limiting the development of high-integration CISs.

[0003] Reducing the number of transistors within an image sensor pixel is an effective approach to shrinking its size. Single-transistor active-pixel sensors (1T-APSs) are an innovative solution that demonstrates their compact design advantages, significantly reducing pixel size and improving fill factor. Related technologies include 1T charge modulation technology based on metal-oxide-semiconductor field-effect transistors (MOSFETs), 1T tunneling field-effect transistors (TFETs), 1T phototransistors using germanium gratings, and 1T device technologies based on silicon-on-insulator (SOI).

[0004] However, due to its special structure or the materials used, existing 1T device technology is not compatible with existing standard CMOS manufacturing processes; moreover, the light absorption layer in existing 1T devices is relatively shallow, resulting in insufficient device sensitivity and limiting the ability to respond to strong light; in addition, existing 1T devices usually have high power consumption. Summary of the Invention

[0005] The purpose of the present invention is to provide a pixel device based on a semi-floating gate, a manufacturing method thereof, and an image sensor, so as to solve the problem of how to manufacture a 1T pixel device with strong light response based on the existing CMOS manufacturing process.

[0006] In order to solve the above technical problems, the present invention provides a pixel device based on a semi-floating gate, comprising a deep well and a trench transistor formed between two adjacent shallow trench isolations; the trench transistor comprises an active area, a source, a drain, a semi-floating gate and a control gate; the active area is adjacent to the deep well; the source is located on the top surface of the active area and is separated from the deep well by the semi-floating gate; the drain is located on the top surface of the deep well away from the active area; the semi-floating gate covers part of the surface of the deep well and is partially embedded in the active area, and is separated from the sidewall of the deep well and the active area by a first oxide layer; a second oxide layer and the control gate are sequentially formed on the top surface of the semi-floating gate.

[0007] Optionally, in the pixel device based on the semi-floating gate, the deep well is an N-type doped deep N-well; the active area is lightly P-type doped; the source, the drain and the control gate are heavily N-type doped; and the semi-floating gate is P-type doped.

[0008] Optionally, in the pixel device based on the semi-floating gate, the doping ions of the deep N-well are phosphorus; the doping ions of the source, the drain and the control gate are arsenic, and the doping concentration of the source and the drain is 4.5×10 2 cm -3 The doping ion of the semi-floating gate is boron, and the doping concentration is 1×10 18 cm -3 .

[0009] Optionally, in the semi-floating gate-based pixel device, the pitch of the pixel device is 1.8 μm; the depth of the deep well is greater than 4 μm; the thickness of the first oxide layer is 5 to 10 nm; and the thickness of the second oxide layer is 10 to 15 nm.

[0010] Optionally, in the pixel device based on the semi-floating gate, sidewalls of the semi-floating gate, sidewalls of the second oxide layer, and sidewalls of the control gate are formed with spacers.

[0011] To solve the above technical problems, the present invention further provides a method for manufacturing a pixel device based on a half-floating gate, for manufacturing a pixel device based on a half-floating gate as described in any one of the above items, the manufacturing method comprising:

[0012] forming shallow trench isolations on the basic device, wherein a basic active area is formed between two adjacent shallow trench isolations;

[0013] A deep well is formed on the left side of the base active region and an active region is formed on the right side;

[0014] forming a drain electrode on the surface of the deep well and a source electrode on the surface of the active area;

[0015] forming a half-floating gate so that the half-floating gate covers a portion of the surface of the deep well and is partially embedded in a side of the active region close to the deep well;

[0016] A second oxide layer and a control gate are sequentially formed on the surface of the semi-floating gate.

[0017] Optionally, in the method for manufacturing a pixel device based on a half-floating gate, the method of forming a deep well on the left side of the basic active area and forming an active area on the right side includes:

[0018] Ion implantation and annealing are sequentially performed on the left side of the basic active region to form a deep well, wherein the ion implanted element is an N-type element;

[0019] Ion implantation is performed on the right side of the basic active region to form an active region, wherein the ion implanted elements are P-type elements.

[0020] Optionally, in the method for manufacturing a pixel device based on a semi-floating gate, the method of forming a drain on the surface of the deep well and forming a source on the surface of the active area includes:

[0021] Depositing a pad oxide layer and a silicon nitride layer on the surface of the active region close to the deep well and on the surface of the deep well close to the active region to form a simulated gate;

[0022] The self-aligned technology is used to define the drain on the surface of the deep well and the source on the surface of the active area to obtain N-type heavily doped drain and source.

[0023] Optionally, in the method for manufacturing a pixel device based on a semi-floating gate, the method for forming a semi-floating gate includes:

[0024] A trench is etched on one side of the active area close to the deep well using a photolithography process;

[0025] forming a first oxide layer in the trench by a thermal oxidation process, wherein the first oxide layer covers the surface of the trench;

[0026] depositing a boron-doped polysilicon layer, wherein the boron-doped polysilicon layer fills the trench and covers a portion of the deep well surface;

[0027] Chemical mechanical polishing is used to smooth the boron-doped polysilicon layer to obtain a semi-floating gate.

[0028] Optionally, in the method for manufacturing a pixel device based on a semi-floating gate, after forming the control gate, the method further includes:

[0029] forming a gate pattern on the surface of the control gate by using photolithography and anisotropic etching processes;

[0030] forming sidewall spacers on the sidewalls of the semi-floating gate, the sidewalls of the second oxide layer, and the sidewalls of the control gate;

[0031] Passivation treatment is performed to obtain a pixel device.

[0032] In order to solve the above technical problems, the present invention further provides an image sensor, comprising a half-floating gate based pixel device as described in any one of the above items.

[0033] The present invention provides a semi-floating gate-based pixel device, a manufacturing method thereof, and an image sensor, comprising a deep well and a trench transistor formed between two adjacent shallow trench isolations; the trench transistor comprises an active region, a source, a drain, a semi-floating gate, and a control gate; the active region is adjacent to the deep well; the source is located on the top surface of the active region and is separated from the deep well by the semi-floating gate; the drain is located on the top surface of the deep well away from the active region; the semi-floating gate covers a portion of the surface of the deep well and is partially embedded in the active region, and is separated from the sidewalls of the deep well and the active region by a first oxide layer; a second oxide layer and the control gate are sequentially formed on the top surface of the semi-floating gate. The deep well acts as a photodiode, so that when the deep well is exposed to a light source, carriers generate a photocurrent, holes are collected by the semi-floating gate, causing a change in potential, and illumination information can be obtained based on the current difference. This pixel device can realize all operations of a single pixel through a single transistor, effectively increasing the pixel's photosensitivity area. The manufacturing process of this pixel device is fully compatible with standard CMOS technology, solving the problem of how to manufacture a 1T pixel device with strong light response based on the existing CMOS manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic structural diagram of a half-floating gate-based pixel device provided in this embodiment;

[0035] Figure 2 A circuit schematic diagram of a pixel device based on a half-floating gate provided in this embodiment;

[0036] Figure 3 A flow chart of a method for manufacturing a pixel device based on a half-floating gate provided in this embodiment;

[0037] 4(A) to 4(L) are schematic diagrams of device structures at various steps in the manufacturing method provided in this embodiment;

[0038] The descriptions of the reference numerals are as follows:

[0039] 100-basic device; 101-shallow trench isolation; 110-deep well; 121-active area; 122-source; 123-drain; 124-semi-floating gate; 125-control gate; 130-first oxide layer; 140-second oxide layer; 150-sidewall; 160-dummy gate; 170-trench. DETAILED DESCRIPTION

[0040] The following is a further detailed description of the semi-floating gate-based pixel device, its manufacturing method, and image sensor proposed in the present invention, in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise scales, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may sometimes use different scales because they need to show different focuses.

[0041] It should be noted that the terms "first", "second", etc. in the specification, claims, and accompanying drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, and are not used to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or are inherent to these processes, methods, products, or apparatuses.

[0042] Existing image sensors (CIS) have limited strong light response capabilities, leading to reliability issues when imaging under strong background light conditions. The root cause of this problem is that the traditional CIS structure uses PN junction capacitors to store photogenerated charge, but the capacity of PN junction capacitors is limited. While existing technologies can improve dynamic range by expanding the scale of peripheral circuits to achieve a logarithmic response mode or using multiple exposure synthesis techniques, these solutions significantly increase system complexity. Furthermore, the increased number of transistors not only reduces the fill factor but also leads to a decrease in the signal-to-noise ratio, further limiting the improvement of image sensor imaging performance.

[0043] In view of the defects of the prior art, this embodiment provides a pixel device based on a semi-floating gate, such as Figure 1 As shown, it includes a deep well 110 and a trench transistor formed between two adjacent shallow trench isolations 101; the trench transistor includes an active area 121, a source 122, a drain 123, a semi-floating gate 124 and a control gate 125; the active area 121 is adjacent to the deep well 110; the source 122 is located on the top surface of the active area 121 and is separated from the deep well 110 by the semi-floating gate 124; the drain 123 is located on the top surface of the deep well 110 away from the active area 121; the semi-floating gate 124 covers part of the surface of the deep well 110 and is partially embedded in the active area 121, and is separated from the sidewall of the deep well 110 and the active area 121 by a first oxide layer 130; a second oxide layer 140 and the control gate 125 are formed in sequence on the top surface of the semi-floating gate 124.

[0044] The semi-floating gate-based pixel device provided in this embodiment uses the deep well 110 as a photodiode. When the deep well 110 is exposed to light, carriers generate a photocurrent. Holes are collected by the semi-floating gate 124, causing a change in potential. Light information can be obtained based on the current difference. This pixel device can perform all operations of a single pixel using a single transistor, effectively increasing the pixel's photosensitive area. Furthermore, the manufacturing process of this pixel device is fully compatible with standard CMOS technology, solving the problem of how to manufacture a 1T pixel device with strong light response based on existing CMOS manufacturing processes.

[0045] At the same time, the semi-floating gate-based pixel device provided in this embodiment, by locating the source electrode 122 on the top surface of the active area 121 and separating it from the deep well 110 by the semi-floating gate 124; and locating the drain electrode 123 on the top surface of the deep well 110 away from the active area 121 and separating it from the semi-floating gate 124, not only effectively reduces the impact of the gate oxide layer electric field on the pixel device performance during device operation, but also effectively reduces the off-state leakage current of the pixel device due to the increased channel length between the source and drain electrodes, thereby enhancing the pixel device's anti-noise interference capability. In addition, the semi-floating gate-based pixel device structure provided in this embodiment is easier to implement in terms of process, reducing the process difficulty.

[0046] In addition, the half-floating gate-based pixel device provided in this embodiment, by having the half-floating gate 124 cover part of the surface of the deep well 110 and partially embed it in the active area 121, and separated from the sidewalls of the deep well 110 and the active area 121 by the first oxide layer 130, not only further reduces the lateral size of the pixel device, but also because the deep well 110 is not blocked by the half-floating gate 124 as much as possible, the pixel device has a larger photosensitive area, thereby greatly improving the light response capability of the pixel device; at the same time, it also ensures that the half-floating gate 124 does not affect the movement of photogenerated charges, thereby effectively improving the response speed of the pixel device.

[0047] Specifically, in this embodiment, the deep well 110 is an N-type doped deep N-well; the active area 121 is P-type lightly doped; the source 122, the drain 123 and the control gate 125 are N-type heavily doped; and the half-floating gate 124 is P-type doped.

[0048] In a specific embodiment, the doping ions of the deep well 110 are phosphorus P; the doping ions of the source 122, the drain 123 and the control gate 125 are arsenic As, and the doping concentration of the source 122 and the drain 123 is 4.5×10 2 cm -3 The doping ion of the semi-floating gate 124 is boron B, and the doping concentration is 1×10 18 cm -3 .

[0049] Of course, in practical applications, corresponding doping ions and doping concentrations can also be selected according to actual process requirements, and this application does not impose any restrictions on this.

[0050] Furthermore, in this embodiment, to simplify the process, the first oxide layer 130 and the second oxide layer 140 can be made of the same material, such as silicon oxide. The semi-floating gate 124 can be made of boron-doped polysilicon, and the control gate 125 can be made of polysilicon.

[0051] Furthermore, in this embodiment, to ensure that the pixel device has good strong light response performance, the pitch of the pixel device is controlled to 1.8 μm, and the depth of the deep well 110 is 3-5 μm. Correspondingly, the thickness of the first oxide layer 130 is 5-10 nm, and the thickness of the second oxide layer 140 is 10-15 nm.

[0052] In practical applications, the material and thickness of each layer structure can be selected according to actual process requirements.

[0053] Furthermore, in this embodiment, Figure 1 As shown, sidewalls 150 are formed on the sidewalls of the semi-floating gate 124 , the sidewalls of the second oxide layer 140 , and the sidewalls of the control gate 125 .

[0054] In practical applications, the material of the sidewall spacer 150 may be nitride, such as silicon nitride.

[0055] The semi-floating gate-based pixel device provided in this embodiment utilizes a trench transistor (the bottom of the semi-floating gate 124 extends between the deep well 110 and the active area 121). Compared to a planar transistor structure, this shifts the conduction channel to a longitudinal direction, further reducing the lateral dimensions of the pixel device, allowing the pixel area to be reduced to less than 1μm, facilitating large-scale device integration. Furthermore, this trench transistor structure further increases the area of ​​the semi-floating gate 124, facilitating the storage of more photogenerated holes, thereby effectively increasing the full well capacity and further enhancing the dynamic range of the pixel device.

[0056] The pixel device based on the half-floating gate provided in this embodiment has a circuit schematic diagram in practical application as shown below: Figure 2 As shown, the photodiode PD is implemented by a deep well 110, and the control gate CG, the semi-floating gate SFG, the source Source and the drain Drain constitute a semi-floating gate field effect transistor SFG-MOSFET; the control gate CG is connected to the row select line Rowselect line of the pixel array in the image sensor, the semi-floating gate SFG is connected to the anode of the photodiode PD, the drain D is connected to the cathode of the photodiode PD, and the source S is grounded.

[0057] The operating principle of the semi-floating gate-based pixel device provided in this embodiment is roughly as follows: the deep well on the left side serves as a photodiode. The photogenerated holes generated by the deep well are collected by the semi-floating gate (SFG) and used to modulate the gate voltage of the MOSFET, thereby converting the light signal into a current signal for readout. Furthermore, the MOSFET can select the operating region as needed, providing high adjustability. Furthermore, because the MOSFET has an extremely low off-state current, the device's dark current performance is significantly enhanced.

[0058] The semi-floating gate-based pixel device provided in this embodiment can realize the functions of existing conventional 3T or 4T pixels using a single transistor structure, thus having obvious advantages in terms of integration. In addition, compared with the existing typical 4T1P pixel structure, the fill factor of the semi-floating gate-based pixel device provided in this embodiment has increased by more than 30%, effectively improving the strong light response capability of the pixel device. In addition, the existing pixel structure relies on the series operation of multiple transistors, resulting in high power consumption. In contrast, the semi-floating gate-based pixel device provided in this embodiment only generates source leakage current when reading signals, thereby greatly reducing power consumption. Through actual measurements, at the same resolution, the pixel array composed of the pixel device provided in this embodiment reduces the power consumption per column by about 10 times compared with the traditional pixel array.

[0059] This embodiment also provides a method for manufacturing a pixel device based on a semi-floating gate, which is used to manufacture the pixel device based on a semi-floating gate as described above. Figure 3 As shown, the manufacturing method includes:

[0060] S1, forming shallow trench isolation on the basic device, wherein a basic active area is formed between two adjacent shallow trench isolations;

[0061] S2, forming a deep well on the left side of the base active area and an active area on the right side;

[0062] S3, forming a drain on the surface of the deep well and a source on the surface of the active area;

[0063] S4, forming a half floating gate so that the half floating gate covers a portion of the surface of the deep well and is partially embedded in a side of the active region close to the deep well;

[0064] S5, forming a second oxide layer and a control gate in sequence on the surface of the semi-floating gate.

[0065] This embodiment provides a method for manufacturing a semi-floating gate-based pixel device. The resulting pixel device uses a deep well as a photodiode. When the deep well is exposed to a light source, carriers generate a photocurrent. Holes are collected by the semi-floating gate, causing a change in potential. Light information can be obtained based on the current difference. This pixel device can perform all operations of a single pixel using a single transistor, effectively increasing the pixel's photosensitive area. The manufacturing process for this pixel device is fully compatible with standard CMOS technology, solving the problem of how to manufacture a 1T pixel device with strong light response based on existing CMOS manufacturing processes.

[0066] Specifically, in this embodiment, in step S1 , shallow trench isolations are formed on the basic device, wherein a basic active region is formed between two adjacent shallow trench isolations.

[0067] In practical applications, shallow trench isolation 101 can be formed on base device 100 using existing shallow trench isolation formation processes. For example, a channel can be formed on base device 100 using processes such as photolithography, and then ion implantation is performed in the channel to form a P-type doped region. Finally, an oxide layer is deposited to form shallow trench isolation 101. The specific implementation method is well known to those skilled in the art and will not be described in detail in this application. In addition, base device 100 in this embodiment can be a substrate or a device structure with certain functional areas formed therein, and this application does not limit this.

[0068] The device structure obtained in this step is shown in Figure 4(A).

[0069] Furthermore, in this embodiment, step S2, the method of forming a deep well on the left side of the base active region and forming an active region on the right side includes:

[0070] S21 , as shown in FIG4(B), ion implantation and annealing are sequentially performed on the left side of the base active region to form a deep well 110 , wherein the ion implanted element is an N-type element.

[0071] In one embodiment, phosphorus is ion-implanted into the left side of the base active region to form a deep well 110 with a depth greater than 4 μm. The concentration of the ion implantation can be appropriately determined based on the desired depth of the deep well 110. Annealing is then performed for approximately 10 minutes until the device structure stabilizes.

[0072] S22 , as shown in FIG4 (C), ion implantation is performed on the right side of the base active region to form an active region, wherein the ion implanted elements are P-type elements.

[0073] In one embodiment, boron is ion-implanted into the right side of the basic active region to form a lightly doped active region 121. Subsequently, boron can be further doped into the right side of the basic active region to adjust the threshold voltage of the transistor.

[0074] Furthermore, in this embodiment, the method of forming a drain on the surface of the deep well and a source on the surface of the active area in step S3 includes:

[0075] S31 , as shown in FIG. 4 (D) , a pad oxide layer and a silicon nitride layer are deposited on the surface of the active region 121 close to the deep well 110 and on the surface of the deep well 110 close to the active region 121 to form a dummy gate 160 .

[0076] S32 , as shown in FIG4 (E), a drain 123 is defined on the surface of the deep well 110 and a source 122 is defined on the surface of the active region 121 by using a self-alignment technique, so as to obtain an N-type heavily doped drain 123 and source 122 .

[0077] After the source 122 and the drain 123 are formed, the dummy gate 160 is removed. At this time, the device structure is as shown in FIG. 4(F).

[0078] Furthermore, in this embodiment, step S4, the method of forming a half-floating gate includes:

[0079] S41, using a photolithography process to etch a trench on a side of the active region close to the deep well.

[0080] Specifically, as shown in FIG4(G), a trench 170 is etched on a side of the active region 121 close to the deep well 110 using a photoresist as a mask layer, and then the photoresist is removed.

[0081] In practical applications, the depth and width of the trench 170 may be determined based on process capabilities and device performance requirements.

[0082] S42, forming a first oxide layer in the trench using a thermal oxidation process, wherein the first oxide layer covers the surface of the trench;

[0083] Specifically, as shown in Figure 4(H), a first oxide layer 130 is formed on the surface of trench 170 using a thermal oxidation process. Thermal oxidation is a core process in semiconductor manufacturing that generates silicon dioxide thin films by reacting silicon with oxygen or water vapor at high temperatures. The oxide layers produced by this process are widely used in MOS device gate dielectrics, ion implantation masking layers, and device protection isolation layers due to their excellent electrical insulation, heat resistance, and interfacial bonding strength. The specific implementation of the thermal oxidation process is well known to those skilled in the art and will not be detailed in this application.

[0084] In practical applications, the thickness of the formed first oxide layer 130 is 5-10 nm, for example, 8 nm.

[0085] Of course, in other embodiments, a deposition process and an etching process may also be used to first deposit an oxide layer to cover the trench and the device surface, and then etch the oxide layer to remove the oxide layer covering the outside of the trench 170 and expose the trench structure to obtain the first oxide layer 130. However, due to the deep depth of the trench 170, the etching process cannot ensure that the morphology of the first oxide layer 130 meets the device requirements. Therefore, this embodiment uses a thermal oxidation process to form the first oxide layer 130 on the surface of the trench 170. This not only eliminates the deposition process and simplifies the process steps, but also ensures that the morphology of the first oxide layer 130 meets the device requirements.

[0086] S43 , depositing a boron-doped polysilicon layer, wherein the boron-doped polysilicon layer fills the trench and covers a portion of the deep well surface.

[0087] Specifically, as shown in FIG4 (I), boron-doped polysilicon is deposited to fill the trench 170 and then continues to grow to a certain thickness until the thickness meets the semi-floating gate thickness requirement. At this point, the semi-floating gate 124 may cover the source 122 and the drain 123.

[0088] In actual applications, when depositing the boron-doped polysilicon layer, the boron-doped polysilicon can be controlled to only cover the surface of the deep well 110 close to the trench 170, ensuring that there is no boron-doped polysilicon on the surface of the source 122, the surface of the drain 123, the surface of the deep well 110 away from the active area 121, and the surface of the shallow trench isolation 101.

[0089] Specifically, a mask can be used to define the area to be deposited. The mask is then used to cover the surface of the source 122, the surface of the drain 123, the portion of the deep well 110 away from the active area 121, and the surface of the shallow trench isolation 101. After depositing the boron-doped polysilicon, the mask and the boron-doped polysilicon thereon are removed. Alternatively, a boron-doped polysilicon layer can be deposited to cover the entire device surface, and then the boron-doped polysilicon on the surface of the source 122, the surface of the drain 123, the portion of the deep well 110 away from the active area 121, and the surface of the shallow trench isolation 101 is removed by etching.

[0090] S44 , smoothing the boron-doped polysilicon layer by chemical mechanical polishing (CMP) and determining the height of the boron-doped polysilicon layer to obtain the half-floating gate 124 .

[0091] Furthermore, in this embodiment, in step S5, a second oxide layer and a control gate are sequentially formed on the surface of the semi-floating gate.

[0092] Specifically, as shown in FIG4 (J), a deposition process, such as a chemical vapor deposition process, is used to sequentially form a second oxide layer 140 and a control gate 125 on the surface of the semi-floating gate 124; thereafter, an etching process is used to remove the semi-floating gate 124, the second oxide layer 140, and the control gate 125 on the surface of the source 122, the surface of the drain 123, the surface of a portion of the deep well 110 away from the active area 121, and the surface of the shallow trench isolation 101. The resulting device structure is shown in FIG4 (K).

[0093] In practical applications, the deposition thickness of the second oxide layer 140 can be 10-15 nm, for example, 12 nm. Thus, the main structure of the pixel device has been completed. Subsequently, in order to ensure the stability of the device structure and the effectiveness of its function, in this embodiment, the manufacturing method further includes:

[0094] S6, using photolithography and anisotropic etching processes, a gate pattern is formed on the surface of the control gate 125. The gate pattern is used to lead out wires later and connect to the row selection line of the pixel array.

[0095] S7, as shown in FIG4(L), forms spacers 150 on the sidewalls of the half-floating gate 124, the sidewalls of the second oxide layer 140, and the sidewalls of the control gate 125. The spacers 150 improve the structural stability of the half-floating gate 124, the second oxide layer 140, and the control gate 125 and isolate them from other device structures.

[0096] In practical applications, the material of the sidewall spacer 150 may be nitride, such as silicon nitride. The formation method of the sidewall spacer is well known to those skilled in the art and will not be described in detail in this application.

[0097] S8, passivation treatment to obtain a pixel device.

[0098] Through the passivation treatment, a protective film is formed on the surface of the device, thereby improving the reliability and stability of the pixel device. The material used for the passivation treatment can be silicon oxide or silicon nitride. Specifically, a silicon oxide layer or a silicon nitride layer can be formed on the surface of the device by chemical vapor deposition or physical vapor deposition. Among them, silicon oxide has good insulation and the ability to adsorb impurities; silicon nitride has high density, low water permeability and good adhesion, which can effectively protect the device. The specific process of the passivation treatment is well known to those skilled in the art and will not be described in detail in this application.

[0099] The manufacturing method of the semi-floating gate-based pixel device provided in this embodiment can be implemented based on a 0.13 μm CMOS standard process, and is therefore fully compatible with existing CMOS processes, thereby reducing the manufacturing cost of single-transistor pixel devices.

[0100] It should be noted that Figures 4(A) to 4(L) only illustrate the relationship between the various hierarchical structures. However, in actual applications, due to factors such as the process, the edges of the actual structures of each level may have inclinations, curvatures, etc., which can be understood by those skilled in the art.

[0101] Furthermore, this embodiment further provides an image sensor, comprising the above-described half-floating gate-based pixel device.

[0102] In actual applications, multiple pixel devices are arranged in an array and connected through row selection lines to obtain a pixel array.

[0103] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.

[0104] The semi-floating gate-based pixel device, its manufacturing method, and image sensor provided in this embodiment include a deep well and a trench transistor formed between two adjacent shallow trench isolations. The trench transistor includes an active region, a source, a drain, a semi-floating gate, and a control gate. The active region is adjacent to the deep well. The source is located on the top surface of the active region and is separated from the deep well by the semi-floating gate. The drain is located on the top surface of the deep well away from the active region. The semi-floating gate covers a portion of the surface of the deep well and is partially embedded in the active region, and is separated from the sidewalls of the deep well and the active region by a first oxide layer. A second oxide layer and the control gate are sequentially formed on the top surface of the semi-floating gate. The deep well acts as a photodiode, so that when the deep well is exposed to a light source, carriers generate photocurrent, holes are collected by the semi-floating gate, causing a potential change, and light information can be obtained based on the current difference. This pixel device can realize all operations of a single pixel through a single transistor, effectively increasing the pixel's photosensitivity area. The manufacturing process of this pixel device is fully compatible with standard CMOS technology, solving the problem of how to manufacture a 1T pixel device with strong light response based on the existing CMOS manufacturing process.

[0105] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A pixel device based on a semi-floating gate, characterized in that: The invention comprises a deep well and a trench transistor formed between two adjacent shallow trench isolations; the trench transistor comprises an active area, a source, a drain, a semi-floating gate, and a control gate; the active area is adjacent to the deep well; the source is located on the top surface of the active area and is separated from the deep well by the semi-floating gate; the drain is located on the top surface of the deep well away from the active area; The semi-floating gate covers part of the surface of the deep well and is partially embedded in the active area, and is separated from the sidewall of the deep well and the active area by a first oxide layer; a second oxide layer and the control gate are sequentially formed on the top surface of the semi-floating gate.

2. The pixel device based on a half-floating gate according to claim 1, characterized in that: The deep well is an N-type doped deep N-well; the active area is lightly P-type doped; the source, the drain and the control gate are heavily N-type doped; and the semi-floating gate is P-type doped.

3. The pixel device based on a half-floating gate according to claim 2, characterized in that: The doping ions of the deep N-well are phosphorus; the doping ions of the source, the drain and the control gate are arsenic, and the doping concentration of the source and the drain is 4.5×10 2 cm -3 The doping ion of the semi-floating gate is boron, and the doping concentration is 1×10 18 cm -3 .

4. The pixel device based on a half-floating gate according to claim 1, characterized in that: The pitch of the pixel device is 1.8 μm; the depth of the deep well is greater than 4 μm; the thickness of the first oxide layer is 5-10 nm; and the thickness of the second oxide layer is 10-15 nm.

5. The pixel device based on a half-floating gate according to claim 1, characterized in that: Sidewall spacers are formed on the sidewalls of the semi-floating gate, the sidewalls of the second oxide layer, and the sidewalls of the control gate.

6. A method for manufacturing a pixel device based on a semi-floating gate, for manufacturing the pixel device based on a semi-floating gate according to any one of claims 1 to 5, characterized in that: The manufacturing method comprises: forming shallow trench isolations on the basic device, wherein a basic active area is formed between two adjacent shallow trench isolations; A deep well is formed on the left side of the base active region and an active region is formed on the right side; forming a drain electrode on the surface of the deep well and a source electrode on the surface of the active area; forming a half-floating gate so that the half-floating gate covers a portion of the surface of the deep well and is partially embedded in a side of the active region close to the deep well; A second oxide layer and a control gate are sequentially formed on the surface of the semi-floating gate.

7. The method for manufacturing a pixel device based on a half-floating gate according to claim 6, characterized in that: The method of forming a deep well on the left side of the base active region and forming an active region on the right side includes: Ion implantation and annealing are sequentially performed on the left side of the basic active region to form a deep well, wherein the ion implanted element is an N-type element; Ion implantation is performed on the right side of the basic active region to form an active region, wherein the ion implanted elements are P-type elements.

8. The method for manufacturing a pixel device based on a half-floating gate according to claim 6, wherein: The method of forming a drain on the surface of the deep well and a source on the surface of the active area includes: Depositing a pad oxide layer and a silicon nitride layer on the surface of the active region close to the deep well and on the surface of the deep well close to the active region to form a simulated gate; The self-aligned technology is used to define the drain on the surface of the deep well and the source on the surface of the active area to obtain N-type heavily doped drain and source.

9. The method for manufacturing a pixel device based on a half-floating gate according to claim 6, characterized in that: The method for forming a half floating gate comprises: A trench is etched on one side of the active area close to the deep well using a photolithography process; forming a first oxide layer in the trench by a thermal oxidation process, wherein the first oxide layer covers the surface of the trench; depositing a boron-doped polysilicon layer, wherein the boron-doped polysilicon layer fills the trench and covers a portion of the deep well surface; Chemical mechanical polishing is used to smooth the boron-doped polysilicon layer to obtain a semi-floating gate.

10. The method for manufacturing a pixel device based on a half-floating gate according to claim 6, wherein: After forming the control gate, the manufacturing method further includes: forming a gate pattern on the surface of the control gate by using photolithography and anisotropic etching processes; forming sidewall spacers on the sidewalls of the semi-floating gate, the sidewalls of the second oxide layer, and the sidewalls of the control gate; Passivation treatment is performed to obtain a pixel device.

11. An image sensor, characterized in that: The device comprises a half-floating gate-based pixel device as claimed in any one of claims 1 to 5.

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