Selective etching method of P-type polycrystalline silicon layer and application thereof

Abstract

The invention relates to the technical field of solar cell wet etching, and discloses a selective etching method of a P-type polycrystalline silicon layer and application of the selective etching method. The method comprises the following steps: preparing a tunneling oxide layer, a first p-type polycrystalline silicon layer and a borosilicate glass layer on the back surface of a silicon wafer in sequence; preparing a reverse osmosis layer on the back surface of the first p-type polycrystalline silicon layer; patterning laser sintering is carried out on the back surface of the reverse osmosis layer, so that each layer in a laser sintering area and the back surface layer of the silicon wafer are sequentially fused from outside to inside, and boron is promoted to diffuse towards the reverse osmosis layer and the back surface layer of the silicon wafer; sequentially forming a second p-type polycrystalline silicon layer (the boron doping concentration of the second p-type polycrystalline silicon layer is smaller than that of the first p-type polycrystalline silicon layer) and a surface oxide layer on the back surface of the silicon wafer in the laser sintering region; and performing wet etching to remove the surface oxide layer and the second p-type polycrystalline silicon layer to expose the silicon surface of the laser sintering region, and removing the reverse osmosis layer of the non-laser sintering region. According to the method, the local wet etching difficulty of the p-type polycrystalline silicon layer can be reduced, the method is simple, the etching efficiency is high, no new equipment cost is added, and the universality is good.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cell wet etching, and in particular to a selective etching method for a P-type polysilicon layer and application thereof. Background Art

[0002] TBC cells (Tunneling Oxide Passivated Contact (TOPCon) back-contact cells) are a novel type of crystalline silicon cell structure developed based on TOPCon cell technology. They feature an emitter, surface field, and metal electrodes located on the back of the cell, arranged in an interdigitated pattern. Because the front of the TBC cell is free of any electrode grid lines, it maximizes the use of incident light, reduces optical losses, and creates a larger effective power generation area, resulting in higher photoelectric conversion efficiency. Furthermore, the solid-color front of the TBC cell is more aesthetically pleasing and in line with popular tastes, making it more competitive in the market.

[0003] In TBC cells (i.e., tunneling oxide passivation contact (TOPCon) back contact cells), the n+ and p+ emitters are located on the back of the crystalline silicon cell and arranged in an interdigitated pattern. Currently, one strategy for fabricating the n+ and p+ emitters is as follows (see publications CN119342910B and CN116845140A):

[0004] First, any side of a double-sided polished n-type silicon wafer can be used as the back side, and a first tunneling oxide layer and an intrinsic amorphous silicon layer (ia-Si layer) are sequentially deposited on the back side of the silicon wafer; then, the ia-Si layer is converted into a P-type Poly Si layer (i.e., a P-type polysilicon layer, such as a boron-doped polysilicon layer) by boron doping, and a borosilicate glass layer (BSG layer) is simultaneously formed on the back surface of the P-type polysilicon layer; thereafter, the BSG layer is patterned laser opened (also known as selective laser opening) according to a specific pattern to remove the BSG layer in the laser opened area; then, the P-type polysilicon layer and the first tunneling oxide layer in the laser opened area are etched away longitudinally along the removed portion of the BSG layer by alkaline etching to expose the back surface of the silicon wafer in the laser opened area, while retaining the P-type polysilicon layer and the first tunneling oxide layer in the non-laser opened area; finally, a second tunneling oxide layer and an n-type Poly Si layer (i.e., an n-type polysilicon layer) are sequentially deposited on the back side of the exposed silicon wafer by secondary deposition. This creates an interdigitated structure on the back of the silicon wafer, with the n+ emitter (which includes a first tunneling oxide layer and a p-type polysilicon layer located in a localized area on the back of the silicon wafer) and the p+ emitter (which includes a second tunneling oxide layer and an n-type polysilicon layer located in a localized area on the back of the silicon wafer) interdigitated. This interdigitated structure is key to the fabrication of TBC cells. Subsequent processes such as laser grooving, wet etching, passivation, and metallization ultimately result in a TBC cell with a complete interdigitated distribution of n+ and p+ emitters, and an isolation region between them.

[0005] In order to achieve the best photoelectric performance of TBC cells, the boron doping amount in the P-type polysilicon layer needs to meet a higher specific doping concentration range. However, the difficulty of etching the P-type polysilicon layer with the alkaline solution used for alkaline etching increases exponentially with the increase of boron doping concentration. The P-type polysilicon layer with a high boron doping concentration cannot be etched and removed well, which will seriously affect the improvement of TBC cell efficiency. In this regard, the current solutions are mainly: (1) increasing the alkaline etching time of the P-type polysilicon layer. (2) regulating the junction depth and doping concentration of the boron doping of the intrinsic amorphous silicon layer, that is, preparing a P-type polysilicon layer with a shallower junction depth and a lower doping concentration, to reduce the difficulty of etching and removing the P-type polysilicon layer. (3) when laser opening the film, replacing the laser with higher power and emission frequency, so as to destroy part of the P-type polysilicon layer with a high boron doping concentration while selectively laser opening the film (removing the BSG layer), thereby reducing the burden of alkaline etching. (4) In addition, as shown in publication number CN119342910B, by regulating the deposition temperature and deposition pressure of the polysilicon layer, a low-concentration doping region is formed on the back side of the high-concentration doping region of the first doped polysilicon layer to offset the effect of laser treatment on increasing the doping concentration of the doped polysilicon layer as much as possible, so as to avoid bringing a greater burden to the alkaline etching of the doped polysilicon layer.

[0006] However, while increasing the alkaline etching time can more thoroughly remove the P-type polysilicon layer in the laser-opened region, this extended alkaline etching time also leads to a decrease in the production capacity of the TBC cell. Regulating the junction depth and doping concentration of the boron doping in the intrinsic amorphous silicon layer not only requires a long process development period, but also reduces the boron doping concentration of the P-type polysilicon layer, making it incompatible with the optimal TBC cell structure, further affecting the photovoltaic performance (such as contact performance) of the finished cell. While replacing a laser with a higher power and emission frequency can achieve the desired effect of removing the P-type polysilicon layer in the laser-opened region, it requires additional investment in new equipment, resulting in high equipment investment costs. Furthermore, the solution shown in CN119342910B only offsets the effect of laser treatment on the doping concentration of the doped polysilicon layer, and has limited effect on reducing the difficulty of alkaline etching the doped polysilicon layer. Furthermore, it increases the difficulty and cost of the polysilicon layer deposition process and the subsequent metallization process (the first metal electrode must pass through the low-concentration doped region to contact the high-concentration doped region). Summary of the Invention

[0007] The purpose of the present invention is to overcome the shortcomings of the existing technology and provide a selective etching method for a P-type polysilicon layer and its application to solve the problem of difficulty in wet etching local areas of a P-type polysilicon layer with a high boron doping concentration in the current TBC battery production process.

[0008] Based on this, the present invention discloses a method for selectively etching a P-type polysilicon layer, comprising the following steps:

[0009] Step 1: sequentially preparing a tunneling oxide layer, a first p-type polysilicon layer, and a borosilicate glass layer on the back side of the silicon wafer;

[0010] Step 2: preparing a reverse osmosis layer on the back side of the first p-type polysilicon layer;

[0011] Step 3: performing patterned laser sintering on the back side of the reverse osmosis layer to melt the reverse osmosis layer, the borosilicate glass layer, the first p-type polysilicon layer, the tunneling oxide layer, and the back surface layer of the silicon wafer in the laser sintering region in sequence, thereby promoting the diffusion of boron in the borosilicate glass layer and the first p-type polysilicon layer into the reverse osmosis layer and the back surface layer of the silicon wafer, thereby forming a second p-type polysilicon layer on the back surface of the silicon wafer in the laser sintering region, wherein the boron doping concentration is less than that of the first p-type polysilicon layer, and forming a surface oxide layer on the back side of the second p-type polysilicon layer;

[0012] Step 4: wet etching to remove the surface oxide layer and the second p-type polysilicon layer in the laser sintering area to expose the silicon surface in the laser sintering area, and remove the reverse osmosis layer in the non-laser sintering area.

[0013] Preferably, in step 1, the silicon wafer is an n-type silicon wafer after double-side polishing;

[0014] The step 1 specifically includes:

[0015] Step 11: depositing a tunneling oxide layer and an intrinsic amorphous silicon layer on the back side of the silicon wafer in sequence;

[0016] Step 12: performing a boron diffusion process on the intrinsic amorphous silicon layer to transform the intrinsic amorphous silicon layer into a first p-type polycrystalline silicon layer and a borosilicate glass layer located on the outer surface of the first p-type polycrystalline silicon layer.

[0017] Specifically, in step 12, the boron doping concentration of the first p-type polysilicon layer is 2E19-1E20 cm -3 (such as 6E19cm -3 ); Correspondingly, after the patterned laser sintering in step 3, the boron doping concentration of the first p-type polysilicon layer in the non-laser sintering area is still 2E19~1E20cm -3 , and the boron doping concentration of the surface oxide layer and the second p-type polysilicon layer in the laser sintering area is less than the boron doping concentration of the first p-type polysilicon layer in the non-laser sintering area.

[0018] Preferably, in step 2, the reverse osmosis layer is an intrinsic amorphous silicon layer with a thickness of 100-500 nm;

[0019] The preparation method of the reverse osmosis layer includes chemical vapor deposition or physical vapor deposition.

[0020] Further preferably, in step 2, when the reverse osmosis layer is prepared by chemical vapor deposition, the amount of silicon source introduced is 500-2000 sccm, and the deposition temperature is 550-650° C.;

[0021] Alternatively, when the reverse osmosis layer is prepared by physical vapor deposition, a silicon deposition target is used, the deposition power is 10-50 KV, the deposition temperature is 200-400° C., and the pressure in the deposition chamber is lower than 10 Pa.

[0022] Preferably, in step 3, the process conditions of the patterned laser sintering include: laser power of 5-30W, laser wavelength of 400-700nm, laser spot area of 200-3000μm 2 The number of repeated sintering of the spot is 1-20 times.

[0023] Further preferably, in the step 3, the patterned laser sintering is performed using SE equipment of a tunneling oxide layer passivation contact cell production line or laser enhanced contact optimization equipment.

[0024] Preferably, the step 4 specifically includes:

[0025] Step 41: Acid etching is first performed to remove the surface oxide layer of the laser sintering area;

[0026] Step 42 : Perform alkaline etching again to remove the second p-type polysilicon layer in the laser sintering area and remove the reverse osmosis layer in the non-laser sintering area.

[0027] Further preferably, in step 41, the process conditions of the acid etching include: using a hydrofluoric acid solution for acid etching, the HF concentration is 0.5-10 w.t.%, the etching temperature is 40-80° C., and the etching time is 50-500 s.

[0028] Further preferably, in step 42, the process conditions of the alkaline etching include: alkaline etching using an aqueous solution mixed with NaOH and a surface modification additive, the concentration of NaOH is 0.3-5wt%, the concentration of the surface modification additive is 0.01-0.5wt%, the etching temperature is 50-90°C, and the etching time is 50-500s.

[0029] The present invention also discloses an application of a selective etching method for a P-type polysilicon layer, and applies the selective etching method for a P-type polysilicon layer described above in the present invention to prepare a tunneling oxide layer passivation contact back contact battery (especially a TBC battery).

[0030] The technical principles and advantages of the selective etching method for a P-type polysilicon layer of the present invention are as follows:

[0031] 1. In practice, the lower the boron doping concentration in boron-doped polysilicon, the less difficult the wet etching of boron-doped polysilicon. The present invention prepares an ia-Si layer (intrinsic amorphous silicon layer) as a reverse osmosis layer on the back surface of the borosilicate glass layer (BSG layer) after boron expansion. During the laser sintering process, the temperature of laser heating decreases along the reverse osmosis layer (such as the intrinsic amorphous silicon reverse osmosis layer) toward the back surface of the silicon wafer, causing the solid solubility of silicon in boron to decrease from the outside to the inside (that is, the solid solubility of silicon in boron decreases from the intrinsic amorphous silicon reverse osmosis layer to the back surface of the silicon wafer), and there is a difference in boron concentration between the intrinsic amorphous silicon reverse osmosis layer and the internal borosilicate glass layer and the first p-type polysilicon layer itself, so it is beneficial for the boron in the borosilicate glass layer and the first p-type polysilicon layer to diffuse in reverse to the intrinsic amorphous silicon reverse osmosis layer, thereby reducing the original borosilicate glass. The boron doping concentration in the glass layer and the first p-type polycrystalline silicon layer (that is, the boron doping concentration of the second p-type polycrystalline silicon layer formed after laser sintering is lower than the boron doping concentration of the first p-type polycrystalline silicon layer in the non-laser sintering area) is reduced, thereby reducing the difficulty of wet etching (including alkaline etching) of a local area (the local area is the laser sintering area of the present invention) of the original p-type polycrystalline silicon layer (the original p-type polycrystalline silicon layer refers to the first p-type polycrystalline silicon layer before the laser sintering step, corresponding to the first p-type polycrystalline silicon layer in the non-laser sintering area after the laser sintering step).

[0032] 2. It should be noted that laser sintering can melt the intrinsic amorphous silicon reverse osmosis layer, borosilicate glass layer, first p-type polysilicon layer, tunnel oxide layer and the surface layer of the back contact surface of the silicon wafer in the laser sintering area from the outside to the inside in a short period of time. This is conducive to the rapid diffusion (reverse diffusion) of the boron-oriented intrinsic amorphous silicon reverse osmosis layer in the original borosilicate glass layer and the first p-type polysilicon layer, forming a second p-type polysilicon layer in the laser sintering area with a boron doping concentration lower than the boron doping concentration of the first p-type polysilicon layer in the non-laser sintering area, thereby reducing the difficulty of wet etching in local areas of the original p-type polysilicon layer.

[0033] 3. Moreover, laser sintering can destroy the passivation layer such as the tunnel oxide layer, causing the boron in the first p-type polysilicon layer to diffuse toward the surface layer of the back contact surface of the silicon wafer, further reducing the boron doping concentration in the original first p-type polysilicon layer (that is, further reducing the boron doping concentration of the second p-type polysilicon layer in the laser sintering area of the present invention), and further reducing the difficulty of wet etching in local areas of the original p-type polysilicon layer.

[0034] 4. In addition, the laser sintering process can be carried out using equipment such as SE (Selective emitter) in the existing TOPCon battery production line, without the need to purchase new equipment, which can greatly reduce equipment investment costs; the selective etching method of the present invention is highly compatible with the existing TOPCon battery and TBC battery production lines.

[0035] In summary, the selective etching method of the present invention can not only effectively reduce the difficulty of wet etching in local areas of the original p-type polysilicon layer, and effectively remove the second p-type polysilicon layer in the laser sintering area, but also has the following advantages: the method is simple, the etching efficiency is high, it is beneficial to improve the production capacity of TBC batteries, there is no need to add new equipment, it can reduce equipment costs, and help reduce the production cost of TBC batteries, it has good compatibility with the existing TOPCon battery and TBC battery production lines, will not affect the subsequent TBC battery process, and has good universality.

[0036] Compared with the prior art, the present invention has at least the following beneficial effects:

[0037] A reverse osmosis layer is prepared on the back of the borosilicate glass layer, and then the original SE and other equipment in the TOPCon battery production line are used to perform laser sintering to cause secondary boron diffusion (i.e., reverse diffusion) in the local high boron doping concentration area, so as to reduce the boron doping concentration of the second p-type polysilicon layer in the laser sintering area, so that the boron doping concentration of the second p-type polysilicon layer in the laser sintering area is less than the boron doping concentration of the first p-type polysilicon layer in the non-laser sintering area, thereby reducing the difficulty of wet etching of the local area of the original p-type polysilicon layer (this is the first p-type polysilicon layer before the laser sintering step, corresponding to the first p-type polysilicon layer in the non-laser sintering area after the laser sintering step), and then the second p-type polysilicon layer in the laser sintering area can be completely removed by wet etching, which is helpful for the subsequent preparation of the n-type polysilicon layer.

[0038] Moreover, compared with existing solutions such as CN119342910B, the selective etching method of the present invention can not only effectively reduce the difficulty of wet etching in local areas of the original p-type polysilicon layer, and effectively remove the second p-type polysilicon layer in the laser sintering area, but also has the following advantages: the method is simple, the etching efficiency is high, it is beneficial to improve the production capacity of TBC batteries, there is no need to add new equipment, it can reduce equipment costs, and help reduce the production cost of TBC batteries. It has good compatibility with the existing TOPCon battery and TBC battery production lines, will not affect the subsequent TBC battery process, and has good universality. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a schematic diagram of the partial cross-sectional structure of a selective etching method for a P-type polysilicon layer after processing in step S1 of the present invention.

[0040] Figure 2 It is a schematic diagram of the partial cross-sectional structure of a selective etching method for a P-type polysilicon layer after processing in step S2 of the present invention.

[0041] Figure 3It is a schematic diagram of the partial cross-sectional structure of a selective etching method for a P-type polysilicon layer after processing in step S3 of the present invention.

[0042] Figure 4 It is a schematic diagram of the partial cross-sectional structure of a selective etching method for a P-type polysilicon layer after processing in step S4 of the present invention.

[0043] Figure 5 It is a schematic diagram of the partial cross-sectional structure of a selective etching method for a P-type polysilicon layer after processing in step S5 of the present invention.

[0044] Figure 6 Surface micrographs of the laser sintering area and the non-laser sintering area on the back surface of the sample after wet etching in Example 1 of the present invention.

[0045] Figure 7 This is a 3D photograph of the etching depth analysis of the laser sintering area and the non-laser sintering area on the back surface of the sample after wet etching in Example 1 of the present invention.

[0046] Figure 8 Surface micrographs of the laser sintering area and the non-laser sintering area on the back surface of the sample after wet etching in Comparative Example 1.

[0047] Figure 9 This is a 3D photograph of the etching depth analysis of the laser sintering area and the non-laser sintering area on the back surface of the sample after wet etching in Example 1.

[0048] Figure 10 This is a surface micrograph of the back surface of the sample of Comparative Example 2 after wet etching.

[0049] Explanation of the accompanying drawings: silicon wafer 1; tunneling oxide layer 2; intrinsic amorphous silicon layer 3; first p-type polysilicon layer 31; borosilicate glass layer 32; intrinsic amorphous silicon reverse osmosis layer 4; second p-type polysilicon layer 5; surface oxide layer 51; clean n-type silicon surface 6. DETAILED DESCRIPTION

[0050] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0051] A selective etching method for a P-type polysilicon layer of the present invention, see Figure 1-5 , including the following steps:

[0052] Step S1: Deposit a tunnel oxide layer 2 and an intrinsic amorphous silicon layer 3 (ia-Si layer) on the back of the silicon wafer 1 in sequence. Therefore, after the step S1, a silicon wafer 1 (such as Figure 1 shown).

[0053] In step S1 , the silicon wafer 1 is a double-sided polished silicon wafer, that is, both the front and back sides of the silicon wafer 1 are polished; moreover, the silicon wafer 1 is an n-type silicon wafer.

[0054] Step S2: Boron diffusion is performed on the back side of the silicon wafer 1 after the processing in step S1 to perform boron doping and diffusion on the intrinsic amorphous silicon layer 3 and convert the amorphous silicon into polysilicon; therefore, after the boron diffusion, the intrinsic amorphous silicon layer 3 is converted into the first p-type polysilicon layer 31 (i.e., the first p-type Si layer, i.e., the first boron-doped polysilicon layer) and the borosilicate glass layer 32 (BSG layer) formed on the outer surface (the outer surface includes the back side) of the first p-type polysilicon layer 31. That is, after the boron diffusion in step S2, the intrinsic amorphous silicon layer 3 is converted into the first p-type polysilicon layer 31 and the borosilicate glass layer 32 (BSG layer). Figure 2 shown).

[0055] The specific process of step S1 and step S2 refers to the existing technology and will not be described in detail here.

[0056] Step S3: See Figure 3 , an intrinsic amorphous silicon reverse osmosis layer 4 (ie, ia-Si reverse osmosis layer) is deposited on the back side of the borosilicate glass layer 32 .

[0057] In step S3, the deposition process of the intrinsic amorphous silicon reverse osmosis layer 4 includes, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD) and other methods. Among them, chemical vapor deposition includes atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD) and atomic layer deposition (ALD). Among them, physical vapor deposition includes vacuum evaporation coating, vacuum sputtering coating and vacuum ion plating.

[0058] In one example of the present invention, when the deposition process of the intrinsic amorphous silicon reverse osmosis layer 4 is CVD, the silicon source input is 500-2000sccm (such as 1000sccm), the deposition temperature is 550-650℃ (such as 600℃), and the thickness of the intrinsic amorphous silicon reverse osmosis layer 4 is 100-500nm (such as 200nm).

[0059] In another example of the present invention, when the deposition process of the intrinsic amorphous silicon reverse osmosis layer 4 is PVD, the main component of the deposition target material is silicon (Si), the deposition power is 10-50KV, the deposition temperature is 200-400°C, the pressure in the deposition chamber is lower than 10Pa, and the thickness of the intrinsic amorphous silicon reverse osmosis layer 4 is 100-500nm.

[0060] Step S4: Laser sintering is performed on the back of the intrinsic amorphous silicon reverse osmosis layer 4 according to a preset pattern (i.e., patterned laser sintering, also called selective laser sintering, also called local laser sintering), so that the intrinsic amorphous silicon reverse osmosis layer 4, the borosilicate glass layer 32, the first p-type polysilicon layer 31, the tunneling oxide layer 2 and the back surface layer of the silicon wafer 1 in the laser sintering area are melted in sequence from the outside to the inside, and the boron in the borosilicate glass layer 32 and the first p-type polysilicon layer 31 is reversely osmotic to the intrinsic amorphous silicon. The back surface layer 4 and the silicon wafer 1 are reversely diffused, thereby forming a second p-type polysilicon layer 5 (i.e., a second boron-doped polysilicon layer) in the laser sintering area and a surface oxide layer 51 (surface SiOx layer) formed on the back surface of the second p-type polysilicon layer 5 by oxidation. The front of the second p-type polysilicon layer 5 reaches the back surface layer of the silicon wafer 1, and the boron doping concentration of the second p-type polysilicon layer 5 and the surface oxide layer 51 is less than the boron doping concentration of the first p-type polysilicon layer 31. That is, after the patterned laser sintering in step S4, the laser sintering area forms the second p-type polysilicon layer 5 and the surface oxide layer 51 (i.e., Figure 4 Moreover, the boron doping concentration of the first p-type polysilicon layer 31 in the non-laser sintering region is still 2E19~1E20cm -3 (such as 6E19cm -3 ), and the boron doping concentration of the surface oxide layer 51 and the second p-type polysilicon layer 5 in the laser sintering area is lower than the boron doping concentration of the first p-type polysilicon layer 31 in the non-laser sintering area.

[0061] In step S4, the equipment used in the patterned laser sintering process includes but is not limited to SE (Selective emitter) equipment of the TOPCon cell (tunneling oxide passivation contact cell) production line, LECO equipment (laser enhanced contact optimization equipment) and other equipment that can emit lasers with sintering effects.

[0062] In step S4, when patterned laser sintering is performed on the back of the intrinsic amorphous silicon reverse osmosis layer 4 using SE equipment, the laser power is 5-30W, the laser wavelength is 400-700nm, and the laser spot area is 200-3000μm 2 The number of repeated sintering of the spot is 1-20 times.

[0063] Step S5: wet-etching the silicon wafer 1 after the step S4 to remove the surface oxide layer 51 of the laser sintering area, the second p-type polysilicon layer 5 of the laser sintering area, and the intrinsic amorphous silicon reverse osmosis layer 4 of the non-laser sintering area, thereby exposing a clean n-type silicon surface 6 (such as Figure 5 shown).

[0064] In step S5, the wet etching process includes:

[0065] Step S51: first perform etching with an acidic solution (acid etching for short) to remove the surface oxide layer 51; during the acidic solution etching process, the intrinsic amorphous silicon reverse osmosis layer 4 in the non-laser sintering area will not be removed; and, during the acidic solution etching process, the borosilicate glass layer 32 in the non-laser sintering area is covered and protected by the intrinsic amorphous silicon reverse osmosis layer 4 and will not be removed.

[0066] In step S51, the acidic solution includes but is not limited to a deionized aqueous solution of HF (hydrofluoric acid solution), wherein the concentration of HF is 0.5-10 w.t.%, the etching temperature is 40-80°C, and the etching time is 50-500s.

[0067] Step S52: performing etching with an alkaline solution (alkaline etching for short) to remove the second p-type polysilicon layer 5 in the laser sintering area and the intrinsic amorphous silicon reverse osmosis layer 4 in the non-laser sintering area.

[0068] In step S52, the alkaline solution includes a deionized water solution of NaOH (sodium hydroxide) and a surface modification additive (ADD), wherein the concentration of NaOH is 0.3-5 wt.%, the concentration of the surface modification additive is 0.01-0.5 wt.%, the etching temperature is 50-90°C, and the etching time is 50-500s.

[0069] At this time, it should be noted that before and after the etching in steps S51 and S52, the residual liquid on the surface needs to be completely cleaned with deionized water.

[0070] The selective etching method for a P-type polysilicon layer shown in the above steps S1-S5 of the present invention can be applied to the preparation of solar cells, especially TBC cells.

[0071] A specific embodiment of a selective etching method for a P-type polysilicon layer of the present invention is given below:

[0072] Example 1

[0073] A selective etching method for a P-type polysilicon layer in this embodiment is described in detail. Figure 1-5 , including the following steps:

[0074] Step S1: On the back side of the silicon wafer 1 (which is a double-sided polished n-type silicon wafer), a tunneling oxide layer 2 and an intrinsic amorphous silicon layer 3 are sequentially deposited. Therefore, after the step S1, a silicon wafer 1 (such as Figure 1 shown).

[0075] Step S2: See Figure 2The back side of the silicon wafer 1 after the treatment in step S1 is subjected to a boron diffusion treatment, so that the intrinsic amorphous silicon layer 3 is transformed into a first p-type polysilicon layer 31 (i.e., a first boron-doped polysilicon layer) and a borosilicate glass layer 32 formed on the outer surface of the first p-type polysilicon layer 31.

[0076] Step S3: See Figure 3 , an intrinsic amorphous silicon reverse osmosis layer 4 is deposited on the back side of the borosilicate glass layer 32 .

[0077] In step S3 of this embodiment, a PVD deposition process is used to prepare the intrinsic amorphous silicon reverse osmosis layer 4. The deposition process includes: the deposition target is a silicon target, the deposition power is 25KV, the deposition temperature is 300°C, the pressure in the deposition chamber is lower than 10Pa, and the thickness of the intrinsic amorphous silicon reverse osmosis layer 4 is 200nm.

[0078] Step S4: See Figure 4 Laser sintering is performed on the back side of the intrinsic amorphous silicon reverse osmosis layer 4 according to a preset pattern, so that the intrinsic amorphous silicon reverse osmosis layer 4, the borosilicate glass layer 32, the first p-type polycrystalline silicon layer 31, the tunneling oxide layer 2 and the back surface layer of the silicon wafer 1 in the laser sintering area are melted in sequence from the outside to the inside, and the boron in the borosilicate glass layer 32 and the first p-type polycrystalline silicon layer 31 is reversely diffused toward the intrinsic amorphous silicon reverse osmosis layer 4 and the back surface layer of the silicon wafer 1, thereby forming a second p-type polycrystalline silicon layer 5 (i.e., a second boron-doped polycrystalline silicon layer) and a surface oxide layer 51 formed on the back surface of the second p-type polycrystalline silicon layer 5 in the laser sintering area, the front side of the second p-type polycrystalline silicon layer 5 reaches the back surface layer of the silicon wafer 1, and the boron doping concentration of the second p-type polycrystalline silicon layer 5 and the surface oxide layer 51 is less than the boron doping concentration of the first p-type polycrystalline silicon layer 31.

[0079] In step S4 of this embodiment, patterned laser sintering is performed on the back of the intrinsic amorphous silicon reverse osmosis layer 4 using SE equipment, with a laser power of 15W, a laser wavelength of 550nm, and a laser spot area of 1500μm. 2 , the spot sintering is repeated 10 times.

[0080] Step S5: See Figure 5 The silicon wafer 1 treated in step S4 is wet-etched to remove the surface oxide layer 51 in the laser sintering area, the second p-type polysilicon layer 5 in the laser sintering area, and the intrinsic amorphous silicon reverse osmosis layer 4 in the non-laser sintering area, thereby exposing a clean n-type silicon surface 6 in the laser sintering area.

[0081] In step S5, the wet etching process includes:

[0082] Step S51 : firstly perform etching with an acidic solution (acid etching for short) to remove the surface oxide layer 51 .

[0083] In step S51, the acidic solution is a deionized aqueous solution of HF (hydrofluoric acid solution), wherein the concentration of HF is 5 w.t.%, the etching temperature is 60° C., and the etching time is 250 s.

[0084] Step S52: performing etching with an alkaline solution (alkaline etching for short) to remove the second p-type polysilicon layer 5 in the laser sintering area and the intrinsic amorphous silicon reverse osmosis layer 4 in the non-laser sintering area.

[0085] In step S52 , the alkaline solution is a deionized water solution of NaOH and a surface modification additive (ADD), wherein the concentration of NaOH is 2.5 wt %, the concentration of the surface modification additive is 0.3 wt %, the etching temperature is 80° C., and the etching time is 250 s.

[0086] Before and after etching in steps S51 and S52, the residual liquid on the surface needs to be completely cleaned with deionized water.

[0087] The selective etching method for a P-type polysilicon layer shown in steps S1 to S5 of this embodiment can be applied to the preparation of solar cells, especially TBC cells.

[0088] Comparative Example 1

[0089] In this comparative example, a method for selectively etching a P-type polysilicon layer is provided, wherein steps 1 and 2 are respectively the same as steps S1 and S2 of Example 1, and steps 3 and 4 are respectively the same as steps S4 and S5 of Example 1. The main difference between this comparative example and Example 1 is that:

[0090] In this comparative example, step S3 of Example 1 was omitted.

[0091] Comparative Example 2

[0092] In this comparative example, a method for etching a P-type polysilicon layer, steps 1 and 2 of which are respectively the same as steps S1 and S2 of Example 1, and the main difference between this method and Example 1 is that:

[0093] Steps S3 and S4 of Example 1 are omitted.

[0094] Moreover, the process conditions of the wet etching in step 3 of this comparative example are as follows:

[0095] In the acid etching of step 3 of this comparative example, the acidic solution is a deionized aqueous solution of HF (hydrofluoric acid solution), wherein the HF concentration is 10 w.t.%, the etching temperature is 80° C., and the etching time is 500 s.

[0096] In the alkaline etching of step 3 of this comparative example, the alkaline solution is a deionized water solution mixed with NaOH and a surface modification additive (ADD), wherein the concentration of NaOH is 5 wt.%, the concentration of the surface modification additive is 0.5 wt.%, the etching temperature is 90°C, and the etching time is 500 s to accelerate the etching; the remaining wet etching processes of step 3 of this comparative example are all referred to step S5 of Example 1.

[0097] Performance Testing

[0098] 1. Collect surface micrographs of the back surface of the wet-etched samples of Example 1, Comparative Example 1 and Comparative Example 2, respectively. Figure 6 、 Figure 8 and Figure 10 shown.

[0099] 2. Collect 3D photos of the etching depth analysis of the back surface of the sample after wet etching of Example 1 and Comparative Example 1, respectively. Figure 7 and Figure 9 shown.

[0100] Combine Figure 6-10 , we can know that:

[0101] (1) There is no obvious difference in etching depth between the laser sintering area and the non-laser sintering area on the back surface of the sample after wet etching in Example 1 (e.g. Figure 8-9 As shown). It can be seen that if step S3 (depositing the intrinsic amorphous silicon reverse osmosis layer 4 on the back side of the borosilicate glass layer 32) is omitted and patterned laser sintering and wet etching are directly performed (as shown in Comparative Example 1); it is difficult to guide the boron in the borosilicate glass layer 32 and the first p-type polysilicon layer 31 in the laser sintering area to diffuse back to other layers, so that it is difficult to obtain a p-type polysilicon layer in the laser sintering area with a boron doping concentration lower than that of the p-type polysilicon layer in the non-laser sintering area, and further it is difficult to reduce the difficulty of wet etching of a local area of the p-type polysilicon layer (the local area is the laser sintering area of the present invention), which results in an unclear difference in etching depth between the laser sintering area and the non-laser sintering area.

[0102] (2) The back surface of the sample after wet etching in Example 2 also did not show obvious etching depth (e.g. Figure 10As shown). It can be seen that if steps S3 (deposition of the intrinsic amorphous silicon reverse osmosis layer 4) and S4 (patterned laser sintering) are omitted, and a local area of the first p-type polysilicon layer 31 is directly wet-etched (as shown in Comparative Example 2); even if the etching time is extended to 1000s (500s of acid etching time + 500s of alkaline etching time) for 500s, it is still difficult to completely remove the local area of the first p-type polysilicon layer 31, which will result in an unclear etching depth on the back surface of the sample of Comparative Example 2. This further verifies that a p-type polysilicon layer with a high boron doping concentration is difficult to be directly removed by wet etching.

[0103] (3) Compared with Comparative Examples 1 and 2, the etching depth of the laser sintered area and the non-laser sintered area on the back surface of the sample after wet etching in Example 1 is significantly different. It can be seen that the selective etching method of a P-type polysilicon layer of the present invention, based on steps S1-S2, is combined with steps S3 (deposition of intrinsic amorphous silicon reverse osmosis layer 4), S4 (patterned laser sintering) and S5 (wet etching), which can not only shorten the wet etching time, improve the etching efficiency and production capacity, but also ensure the removal effect of the p-type polysilicon layer (i.e., the second p-type polysilicon layer 5) in the laser sintered area and reduce its wet etching.

[0104] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0105] The technical solution provided by the present invention is introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of the present invention, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for selectively etching a P-type polysilicon layer, characterized in that: The steps include: Step 1: sequentially preparing a tunneling oxide layer, a first p-type polysilicon layer, and a borosilicate glass layer on the back side of the silicon wafer; Step 2: preparing a reverse osmosis layer on the back side of the first p-type polysilicon layer; Step 3: performing patterned laser sintering on the back side of the reverse osmosis layer, so that the reverse osmosis layer, the borosilicate glass layer, the first p-type polysilicon layer, the tunneling oxide layer, and the back surface layer of the silicon wafer in the laser sintering region are melted in sequence, so that the boron in the borosilicate glass layer and the first p-type polysilicon layer is diffused into the reverse osmosis layer and the back surface layer of the silicon wafer, so as to form a second p-type polysilicon layer on the back surface of the silicon wafer in the laser sintering region, wherein the boron doping concentration is less than that of the first p-type polysilicon layer, and a surface oxide layer is formed on the back side of the second p-type polysilicon layer; Step 4: wet etching to remove the surface oxide layer and the second p-type polysilicon layer in the laser sintering area to expose the silicon surface in the laser sintering area, and remove the reverse osmosis layer in the non-laser sintering area.

2. The selective etching method for a P-type polysilicon layer according to claim 1, wherein: In step 1, the silicon wafer is an n-type silicon wafer after double-side polishing; The step 1 specifically includes: Step 11: depositing a tunneling oxide layer and an intrinsic amorphous silicon layer on the back side of the silicon wafer in sequence; Step 12: performing a boron diffusion process on the intrinsic amorphous silicon layer to transform the intrinsic amorphous silicon layer into a first p-type polycrystalline silicon layer and a borosilicate glass layer located on the outer surface of the first p-type polycrystalline silicon layer.

3. The selective etching method for a P-type polysilicon layer according to claim 1, wherein: In step 2, the reverse osmosis layer is an intrinsic amorphous silicon layer with a thickness of 100-500 nm; The preparation method of the reverse osmosis layer includes chemical vapor deposition or physical vapor deposition.

4. The selective etching method for a P-type polysilicon layer according to claim 3, characterized in that: In the step 2, when the reverse osmosis layer is prepared by chemical vapor deposition, the amount of silicon source introduced is 500-2000 sccm, and the deposition temperature is 550-650° C.; Alternatively, when the reverse osmosis layer is prepared by physical vapor deposition, a silicon deposition target is used, the deposition power is 10-50 KV, the deposition temperature is 200-400° C., and the pressure in the deposition chamber is lower than 10 Pa.

5. The selective etching method for a P-type polysilicon layer according to claim 1, wherein: In step 3, the process conditions of patterned laser sintering include: laser power of 5-30W, laser wavelength of 400-700nm, laser spot area of 200-3000μm 2 The number of repeated sintering of the spot is 1-20 times.

6. A method for selectively etching a P-type polysilicon layer according to claim 1 or 5, characterized in that: In the step 3, the patterned laser sintering is performed using SE equipment of a tunneling oxide layer passivation contact cell production line or laser enhanced contact optimization equipment.

7. The selective etching method for a P-type polysilicon layer according to claim 1, characterized in that: The step 4 specifically includes: Step 41: Acid etching is first performed to remove the surface oxide layer of the laser sintering area; Step 42 : Perform alkaline etching again to remove the second p-type polysilicon layer in the laser sintering area and remove the reverse osmosis layer in the non-laser sintering area.

8. The selective etching method for a P-type polysilicon layer according to claim 7, characterized in that: In step 41, the process conditions of the acid etching include: using a hydrofluoric acid solution for acid etching, the HF concentration is 0.5-10wt.%, the etching temperature is 40-80°C, and the etching time is 50-500s.

9. The selective etching method for a P-type polysilicon layer according to claim 7, characterized in that: In step 42, the process conditions of the alkaline etching include: using an aqueous solution mixed with NaOH and a surface modification additive for alkaline etching, the concentration of NaOH is 0.3-5wt%, the concentration of the surface modification additive is 0.01-0.5wt%, the etching temperature is 50-90°C, and the etching time is 50-500s.

10. Application of a selective etching method for a P-type polysilicon layer, characterized in that: The selective etching method for a P-type polysilicon layer according to any one of claims 1 to 9 is applied to the preparation of a tunnel oxide layer passivation contact back contact battery.

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