Display device

Abstract

A display device is provided. The display device includes a substrate on which a plurality of sub-pixels are defined; each of the sub-pixels includes a first region and a second region; a plurality of reflective electrodes disposed on the substrate; a plurality of transistors disposed in each of the plurality of sub-pixels on the substrate; a plurality of first light emitting diodes disposed in the first regions of the plurality of sub-pixels, respectively; and at least one second light emitting diode disposed in a second region of at least one of the plurality of sub-pixels and different from the plurality of first light emitting diodes, wherein a bottom surface of the second light emitting diode and a bottom surface of the plurality of first light emitting diodes are disposed on different planes.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0018447 filed on February 6, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device using a light emitting diode (LED). Background Art

[0004] As displays used for computers, televisions, mobile phones, and the like, there are organic light emitting display (OLED) devices that are self-luminous devices, liquid crystal display (LCD) devices that require a separate light source, and the like.

[0005] The application range of display devices includes not only monitors of computers and televisions but also personal digital assistants, and research is underway on display devices with large display areas and small size and weight.

[0006] In addition, display devices including light-emitting diodes (LEDs) have recently attracted attention as next-generation display devices. Because LEDs are made of inorganic materials rather than organic materials, they are highly reliable, resulting in a longer lifespan than liquid crystal display devices or organic light-emitting display devices. In addition, LEDs have a fast response speed, excellent luminous efficiency, and strong impact resistance, resulting in excellent stability and the ability to display images with high brightness. Summary of the Invention

[0007] One object to be achieved by the present disclosure is to provide a display device that can transfer and repair a light-emitting device when a defect occurs, thereby reducing process costs.

[0008] Another object to be achieved by the present disclosure is to provide a display apparatus capable of suppressing a short circuit problem in a light emitting device.

[0009] Yet another object to be achieved by the present disclosure is to provide a display device capable of stably performing a repair process.

[0010] The objects of the present disclosure are not limited to the above objects, and those skilled in the art can clearly understand other objects not mentioned above from the following description.

[0011] According to one aspect of the present disclosure, a display device includes: a substrate; a plurality of sub-pixels on the substrate, each sub-pixel including a first region and a second region; a plurality of reflective electrodes on the substrate; a plurality of transistors in each of the plurality of sub-pixels on the substrate; a plurality of first light-emitting diodes, each first light-emitting diode being located in the first region of a corresponding sub-pixel among the plurality of sub-pixels; and a second light-emitting diode located in the second region of at least one sub-pixel among the plurality of sub-pixels, wherein the second light-emitting diode is different from the plurality of first light-emitting diodes, and in a cross-sectional view of the display device, a bottom surface of the second light-emitting diode and a bottom surface of the plurality of first light-emitting diodes are on different planes.

[0012] According to another aspect of the present disclosure, a display device includes: a substrate; a sub-pixel on the substrate, the sub-pixel including a first region and a second region separated from the first region; a transistor on the substrate; a light-emitting diode in the first region, the light-emitting diode including a first electrode and a second electrode; a first connecting electrode connected to the first electrode of the light-emitting diode in the first region, the first connecting electrode electrically connecting the first electrode and the transistor; an additional connecting electrode, the additional connecting electrode including: a first portion of the additional connecting electrode connected to the second electrode in the first region, and a second portion located in the second region at a height smaller than the height of the first portion of the additional connecting electrode in the first region, the additional connecting electrode electrically connecting the second electrode of the light-emitting diode and a power line together; and a dam, the dam including: a first portion of the dam in the first region, a second portion of the dam on the second portion of the additional connecting electrode in the second region, and an opening overlapping with the light-emitting diode in the first region.

[0013] Additional details of exemplary embodiments are included in the detailed description and accompanying drawings.

[0014] According to the present disclosure, the manufacturing cost of a display device can be reduced by transferring and repairing a light emitting device only when a defect occurs in a specific sub-pixel.

[0015] According to the present disclosure, by forming a step structure at the lower portion of the electrode for repairing the light emitting device, the repair of the light emitting device can be facilitated.

[0016] According to the present disclosure, by using the stepped structure of the contact hole, a short circuit problem that may occur during a repair process may be suppressed.

[0017] The effects according to the present disclosure are not limited to those exemplified above, and more effects are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which

[0019] Figure 1 is a schematic configuration diagram of a display device according to an exemplary embodiment of the present disclosure;

[0020] Figure 2 is an enlarged plan view of a display device according to an exemplary embodiment of the present disclosure;

[0021] Figure 3 It is along Figure 2 A cross-sectional view taken along line AB;

[0022] Figure 4 is an enlarged plan view of a display device before a repair process according to an exemplary embodiment of the present disclosure;

[0023] Figures 5A to 5C is a diagram illustrating a repair process of a display device according to an exemplary embodiment of the present disclosure;

[0024] Figure 6 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] The advantages and features of the present disclosure and the methods for achieving these advantages and features are described in detail below and in the accompanying drawings. Figure 1 The exemplary embodiments described in detail below will become clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example to enable those skilled in the art to fully understand the disclosure of the present invention and the scope of the present disclosure.

[0026] The shapes, sizes, proportions, angles, quantities, etc. shown in the accompanying drawings for the purpose of describing exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. The same reference numerals generally represent the same elements throughout the application. In addition, in the description below the present disclosure, detailed explanations of known related arts may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including," "having," and "consisting of" used herein are generally intended to allow the addition of other components, unless the term "only" is used in these terms. Any reference in the singular may include the plural, unless otherwise expressly stated.

[0027] Even if not explicitly stated, parts are interpreted as including the usual margin of error.

[0028] When terms such as “on,” “above,” “below,” and “after” are used to describe the positional relationship between two parts, one or more parts may be set between the two parts unless these terms use the terms “immediately” or “directly”.

[0029] When an element or layer is referred to as being “on” another element or layer, the element or layer can be directly on the other element or layer or other elements or layers may be interposed therebetween.

[0030] Although the terms "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from other components. Therefore, within the technical concept of the present disclosure, the first component mentioned below may be the second component.

[0031] Like reference numbers generally refer to like elements throughout the application.

[0032] The size and thickness of each component shown in the drawings are shown for convenience of description, and the present disclosure is not limited to the size and thickness of the components shown in the drawings.

[0033] The features of the various embodiments of the present disclosure may be combined or coupled with each other in part or in whole, and may be interconnected and operated in various technical ways, and the various embodiments may be implemented independently of each other, or in association with each other.

[0034] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] Figure 1 : is a schematic configuration diagram of a display device according to an exemplary embodiment of the present disclosure. For ease of explanation, Figure 1 Only the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC among various components of the display device 100 are illustrated.

[0036] Reference Figure 1 The display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD providing various signals to the display panel PN, and a timing controller TC controlling the gate driver GD and the data driver DD.

[0037] The gate driver GD provides a plurality of scan signals to the plurality of scan lines SL according to a plurality of gate control signals provided from the timing controller TC. Figure 1 , one gate driver GD is shown separated from one side of the display panel PN, but the number and arrangement of the gate drivers GD are not limited thereto.

[0038] The data driver DD converts image data input from the timing controller TC into data voltages using reference gamma voltages according to a plurality of data control signals supplied from the timing controller TC. The data driver DD may supply the converted data voltages to a plurality of data lines DL.

[0039] The timing controller TC sorts image data input from the outside and provides the sorted image data to the data driver DD. The timing controller TC can generate gate control signals and data control signals using external synchronization signals, such as a dot clock signal, a data enable signal, and horizontal / vertical synchronization signals. The timing controller TC can provide the generated gate control signals and data control signals to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0040] The display panel PN is a component that displays images to a user and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL intersect each other, and each of the plurality of sub-pixels SP is connected to the scan lines SL and the data lines DL. In addition, although not shown in the figure, each of the plurality of sub-pixels SP can be connected to a high-potential power line, a low-potential power line, a reference line, etc.

[0041] A display area AA and a non-display area NA surrounding the display area AA are defined in the display panel PN.

[0042] The display area AA is the area on the display device 100 where images are displayed. Multiple sub-pixels SP constituting multiple pixels and circuits for driving the multiple sub-pixels SP may be provided in the display area AA. The multiple sub-pixels SP are the smallest units constituting the display area AA, with n sub-pixels SP forming one pixel. Each of the multiple sub-pixels SP may include a light-emitting device, a thin-film transistor for driving the light-emitting device, and the like. The multiple light-emitting devices may be defined differently depending on the type of display panel PN. For example, when the display panel PN is an inorganic light-emitting display panel, the light-emitting device may be a light-emitting diode (LED) or a micro light-emitting diode (microLED).

[0043] A plurality of signal lines are provided in the display area AA for transmitting various signals to the plurality of sub-pixels SP. For example, the plurality of signal lines may include a plurality of data lines DL for supplying data voltages to each of the plurality of sub-pixels SP, a plurality of scan lines SL for supplying gate voltages to each of the plurality of sub-pixels SP, and the like. The plurality of scan lines SL may extend in one direction in the display area AA and may be connected to the plurality of sub-pixels SP. Furthermore, the plurality of data lines DL may extend in a direction different from the one direction in the display area AA and may be connected to the plurality of sub-pixels SP. Furthermore, low-potential power lines and high-potential power lines may be further provided in the display area AA, but are not limited thereto.

[0044] The non-display area NA is an area where no image is displayed and can be defined as an area extending from the display area AA. Wiring and pad electrodes for transmitting signals to the sub-pixels SP in the display area AA, driver ICs such as gate driver ICs and data driver ICs, and the like may be disposed in the non-display area NA. The non-display area NA may be located on the rear surface of the display panel PN, i.e., on a surface without the sub-pixels SP, or may be omitted, without limitation to that shown in this figure.

[0045] In addition, drivers such as the gate driver GD, the data driver DD, and the timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD can be installed in the non-display area NA in a gate-in-panel (GIP) manner or can be installed between the multiple sub-pixels SP in the display area AA in a gate-in-display-area (GIA) manner. For example, the data driver DD and the timing controller TC can be formed on a separate flexible film and a printed circuit board, and can be connected to the display panel PN by combining the flexible film and the printed circuit board to a pad electrode formed in the non-display area NA of the display panel PN. When the gate driver GD is installed in a GIP manner and the data driver DD and the timing controller TC transmit signals to the display panel PN through the pad electrode in the non-display area NA, the area of the non-display area NA must be ensured to accommodate the gate driver GD and the pad electrode, which increases the border.

[0046] In contrast, when the gate driver GD is installed in the display area AA in a GIA manner and side wiring is formed to connect the signal lines on the front surface of the display panel PN with the pad electrodes on the rear surface of the display panel PN, thereby bonding the flexible film and printed circuit board to the rear surface of the display panel PN, the non-display area NA on the front surface of the display panel PN can be minimized. That is, when the gate driver GD, data driver DD, and timing controller TC are connected to the display panel PN in the same manner as described above, a zero-bezel (zero border) with substantially no border can be achieved.

[0047] Figure 2: is an enlarged plan view of a display device according to an exemplary embodiment of the present disclosure. Figure 2 Only the plurality of sub-pixels SP, the plurality of reflective electrodes RE, the plurality of light emitting diodes ED, and the plurality of connection electrodes CE are illustrated. Figure 2 The diagram illustrates a case where a repair process is performed on the first subpixel SP1 because, among the plurality of subpixels SP, the first red LED EDR1 provided in the first subpixel SP1 is defective and the first green LED EDG1 provided in the second subpixel SP2 and the first blue LED EDB1 provided in the third subpixel SP3 are normal. Here, a defective LED refers to a case where the LED does not light up or does not light up properly because the LED itself is defective or the LED itself is not defective but the electrical connection between the LED and other components is defective.

[0048] First, refer to Figure 2 The display panel PN includes a plurality of pixels composed of a plurality of sub-pixels SP. Each of the plurality of sub-pixels SP includes a light-emitting diode ED and a pixel circuit, and can thus independently emit light. A pixel may include one or more first sub-pixels SP1, one or more second sub-pixels SP2, and one or more third sub-pixels SP3. For example, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, and the third sub-pixel SP3 may be a blue sub-pixel, but the present disclosure is not limited thereto.

[0049] Each of the plurality of sub-pixels SP may include a first region A1 and a second region A2. Details of the first region A1 and the second region A2 are described below. Figure 3 Provide a description.

[0050] A plurality of reflective electrodes RE are provided in the plurality of sub-pixels SP, and the plurality of reflective electrodes RE may include a plurality of first reflective electrodes RE1 and a plurality of second reflective electrodes RE2.

[0051] The plurality of first reflective electrodes RE1 may include a 1-1th reflective electrode RE1a, a 1-2th reflective electrode RE1b, and a 1-3th reflective electrode RE1c.

[0052] The 1-1st reflective electrode RE1a may be disposed adjacent to the first subpixel SP1 among the plurality of subpixels SP. Therefore, the 1-1st reflective electrode RE1a may reflect light emitted from the first and second red light emitting diodes EDR1 and EDR2 toward an upper portion of the 1-1st reflective electrode RE1a.

[0053] The 1-2 reflective electrode RE1b may be disposed adjacent to the second sub-pixel SP2 among the plurality of sub-pixels SP. Therefore, when a second green light-emitting diode is disposed in the second area A2 of the second sub-pixel SP2, the 1-2 reflective electrode RE1b may reflect light emitted from the first green light-emitting diode EDG1 and the second green light-emitting diode toward an upper portion of the 1-2 reflective electrode RE1b.

[0054] The 1-3rd reflective electrode RE1c may be disposed adjacent to the third sub-pixel SP3 among the plurality of sub-pixels SP. Therefore, when the second blue LED is disposed in the second area A2 of the third sub-pixel SP3, the 1-3rd reflective electrode RE1c may reflect light emitted from the first blue LED EDB1 and the second blue LED toward an upper portion of the 1-3rd reflective electrode RE1c.

[0055] Each of the 1-1st reflective electrode RE1a, the 1-2nd reflective electrode RE1b, and the 1-3rd reflective electrode RE1c may electrically connect the driving transistor to the plurality of light emitting diodes ED.

[0056] In addition, the second reflective electrode RE2 may be disposed to overlap with the plurality of sub-pixels SP. The second reflective electrode RE2 may be disposed to overlap with all of the plurality of first light emitting diodes ED1, and may not be disposed to overlap with the second light emitting diode ED2. Figure 2 The second reflective electrode RE2 may overlap the entire first red light emitting diode EDR1 and may not overlap the second red light emitting diode EDR2. Therefore, the second reflective electrode RE2 may reflect light emitted from the plurality of first light emitting diodes ED1 toward an upper portion of the second reflective electrode RE2.

[0057] However, the present disclosure is not limited thereto, and the second reflective electrode RE2 may be disposed to overlap the entire bottom surface of the second light emitting diode ED2 disposed in the second area A2 to reflect light emitted from the second light emitting diode ED2 toward an upper portion of the second reflective electrode RE2.

[0058] The second reflective electrode RE2 may be disposed to be spaced apart from the plurality of first reflective electrodes RE1. Figure 2 When the first to third subpixels SP1, SP2, and SP3 are arranged in one direction, the second reflective electrode RE2 may be arranged to extend along the direction in which the first to third subpixels SP1, SP2, and SP3 are arranged, but is not limited thereto.

[0059] The second reflective electrode RE2 may electrically connect the plurality of power lines VL1 to the plurality of light emitting diodes ED.

[0060] A plurality of connection electrodes CE are disposed above the plurality of reflective electrodes RE. The plurality of connection electrodes CE may be disposed in each of the plurality of sub-pixels SP to electrically connect the plurality of reflective electrodes RE to the plurality of first and second light emitting diodes ED1 and ED2.

[0061] The plurality of connection electrodes CE include a first connection electrode CE1 , a second connection electrode CE2 , and a third connection electrode CE3 .

[0062] The first and second connection electrodes CE1 and CE2 may electrically connect the first and second light emitting diodes ED1 and ED2 to each of the first reflective electrodes RE1, respectively. The third connection electrode CE3 may electrically connect the first and second light emitting diodes ED1 and ED2 to each of the first reflective electrodes RE1. Therefore, the third connection electrode CE3 may be referred to as an additional connection electrode.

[0063] Furthermore, the second and third connection electrodes CE2 and CE3 may be designed in consideration of the electrical characteristics of the second light-emitting diode ED2. For example, the second and third connection electrodes CE2 and CE3 may have widths wider than that of the first connection electrode CE1 in the region overlapping with the second light-emitting diode ED2 in the second area A2. Thus, the electrical characteristics of the second and third connection electrodes CE2 and CE3, and the second light-emitting diode ED2, may be improved, but the present disclosure is not limited thereto.

[0064] The following will refer to Figure 3 Details of the plurality of connection electrodes CE are described.

[0065] A plurality of light emitting diodes ED including a plurality of first light emitting diodes ED1 and a plurality of second light emitting diodes ED2 may be provided in the first area A1 and the second area A2.

[0066] The first light emitting diode ED1 among the multiple light emitting diodes ED is disposed in the first area A1 of the plurality of sub-pixels SP.

[0067] The plurality of first light-emitting diodes ED1 are the light-emitting diodes ED that are initially transferred to the substrate during the manufacturing process of the display device. That is, regardless of whether the plurality of first light-emitting diodes ED1 are defective, the plurality of first light-emitting diodes ED1 are provided in each of the plurality of sub-pixels SP. Therefore, the first light-emitting diodes ED1 may be referred to as main light-emitting diodes.

[0068] The plurality of first light-emitting diodes ED1 include a first red light-emitting diode EDR1, a first green light-emitting diode EDG1, and a first blue light-emitting diode EDB1. The first red light-emitting diode EDR1 may be disposed in the first sub-pixel SP1, the first green light-emitting diode EDG1 may be disposed in the second sub-pixel SP2, and the first blue light-emitting diode EDB1 may be disposed in the third sub-pixel SP3.

[0069] A second light-emitting diode ED2 among the plurality of light-emitting diodes ED is disposed in the second region A2 of the plurality of sub-pixels SP. The second light-emitting diode ED2 is a light-emitting diode that is transferred to the substrate when the first light-emitting diode ED1 disposed in the corresponding sub-pixel is defective. Therefore, the second light-emitting diode ED2 can be referred to as a repair light-emitting diode.

[0070] As described above, when the first red LED EDR1 provided in the first subpixel SP1 is defective, the second LED ED2 may include the second red LED EDR2. Therefore, the second red LED EDR2 may be provided in the first subpixel SP1, but the second LED ED2 may not be provided in the second subpixel SP2 or the third subpixel SP3. However, the present disclosure is not limited thereto. When the first green LED EDG1 provided in the second subpixel SP2 is defective, the second LED ED2 may include the second green LED provided in the second subpixel SP2. Furthermore, when the first blue LED EDB1 provided in the third subpixel SP3 is defective, the second LED ED2 may include the second blue LED provided in the third subpixel SP3.

[0071] Furthermore, the second LED ED2 may have a different structure than the plurality of first LEDs ED1. For example, the second LED ED2 may have a structure that is the inverse of the structure of the first LED ED1. That is, the first LED ED1 and the second LED ED2 may have the same configuration, but in a cross-sectional view, the stacking order of the second LEDs ED2 may be opposite to the stacking order of the first LEDs ED1. Furthermore, in a cross-sectional view of the display device, the bottom surface of the second LED ED2 and the bottom surfaces of the plurality of first LEDs ED1 may be disposed on different planes.

[0072] In addition, although Figure 2 Although not shown, a driving transistor DT may be provided in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, the driving transistor DT may include a first driving transistor provided in the first sub-pixel SP1, a second driving transistor provided in the second sub-pixel SP2, and a third driving transistor provided in the third sub-pixel SP3.

[0073] In this case, when both the first light-emitting diode ED1 and the second light-emitting diode ED2 are provided in one sub-pixel SP, the first light-emitting diode ED1 and the second light-emitting diode ED2 can be connected to the same driving transistor. Therefore, among the plurality of light-emitting diodes ED, the light-emitting diodes ED provided in the same sub-pixel SP can be driven by the same driving transistor.

[0074] However, the present disclosure is not limited thereto, and a plurality of first driving transistors may be provided in the first sub-pixel SP1, a plurality of second driving transistors may be provided in the second sub-pixel SP2, and a plurality of third driving transistors may be provided in the third sub-pixel SP3. Therefore, among the plurality of light-emitting diodes ED, the first light-emitting diode ED1 and the second light-emitting diode ED2 provided in the same sub-pixel SP may be driven by different driving transistors.

[0075] In the following, reference will be made to Figure 3 The first light emitting diode ED1 and the second light emitting diode ED2 are described in more detail.

[0076] Figure 3 It is along Figure 2 The cross-sectional view taken along line AB of FIG. Figure 3 In each of the plurality of sub-pixels SP of the display device 100 according to an exemplary embodiment of the present disclosure, a light shielding layer BSM, a driving transistor DT, a first capacitor C1, a second capacitor C2, a plurality of reflective electrodes RE, a plurality of light emitting diodes ED, a plurality of connecting electrodes CE, a plurality of bonding layers BDL, a plurality of power lines VL1, a dam BB, a third planarization layer 117, a protective layer 160, and an optical film MF may be provided.

[0077] Among the insulating layers disposed on the substrate 110 , the plurality of inorganic insulating layers may include a buffer layer 111 , a gate insulating layer 112 , a first interlayer insulating layer 113 , a second interlayer insulating layer 114 , a first passivation layer 115 a , and a second passivation layer 115 b .

[0078] In addition, among the insulating layers disposed on the substrate 110 , the plurality of organic insulating layers may include a first planarization layer 116 a , an adhesive layer AD, a second planarization layer 116 b , and a third planarization layer 116 c .

[0079] First, the substrate 110 is configured to support various components included in the display device 100 and may be formed of an insulating material. For example, the substrate 110 may be formed of glass, resin, etc. In addition, the substrate 110 may be formed of a polymer or plastic, or may be formed of a flexible material.

[0080] Reference Figure 3, a light shielding layer BSM is provided on the substrate 110. The light shielding layer BSM can minimize leakage current by blocking light incident on the active layer ACT of the plurality of transistors. For example, the light shielding layer BSM can be provided under the active layer ACT of the driving transistor DT to block light incident on the active layer ACT. When light is irradiated on the active layer ACT, leakage current may be generated, thereby deteriorating the reliability of the transistor. Therefore, a light shielding layer BSM that blocks light may be provided on the substrate 110 to improve the reliability of the driving transistor DT. The light shielding layer BSM may be formed of an opaque conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0081] A buffer layer 111 is provided on the light shielding layer BSM. The buffer layer 111 is an inorganic insulating layer that can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 can be composed of, for example, a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, the buffer layer 111 can be omitted depending on the type of substrate 110 or the type of thin film transistor, but is not limited thereto.

[0082] A driving transistor DT including an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE is disposed on the buffer layer 111 .

[0083] In addition, although Figure 3 Although not shown, an additional buffer layer may be provided between the substrate 110 and the light shielding layer BSM. The additional buffer layer is an inorganic insulating layer that can reduce the penetration of moisture or impurities through the substrate 110 in the same manner as the buffer layer 111 described above, and may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0084] First, an active layer ACT of the driving transistor DT is provided on the buffer layer 111. The active layer ACT may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto. In addition, although not shown in the figures, in addition to the driving transistor DT, other transistors such as a switching transistor, a sensing transistor, and a light-emitting control transistor may be provided, and the active layers of these transistors may also be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but the present disclosure is not limited thereto. In addition, the active layers of transistors such as the driving transistor DT, the switching transistor, the sensing transistor, and the light-emitting control transistor included in the pixel circuit may be formed of the same material or may be formed of different materials.

[0085] The gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 is an inorganic insulating layer for electrically insulating the active layer ACT and the gate electrode GE and may be composed of a single layer or double layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0086] The gate electrode GE is disposed on the gate insulating layer 112. The gate electrode GE may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0087] A first interlayer insulating layer 113 and a second interlayer insulating layer 114 are provided on the gate electrode GE. Contact holes for connecting the source electrode SE and the drain electrode DE to the active layer ACT, respectively, are formed in the first interlayer insulating layer 113 and the second interlayer insulating layer 114. The first interlayer insulating layer 113 and the second interlayer insulating layer 114 may be formed of an inorganic insulating layer to protect components below the first interlayer insulating layer 113 and the second interlayer insulating layer 114, and may be formed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but are not limited thereto.

[0088] A source electrode SE and a drain electrode DE electrically connected to the active layer ACT are provided on the second interlayer insulating layer 114. The source electrode SE is connected to the second capacitor C2 and the first electrode 134 of the light-emitting diode ED, and the drain electrode DE is connected to other components of the pixel circuit. The source electrode SE and the drain electrode DE may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but are not limited thereto.

[0089] A plurality of power lines VL1 are provided on the second interlayer insulating layer 114. The plurality of power lines VL1 may transmit a power voltage to the light-emitting diode ED of each of the plurality of sub-pixels SP. For example, the plurality of power lines VL1 may transmit a high-potential power voltage or a low-potential power voltage. The plurality of power lines VL1 may be formed of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof.

[0090] Next, a first capacitor C1 is provided on the gate insulating layer 112. The first capacitor C1 includes a 1-1 capacitor electrode C1a and a 1-2 capacitor electrode C1b.

[0091] First, the 1-1th capacitor electrode C1a is disposed on the gate insulating layer 112. The 1-1th capacitor electrode C1a may be integrated with the gate electrode GE of the driving transistor DT.

[0092] The 1-2 capacitor electrode C1b is provided on the first interlayer insulating layer 113. The 1-2 capacitor electrode C1b is provided so as to overlap with the 1-1 capacitor electrode C1a with the first interlayer insulating layer 113 interposed therebetween.

[0093] Therefore, the first capacitor C1 may be connected to the gate electrode GE of the driving transistor DT and may maintain the voltage of the gate electrode GE of the driving transistor DT for a certain period of time.

[0094] Next, a second capacitor C2 is provided on the substrate 110. The second capacitor C2 includes a 2-1st capacitor electrode C2a, a 2-2nd capacitor electrode C2b, and a 2-3rd capacitor electrode C2c. The second capacitor C2 includes the 2-1st capacitor electrode C2a as a lower capacitor electrode, the 2-2nd capacitor electrode C2b as a middle capacitor electrode, and the 2-3rd capacitor electrode C2c as an upper capacitor electrode.

[0095] The 2-1st capacitor electrode C2a is provided on the substrate 110. The 2-1st capacitor electrode C2a is provided on the same layer as the light shielding layer BSM and may be formed of the same material as the light shielding layer BSM.

[0096] The 2-2nd capacitor electrode C2b is provided on the gate insulating layer 112. The 2-2nd capacitor electrode C2b is provided on the same layer as the gate electrode GE and may be formed of the same material as the gate electrode GE.

[0097] The 2-3 capacitor electrode C2c is disposed on the first interlayer insulating layer 113. The 2-3 capacitor electrode C2c may be composed of a first layer C2c1 and a second layer C2c2. The first layer C2c1 of the 2-3 capacitor electrode C2c may be formed from the same material as the 1-2 capacitor electrode C1b and in the same layer as the 1-2 capacitor electrode C1b. The first layer C2c1 may be disposed so as to overlap the 2-1 capacitor electrode C2a and the 2-2 capacitor electrode C2b with the first interlayer insulating layer 113 interposed therebetween.

[0098] The second layer C2c2 of the 2-3 capacitor electrode C2c is disposed on the second interlayer insulating layer 114. The second layer C2c2 is a portion extending from the source electrode SE of the driving transistor DT and may be connected to the first layer C2c1 through a contact hole in the second interlayer insulating layer 114.

[0099] Therefore, the second capacitor C2 is electrically connected between the source electrode SE of the driving transistor DT and the light emitting diode ED, and thus capacitance inherent in the light emitting diode ED may increase and light with higher brightness may be emitted from the light emitting diode ED.

[0100] A first passivation layer 115a is disposed on the driving transistor DT, the first capacitor C1, and the second capacitor C2. The first passivation layer 115a is an inorganic insulating layer that protects components thereunder and may be formed of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0101] A first planarization layer 116a is provided on the first passivation layer 115a. The first planarization layer 116a may planarize the upper portion of the pixel circuit including the driving transistor DT. The first planarization layer 116a may be composed of a single layer or a double layer and may be formed of, for example, a benzocyclobutene or acrylic-based organic insulating layer.

[0102] Reference Figure 3 A plurality of reflective electrodes RE are provided on the first planarization layer 116 a. The plurality of reflective electrodes RE can function as reflectors that reflect light emitted from the plurality of light-emitting diodes ED toward the upper portion of the substrate 110 while electrically connecting the plurality of light-emitting diodes ED to the plurality of power lines VL1 and the driving transistor DT. The plurality of reflective electrodes RE are formed of a conductive material having excellent reflective properties and can reflect light emitted from the light-emitting diodes ED toward the upper portion of the light-emitting diodes ED.

[0103] Considering light reflection efficiency and resistance, the reflective electrode RE may include various conductive layers. For example, the reflective electrode RE may include an opaque conductive layer such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), or alloys thereof, and a transparent conductive layer such as indium tin oxide (ITO). The structure of the reflective electrode RE is not limited thereto.

[0104] The reflective electrode RE may include a plurality of first reflective electrodes RE1 and a second reflective electrode RE2 disposed to be spaced apart from the plurality of first reflective electrodes RE1 .

[0105] The plurality of first reflective electrodes RE1 may be disposed in a region adjacent to the plurality of sub-pixels SP to reflect light emitted from the plurality of light emitting diodes ED toward upper portions of the plurality of first reflective electrodes RE1.

[0106] The plurality of first reflective electrodes RE1 may include a 1-1th reflective electrode RE1a, a 1-2th reflective electrode RE1b, and a 1-3th reflective electrode RE1c.

[0107] The 1-1st reflective electrode RE1a, the 1-2nd reflective electrode RE1b, and the 1-3rd reflective electrode RE1c may each be connected to the source electrode SE or the drain electrode DE of the driving transistor DT through a contact hole formed in the first planarization layer 116a, and may also be connected to a plurality of individual light emitting diodes ED. Figure 3As shown in FIG, the 1-1st reflective electrode RE1a, the 1-2nd reflective electrode RE1b, and the 1-3rd reflective electrode RE1c may be connected to the source electrode SE of the driving transistor DT, but are not limited thereto.

[0108] First, the 1-1st reflective electrode RE1a, the 1-2nd reflective electrode RE1b, and the 1-3rd reflective electrode RE1c may be connected to the first and second light emitting diodes ED1 and ED2 through the plurality of connection electrodes CE. Figure 3 The 1-1st reflective electrode RE1a can be electrically connected to the first electrode 124 of the first red light emitting diode EDR1 and the first semiconductor layer 121 through the first connection electrode CE1 in the first subpixel SP1, and can be electrically connected to the first electrode 134 of the second red light emitting diode EDR2 and the first semiconductor layer 131 through the second connection electrode CE2.

[0109] Next, among the plurality of connection electrodes CE, the second reflective electrode RE2 may reflect light emitted from the light emitting diode ED toward an upper portion of the second reflective electrode RE2.

[0110] The second reflective electrode RE2 can electrically connect the plurality of power lines VL1 to the plurality of light emitting diodes ED. The second reflective electrode RE2 can be connected to the plurality of power lines VL1 through contact holes formed in the first planarization layer 116a and the first passivation layer 115a. In addition, the second reflective electrode RE2 can be electrically connected to the second electrodes and the second semiconductor layer of the plurality of first light emitting diodes ED1 through the plurality of connection electrodes CE, and can be electrically connected to the second electrodes and the second semiconductor layer of the second light emitting diodes ED2. For example, referring to Figure 3 The second reflective electrode RE2 may be electrically connected to the second electrode 125 and the second semiconductor layer 123 of the first red light emitting diode EDR1 through the third connection electrode CE3 and may be electrically connected to the second electrode 135 and the second semiconductor layer 133 of the second red light emitting diode EDR2.

[0111] In addition, all of the plurality of light emitting diodes ED may be individually connected to the plurality of power lines VL1 without being connected to the reflective electrode RE, but is not limited thereto.

[0112] Reference Figure 3 A second passivation layer 115b is disposed on the plurality of reflective electrodes RE. The second passivation layer 115b is an inorganic insulating layer that protects components thereunder and may be composed of a single layer or double layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0113] A plurality of contact holes may be formed in the second passivation layer 115b to connect the plurality of connection electrodes CE to the plurality of reflective electrodes RE. Therefore, the second passivation layer 115b may expose top surfaces of the plurality of reflective electrodes RE in regions where the plurality of contact holes are provided.

[0114] Reference Figure 2 and Figure 3 , the plurality of contact holes may include a first contact hole CH1 and a plurality of second contact holes CH2 .

[0115] The first contact hole CH1 is provided in the first area A1. Figure 3 The second passivation layer 115b may expose top surfaces of the plurality of first reflective electrodes RE1 in the first contact hole CH1 provided in the first area A1. In the first contact hole CH1, each of the plurality of first light emitting diodes ED1 and each of the plurality of driving transistors DT may be electrically connected through the plurality of first reflective electrodes RE1.

[0116] A plurality of second contact holes CH2 are provided in the second region A2. Figure 3 The second passivation layer 115b may expose the top surfaces of the first reflective electrode RE1 and the second reflective electrode RE2 in the second contact hole CH2 provided in the second area A2. The plurality of second light-emitting diodes ED2, the first reflective electrode RE1, and the second reflective electrode RE2 may be electrically connected in the plurality of second contact holes CH2. For example, in one of the plurality of second contact holes CH2, the plurality of second light-emitting diodes ED2 and the driving transistor DT may be electrically connected, and in another of the plurality of second contact holes CH2, the plurality of second light-emitting diodes ED2 and the plurality of power lines VL1 may be electrically connected.

[0117] In addition, multiple second contact holes CH2 may be provided at both ends of the second area A2. For example, the multiple second contact holes CH2 may expose the top surfaces of the first reflective electrode RE1 and the second reflective electrode RE2 provided at both ends of the second area A2. Furthermore, the multiple second contact holes CH2 may be provided outside the second light-emitting diode ED2 and face each other across the second light-emitting diode ED2. The multiple second contact holes CH2 may be provided on both sides of the concave pattern CP across the concave pattern CP, but are not limited thereto.

[0118] An adhesive layer AD is provided on the second passivation layer 115b. The adhesive layer AD is formed on the front surface of the substrate 110 and can secure the light-emitting diodes ED provided on the adhesive layer AD. The adhesive layer AD can be composed of an organic insulating layer. The adhesive layer AD can be formed of a light-curable adhesive material that can be cured by light. For example, the adhesive layer AD can be formed of an acrylic-based material containing a photosensitizer, but is not limited thereto.

[0119] The adhesive layer AD may planarize the upper portions of the plurality of reflective electrodes RE. For example, the adhesive layer AD may cover between the plurality of reflective electrodes RE spaced apart from each other and planarize the upper portions of the plurality of reflective electrodes RE, but is not limited thereto.

[0120] In the adhesive layer AD, a first contact hole CH1 and a plurality of second contact holes CH2 may be provided to connect the plurality of connection electrodes CE to the plurality of reflective electrodes RE. Therefore, the adhesive layer AD may expose top surfaces of the plurality of reflective electrodes RE in the first contact hole CH1 and the plurality of second contact holes CH2.

[0121] In addition, the adhesive layer AD may have a concave pattern CP in the second area A2. The concave pattern CP is provided at a lower portion of the second light emitting diode ED2 in a stepped structure.

[0122] in addition, Figure 3 Although the adhesive layer AD is illustrated as being relatively thin in the concave pattern CP of the second area A2, the present disclosure is not limited thereto. The adhesive layer AD may not be provided in the concave pattern CP. For example, the adhesive layer AD may be provided only in areas other than the concave pattern CP in the second area A2. That is, the concave pattern CP extends through the entire thickness of the second planarization layer 116b and a portion of the adhesive layer AD in the second area A2, such that the depth of the concave pattern CP is less than the thickness of the second planarization layer 116b and the adhesive layer AD in the second area A2.

[0123] The concave pattern CP may be provided in a region overlapping with the second light emitting diode ED2. Figure 3 , the concave pattern CP may be disposed between the first electrode 134 and the second electrode 135 of the second red light emitting diode EDR2 in the second area A2.

[0124] Reference Figure 2 and Figure 3 , a plurality of light emitting diodes ED are provided in each of the plurality of sub-pixels SP on the adhesive layer AD.

[0125] A first light emitting diode ED1 among the plurality of light emitting diodes ED is disposed in each first area A1 of the plurality of sub-pixels SP.

[0126] Each of the plurality of first light emitting diodes ED1 includes a first semiconductor layer, a light emitting layer, a second semiconductor layer, a first electrode, a second electrode and an encapsulation film. Figure 3 The first red light emitting diode EDR1 may include a first semiconductor layer 121 , a light emitting layer 122 , a second semiconductor layer 123 , a first electrode 124 , a second electrode 125 and an encapsulation film 126 .

[0127] Hereinafter, description will be made assuming that the plurality of first light emitting diodes ED1 have a horizontal structure, but the type of the plurality of first light emitting diodes ED1 is not limited thereto.

[0128] The first semiconductor layer 121 of the first red light-emitting diode EDR1 is disposed on the adhesive layer AD, and the second semiconductor layer 123 is disposed above the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may be layers formed by doping n-type and p-type impurities into a specific material. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may be layers doped with n-type and p-type impurities, respectively, into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), and gallium arsenide (GaAs). In addition, the p-type impurity may be magnesium, zinc (Zn), beryllium (Be), etc., and the n-type impurity may be silicon (Si), germanium, tin (Sn), etc., but the present disclosure is not limited thereto.

[0129] The light emitting layer 122 is provided between the first semiconductor layer 121 and the second semiconductor layer 123. The light emitting layer 122 can emit light by receiving holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123. The light emitting layer 122 may be formed of a single layer or a multiple quantum well (MQW) structure and, for example, may be formed of indium gallium nitride (InGaN), gallium nitride (GaN), etc., but is not limited thereto.

[0130] The light emitting layer 122 and the second semiconductor layer 123 of the first red light emitting diode EDR1 may be disposed to protrude upward from a top surface of the first semiconductor layer 121 .

[0131] The first electrode 124 of the first red light-emitting diode EDR1 is disposed on the first semiconductor layer 121. The first electrode 124 is an electrode for electrically connecting the drive transistor DT to the first semiconductor layer 121. In this case, the first semiconductor layer 121 may be a semiconductor layer doped with n-type impurities, and the first electrode 124 may be a cathode. The first electrode 124 is disposed on the top surface of the first semiconductor layer 121 exposed from the light-emitting layer 122 and the second semiconductor layer 123.

[0132] The first electrode 124 may be formed of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO); an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), alloys thereof, etc., but is not limited thereto.

[0133] The second electrode 125 of the first red light emitting diode EDR1 is disposed on the second semiconductor layer 123. The second electrode 125 may be in contact with the top surface of the second semiconductor layer 123. The second electrode 125 is an electrode for electrically connecting the plurality of power lines VL1 to the second semiconductor layer 123. In this case, the second semiconductor layer 123 may be a semiconductor layer doped with p-type impurities, and the second electrode 125 may be an anode.

[0134] The second electrode 125 may be formed of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO); an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), alloys thereof, etc., but is not limited thereto.

[0135] Next, an encapsulation film 126 is provided around the first semiconductor layer 121, the light emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The encapsulation film 126 is formed of an insulating material and can protect the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123. In addition, contact holes are formed in the encapsulation film 126 to expose the first and second electrodes 124 and 125, so that the first and third connection electrodes CE1 and CE3 can be electrically connected to the first and second electrodes 124 and 125.

[0136] Next, a second planarization layer 116 b and a third planarization layer 116 c are provided on the adhesive layer AD.

[0137] The second planarization layer 116b may be disposed around the side surface portions of the plurality of first light emitting diodes ED1 in the first area A1 to fix and protect the plurality of first light emitting diodes ED1. For example, the second planarization layer 116b may be disposed around the lower side surfaces of the plurality of first light emitting diodes ED1 in the first area A1.

[0138] The second planarization layer 116b may be composed of a single layer or a double layer and may be formed of, for example, a benzocyclobutene or acrylic-based organic insulating layer. The second planarization layer 116b may be formed using a halftone mask. In the second planarization layer 116b, a portion relatively close to the first light-emitting diode ED1 may be formed to have a relatively thin thickness, while a portion relatively far from the first light-emitting diode ED1 may be formed to have a relatively thick thickness.

[0139] The second planarization layer 116 b may cover side surfaces of the plurality of first light emitting diodes ED1 and suppress contact and short circuit defects between the plurality of connection electrodes CE and the first light emitting diodes ED1 .

[0140] The second planarization layer 116 b may cover the top surface of the adhesive layer AD in the second area A2 .

[0141] Additionally, in the first area A1, the first light-emitting diode ED1 may be provided on the same layer as the second planarization layer 116b, but in the second area A2, the second light-emitting diode ED2 may be provided above the second planarization layer 116b. Therefore, the bottom surface of the second light-emitting diode ED2 may be provided at a position higher than the bottom surface of the first light-emitting diode ED1 by the thickness of the second planarization layer 116b. In other words, the bottommost surface of the second light-emitting diode ED2 is higher than the bottommost surface of the first light-emitting diode ED1.

[0142] For example, the thickness of the second passivation layer 115b and the adhesive layer AD disposed between the first planarization layer 116a and the first light-emitting diode ED1 in the first area A may be the first thickness T1, and the thickness of the second passivation layer 115b, the adhesive layer AD, and the second planarization layer 116b disposed between the first planarization layer 116a and the second light-emitting diode ED2 in the second area A2 may be T2, and the thickness T2 may be thicker than the first thickness T1.

[0143] However, the present disclosure is not limited thereto. The second planarization layer 116b may be provided on the same layer as the first and second light-emitting diodes ED1 and ED2, or the second planarization layer 116b may be provided below the first and second light-emitting diodes ED1 and ED2. For example, a single insulating layer may be provided between the first planarization layer 116a and the plurality of light-emitting diodes ED. In this case, the insulating layer may be provided to have different thicknesses in the first and second regions A1 and A2. For example, the insulating layer may have a first thickness in the first region A1 and a second thickness greater than the first thickness in the second region A2. Thus, the first light-emitting diode ED1 may be provided spaced apart from the top surface of the first planarization layer 116a by the first thickness, and the second light-emitting diode ED2 may be provided spaced apart from the top surface of the first planarization layer 116a by the second thickness.

[0144] The second planarization layer 116b may have a concave pattern CP in the second area A2. The concave pattern CP may be provided in an area overlapping with the second light emitting diode ED2.

[0145] Reference Figure 3 The concave pattern CP may be disposed between the first electrode 134 and the second electrode 135 of the second red light emitting diode EDR2 in the second area A2. Therefore, the first electrode 134 and the second electrode 135 may be disposed to be spaced apart from the top surface of the second planarization layer 116b in the concave pattern CP, but is not limited thereto.

[0146] Furthermore, in the cross-sectional view of the display device, the concave pattern CP may be provided between the second connection electrode CE2 and the third connection electrode CE3. Furthermore, with the concave pattern CP interposed between the plurality of bonding layers BDL, the plurality of bonding layers BDL overlap with the second connection electrode CE2 and the third connection electrode CE3. Therefore, the plurality of bonding layers BDL may be spaced apart from one another with the concave pattern CP interposed therebetween. Consequently, the concave pattern CP can suppress short-circuit defects in the second light-emitting diode ED2, in the plurality of bonding layers BDL, and in the second connection electrode CE2 and the third connection electrode CE3.

[0147] in addition, Figure 3 It is illustrated that the second planarization layer 116b is disposed only in the area other than the concave pattern CP in the second area A2, but is not limited thereto. The second planarization layer 116b may be disposed to have a relatively thin thickness in the concave pattern CP and to have a relatively thick thickness in the second area A2 other than the concave pattern CP.

[0148] A first contact hole CH1 and a plurality of second contact holes CH2 may be provided in the second planarization layer 116b to connect the plurality of connection electrodes CE to the plurality of reflective electrodes RE. Therefore, the second planarization layer 116b may expose top surfaces of the plurality of reflective electrodes RE in the first contact hole CH1 and the plurality of second contact holes CH2.

[0149] The third planarization layer 116c may cover the second planarization layer 116b and the upper portion of the first light emitting diode ED1 in the first region A1. In addition, a contact hole exposing the first electrode and the second electrode of the first light emitting diode ED1 may be formed in the third planarization layer 116c. Figure 3 A contact hole exposing the first electrode 124 and the second electrode 125 of the first red light emitting diode EDR1 may be provided in the third planarization layer 116c. The first electrode 124 and the second electrode 125 of the first red light emitting diode EDR1 may be exposed from the third planarization layer 116c, and the third planarization layer 116c may be partially provided in a region between the first electrode 124 and the second electrode 125 to reduce short circuit defects.

[0150] In addition, the third planarization layer 116c may not be provided in the second area A2. For example, the third planarization layer 116c may be provided only in areas other than the second area A2 among the plurality of sub-pixels SP, but is not limited thereto.

[0151] The third planarization layer 116 c may be composed of a single layer or a double layer, and may be formed of, for example, a photoresist or an acrylic-based organic insulating layer.

[0152] in addition, Figure 3The second planarization layer 116b and the third planarization layer 116c are illustrated as being disposed so as to surround the side surface portions of the plurality of first light-emitting diodes ED1 in the first area A1, but the second planarization layer 116b may be disposed so as to surround all side surface portions of the plurality of first light-emitting diodes ED1. In this case, the second planarization layer 116b may be disposed to have different thicknesses in the first area A1 and the second area A2. For example, the second planarization layer 116b may be disposed to have a thickness corresponding to the thickness of the plurality of first light-emitting diodes ED1 in the first area A1 to surround the side surface portions of the plurality of first light-emitting diodes ED1, but may be disposed to have a thickness thinner than the thickness of the plurality of first light-emitting diodes ED1 in the second area A2 to cover the top surface of the adhesive layer AD, but the present invention is not limited thereto.

[0153] A plurality of connection electrodes CE are disposed on the third planarization layer 116 c , and the plurality of connection electrodes CE may include a first connection electrode CE1 , a second connection electrode CE2 , and a third connection electrode CE3 .

[0154] The first connection electrode CE1 may connect the plurality of first light emitting diodes ED1 to the plurality of first reflective electrodes RE1 in the first area A1. In addition, the first connection electrode CE1 may electrically connect the plurality of first light emitting diodes ED1 to the plurality of driving transistors DT.

[0155] The second connection electrode CE2 may electrically connect the second light emitting diode ED2 to the plurality of driving transistors DT in the second area A2.

[0156] The third connection electrode CE3 is connected to the plurality of first and second light-emitting diodes ED1 and ED2 in the first and second areas A1 and A2, and can be electrically connected to the second reflective electrode RE2. Furthermore, the third connection electrode CE3 can be electrically connected to the first and second light-emitting diodes ED1 and ED2 in the first and second areas A1 and A2 through the plurality of second contact holes CH2 formed in the second passivation layer 115b, the adhesive layer AD, and the second planarization layer 116b. Thus, the third connection electrode CE3 can electrically connect the power line VL1 to the first and second light-emitting diodes ED1 and ED2 in one sub-pixel SP.

[0157] In addition, refer to Figure 3 , the second link electrode CE2 and the third link electrode CE3 may be disposed to be spaced apart from each other with the concave pattern CP interposed therebetween.

[0158] The plurality of connection electrodes CE may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0159] In addition, in the drawings, although the first link electrode CE1 and the first reflective electrode RE1 are shown as being electrically connected to the source electrode SE of the driving transistor DT, the third link electrode CE3 and the second reflective electrode RE2 may be connected to the drain electrode DE of the driving transistor DT, but are not limited thereto.

[0160] In addition, the plurality of connection electrodes CE may be provided to have steps along the surface of the insulating layer provided below the plurality of connection electrodes CE. Figure 3 The first connection electrode CE1 may be disposed along the surface of the third planarization layer 116c in the first area A1, and the second connection electrode CE2 and the third connection electrode CE3 may be disposed along the side surface of the second planarization layer 116b in the second area A2. Therefore, the distance between the first connection electrode CE1 and the substrate 110 in the first area A1 may be longer than the distance between the second connection electrode CE2 and the third connection electrode CE3 and the substrate 110 in the second area A2.

[0161] In addition, the plurality of connection electrodes CE may cover the side surfaces of the second passivation layer 115b, the adhesive layer AD, and the second planarization layer 116b in the first contact hole CH1 and the plurality of second contact holes CH2. In this case, the second connection electrode CE2 and the third connection electrode CE3 may be arranged in a stepped shape along the surfaces of the second passivation layer 115b, the adhesive layer AD, and the second planarization layer 116b in the second area A2.

[0162] Reference Figure 3 A bank BB may be provided on the plurality of connection electrodes CE. The bank BB may be formed of an opaque material to reduce color mixing between the plurality of sub-pixels SP, for example, may be formed of black resin, but is not limited thereto.

[0163] The bank BB may be disposed at a distance from the plurality of light emitting diodes ED and may overlap at least a portion of the reflective electrode RE.

[0164] The bank BB may include an opening area corresponding to the second area A2. The opening area of the bank BB may overlap with the second light emitting diode ED2. The bank BB may surround a side surface portion of the second light emitting diode ED2 in the second area A2.

[0165] In addition, the opening area of the bank BB may overlap with the plurality of second contact holes CH2 connecting the second light emitting diode ED2 and the plurality of reflective electrodes RE. Therefore, the bank BB may be provided in an area other than the plurality of second contact holes CH2 connecting the second light emitting diode ED2 and the plurality of reflective electrodes RE. For example, referring to Figure 3The bank BB may be provided in a region other than the plurality of second contact holes CH2 provided on both sides of the second light emitting diode ED2. Therefore, the bank BB may cover a portion of the second and third connection electrodes CE2 and CE3 provided outside the plurality of second contact holes CH2.

[0166] In addition, the present disclosure is not limited thereto, and the bank BB may cover a portion of the second and third connection electrodes CE2 and CE3 formed in the contact holes of the second passivation layer 115 b and the adhesive layer AD.

[0167] In the second area A2, a plurality of bonding layers BDL are provided above the plurality of connection electrodes CE. Figure 3 A plurality of bonding layers BDL are disposed above the second connection electrode CE2 and the third connection electrode CE3. The bonding layer BDL includes a first portion between the second light-emitting diode EDR2 and the second connection electrode CE2, and a second portion between the second light-emitting diode EDR2 and the third connection electrode CE3 in the second area A2. The plurality of bonding layers BDL can secure the second light-emitting diode ED2 to the substrate 110.

[0168] A plurality of bonding layers BDL may be disposed in the second area A2 of the plurality of sub-pixels SP. The plurality of bonding layers BDL are disposed on the second connection electrode CE2 and the third connection electrode CE3 exposed by the bank BB. Thus, the plurality of bonding layers BDL may be electrically connected to the top surfaces of the second connection electrode CE2 and the third connection electrode CE3, respectively disposed below the plurality of bonding layers BDL.

[0169] The plurality of bonding layers BDL may be provided to overlap with the second light emitting diode ED2 among the plurality of light emitting diodes ED. In this case, the bottom surfaces of the plurality of bonding layers BDL may be in contact with the second connection electrode CE2 and the third connection electrode CE3, and the top surfaces of the plurality of bonding layers BDL may be in contact with the first electrode and the second electrode of the second light emitting diode ED2. For example, referring to Figure 3 , top surfaces of the plurality of bonding layers BDL may be in contact with the first electrode 134 and the second electrode 135 of the second red light emitting diode EDR2. Therefore, the plurality of bonding layers BDL may be connected to the second electrode of the second light emitting diode ED2 and the second semiconductor layer, thereby electrically connecting the second light emitting diode ED2 to the driving transistor DT and electrically connecting the second light emitting diode ED2 to the plurality of power lines VL1.

[0170] in addition, Figure 3The diagram illustrates that the plurality of bonding layers BDL are disposed so as not to overlap with the concave pattern CP, but the plurality of bonding layers BDL may be disposed so as to overlap with the concave pattern CP. For example, the plurality of bonding layers BDL may extend from the top surfaces of the second connection electrode CE2 and the third connection electrode CE3 and may also contact the side surface of the second planarization layer 116b surrounding the concave pattern CP and the side surface of the adhesive layer AD. In addition, Figure 3 It is illustrated that the plurality of bonding layers BDL are disposed not to overlap with the plurality of second contact holes CH2 , but the plurality of bonding layers BDL may extend from the second and third connection electrodes CE2 and CE3 to fill the plurality of second contact holes CH2 .

[0171] The multiple bonding layers BDL may be formed of a conductive material. Furthermore, the multiple bonding layers BDL may be formed of a reflective material. For example, the multiple bonding layers BDL may be formed of silver (Ag) or a silver (Ag) alloy, but is not limited thereto. Furthermore, the multiple bonding layers BDL may be formed of any one of silver (Ag) paste, aluminum (Al) paste, gold (Au) paste, and copper (Cu) paste, and may be formed of silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), or alloys thereof, but is not limited thereto.

[0172] Reference Figure 2 and Figure 3 , a second light emitting diode ED2 is provided on the plurality of bonding layers BDL.

[0173] The second light emitting diode ED2 is disposed in at least one sub-pixel SP among the plurality of sub-pixels SP. The second light emitting diode ED2 may be disposed in a second area A2 in the sub-pixel SP.

[0174] The second light emitting diode ED2 may include a first semiconductor layer, a light emitting layer, a second semiconductor layer, a first electrode, a second electrode and an encapsulation film. Figure 3 The second red light emitting diode EDR2 includes a first semiconductor layer 131 , a light emitting layer 132 , a second semiconductor layer 133 , a first electrode 134 , a second electrode 135 and an encapsulation film 136 .

[0175] The second semiconductor layer 133 of the second red light-emitting diode EDR2 is disposed above the second connection electrode CE2, the third connection electrode CE3, and the plurality of bonding layers BDL, and the first semiconductor layer 131 of the second red light-emitting diode EDR2 is disposed above the second semiconductor layer 133. The first semiconductor layer 131 and the second semiconductor layer 133 may be layers formed by doping n-type and p-type impurities into a specific material. For example, the first semiconductor layer 131 and the second semiconductor layer 133 may be layers doped with n-type and p-type impurities, respectively, into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), and gallium arsenide (GaAs). In addition, the p-type impurity may be magnesium, zinc (Zn), beryllium (Be), etc., and the n-type impurity may be silicon (Si), germanium, tin (Sn), etc., but the present disclosure is not limited thereto.

[0176] The light emitting layer 132 of the second red light emitting diode EDR2 is provided between the first semiconductor layer 131 and the second semiconductor layer 133. The light emitting layer 132 can emit light by receiving holes and electrons from the first semiconductor layer 131 and the second semiconductor layer 133. The light emitting layer 132 can be formed of a single layer or a multiple quantum well (MQW) structure and can be formed of, for example, indium gallium nitride (InGaN), gallium nitride (GaN), etc., but is not limited thereto.

[0177] In addition, the light emitting layer 132 and the second semiconductor layer 133 of the second red light emitting diode EDR2 may be disposed to protrude downward from the bottom surface of the first semiconductor layer 131 .

[0178] The first electrode 134 of the second red light emitting diode EDR2 is disposed under the first semiconductor layer 131. The first electrode 134 is an electrode for electrically connecting the driving transistor DT to the first semiconductor layer 131. In this case, the first semiconductor layer 131 may be a semiconductor layer doped with n-type impurities, and the first electrode 134 may be a cathode.

[0179] The first electrode 134 may be formed of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO); an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), alloys thereof, etc., but is not limited thereto.

[0180] The second electrode 135 of the second red light emitting diode EDR2 is disposed under the second semiconductor layer 133. The second electrode 135 may make contact with the second semiconductor layer 133. The second electrode 135 is an electrode for electrically connecting the plurality of power lines VL1 to the second semiconductor layer 133.

[0181] The second electrode 135 may be formed of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO); an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), alloys thereof, etc., but is not limited thereto.

[0182] Next, an encapsulation film 136 is provided around the first semiconductor layer 131, the light emitting layer 132, the second semiconductor layer 133, the first electrode 134, and the second electrode 135. The encapsulation film 136 is formed of an insulating material and can protect the first semiconductor layer 131, the light emitting layer 132, and the second semiconductor layer 133. In addition, contact holes are formed in the encapsulation film 136 to expose the first electrode 134 and the second electrode 135, so that the plurality of bonding layers BDL can be electrically connected to the first electrode 134 and the second electrode 135.

[0183] In addition, the bottom surface of the second light emitting diode ED2 may be disposed at a position higher than the bottom surfaces of the plurality of first light emitting diodes ED1. Figure 3 The first semiconductor layer 121 of the plurality of first red light-emitting diodes EDR1 may be disposed on the adhesive layer AD, and the first and second electrodes 134 and 135 of the second red light-emitting diodes EDR2 may be disposed on the second planarization layer 116 b. Therefore, the bottom surfaces of the second light-emitting diodes ED2 may be disposed higher than the bottom surfaces of the first light-emitting diodes ED1 by the thickness of the second planarization layer 116 b.

[0184] Furthermore, the first red LED EDR1 and the second red LED EDR2 may have the same structure, but the stacking order of the second red LED EDR2 may be opposite to that of the first red LED EDR1. For example, the first red LED EDR1 may be a lateral LED, and the second red LED EDR2 may be a flip-chip LED. Furthermore, the first green LED EDG1 and the first blue LED EDB1 may be lateral LEDs, and the second green LED and the second blue LED may be flip-chip LEDs.

[0185] A fourth planarization layer 117 is provided on the plurality of connection electrodes CE and the bank BB. The fourth planarization layer 117 is a layer for protecting components below the fourth planarization layer 117. The fourth planarization layer 117 may be composed of a single layer or a double layer and may be formed of, for example, benzocyclobutene, a light-transmitting epoxy resin, a photoresist, or an acrylic-based organic material, but is not limited thereto.

[0186] The fourth planarization layer 117 may be disposed to overlap at least a portion of the plurality of light emitting diodes ED. For example, the fourth planarization layer 117 may be disposed in the first area A1 to overlap only the first light emitting diode ED1 among the plurality of light emitting diodes ED.

[0187] In addition, the fourth planarization layer 117 may include an opening region corresponding to the second area A2. The opening region of the fourth planarization layer 117 may overlap with the opening region of the bank BB. For example, in the opening region of the fourth planarization layer 117, the side surface of the fourth planarization layer 117 may be arranged on the same plane as the side surface of the bank BB, but the present invention is not limited thereto. A protective layer 160 may be disposed above the fourth planarization layer 117.

[0188] The protective layer 160 may fill the opening area of the fourth planarization layer 117 and the opening area of the bank BB in the second area A2, cover the second light-emitting diode ED2 disposed in the second area A2, and fix and protect the second light-emitting diode ED2. For example, the protective layer may be formed of a photoresist, an acrylic-based organic material, or a light-transmitting epoxy resin, but is not limited thereto.

[0189] Reference Figure 3 An optical film MF covering the upper portion of the protective layer 160 is provided on the entire upper area of the substrate 110. The optical film MF may be a functional film that protects the display device 100 while achieving a higher definition image. For example, the optical film MF may include an anti-scattering film, an anti-glare film, an anti-reflection film, a low-reflection film, a brightness enhancement film (OLED transmittance controllable film), a polarizer, etc., but is not limited thereto.

[0190] Additionally, an adhesive portion is provided between the protective layer 160 and the optical film MF above the substrate 110. The adhesive portion may be formed on the front surface of the substrate 110 to bond the protective layer 160 and the optical film MF. The adhesive portion may be formed of a light-curable adhesive material that can be cured by light. For example, the adhesive portion may be formed of an acrylic-based material containing a photosensitizer, but is not limited thereto.

[0191] Figure 4 is an enlarged plan view of a display device before a repair process according to an exemplary embodiment of the present disclosure.

[0192] Reference Figure 4 The subpixel SP includes a plurality of first light-emitting diodes ED1 disposed in a first area A1. For example, a first red light-emitting diode EDR1 may be disposed in the first subpixel SP1, a first green light-emitting diode EDG1 may be disposed in the second subpixel SP2, and a first blue light-emitting diode EDB1 may be disposed in the third subpixel SP3. On the other hand, no second light-emitting diode ED2 is disposed in the second area A2.

[0193] A plurality of connection electrodes CE are disposed above the first light emitting diode ED1 in the first area A1 .

[0194] Among the plurality of connection electrodes CE, the second connection electrode CE2 and the third connection electrode CE3 cover an upper portion of the second area A2 where the second light emitting diode ED2 is not disposed.

[0195] Thereafter, a lighting inspection may be performed on the plurality of first light emitting diodes ED1 disposed in the first area A1 of the plurality of sub-pixels SP.

[0196] Figures 5A to 5C 2 is a view illustrating a repair process of a display device according to an exemplary embodiment of the present disclosure.

[0197] Reference Figure 5A , a plurality of first light emitting diodes ED1 are disposed in the first area A1 of the sub-pixel SP, while no second light emitting diode ED2 is disposed in the second area A2.

[0198] A plurality of connection electrodes CE are disposed above the plurality of first light emitting diodes ED1 in the first area A1. The first connection electrode CE1 and the third connection electrode CE3 among the plurality of connection electrodes CE are disposed above the plurality of first light emitting diodes ED1 in the first area A1, and the second connection electrode CE2 and the third connection electrode CE3 cover the upper portion of the second planarization layer 116b in the second area A2. That is, the second connection electrode CE2 and the third connection electrode CE3 in the second area A2 are in contact with the upper surface of the second planarization layer 116b. Figure 5A As shown in FIG, the third link electrode CE3 includes a first portion connected to the second electrode 125 in the first area A1 and a second portion located in the second area A2 at a height less than that of the first portion of the third link electrode CE3 in the first area A1.

[0199] In addition, the second planarization layer 116b is provided to have a flat top surface in the region except for the plurality of second contact holes CH2 in the second area A2. Therefore, in the second area A2, the top surface of the second planarization layer 116b and the bottom surfaces of the second and third connection electrodes CE2 and CE3 may be provided on the same plane.

[0200] The bank BB and the fourth planarization layer 117 are sequentially disposed on the plurality of connection electrodes CE. Figure 5A As shown in FIG, the bank BB is within the first contact hole CH1 in the first area A1 and within the second contact hole CH2 in the second area A2. Figure 5A The structure shown in FIG1 is a representative example of a normal operation of the first red light emitting diode ED1. That is, the first red light emitting diode EDR1 has no defects.

[0201] A lighting inspection may be performed on the plurality of first light-emitting diodes ED1 disposed in the first area A1 of the plurality of sub-pixels SP, and a repair process may be performed on the defective sub-pixel SP. As described above, a case will be described where, among the plurality of sub-pixels SP, the first red light-emitting diode EDR1 disposed in the first sub-pixel SP1 is defective and the first green light-emitting diode EDG1 disposed in the second sub-pixel SP2 and the first blue light-emitting diode EDB1 disposed in the third sub-pixel SP3 are normal, and therefore a repair process is performed on the first sub-pixel SP1.

[0202] Reference Figure 5B , the bank BB and the fourth planarization layer 117 are removed from the second area A2 of the defective sub-pixel SP. For example, the bank BB and the fourth planarization layer 117 located in the second area A2 are removed using a laser process. In this case, the laser process may be performed with a width greater than the width of the second red light-emitting diode EDR2 to be located in the second area A2. Furthermore, the laser process may expose portions of the top surfaces of the second and third connection electrodes CE2 and CE3 corresponding to the region of the second red light-emitting diode EDR2, as well as the top surfaces of the second and third connection electrodes CE2 and CE3 that overlap with the plurality of second contact holes CH2.

[0203] In this case, portions of the second planarization layer 116b and the adhesive layer AD exposed between the second and third connection electrodes CE2 and CE3 are removed. Thus, a concave pattern CP disposed between the second and third connection electrodes CE2 and CE3 is formed in the second planarization layer 116b and the adhesive layer AD.

[0204] Next, refer to Figure 5C Liquid metal ink is applied to the exposed second connection electrode CE2 and third connection electrode CE3. The liquid metal ink may be a solution in which metal nanoparticles are dispersed. The liquid metal ink may be, for example, a metal organic ion ink, a metal nanoparticle ink, or a metal nanoparticle paste. When the liquid metal ink is a silver (Ag) paste, it may be a solution in which silver (Ag) nanoparticles are uniformly dispersed in an organic solvent.

[0205] Next, the second red LED EDR2 as the repair LED is transferred onto the liquid metal ink. The second red LED EDR2 can be partially transferred using a stamping (STP), but is not limited thereto.

[0206] The second semiconductor layer 133 of the second red light emitting diode EDR2 is disposed below the first semiconductor layer 131. In this case, the second electrode 135 of the second red light emitting diode EDR2 contacts the liquid metal ink disposed above the third connection electrode CE3, and the first electrode 134 of the second red light emitting diode EDR2 contacts the liquid metal ink disposed above the second connection electrode CE2.

[0207] Afterwards, a sintering process is performed on the liquid metal ink. During the sintering process, the solvent contained in the liquid metal ink is evaporated. Therefore, after the sintering process, a plurality of bonding layers BDL may be formed on the second connection electrode CE2 and the third connection electrode CE3, and the first electrode 134 and the second connection electrode CE2 of the second red light emitting diode EDR2 may be electrically connected, and the second electrode 135 and the third connection electrode CE3 of the second red light emitting diode EDR2 may be electrically connected.

[0208] Thereafter, a protection layer 160 may be applied on an upper portion of the second red light emitting diode EDR2 to surround side surfaces of the second red light emitting diode EDR2 and side surfaces of the bank BB.

[0209] Typically, among the multiple sub-pixels provided on the substrate, defective sub-pixels that do not emit light normally may appear. For example, a defective sub-pixel may appear in which the light-emitting diode itself is defective or the electrical connection between the light-emitting diode and the transistor and the power line is defective. In this case, the defective sub-pixel does not light up, or even if the defective sub-pixel emits light, the defective sub-pixel emits light very weakly, making it difficult to use as a normal sub-pixel. Therefore, in the display device, after the lighting inspection, only the sub-pixel illuminated by the defective first light-emitting diode is transferred to emit a second light-emitting diode that emits the same color as the first light-emitting diode. For example, after the lighting inspection, a laser process is performed to perform local repair. In the repair process, the embankment is opened in the second area of the sub-pixel that needs to be repaired, exposing a plurality of connection electrodes, and the second light-emitting diode is transferred to the plurality of connection electrodes.

[0210] However, it is difficult to accurately transfer the second LED within the repair area. For example, when using a laser process to perform repair locally, process errors may occur, making it difficult to accurately transfer the second LED to the repair location. For example, when transferring the second LED by removing an insulating layer including a bank, as the movement distance corresponding to the thickness of the insulating layer increases, alignment errors may increase, or the second LED may become misaligned or tilted. As a result, contact defects may occur between the multiple connection electrodes and the second LED, or short circuit defects may occur between the multiple connection electrodes and the electrodes of the second LED.

[0211] Therefore, in the exemplary display device 100 according to the present disclosure, the second light-emitting diodes ED2 are arranged in the second area A2 so as to protrude upwards relative to the plurality of first light-emitting diodes ED1. For example, the insulating layer disposed on the first planarization layer 116a is thicker in the second area A2 than in the first area A1. Therefore, the top surfaces of the second connection electrodes CE2 and the third connection electrodes CE3 can be disposed above the bottom surfaces of the first light-emitting diodes ED1. Therefore, by reducing the movement distance of the second light-emitting diodes ED2 during the repair process, the transfer position can be easily controlled. Consequently, the second connection electrodes CE2 and the third connection electrodes CE3 can be easily bonded to the second light-emitting diodes ED2, improving the degradation of electrical contact characteristics caused by the deflection or tilting of the second light-emitting diodes ED2. Consequently, the second light-emitting diodes ED2 can be stably fixed to the second area A2, and the reliability of the repair process can be improved.

[0212] Furthermore, in the display device 100 according to an exemplary embodiment of the present disclosure, the plurality of second contact holes CH2 disposed in the second area A2 are disposed at both ends of the bonding layer BDL. Furthermore, the plurality of second contact holes CH2 are disposed at both ends of the second light-emitting diode ED2, and the second planarization layer 116b and the adhesive layer AD within the plurality of second contact holes CH2 may form a stepped structure. Therefore, when the bonding layer BDL overflows in the second area A2, the bonding layer BDL may move to the plurality of second contact holes CH2. Consequently, the plurality of bonding layers BDL may be prevented from moving to the center of the second area A2, and may be prevented from connecting to each other. Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, short-circuit defects between the second connection electrode CE2 and the third connection electrode CE3, as well as short-circuit defects in the second light-emitting diode ED2, may be suppressed.

[0213] Furthermore, in the exemplary display device 100 according to the present disclosure, a concave pattern CP is provided between the second connection electrode CE2 and the third connection electrode CE3 in the second area A2. Therefore, when the bonding layer BDL overflows, the bonding layer BDL can move in the direction in which the concave pattern CP is provided and can move to the stepped region of the concave pattern CP. Consequently, the plurality of bonding layers BDL can be disconnected between the second connection electrode CE2 and the third connection electrode CE3. Therefore, the concave pattern CP can prevent the plurality of bonding layers BDL from connecting to each other, thereby preventing a short circuit between the second connection electrode CE2 and the third connection electrode CE3, and thus a short circuit in the second light-emitting diode.

[0214] Figure 6 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. Figure 6 The display device 600 and Figures 1 to 5CThe display device 100 is different only in the bonding layer BDL, and other components are substantially the same, so repeated description will be omitted.

[0215] Reference Figure 6 A plurality of bonding layers BDL are disposed above the second and third connection electrodes CE2 and CE3 in the second area A2. The plurality of bonding layers BDL can fix the second light emitting diode ED2 on the substrate 110.

[0216] The plurality of bonding layers BDL may be formed of a conductive material. For example, the plurality of bonding layers BDL may be formed of an anisotropic conductive paste (ACP) containing conductive balls. For example, the plurality of bonding layers BDL may be an insulating layer having conductive balls dispersed therein, and the conductive balls may be attached to the lower portions of the first and second electrodes of the second light-emitting diode ED2 to electrically connect the second connection electrode CE2 and the third connection electrode CE3 to the second light-emitting diode ED2.

[0217] Therefore, in the display device 600 according to another exemplary embodiment of the present disclosure, the second light-emitting diode ED2 is arranged to protrude upward from the plurality of first light-emitting diodes ED1 in the second area A2. Therefore, the second and third connection electrodes CE2 and CE3 can be easily bonded to the second light-emitting diode ED2, and the second light-emitting diode ED2 can be stably fixed to the second area A2, thereby improving the reliability of the repair process.

[0218] Furthermore, in a display device 600 according to another exemplary embodiment of the present disclosure, a plurality of second contact holes CH2 disposed in the second area A2 are disposed at both ends of the bonding layer BDL, so that overflowing bonding layer BDL can move to the plurality of second contact holes CH2. Therefore, a short-circuit defect between the second and third connection electrodes CE2 and CE3, as well as a short-circuit defect of the second light-emitting diode ED2, can be suppressed.

[0219] Furthermore, in another exemplary display device 600 according to the present disclosure, a concave pattern CP is provided between the second connection electrode CE2 and the third connection electrode CE3 in the second area A2. Therefore, the concave pattern CP can prevent the multiple bonding layers BDL from connecting to each other. For example, during the process of attaching a light-emitting diode to the ACP, the conductive balls of the ACP can connect to each other due to heat and / or pressure, thereby causing a short circuit. Therefore, in another exemplary display device 600 according to the present disclosure, the concave pattern CP can prevent the multiple bonding layers BDL from connecting to each other, and can also prevent the second connection electrode CE2 and the third connection electrode CE3 from short-circuiting, as well as the second light-emitting diode ED2 from short-circuiting.

[0220] Exemplary embodiments of the present disclosure may also be described as follows:

[0221] According to one aspect of the present disclosure, a display device is provided. The display device includes: a substrate having a plurality of sub-pixels defined thereon, each of the plurality of sub-pixels including a first region and a second region; a plurality of reflective electrodes disposed on the substrate; a plurality of transistors disposed in each of the plurality of sub-pixels on the substrate; a plurality of first light-emitting diodes disposed in the first region of each of the plurality of sub-pixels; and at least one second light-emitting diode disposed in the second region of at least one of the plurality of sub-pixels and different from the plurality of first light-emitting diodes, wherein, in a cross-sectional view of the display device, a bottom surface of the second light-emitting diode and a bottom surface of the plurality of first light-emitting diodes are disposed on different planes.

[0222] With the substrate as a reference, a bottom surface of the second light emitting diode is at a height higher than bottom surfaces of the plurality of first light emitting diodes.

[0223] The display device further includes: an insulating layer disposed on the substrate; and a bank disposed on the insulating layer, wherein the insulating layer includes a plurality of contact holes connecting the second light emitting diode and the plurality of reflective electrodes, and the bank does not overlap with the plurality of contact holes.

[0224] The display device also includes: a planarization layer that planarizes the upper portions of the multiple transistors; and an insulating layer arranged above the planarization layer and below the multiple first light-emitting diodes and the second light-emitting diodes, wherein the thickness of the insulating layer in the first region is different from the thickness of the insulating layer in the second region.

[0225] The thickness of the insulating layer has a first thickness in the first region and has a second thickness greater than the first thickness in the second region.

[0226] In the second region, the insulating layer includes a concave pattern passing through the insulating layer, and in the concave pattern, a thickness of the insulating layer is thinner than the second thickness in the second region.

[0227] The concave pattern overlaps with the second light emitting diode.

[0228] The display device may also include: a connecting electrode electrically connecting the multiple first light-emitting diodes and the second light-emitting diodes to the multiple driving transistors, wherein the connecting electrode is located above the multiple first light-emitting diodes and overlaps with the multiple first light-emitting diodes in the first area, and the connecting electrode overlaps with the second light-emitting diodes in the second area and is located below the second light-emitting diodes.

[0229] The plurality of first light-emitting diodes and the second light-emitting diodes each include a plurality of layers, the plurality of layers including: a first semiconductor layer; a second semiconductor layer having a width smaller than that of the first semiconductor layer; a light-emitting layer having a width smaller than that of the first semiconductor layer, the light-emitting layer being between the first semiconductor layer and the second semiconductor layer; a first electrode in contact with the first semiconductor layer; and a second electrode in contact with the second semiconductor layer, wherein the stacking order of the plurality of layers of the plurality of first light-emitting diodes is reversed from the stacking order of the plurality of layers of the second light-emitting diodes.

[0230] The plurality of reflective electrodes include: a plurality of first reflective electrodes; and a second reflective electrode that is separated from the plurality of first reflective electrodes and is on the same plane as the plurality of first reflective electrodes, the second reflective electrode overlapping the plurality of first light-emitting diodes in the first area, wherein the connecting electrodes include: a first connecting electrode connected to the plurality of first light-emitting diodes and the plurality of first reflective electrodes; a second connecting electrode connected to the second light-emitting diodes and the plurality of first reflective electrodes; and a third connecting electrode connected to the plurality of first light-emitting diodes, the second light-emitting diodes, and the second reflective electrode.

[0231] The display device further includes a bonding layer provided between the second light emitting diode and the second connection electrode and between the second light emitting diode and the third connection electrode in the second region.

[0232] The display device further includes an insulating layer under a portion of the second connecting electrode and a portion of the third connecting electrode, wherein the insulating layer includes a concave pattern between the portion of the second connecting electrode and the portion of the third connecting electrode.

[0233] The bonding layer includes silver paste.

[0234] The bonding layer includes anisotropic conductive paste.

[0235] According to another aspect of the present disclosure, a display device is provided. The display device includes: a substrate; a subpixel on the substrate, the subpixel including a first region and a second region separated from the first region; a transistor on the substrate; a light-emitting diode in the first region, the light-emitting diode including a first electrode and a second electrode; a first connecting electrode connected to the first electrode of the light-emitting diode in the first region, the first connecting electrode electrically connecting the first electrode to the transistor; an additional connecting electrode including: a first portion of the additional connecting electrode connected to the second electrode in the first region, and a second portion located in the second region at a height less than that of the first portion of the additional connecting electrode in the first region, the additional connecting electrode electrically connecting the second electrode of the light-emitting diode to a power line; and a dam including: a first portion of the dam in the first region, a second portion of the dam on the second portion of the additional connecting electrode in the second region, and an opening overlapping the light-emitting diode in the first region.

[0236] The display device further includes: a planarization layer in the first region and the second region, the planarization layer being located on the transistor in the first region; a first reflective electrode on the planarization layer, the first reflective electrode being connected to the first connection electrode in the first region and to the transistor; and a second reflective electrode on the planarization layer and on the same plane as the first reflective electrode, the second reflective electrode being connected to the second portion of the additional connection electrode in the second region.

[0237] The display device further includes an insulating layer, the insulating layer including a first portion of the insulating layer between the light-emitting diode and the second reflective electrode in the first region, and a second portion of the insulating layer overlapping the second portion of the additional connection electrode in the second region, wherein a thickness of the second portion of the insulating layer in the second region is greater than a thickness of the first portion of the insulating layer in the first region.

[0238] The second portion of the additional connection electrode in the second region is in contact with an upper surface of the second portion of the insulating layer in the second region.

[0239] The display device further includes a second connection electrode in contact with an upper surface of the second portion of the insulating layer in the second region, the second connection electrode being spaced apart from the additional connection electrode on the upper surface of the second portion of the insulating layer.

[0240] The display device further includes: a first contact hole passing through the first portion of the insulating layer in the first region, the first connection electrode being connected to the first reflective electrode through the first contact hole; and a second contact hole passing through the second portion of the insulating layer in the second region, the additional connection electrode being connected to the second reflective electrode through the second contact hole.

[0241] The first portion of the bank is within the first contact hole, and the second portion of the bank is within the second contact hole.

[0242] The light emitting diode includes: a first semiconductor layer, the first semiconductor layer including a first portion of the first semiconductor layer and a second portion of the first semiconductor layer; a second semiconductor layer, the second semiconductor layer overlapping the first portion of the first semiconductor layer but not overlapping the second portion of the first semiconductor layer; and a light emitting layer between the second semiconductor layer and the first portion of the first semiconductor layer, wherein the first electrode is on the first portion of the first semiconductor layer and the second electrode is on the second semiconductor layer.

[0243] A portion of the first connection electrode connected to the first electrode is above the light emitting diode, and a portion of the additional connection electrode connected to the second connection electrode is above the light emitting diode.

[0244] The second portion of the additional connection electrode in the second region is configured to be connected to another light emitting diode in the second region, except that the second region does not have another light emitting diode.

[0245] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto, and the present disclosure can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided only for the purpose of illustration and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are merely illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the subsequent claims, and all technical concepts within the equivalent scope should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device comprising: a substrate having a plurality of sub-pixels defined thereon, each of the plurality of sub-pixels comprising a first region and a second region; a plurality of reflective electrodes disposed on the substrate; a plurality of transistors disposed in each of the plurality of sub-pixels on the substrate; a plurality of first light emitting diodes respectively disposed in the first regions of the plurality of sub-pixels; and at least one second light emitting diode that is provided in the second region of at least one sub-pixel among the plurality of sub-pixels and is different from the plurality of first light emitting diodes, In the cross-sectional view of the display device, the bottom surface of the second light-emitting diode and the bottom surfaces of the plurality of first light-emitting diodes are arranged on different planes. 2 . The display device according to claim 1 , wherein a bottom surface of the second light emitting diode is at a higher height than bottom surfaces of the plurality of first light emitting diodes with reference to the substrate.

3. The display device according to claim 1, further comprising: an insulating layer disposed on the substrate; and a bank provided on the insulating layer, wherein the insulating layer comprises a plurality of contact holes connecting the second light emitting diode and the plurality of reflective electrodes, and The bank does not overlap with the plurality of contact holes.

4. The display device according to claim 1, further comprising: a planarization layer for planarizing upper portions of the plurality of transistors; and an insulating layer disposed above the planarization layer and below the plurality of first light emitting diodes and the second light emitting diodes, The thickness of the insulating layer in the first region is different from the thickness of the insulating layer in the second region. 5 . The display device according to claim 4 , wherein a thickness of the insulating layer has a first thickness in the first region and has a second thickness greater than the first thickness in the second region. The display device according to claim 5 , wherein: In the second region, the insulating layer includes a concave pattern passing through the insulating layer, and In the concave pattern, the thickness of the insulating layer is thinner than the second thickness in the second region. The display device according to claim 6 , wherein the concave pattern overlaps with the second light emitting diode.

8. The display device according to claim 1, further comprising: electrically connecting the plurality of first light emitting diodes and the second light emitting diodes to the connection electrodes of the plurality of driving transistors, The connecting electrode is located above and overlaps the first light emitting diodes in the first region, and the connecting electrode overlaps and is located below the second light emitting diodes in the second region.

9. The display device according to claim 8, wherein each of the plurality of first light emitting diodes and the second light emitting diodes comprises a plurality of layers, the plurality of layers comprising: a first semiconductor layer; a second semiconductor layer having a width smaller than that of the first semiconductor layer; a light emitting layer having a width smaller than that of the first semiconductor layer, the light emitting layer being between the first semiconductor layer and the second semiconductor layer; a first electrode in contact with the first semiconductor layer; and a second electrode in contact with the second semiconductor layer, The stacking order of the multiple layers of the multiple first light-emitting diodes is reversed to the stacking order of the multiple layers of the second light-emitting diodes.

10. The display device according to claim 8, wherein the plurality of reflective electrodes comprises: a plurality of first reflective electrodes; and a second reflective electrode separated from the plurality of first reflective electrodes and on the same plane as the plurality of first reflective electrodes, the second reflective electrode overlapping the plurality of first light emitting diodes in the first region, The connecting electrodes include: a first connection electrode connected to the plurality of first light emitting diodes and the plurality of first reflective electrodes; a second connection electrode connected to the second light emitting diode and the plurality of first reflective electrodes; and A third connection electrode is connected to the plurality of first light emitting diodes, the second light emitting diode, and the second reflective electrode.

11. The display device according to claim 10, further comprising: A bonding layer is provided between the second light emitting diode and the second connection electrode and between the second light emitting diode and the third connection electrode in the second region.

12. The display device according to claim 11, further comprising: an insulating layer below a portion of the second connection electrode and a portion of the third connection electrode, wherein the insulating layer includes a concave pattern between the portion of the second connecting electrode and the portion of the third connecting electrode. The display device according to claim 11 , wherein the bonding layer comprises silver paste. The display device according to claim 11 , wherein the bonding layer comprises an anisotropic conductive paste.

15. A display device comprising: substrate; a sub-pixel on the substrate, the sub-pixel comprising a first region and a second region separated from the first region; a transistor on the substrate; a light emitting diode in the first region, the light emitting diode comprising a first electrode and a second electrode; a first connecting electrode connected to the first electrode of the light emitting diode in the first region, the first connecting electrode electrically connecting the first electrode and the transistor; an additional connection electrode, the additional connection electrode comprising: a first portion of the additional connection electrode connected to the second electrode in the first region, and a second portion located in the second region at a height smaller than that of the first portion of the additional connection electrode in the first region, the additional connection electrode electrically connecting the second electrode of the light emitting diode and a power line; and The bank includes a first portion of the bank in the first region, a second portion of the bank on the second portion of the additional connection electrode in the second region, and an opening overlapping the light emitting diode in the first region.

16. The display device according to claim 15, further comprising: a planarization layer in the first region and the second region, the planarization layer being located on the transistor in the first region; a first reflective electrode on the planarization layer, the first reflective electrode being connected to the first connection electrode in the first region and to the transistor; as well as A second reflective electrode is provided on the planarization layer and on the same plane as the first reflective electrode, the second reflective electrode being connected to the second portion of the additional connection electrode in the second region.

17. The display device according to claim 16, further comprising: an insulating layer, the insulating layer comprising: a first portion of the insulating layer between the light-emitting diode and the second reflective electrode in the first region, and a second portion of the insulating layer overlapping the second portion of the additional connection electrode in the second region, The thickness of the second portion of the insulating layer in the second region is greater than the thickness of the first portion of the insulating layer in the first region. 18 . The display device according to claim 17 , wherein the second portion of the additional connection electrode in the second region is in contact with an upper surface of the second portion of the insulating layer in the second region.

19. The display device according to claim 18, further comprising: A second connection electrode is in contact with an upper surface of the second portion of the insulating layer in the second region, the second connection electrode being spaced apart from the additional connection electrode on the upper surface of the second portion of the insulating layer.

20. The display device according to claim 17, further comprising: a first contact hole passing through the first portion of the insulating layer in the first region, the first connection electrode being connected to the first reflective electrode through the first contact hole; and The additional connection electrode is connected to the second reflective electrode through a second contact hole passing through the second portion of the insulating layer in the second region. 21 . The display device of claim 20 , wherein the first portion of the bank is within the first contact hole, and the second portion of the bank is within the second contact hole.

22. The display device according to claim 15, wherein the light emitting diode comprises: a first semiconductor layer, the first semiconductor layer comprising a first portion of the first semiconductor layer and a second portion of the first semiconductor layer; a second semiconductor layer, the second semiconductor layer overlapping the first portion of the first semiconductor layer but not overlapping the second portion of the first semiconductor layer; and a light emitting layer between the second semiconductor layer and the first portion of the first semiconductor layer, The first electrode is on the first portion of the first semiconductor layer and the second electrode is on the second semiconductor layer. 23 . The display device according to claim 22 , wherein a portion of the first connection electrode connected to the first electrode is above the light emitting diode, and a portion of the additional connection electrode connected to the second connection electrode is above the light emitting diode. 24 . The display device according to claim 15 , wherein the second portion of the additional connection electrode in the second region is configured to be connected to another light emitting diode in the second region except that the second region does not have another light emitting diode.

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