Display device

Abstract

A display device according to one embodiment is provided with: first pixels disposed in a display region in which an image is displayed; a transmissive region disposed in the display region; and a partition wall disposed in the display region, the partition wall including a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion. The first pixel includes a plurality of sub-pixels surrounded by the partition wall. The transmissive region includes a plurality of sub-regions surrounded by the partition wall and transmitting at least a portion of the light incident on the transmissive region.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority based on Japanese Patent Application No. 2024-11695, filed on January 30, 2024, and incorporates by reference all the contents described in that Japanese Patent Application. Technical Field

[0003] Embodiments of the present invention relate to a display device. Background Art

[0004] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have become practical. These display elements include a lower electrode, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. A common voltage is applied to the upper electrode of each display element via wiring arranged in the display area.

[0005] In addition, sometimes at least a portion of the display region where the display elements are arranged is desired to be light-transmissive. However, if the lower electrode and wiring are formed of a light-shielding material such as metal, the light transmittance of the display device may be significantly reduced. Summary of the Invention

[0006] Generally speaking, according to an embodiment, a display device includes: a first pixel disposed in a display area for displaying an image; a transmissive region disposed in the display area; and a partition wall disposed in the display area, including a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion. The first pixel includes a plurality of sub-pixels surrounded by the partition wall. The transmissive region includes a plurality of sub-regions surrounded by the partition wall and transmitting at least a portion of light incident on the transmissive region.

[0007] According to the embodiment, a display device having excellent light transmittance can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a diagram showing a configuration example of a display device according to the first embodiment.

[0009] Figure 2 1 is a circuit diagram showing an example of a configuration applicable to a pixel circuit included in each sub-pixel.

[0010] Figure 3 This is a schematic plan view showing an example of the layout of sub-pixels in one pixel.

[0011] Figure 4 It is along Figure 3 A schematic cross-sectional view of the display panel taken along line IV-IV in FIG.

[0012] Figure 5This is a schematic plan view showing a portion of the first area.

[0013] Figure 6 It is a schematic plan view showing a part of the second area.

[0014] Figure 7 This is another schematic plan view showing a portion of the second area.

[0015] Figure 8 It is along Figure 6 A schematic cross-sectional view of the second region along line VIII-VIII in FIG.

[0016] Figure 9 It is a schematic cross-sectional view showing another structure that can be applied to the second region.

[0017] Figure 10 It is a schematic plan view showing still another structure that can be applied to the second area.

[0018] Figure 11 It is a schematic plan view showing another example of the opening of the rib layer.

[0019] Figure 12 It is along Figure 10 A schematic cross-sectional view of the second region along line XII-XII.

[0020] Figure 13A It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0021] Figure 13B It means next Figure 13A A schematic cross-sectional view of the process.

[0022] Figure 13C It means next Figure 13B A schematic cross-sectional view of the process.

[0023] Figure 13D It means next Figure 13C A schematic cross-sectional view of the process.

[0024] Figure 13E It means next Figure 13D A schematic cross-sectional view of the process.

[0025] Figure 13F It means next Figure 13E A schematic cross-sectional view of the process.

[0026] Figure 13G It means next Figure 13F A schematic cross-sectional view of the process.

[0027] Figure 13H It means next Figure 13G A schematic cross-sectional view of the process.

[0028] Figure 13I It means next Figure 13H A schematic cross-sectional view of the process.

[0029] Figure 14 This is a schematic plan view showing a portion of the second region in the second embodiment.

[0030] Figure 15 It is a schematic plan view showing a part of the second area of the third embodiment. DETAILED DESCRIPTION

[0031] Refer to the attached Figure 1 Several implementation methods are described.

[0032] The disclosed content is merely an example, and those skilled in the art will readily be able to conceive of appropriate modifications that maintain the spirit of the invention, which are naturally included in the scope of the present invention. In addition, in order to make the description clearer, there are cases where the width, thickness, shape, etc. of each part are schematically shown in the drawings compared to the actual state, but this is merely an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, structural elements that perform the same or similar functions as the structural elements described above with respect to the existing figures are sometimes marked with the same reference numerals, and repeated detailed descriptions are appropriately omitted.

[0033] In the drawings, for ease of understanding, mutually orthogonal X-axis, Y-axis, and Z-axis are depicted. The direction along the X-axis is referred to as the X-direction, the direction along the Y-axis is referred to as the Y-direction, and the direction along the Z-axis is referred to as the Z-direction. The Z-direction is the normal direction of the plane containing the X-direction and the Y-direction. Observing various elements parallel to the Z-direction is referred to as planar observation.

[0034] The display device of each embodiment is an organic electroluminescent display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, vehicle-mounted equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0035] [First embodiment]

[0036] Figure 1 This diagram shows an example configuration of a display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 includes a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0037] In this embodiment, the shape of the substrate 10 in plan view is a rectangle. However, the shape of the substrate 10 in plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0038] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of sub-pixels SP that display different colors. In this embodiment, a pixel PX is assumed to include three sub-pixels SP1, SP2, and SP3 (the first to third sub-pixels). For example, sub-pixel SP1 displays green, sub-pixel SP2 displays blue, and sub-pixel SP3 displays red. However, the colors displayed by sub-pixels SP1, SP2, and SP3 are not limited to this example. Furthermore, the pixel PX may include sub-pixels SP of other colors, such as white, in addition to or instead of sub-pixels SP1, SP2, and SP3.

[0039] The display area DA includes a first area A1 and a second area A2 with higher light transmittance than the first area A1. A camera CR, for example, is positioned behind the second area A2. This camera CR can capture images of objects on the display surface through the second area A2. Alternatively, another type of light-receiving element, such as an illuminance sensor that detects external light, may be positioned in place of the camera CR. Furthermore, the display area DA may include multiple second areas A2 facing the camera CR or illuminance sensor.

[0040] For example, the second area A2 is smaller than the first area A1. Figure 1 In the example shown, the second area A2 is located near the end of the display area DA and is surrounded by the first area A1. However, the arrangement of the second area A2 is not limited to this example. The second area A2 does not necessarily need to be completely surrounded by the first area A1; it can also be arranged so that one or both sides face the surrounding area SA. The second area A2 is, for example, rectangular, but may also be a circular or other shape.

[0041] Figure 2 1 is a circuit diagram showing an example of a configuration applicable to a pixel circuit PC included in each of the sub-pixels SP (SP1, SP2, SP3). The pixel circuit PC shown in the figure includes seven transistors TR1 to TR7 and one storage capacitor Cst.

[0042] In the following description, one of the source / drain electrodes of each of transistors TR1 to TR7 is referred to as a first electrode, and the other as a second electrode. Similarly, one of a pair of electrodes constituting storage capacitor Cst is referred to as a first electrode, and the other as a second electrode.

[0043] A first electrode of the transistor TR1 is connected to a node n1, and a second electrode of the transistor TR1 is connected to a signal line SL that supplies a video signal Sdata. The video signal Sdata is a signal written into a pixel to display an image.

[0044] The transistor TR2 corresponds to a driving transistor for supplying current to the light-emitting element DE included in the sub-pixel SP. A first electrode of the transistor TR2 is connected to the node n1. A second electrode of the transistor TR2 is connected to the node n2.

[0045] A first electrode of the transistor TR3 is connected to the node n3, and a second electrode of the transistor TR3 is connected to the node n2.

[0046] A first electrode of the transistor TR4 is connected to the node n2, and a second electrode of the transistor TR4 is connected to a power supply line PL1 that supplies a power supply voltage VDDEL.

[0047] A first electrode of the transistor TR5 is connected to the node n4, and a second electrode of the transistor TR5 is connected to the node n1.

[0048] A first electrode of the transistor TR6 is connected to the node n4, and a second electrode of the transistor TR6 is connected to an initialization line IL to which an initialization voltage Vini is supplied.

[0049] A first electrode of the transistor TR7 is connected to the node n2, and a second electrode of the transistor TR7 is connected to a power supply line PL2 that supplies a power supply voltage VSH.

[0050] A first electrode of the storage capacitor Cst is connected to the node n3 , and a second electrode of the storage capacitor Cst is connected to the node n4 .

[0051] The gate electrode of transistor TR1 is connected to scanning line GL1 to which scanning signal Sg1 is supplied. The gate electrode of transistor TR3 is connected to scanning line GL2 to which scanning signal Sg2 is supplied. The gate electrodes of transistors TR4, TR5, and TR6 are connected to scanning line GL3 to which scanning signal Sg3 is supplied. The gate electrode of transistor TR7 is connected to scanning line GL4 to which scanning signal Sg4 is supplied.

[0052] The anode of the display element DE is connected to the node n4. The cathode of the display element DE is connected to the power supply line PL3 that supplies the power supply voltage VSSEL. The power supply voltage VDDEL corresponds to the anode voltage supplied to the display element DE, and the power supply voltage VSSEL corresponds to the cathode voltage supplied to the display element DE.

[0053] In addition, the structure of the pixel circuit PC is not limited to Figure 2For example, the pixel circuit PC may include six or fewer transistors or eight or more transistors. In addition, the pixel circuit PC may include multiple holding capacitors Cst. The number of scan lines and power lines connected to the pixel circuit PC can be increased or decreased depending on the structure of the pixel circuit PC.

[0054] Figure 3 1 is a schematic plan view showing an example of the layout of sub-pixels SP1, SP2, and SP3 in one pixel PX. Figure 3 In the example, sub-pixels SP2 and SP3 are arranged in the X direction relative to sub-pixel SP1. In addition, sub-pixels SP2 and SP3 are arranged in the Y direction. In addition, the layout of sub-pixels SP1, SP2, and SP3 is not limited to Figure 3 example.

[0055] The rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel openings AP1, AP2, and AP3 at the sub-pixels SP1, SP2, and SP3, respectively. Figure 3 In the example, the pixel opening AP1 is larger than the pixel opening AP2, and the pixel opening AP2 is larger than the pixel opening AP3. That is, among the sub-pixels SP1, SP2, and SP3, the sub-pixel SP1 has the largest aperture ratio and the sub-pixel SP3 has the smallest aperture ratio.

[0056] The sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with the pixel opening AP1. The sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with the pixel opening AP2. The sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with the pixel opening AP3. Figure 3 In FIG, the lower electrodes LE1, LE2, and LE3 are marked with oblique line patterns.

[0057] The lower electrode LE1, the upper electrode UE1, and the portion of the organic layer OR1 that overlaps with the pixel opening AP1 constitute the display element DE1 of subpixel SP1. The lower electrode LE2, the upper electrode UE2, and the portion of the organic layer OR2 that overlaps with the pixel opening AP2 constitute the display element DE2 of subpixel SP2. The lower electrode LE3, the upper electrode UE3, and the portion of the organic layer OR3 that overlaps with the pixel opening AP3 constitute the display element DE3 of subpixel SP3. The display elements DE1, DE2, and DE3 may further include an overlying layer, described later. The rib layer 5 surrounds each of the display elements DE1, DE2, and DE3.

[0058] Conductive partition walls 6 are arranged on the rib layer 5. Figure 3In the figure, a dot pattern is marked on the partition wall 6. The partition wall 6 entirely overlaps with the rib layer 5 and has the same planar shape as the rib layer 5. That is, the partition wall 6 has openings at the sub-pixels SP1, SP2, and SP3. From another perspective, the rib layer 5 and the partition wall 6 form a grid pattern when viewed in plan, surrounding each of the sub-pixels SP1, SP2, and SP3 (display elements DE1, DE2, and DE3). The partition wall 6 serves as wiring for supplying a common voltage to the upper electrodes UE1, UE2, and UE3.

[0059] exist Figure 3 In the example, the ends of the lower electrodes LE1, LE2, and LE3 entirely overlap with the rib layer 5 and the partition wall 6. As another example, at least a portion of the ends of the lower electrodes LE1, LE2, and LE3 may not overlap with the partition wall 6.

[0060] Figure 4 It is along Figure 3 A schematic cross-sectional view of the display panel PNL taken along line IV-IV in FIG. A circuit layer 11 is provided on the substrate 10. The circuit layer 11 includes Figure 2 The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the unevenness generated by the circuit layer 11.

[0061] The lower electrodes LE1, LE2, and LE3 are arranged on the organic insulating layer 12. The rib layer 5 is arranged on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Figure 4 Although not shown in the cross section, the lower electrodes LE1 , LE2 , and LE3 are connected to the pixel circuit PC of the circuit layer 11 through contact holes provided in the organic insulating layer 12 .

[0062] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a greater width than the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. This shape of the partition wall 6 is called an overhang.

[0063] exist Figure 4 In the example, the lower portion 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. Figure 4 In the example shown in FIG. 5 , both end portions of the bottom layer 63 protrude from the side surfaces of the shaft layer 64 .

[0064] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and is opposite to the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and is opposite to the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and is opposite to the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surface of the lower portion 61 of the partition wall 6.

[0065] Display element DE1 includes an upper cover layer CP1 covering upper electrode UE1. Display element DE2 includes an upper cover layer CP2 covering upper electrode UE2. Display element DE3 includes an upper cover layer CP3 covering upper electrode UE3. The upper cover layers CP1, CP2, and CP3 respectively function as optical adjustment layers, improving the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3.

[0066] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1 and the upper covering layer CP1 is referred to as the stacked film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2 and the upper covering layer CP2 is referred to as the stacked film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3 and the upper covering layer CP3 is referred to as the stacked film FL3.

[0067] A portion of the laminate film FL1 is located above the upper portion 62. This portion is separated from the portion of the laminate film FL1 surrounding the partition wall 6 (the portion constituting the display element DE1). Similarly, a portion of the laminate film FL2 is located above the upper portion 62 and is separated from the portion of the laminate film FL2 surrounding the partition wall 6 (the portion constituting the display element DE2). Furthermore, a portion of the laminate film FL3 is located above the upper portion 62 and is separated from the portion of the laminate film FL3 surrounding the partition wall 6 (the portion constituting the display element DE3).

[0068] Seal layers SE11, SE12, and SE13 (first seal layers) are provided in sub-pixels SP1, SP2, and SP3, respectively. Seal layer SE11 continuously covers overcoat layer CP1 and the partition wall 6 surrounding sub-pixel SP1. Seal layer SE12 continuously covers overcoat layer CP2 and the partition wall 6 surrounding sub-pixel SP2. Seal layer SE13 continuously covers overcoat layer CP3 and the partition wall 6 surrounding sub-pixel SP3.

[0069] exist Figure 4In the example shown in FIG1 , the laminated film FL1 and the sealing layer SE11 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE12 on the partition wall 6. Furthermore, the laminated film FL1 and the sealing layer SE11 on the partition wall 6 between the sub-pixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE13 on the partition wall 6.

[0070] Sealing layers SE11, SE12, and SE13 are covered by resin layer RS1 (first resin layer). Resin layer RS1 is covered by sealing layer SE2 (second sealing layer). Sealing layer SE2 is covered by resin layer RS2 (second resin layer). Resin layers RS1, RS2, and sealing layer SE2 are continuously provided at least throughout the display area DA, and a portion also extends into the peripheral area SA.

[0071] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed on the resin layer RS2. Such a cover member may be bonded to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0072] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0073] The lower electrodes LE1, LE2, and LE3 include a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0074] The upper electrodes UE1, UE2, and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to anodes, and the upper electrodes UE1, UE2, and UE3 correspond to cathodes.

[0075] The organic layers OR1, OR2, and OR3 are composed of multiple thin films including a light-emitting layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are sequentially stacked in the Z direction. However, the organic layers OR1, OR2, and OR3 may also have other structures, such as a so-called tandem structure including multiple light-emitting layers.

[0076] The upper covering layers CP1, CP2, and CP3 have, for example, a stacked structure of multiple transparent layers. These transparent layers can include layers formed from inorganic materials and layers formed from organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers differ from those of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. Furthermore, at least one of the upper covering layers CP1, CP2, and CP3 may be omitted.

[0077] The base layer 63 and the axial layer 64 of the partition wall 6 are formed of a metal material. Examples of the metal material for the base layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), or a molybdenum-niobium alloy (MoNb). Examples of the metal material for the axial layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), or an aluminum-silicon alloy (AlSi). Alternatively, the axial layer 64 may be formed of an insulating material.

[0078] For example, the upper portion 62 of the partition wall 6 has a laminated structure comprising a lower layer formed of a metal material and an upper layer formed of a conductive oxide. Examples of the metal material forming the lower layer include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy. Examples of the conductive oxide forming the upper layer include ITO or IZO. Alternatively, the upper portion 62 may have a single-layer structure of a metal material. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0079] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the side surfaces of the lower portion 61. Pixel voltages corresponding to the video signals on the signal lines SL are supplied to the lower electrodes LE1, LE2, and LE3 via the pixel circuits PC of the sub-pixels SP1, SP2, and SP3, respectively.

[0080] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is established between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the green wavelength range. When a potential difference is established between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the blue wavelength range. When a potential difference is established between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength range.

[0081] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layer into light of the colors corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layer and generate light of the colors corresponding to the sub-pixels SP1, SP2, and SP3.

[0082] Figure 5 This is a schematic plan view showing a portion of the first area A1. The figure shows the rib layer 5, partition walls 6, and lower electrodes LE1, LE2, and LE3, with other elements omitted. The partition walls 6 are marked with a dot pattern, and the lower electrodes LE1, LE2, and LE3 are marked with a hatched pattern.

[0083] In the first area A1, a plurality of pixels PX are arranged in the X direction and the Y direction. The layout of the sub-pixels SP1, SP2, and SP3 in each pixel PX is the same as Figure 3 Thus, in the first area A1, a plurality of columns of sub-pixels SP1 are repeatedly arranged in the Y direction, and a plurality of columns of sub-pixels SP2 and SP3 are alternately arranged in the Y direction. These columns are alternately arranged in the X direction.

[0084] Figure 6 This is a schematic plan view showing a portion of the second area A2. Figure 6 Also, with Figure 5 The rib layer 5, the partition wall 6, and the lower electrodes LE1, LE2, and LE3 are similarly shown, and other elements are omitted.

[0085] The second area A2 includes a plurality of pixels PX and a plurality of transmissive areas TA. The layout of the sub-pixels SP1, SP2, and SP3 in the pixels PX of the second area A2 is the same as that of the pixels PX of the first area A1.

[0086] The transmissive area TA has the same size as the pixel PX. Figure 6In the example shown, pixels PX and transmissive areas TA are arranged alternately in the X and Y directions. Specifically, in the second area A2, pixels PX are arranged at half the density of the first area A1. This example is not limiting; for example, multiple transmissive areas TA may be arranged between two adjacent pixels PX in the X or Y direction. Alternatively, multiple pixels PX may be arranged between two adjacent transmissive areas TA in the X or Y direction.

[0087] The transmission area TA includes a plurality of sub-areas AS surrounded by partition walls 6. The sub-areas AS transmit at least a portion of light incident on the transmission area TA from the display surface side of the display device DSP to the back side of the display device DSP. Figure 1 As described above, the second area A2 has higher light transmittance than the first area A1.

[0088] exist Figure 6 In the example shown in FIG1 , three sub-areas AS1, AS2, and AS3 (first to third sub-areas) are formed in the transmissive area TA. That is, the number of sub-pixels SP (SP1, SP2, SP3) in one pixel PX is the same as the number of sub-areas AS (AS1, AS2, AS3) in one transmissive area TA, both being three. However, the number of sub-pixels SP in one pixel PX does not necessarily have to be the same as the number of sub-areas AS in one transmissive area TA.

[0089] exist Figure 6 In the example, sub-pixel SP1 and sub-region AS1 have the same shape, sub-pixel SP2 and sub-region AS2 have the same shape, and sub-pixel SP3 and sub-region AS3 have the same shape. The shapes of the sub-pixels and sub-regions referred to here refer to the shapes of the regions surrounded by the partition walls 6 when viewed in plan view.

[0090] In addition, Figure 6 In the example, sub-areas AS2 and AS3 are arranged in the Y direction. Furthermore, sub-areas AS2 and AS3 are each arranged in the X direction relative to sub-area AS1. That is, the positional relationship between sub-areas AS1, AS2, and AS3 is the same as the positional relationship between sub-pixels SP1, SP2, and SP3.

[0091] The partition wall 6 includes a first portion P1 that divides the sub-pixels SP1, SP2, and SP3 in each pixel PX, and a second portion P2 that divides the sub-regions AS1, AS2, and AS3 in each transmission area TA. Figure 6In the example shown in FIG. 1 , the first portion P1 and the second portion P2 have the same shape. Specifically, the first portion P1 includes a portion extending in the Y direction between sub-pixel SP1 and sub-pixels SP2 and SP3, and a portion extending in the X direction between sub-pixel SP2 and sub-pixel SP3. Furthermore, the second portion P2 includes a portion extending in the Y direction between sub-area AS1 and sub-areas AS2 and AS3, and a portion extending in the X direction between sub-area AS2 and sub-area AS3.

[0092] As described above, the lower electrodes LE1, LE2, and LE3 are arranged in the sub-pixels SP1, SP2, and SP3. The rib layer 5 is provided with pixel openings AP1, AP2, and AP3 that overlap with the lower electrodes LE1, LE2, and LE3, respectively.

[0093] In contrast, the lower electrodes LE1, LE2, and LE3 are not disposed in the sub-areas AS1, AS2, and AS3. Figure 6 In the example of FIG, the rib layer 5 has no openings in the sub-regions AS1, AS2, and AS3. That is, the sub-regions AS1, AS2, and AS3 entirely overlap with the rib layer 5.

[0094] Figure 7 This is another schematic plan view showing a portion of the second area A2. In the second area A2, various wirings for driving the sub-pixels SP1, SP2, and SP3 are arranged. These wirings include a plurality of wirings Lx extending in the X direction and a plurality of wirings Ly extending in the Y direction. The wirings Lx and Ly are both composed of Figure 4 The metal layer included in the circuit layer 11 is shown to be formed.

[0095] In one example, the plurality of wirings Lx include Figure 2 The scanning lines GL1 to GL4, power supply lines PL2 and PL3, and initialization line IL are shown. Figure 2 The signal line SL and the power line PL1 are shown.

[0096] exist Figure 7 In the example, most of the wirings Lx cross the sub-pixels SP1, SP2, SP3 and the sub-areas AS1, AS2, AS3 in the X direction. In addition, most of the wirings Ly cross the sub-pixels SP1, SP2, SP3 and the sub-areas AS1, AS2, AS3 in the Y direction.

[0097] The wiring lines Lx and Ly formed from a metal layer have light-shielding properties. In sub-areas AS1, AS2, and AS3, light passes through the portions that do not overlap with the wiring lines Lx and Ly. Meanwhile, in sub-pixels SP1, SP2, and SP3, most of the light incident on the display device DSP is reflected or absorbed by the lower electrodes LE1, LE2, and LE3.

[0098] Figure 8 It is along Figure 6 Schematic cross-sectional view of the second region A2 taken along line VIII-VIII in FIG. In this figure, the substrate 10 and the circuit layer 11 are omitted.

[0099] As described above, the rib layer 5 does not have openings in the sub-regions AS1, AS2, and AS3. In addition, the lower electrodes LE1, LE2, and LE3 are not arranged in the sub-regions AS1, AS2, and AS3.

[0100] Moreover, in Figure 8 In the example shown in FIG1 , the laminated films FL1, FL2, and FL3 (organic layers OR1, OR2, OR3, upper electrodes UE1, UE2, UE3, and overlying layers CP1, CP2, and CP3) and the sealing layers SE11, SE12, and SE13 are not provided in sub-region AS1. Therefore, in sub-region AS1, the rib layer 5 is in contact with the resin layer RS1. Similarly, in sub-regions AS2 and AS3, the laminated films FL1, FL2, and FL3 and the sealing layers SE11, SE12, and SE13 are not provided, and the rib layer 5 is in contact with the resin layer RS1.

[0101] With such a structure, at least a portion of the light L incident on the second area A2 from the display surface side passes through the sub-areas AS1, AS2, and AS3. Figure 1 The light L is detected by a light receiving element such as the camera CR shown.

[0102] Figure 9 This is a schematic cross-sectional view illustrating another structure applicable to the second area A2. In the example shown in this figure, a laminate film FL1 and a sealing layer SE11 are arranged in sub-area AS1. The laminate film FL1 is cut by partition walls 6 surrounding sub-area AS1. The sealing layer SE11 continuously covers the cut laminate film FL1 and partition walls 6.

[0103] Even with such a structure, at least a portion of the light L incident on the second area A2 is transmitted through the sub-area AS1. However, since the light L passes through the laminated film FL1 and the sealing layer SE11, Figure 8 The transmittance may be lower than that of the example. From this point of view, Figure 8 The structure shown is advantageous.

[0104] The same can also be applied to sub-areas AS2 and AS3. Figure 9 That is, the laminated film FL2 and the sealing layer SE12 may be arranged in the sub-region AS2, and the laminated film FL3 and the sealing layer SE13 may be arranged in the sub-region AS3.

[0105] Figure 101 is a schematic plan view showing still another structure applicable to the second area A2. In this figure, the rib layer 5 and the partition wall 6 near the transmission area TA are shown, and other elements are omitted.

[0106] The rib layer 5 may also have an opening 50 that overlaps with at least one of the sub-areas AS1, AS2, and AS3. Figure 10 In the example of FIG. 1 , as an example of the openings 50 , a plurality of linear openings 50 x extending in the X direction and a plurality of linear openings 50 y extending in the Y direction are shown.

[0107] Specifically, four linear openings 50x are provided in the sub-area AS1 and arranged in the Y direction, one linear opening 50y is provided in the sub-area AS2, and two linear openings 50y are provided in the sub-area AS3 and arranged in the X direction. The linear openings 50y in the sub-area AS2 are wider in the X direction than the linear openings 50y in the sub-area AS3.

[0108] The number, shape and arrangement of the linear openings 50x and 50y provided in the sub-areas AS1, AS2 and AS3 are not limited to Figure 10 For example, linear openings 50x may be provided in each of the sub-areas AS1, AS2, and AS3. Alternatively, linear openings 50y may be provided in each of the sub-areas AS1, AS2, and AS3.

[0109] Figure 11 1 is a schematic plan view showing another example of the opening 50. In the example of this figure, a plurality of dispersed dot openings 50d are provided in each of the sub-areas AS1, AS2, and AS3.

[0110] exist Figure 11 In the example, each dot opening 50d is a perfect circle with the same diameter. However, the dot opening 50d may also be an ellipse or a square or other shapes. In addition, the diameter (or width) of each dot opening 50d may also be different. The dot opening 50d may also be different from the dot opening 50d. Figure 10 The linear openings 50 x and 50 y shown are provided in the sub-areas AS1 , AS2 , and AS3 .

[0111] Figure 12 It is along Figure 10 A schematic cross-sectional view of the second region A2 along the XII-XII line. Figure 12 In the example, Figure 8 Similarly, in the sub-area AS1 , the laminated films FL1 , FL2 , FL3 and the sealing layers SE11 , SE12 , SE13 are not disposed. Therefore, each linear opening 50 x is filled with the resin layer RS1 . The resin layer RS1 is in contact with the organic insulating layer 12 through each linear opening 50 x .

[0112] As another example, you can also Figure 9 Similarly, a laminated film FL1 and a sealing layer SE11 are disposed in sub-region AS1. In this case, the laminated film FL1 (specifically, the organic layer OR1) contacts the organic insulating layer 12 through each linear opening 50x. Similarly, sub-regions AS2 and AS3 may or may not have laminated films FL2 and FL3 and sealing layers SE12 and SE13 disposed therein.

[0113] When the openings 50 such as the linear openings 50x and 50y or the dot openings 50d are provided in the rib layer 5 in the sub-areas AS1, AS2, and AS3, it is possible to suppress a decrease in transmittance due to the rib layer 5. This further improves the light transmittance of the transmissive area TA.

[0114] Next, an example of a method for manufacturing the display device DSP will be described. 13A to 13I 1 is a schematic cross-sectional view showing the manufacturing process of the display device DSP. 13A to 13I In FIG. 1 , the focus is mainly on the display area DA, and elements below the organic insulating layer 12 are omitted.

[0115] When forming the display device DSP, first, a circuit layer 11 and an organic insulating layer 12 are formed on a substrate 10. Then, as shown in FIG. Figure 13A As shown, lower electrodes LE1 , LE2 , and LE3 are formed on the organic insulating layer 12 .

[0116] Then, if Figure 13B As shown, the rib layer 5 is formed to cover the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The rib layer 5 can be formed by, for example, CVD (Chemical Vapor Deposition).

[0117] Furthermore, if Figure 13C As shown, the partition walls 6 are formed on the rib layer 5. Specifically, first, a layer serving as a base for the bottom layer 63, the shaft layer 64, and the upper portion 62 is formed, and these layers are patterned by etching.

[0118] After the partition wall 6 is formed, Figure 13D As shown, pixel openings AP1, AP2, and AP3 are formed with respect to the rib layer 5 by dry etching.

[0119] Next, the steps for forming display elements DE1, DE2, and DE3 are performed. In this embodiment, it is assumed that display element DE1 is formed first, followed by display element DE2, and finally display element DE3. However, the order of forming display elements DE1, DE2, and DE3 is not limited to this example.

[0120] When forming the display element DE1, first Figure 13E As shown in FIG. 1 , a laminated film FL1 and a sealing layer SE11 are formed. Figure 4 As shown, the structure includes an organic layer OR1 that contacts the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 that covers the organic layer OR1, and a capping layer CP1 that covers the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the capping layer CP1 are formed by evaporation. In addition, the sealing layer SE11 is formed by CVD.

[0121] The laminate film FL1 and the sealing layer SE11 are formed not only in the display area DA but also in the peripheral area SA. The laminate film FL1 is cut into a plurality of parts by the overhanging partition wall 6. The sealing layer SE11 continuously covers the cut parts of the laminate film FL1 and the partition wall 6.

[0122] Next, the laminate film FL1 and the sealing layer SE11 are patterned. Figure 13F As shown in FIG. 1 , a resist film R is disposed on the sealing layer SE11 . The resist film R covers the sub-pixel SP1 and a portion of the partition wall 6 surrounding the sub-pixel SP1 .

[0123] After that, etching is performed by using the resist film R as a mask, as shown in FIG. Figure 13G As shown, the portions of the laminate film FL1 and the sealing layer SE11 exposed from the test resist film R are removed. In other words, the portions of the laminate film FL1 and the sealing layer SE11 that overlap the lower electrode LE1 remain, while the remaining portions are removed. This forms the display element DE1 in the subpixel SP1. This etching process can include wet etching and dry etching, performed sequentially on the sealing layer SE11, the overcoat layer CP1, the upper electrode UE1, and the organic layer OR1. After these etching steps, the test resist film R is removed.

[0124] The display element DE2 is formed in the same order as the display element DE1. That is, when forming the display element DE2, the laminated film FL2 and the sealing layer SE12 are formed in the entire display area DA and the peripheral area SA. Figure 4 As shown, it includes an organic layer OR2 contacting the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and an overcoat layer CP2 covering the upper electrode UE2.

[0125] The organic layer OR2, the upper electrode UE2 and the upper cover layer CP2 are formed by evaporation. In addition, the sealing layer SE12 is formed by CVD. The laminate film FL2 is cut into multiple parts by the overhanging partition wall 6. The sealing layer SE12 continuously covers the cut parts of the laminate film FL2 and the partition wall 6. By patterning the laminate film FL2 and the sealing layer SE2, as shown in FIG. Figure 13H As shown, the display element DE2 is formed in the sub-pixel SP2.

[0126] The display element DE3 is formed in the same order as the display elements DE1 and DE2. That is, when forming the display element DE3, the laminated film FL3 and the sealing layer SE13 are formed in the entire display area DA and the peripheral area SA. Figure 4 As shown, it includes an organic layer OR3 contacting the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and an upper cover layer CP3 covering the upper electrode UE3.

[0127] The organic layer OR3, the upper electrode UE3 and the overcoat layer CP3 are formed by evaporation. In addition, the sealing layer SE13 is formed by CVD. The laminate film FL3 is cut into multiple parts by the overhanging partition wall 6. The sealing layer SE13 continuously covers the cut parts of the laminate film FL3 and the partition wall 6. By patterning the laminate film FL3 and the sealing layer SE13, as shown in FIG. Figure 13I As shown, a display element DE3 is formed in the sub-pixel SP3.

[0128] After forming the display elements DE1, DE2, and DE3, Figure 4 The resin layer RS1, the sealing layer SE2 and the resin layer RS2 are shown. Figure 4 The display device DSP of the structure shown is completed.

[0129] In the above embodiment, the second area A2 having light transmittance is formed in the display area DA. Figure 1 As shown, when a light receiving element such as a camera CR is arranged on the back side of the second area A2, the light incident on the display area DA can also be detected by the light receiving element.

[0130] Furthermore, the laminated films FL1, FL2, and FL3 formed by vapor deposition have poor adhesion to the substrate. Consequently, during the manufacture of the display device DSP, there is a risk that the laminated films FL1, FL2, and FL3 and the sealing layers SE11, SE12, and SE13 covering them may peel from the substrate. In this case, the peeled laminated films FL1, FL2, and FL3 and the sealing layers SE11, SE12, and SE13 may adhere to the substrate and contaminate the chamber of the manufacturing equipment.

[0131] This peeling is more likely to occur when the laminated films FL1, FL2, and FL3 are formed over a large continuous area. In the pixel PX, the laminated films FL1, FL2, and FL3 are narrowly cut by the partition walls 6 surrounding the sub-pixels SP1, SP2, and SP3. This prevents this peeling.

[0132] In this embodiment, the transmissive area TA is divided into a plurality of subareas AS (AS1, AS2, AS3) by the partition walls 6. Thus, in the transmissive area TA, the laminate films FL1, FL2, FL3 are narrowly cut as in the pixels PX, thereby suppressing the above-mentioned peeling.

[0133] In this manner, by suppressing the peeling of the laminated films FL1 , FL2 , FL3 and the sealing layers SE11 , SE12 , SE13 during the manufacturing process, the yield of the display device DSP can be improved.

[0134] [Second embodiment]

[0135] In the second embodiment, another structure applicable to the second area A2 is disclosed. For structures not mentioned in this embodiment, the same structure as in the first embodiment can be applied.

[0136] Figure 14 This is a schematic plan view showing a portion of the second region of the second embodiment. Figure 6 The rib layer 5, the partition wall 6, and the lower electrodes LE1, LE2, and LE3 are similarly shown, and other elements are omitted.

[0137] In this embodiment, the number of sub-pixels SP included in one pixel PX is different from the number of sub-regions AS included in one transmission region TA. Figure 14 In the example of FIG, the pixel PX has three sub-pixels SP (SP1, SP2, SP3), and the transmission area TA has four sub-areas AS (AS1, AS2, AS3, AS4). Figure 14 In the example, the number of sub-regions AS included in one transmissive area TA is greater than the number of sub-pixels SP included in one pixel PX.

[0138] exist Figure 14 In the example shown in FIG, sub-areas AS1 and AS2 are arranged in the X direction, and sub-areas AS3 and AS4 are arranged in the X direction. Furthermore, sub-areas AS1 and AS3 are arranged in the Y direction, and sub-areas AS2 and AS4 are arranged in the Y direction. Furthermore, sub-areas AS1, AS2, AS3, and AS4 have the same shape.

[0139] The partition wall 6 includes a first portion P1 that divides the sub-pixels SP1, SP2, and SP3 in each pixel PX, and a second portion P2 that divides the sub-regions AS1, AS2, AS3, and AS4 in each transmission area TA. Figure 14 In the example, the shapes of the first portion P1 and the second portion P2 are different.

[0140] That is, the first part P1 and Figure 6 Similarly to the example of FIG, the first portion P2 includes a portion extending in the Y direction between sub-pixel SP1 and sub-pixels SP2 and SP3, and a portion extending in the X direction between sub-pixel SP2 and sub-pixel SP3. Meanwhile, the second portion P2 is cross-shaped. Specifically, the second portion P2 includes a portion extending in the Y direction between sub-areas AS1 and AS3 and sub-areas AS2 and AS4, and a portion extending in the X direction between sub-areas AS1 and AS2 and sub-areas AS3 and AS4.

[0141] For the sub-areas AS1, AS2, AS3, and AS4, for example, Figure 8 、 Figure 9 and Figure 12 The sub-area AS1 shown has the same structure. When the rib layer 5 is provided with an opening 50 in the sub-areas AS1, AS2, AS3, and AS4, the opening 50 can be applied. Figure 10 The linear openings 50x, 50y, Figure 11 Point opening 50d as shown.

[0142] As in this embodiment, when the number of sub-pixels SP included in one pixel PX is different from the number of sub-regions AS included in one transmissive region TA, the same effects as those of the first embodiment can be obtained. Figure 14 In the example shown in FIG. 1 , the transmissive area TA is narrowed by the second portion P2 of the partition wall 6 compared to the first embodiment. Consequently, when manufacturing the display device DSP, the laminated films FL1 , FL2 , and FL3 formed in the transmissive area TA are cut narrowly. This further effectively suppresses the aforementioned peeling.

[0143] [Third embodiment]

[0144] In the third embodiment, another structure applicable to the second area A2 is disclosed. For structures not mentioned in this embodiment, the same structures as those in the first and second embodiments can be applied.

[0145] Figure 15 This is a schematic plan view of a portion of the second area A2 of the third embodiment. This figure shows the partition wall 6, the lower electrodes LE1, LE2, and LE3, and the plurality of wirings Lx extending in the X direction; other elements are omitted. The partition wall 6 is indicated with a dot pattern, and the lower electrodes LE1, LE2, and LE3 are indicated with a hatched pattern.

[0146] The structure of the first area A1 in this embodiment is similar to that of, for example, Figure 5 The structure shown is the same. Figure 5 and Figure 15That is, a comparison of the two figures clearly shows that, in this embodiment, the size of the pixel PX (first pixel) arranged in the second area A2 is different from the size of the pixel PX (second pixel) arranged in the first area A1. Specifically, the pixel PX arranged in the second area A2 is smaller than the pixel PX arranged in the first area A1.

[0147] In one example, the density of the pixels PX in the second area A2 is equal to the density of the pixels PX in the first area A1. Here, the density of the pixels PX refers to the number of pixels PX contained in a unit area.

[0148] exist Figure 15 In the example, the pixel PX arranged in the second area A2 has sub-pixels SP1, SP2, and SP3 similarly to the pixel PX arranged in the first area A1. However, the sub-pixels SP1, SP2, and SP3 in the second area A2 have rounded corners.

[0149] The transmissive area TA has four sub-areas AS1, AS2, AS3, and AS4. Figure 15 In the example shown, these sub-areas AS1, AS2, AS3, and AS4 are pentagonal. The second portion P2 of the partition wall 6 is a cross-shaped portion that divides the sub-areas AS1, AS2, AS3, and AS4. The shapes of the sub-areas AS1, AS2, AS3, and AS4 are not limited to this example; various other shapes are applicable.

[0150] For the sub-areas AS1, AS2, AS3, AS4, it is possible to apply, for example, Figure 8 、 Figure 9 and Figure 12 The sub-area AS1 shown has the same structure. When the opening 50 is provided in the rib layer 5 in the sub-areas AS1, AS2, AS3, and AS4, the opening 50 can be applied. Figure 10 The linear openings 50x, 50y, Figure 11 Point opening 50d as shown.

[0151] exist Figure 15 In the example shown in FIG. 1 , no transmissive area TA is provided between pixels PX adjacent to each other in the X direction or between pixels PX adjacent to each other in the Y direction. Each transmissive area TA is provided between pixels PX adjacent to each other in an oblique direction intersecting the X and Y directions. From another perspective, the transmissive area TA is provided at a position offset in the X and Y directions relative to the pixels PX arranged around it.

[0152] exist Figure 15In the example, the area of each of sub-regions AS1, AS2, AS3, and AS4 is larger than the area of any of sub-pixels SP1, SP2, and SP3. However, the present invention is not limited to this example; the area of at least one of sub-regions AS1, AS2, AS3, and AS4 may be smaller than the area of any of sub-pixels SP1, SP2, and SP3.

[0153] Each wiring Lx is arranged so as not to overlap with the sub-areas AS1, AS2, AS3, and AS4. In other words, each wiring Lx entirely overlaps with the partition wall 6. Figure 15 In the example shown in FIG. 5 , the interval between the plurality of wirings Lx is narrowed between two transmission areas TA arranged along the Y direction, and is widened between two pixels PX arranged along the Y direction.

[0154] Although Figure 15 Although not shown in the figure, the plurality of wirings Ly extending in the Y direction (see Figure 7 ) can also be configured in the same shape as the wiring Lx. That is, each wiring Ly can be arranged so as not to overlap with the transmissive area TA. In this case, the spacing between the plurality of wirings Ly can be narrowed between two transmissive areas TA arranged in the X direction and widened between two pixels PX arranged in the X direction.

[0155] As in this embodiment, by reducing the number of pixels PX in the second area A2, the pixels PX can be arranged in the second area A2 at the same density as in the first area A1, thereby improving the display quality of the second area A2. In addition, the light-shielding wiring lines Lx and Ly formed of a metal material can be arranged so as not to overlap with the sub-areas AS1, AS2, AS3, and AS4, thereby further improving the light transmittance of the transmissive area TA.

[0156] In the first to third embodiments described above, the transmissive area TA includes three or four sub-areas AS. However, the present invention is not limited thereto. Each transmissive area TA may include five or more sub-areas AS, or two or less sub-areas AS. Furthermore, the sub-areas AS in each transmissive area TA may have different shapes.

[0157] All display devices that can be implemented by those skilled in the art by appropriately changing the design of the display device described above as the embodiment of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0158] Within the scope of the present invention, those skilled in the art will be able to conceive of various variations, and these variations are also considered to fall within the scope of the present invention. For example, with respect to the above-mentioned embodiments, solutions obtained by those skilled in the art by appropriately adding, deleting, or changing the design of structural elements, or by adding, omitting, or changing the conditions of processes, are included in the scope of the present invention as long as they meet the gist of the present invention.

[0159] Furthermore, regarding other effects brought about by the methods described in the above embodiments, effects that are clear from the description of this specification or effects that can be appropriately imagined by those skilled in the art are naturally interpreted as being brought about by the present invention.

Claims

1. A display device, characterized in that: have: a first pixel disposed in a display area for displaying an image; a transmissive region disposed in the display region; and a partition wall including a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion, and arranged in the display area; The first pixel includes a plurality of sub-pixels surrounded by the partition wall. The transmission region includes a plurality of sub-regions that are surrounded by the partition wall and transmit at least a portion of light incident on the transmission region.

2. The display device according to claim 1, wherein Each of the plurality of sub-pixels comprises: lower electrode; an organic layer covering the lower electrode and emitting light in response to application of a voltage; and an upper electrode covering the organic layer and contacting the lower portion of the partition wall, The lower electrodes are not arranged in the plurality of sub-regions.

3. The display device according to claim 2, wherein: The organic layer and the upper electrode are not arranged in the plurality of sub-regions.

4. The display device according to claim 3, wherein: Each of the plurality of sub-pixels further includes an optical adjustment layer covering the upper electrode. The optical adjustment layer is not disposed in the plurality of sub-regions.

5. The display device according to claim 4, wherein: Each of the plurality of sub-pixels further includes a first sealing layer formed of an inorganic insulating material and covering the optical adjustment layer. The first sealing layer is not arranged in the plurality of sub-regions.

6. The display device according to claim 1, wherein A rib layer formed of an inorganic insulating material is further provided, the rib layer being located below the partition wall and having a pixel opening at each of the plurality of sub-pixels. The plurality of sub-regions overlap with the rib layer.

7. The display device according to claim 6, wherein: The rib layer has an opening overlapping with at least one of the plurality of sub-regions.

8. The display device according to claim 7, wherein: The openings include a plurality of linear openings arranged in one of the sub-regions.

9. The display device according to claim 7, wherein: The opening includes a plurality of point openings dispersed in one of the sub-regions.

10. The display device according to claim 6, wherein It also includes a first resin layer covering the display area, The first resin layer is in contact with the rib layer in the plurality of sub-regions.

11. The display device according to claim 10, wherein: The invention further comprises a second sealing layer formed of an inorganic insulating material and covering the first resin layer.

12. The display device according to claim 11, wherein The invention further comprises a second resin layer covering the second sealing layer.

13. The display device according to claim 1, wherein The number of the plurality of sub-pixels is the same as the number of the plurality of sub-regions.

14. The display device according to claim 13, wherein: The plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel. The plurality of sub-regions include a first sub-region, a second sub-region, and a third sub-region that are arranged in the same positional relationship as that of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

15. The display device according to claim 14, wherein: The partition wall comprises: dividing the first sub-pixel, the second sub-pixel, and the first portion of the third sub-pixel; and The first sub-region, the second sub-region, and the second portion of the third sub-region are divided.

16. The display device according to claim 15, wherein: The first portion and the second portion have the same shape.

17. The display device according to claim 1, wherein The number of the plurality of sub-pixels is different from the number of the plurality of sub-regions.

18. The display device according to claim 17, wherein: The number of the plurality of sub-regions is greater than the number of the plurality of sub-pixels.

19. The display device according to claim 1, wherein Also features: a plurality of pixel circuits, which are arranged in the display area and respectively drive the plurality of sub-pixels; and a plurality of wirings for supplying voltages or signals to the plurality of pixel circuits; At least one of the plurality of wirings overlaps with the partition wall and does not overlap with the plurality of sub-regions.

20. The display device according to claim 19, wherein The display area includes a first area including a second pixel and a second area including the first pixel and the transmissive area. The first pixel is smaller than the second pixel.

Images