Display device

Abstract

The display device includes: a pixel circuit layer; a bonding electrode on the pixel circuit layer; a first electrode on the bonding electrode; a light emitting element on the first electrode and configured to emit light of a first color; a second electrode on the light emitting element; a distributed Bragg reflection layer on the second electrode; and a color filter on the distributed Bragg reflection layer and transmitting light of the second color.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0018459 filed in the Korean Intellectual Property Office on February 6, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Aspects of some embodiments of the present disclosure relate to a display device. Background Art

[0004] With the development of information technology, the importance of display devices as a connection medium between users and information has become prominent. Therefore, display devices such as liquid crystal display devices, organic light emitting diode display devices, etc. are increasingly used.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the Invention

[0006] Aspects of some embodiments of the present disclosure include a display device with improved light efficiency and color purity.

[0007] According to some embodiments of the present disclosure, a display device includes: a pixel circuit layer; a bonding electrode above the pixel circuit layer; a first electrode above the bonding electrode; a light-emitting element above the first electrode for emitting light of a first color; a second electrode above the light-emitting element; a distributed Bragg reflector layer above the second electrode; and a color filter above the distributed Bragg reflector layer for transmitting light of a second color.

[0008] The first color may be orange.

[0009] The second color may be red.

[0010] The color filter may be configured to absorb or reflect light of colors other than red.

[0011] The display device may further include a lens between the distributed Bragg reflective layer and the color filter.

[0012] The display device may further include: a first protective layer on the first electrode, on the side surface of the light-emitting element, and on the second electrode; a second protective layer on the pixel circuit layer, on the bonding electrode, on the first electrode, and on the first protective layer; and a reflective layer on the side surface of the second protective layer and on the pixel circuit layer.

[0013] The reflective layer may not overlap with the light emitting element.

[0014] The display device may further include: a first insulating layer between the pixel circuit layer and the second electrode and covering the reflective layer and the second protection layer; and a second insulating layer between the second electrode and the distributed Bragg reflective layer.

[0015] The distributed Bragg reflector layer may include at least one multilayer in which a first refractive layer, a second refractive layer, and another first refractive layer are sequentially stacked.

[0016] The first refractive layer may include titanium dioxide, wherein the second refractive layer includes silicon dioxide, and wherein the thickness of the multiple layers is from about 130 nm to about 160 nm.

[0017] The first refractive layer may include tantalum dioxide, wherein the second refractive layer includes silicon dioxide, and wherein the thickness of the multiple layers is from about 150 nm to about 180 nm.

[0018] The multilayer may include 3 to 60 layers.

[0019] The display device may further include: a first protective layer on the first electrode, on the side surface of the light-emitting element, and on the side surface of the second electrode; a second protective layer on the side surface of the first protective layer, on the pixel circuit layer, on the bonding electrode, and on the first electrode; and a reflective layer on the side surface of the distributed Bragg reflective layer, on the pixel circuit layer, on the first protective layer, on the second protective layer, and on the second electrode.

[0020] The reflective layer may partially overlap with the light emitting element.

[0021] The display device may further include: a first insulating layer between the reflective layer and the pixel circuit layer; and a second insulating layer between the color filter and the distributed Bragg reflective layer and the reflective layer.

[0022] According to some embodiments of the present disclosure, a display device includes: a first light-emitting element, which is at the same layer as a first insulating layer above a pixel circuit layer and is configured to emit light of a first color; a distributed Bragg reflector layer, which is above the first insulating layer; a color filter, which is above the distributed Bragg reflector layer and is configured to transmit red light; a second light-emitting element, which is at the same layer as a second insulating layer above the color filter and is configured to emit light of a second color; and a third light-emitting element, which is at the same layer as a third insulating layer above the second insulating layer and is configured to emit light of a third color.

[0023] The first color may be orange, wherein the second color is green, and wherein the third color is blue.

[0024] The display device may further include: a first electrode above the pixel circuit layer; a first through hole penetrating the first insulating layer, the distributed Bragg reflective layer, and the color filter; a second through hole penetrating the second insulating layer; a third through hole penetrating the third insulating layer; a second electrode above the third insulating layer; and a lens above the second electrode and overlapping with the first light-emitting element, the second light-emitting element, and the third light-emitting element, respectively.

[0025] The first light-emitting element may be above one of the first electrodes overlapping with the first light-emitting region, and may be electrically connected to the second electrode through one of the first through holes overlapping with the first light-emitting region, one of the second through holes overlapping with the first light-emitting region, and one of the third through holes overlapping with the first light-emitting region.

[0026] The second light-emitting element can be electrically connected to a first electrode among the first electrodes that overlaps with the second light-emitting area through a first through hole among the first through holes that overlaps with the second light-emitting area, and can be electrically connected to the second electrode through a second through hole among the second through holes that overlaps with the second light-emitting area and a third through hole among the third through holes that overlaps with the second light-emitting area.

[0027] The third light-emitting element can be electrically connected to a first electrode among the first electrodes that overlaps with the third light-emitting region through a first through hole among the first through holes that overlaps with the third light-emitting region, and a second through hole among the second through holes that overlaps with the third light-emitting region, and can be electrically connected to the second electrode through a third through hole among the third through holes that overlaps with the third light-emitting region. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects according to embodiments of the present disclosure will become more apparent by describing aspects of some embodiments of the present disclosure in more detail with reference to the accompanying drawings.

[0029] Figure 1 is a block diagram of a display device according to some embodiments.

[0030] Figure 2 is a block diagram of a sub-pixel according to some embodiments.

[0031] Figure 3 is a plan view of a display panel according to some embodiments.

[0032] Figure 4 is a plan view of a pixel according to some embodiments.

[0033] Figure 5 According to some embodiments, Figure 4 A cross-sectional view taken along line II'.

[0034] Figure 6 is a cross-sectional view of a distributed Bragg reflector according to some embodiments.

[0035] Figure 7 According to some embodiments, Figure 4 A cross-sectional view taken along line II'.

[0036] Figure 8 According to some embodiments, Figure 4 A sectional view taken along line II-II'.

[0037] Figure 9 is a block diagram of a display system according to some embodiments.

[0038] Figures 10 to 13 yes Figure 9 A perspective view of an application example of a display system. DETAILED DESCRIPTION

[0039] By referring to the detailed description and drawings of the embodiments, it is easier to understand the aspects of some embodiments of the present disclosure and the methods for realizing them. The described embodiments are provided as examples so that the present disclosure will be thorough and complete and will fully convey the aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments, or unnecessary processes, elements and techniques for a person of ordinary skill in the art to fully understand the aspects of the present disclosure may be omitted. Unless otherwise stated, similar reference numerals, characters or combinations thereof represent similar elements throughout the drawings and written descriptions, and therefore, their repeated descriptions may be omitted.

[0040] The described embodiments may have various modifications and may be implemented in different forms and should not be construed as limited to the embodiments shown herein. The use of "can," "may," or "may not" when describing an embodiment corresponds to one or more embodiments of the present disclosure.

[0041] Considering the entirety of the present disclosure, those skilled in the art will understand that the present disclosure covers all modifications, equivalents and replacements within the scope of the ideas and techniques of the present disclosure, that each of the features of the embodiments of the present disclosure may be combined with each other in part or in whole, and that various technical interlocks and operations are possible, and that each embodiment may be implemented independently of each other, or may be implemented together in association, unless otherwise stated or implied.

[0042] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and / or any other characteristics, attributes, properties, etc. of the elements.

[0043] Various embodiments are described herein with reference to cross-sectional views that are schematic illustrations of embodiments and / or intermediate structures. Therefore, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances, should be anticipated. Furthermore, the specific structural or functional descriptions disclosed herein are merely exemplary and are used for the purpose of describing embodiments according to the concepts of the present disclosure. Therefore, the embodiments disclosed herein should not be construed as being limited to the shapes of the elements, layers, or regions shown, but rather should include deviations in shapes due to, for example, manufacturing.

[0044] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0045] For ease of explanation, spatial relative terms such as "below", "below", "down", "downside", "beneath", "above", "upper side" etc. may be used herein to describe the relationship between an element or feature and another (some) element or feature as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, spatial relative terms are intended to include different orientations of the device in use or in operation. For example, if the device in the drawings is flipped, the element described as being "below", "below" or "below" other elements or features will then be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" can include both above and below orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first portion is described as being arranged "on" a second portion, this means that the first portion is arranged on the upper or lower side of the second portion, and is not limited to its upper side based on the direction of gravity.

[0046] In addition, the phrase "in a plan view" means when an object portion is viewed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-section obtained by vertically cutting an object portion is viewed from the side. The term "overlap" or "overlapped" means that a first object can be above or below a second object, or on one side of the second object, and vice versa. In addition, the term "overlap" can include stacking, facing, or facing, extending over, covering, or partially covering, or any other suitable term as will be understood and understood by a person of ordinary skill in the art. The expression "non-overlapping" can include meanings such as "separated from," "separated from," or "offset from," as well as any other suitable equivalents as will be understood and understood by a person of ordinary skill in the art. The terms "face" and "facing" can mean that a first object can be directly opposite or indirectly opposite to a second object. In the case where a third object is between the first and second objects, the first and second objects can be understood to be indirectly opposite to each other, but still facing each other.

[0047] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it may be directly formed on, directly on, directly connected to, or directly coupled to another element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to another element, layer, region, or component, such that there may be one or more intervening elements, layers, regions, or components. Furthermore, this may collectively mean direct or indirect coupling or connection, as well as integral or non-integrated coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or directly electrically coupled to another layer, region, and / or component, or there may be one or more intervening layers, regions, or components. One or more intervening components may include switches, resistors, capacitors, etc. In describing the embodiments, unless explicitly described as directly connected, the expression "connected" means electrically connected, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or directly coupled to another component, or is directly on another component, without any intervening components.

[0048] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upward direction, but includes forming the part on the side surface or in the downward direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "under" another part, this includes not only the case where the part is "directly under" the other part, but also the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between components such as "between...", "directly between...", or "adjacent to..." and "directly adjacent to..." can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can also be one or more intervening elements or layers.

[0049] For the purposes of this disclosure, expressions such as "at least one of" or "any one of" or "one or more of" when preceding a list of elements modify the entire list of elements and do not modify the individual elements in the list. For example, "at least one of X, Y, and Z," and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z, such as, for example, XYZ, XY, YZ, and XZ, or any variation thereof. Similarly, the expression "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or," and the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, expressions such as "at least one of," "a plurality of," "one of," and other prepositional phrases, when preceding / following a list of elements, modify the entire list of elements and do not modify the individual elements in the list.

[0050] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, areas, layers and / or sections, these elements, components, areas, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or advantage, and are only used to distinguish one element, component, component, area, region, layer, section or part from another element, component, component, area, region, layer, section or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first area, first layer or first section described below may be referred to as the second element, second component, second area, second layer or second section. The description of an element as a "first" element may not require or imply the presence of a second element or other element. The terms "first", "second", etc. may also be used herein to distinguish elements of different categories or groups. For the sake of simplicity, the terms "first", "second", etc. may respectively represent "first category (or first group)", "second category (or second group)", etc.

[0051] In the examples, the x-axis, y-axis, and / or z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0052] The terms used herein are for the purpose of describing the embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to include the plural forms as well, and the plural forms are intended to include the singular forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises," "comprising," "have," "having," "includes," and "including," when used in this specification, specify the presence of stated features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0053] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as approximate terms and not as terms of degree, and are intended to account for inherent deviations in measured or calculated values that will be recognized by one of ordinary skill in the art. For example, "substantially" may include a range of + / - 5% of the corresponding value. In view of the measurements in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein include the values and mean within an acceptable deviation range for the particular value as determined by one of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0054] In some embodiments, known structures and devices can be described in the accompanying drawings about one or more functional blocks (e.g., block diagrams), units and / or modules to avoid unnecessary ambiguity of various embodiments. Those skilled in the art will understand that such blocks, units and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, line connections and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, optionally driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by a combination of dedicated hardware or dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and related circuits) that performs functions different from those functions of the dedicated hardware. In addition, in some embodiments, without departing from the scope of this disclosure, blocks, units and / or modules can be physically separated into two or more interactive discrete blocks, units and / or modules. Furthermore, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0056] Figure 1 is a block diagram of a display device according to some embodiments.

[0057] refer to Figure 1 , the display device DD may include a display panel DP, a gate driver 120 , a data driver 130 , a voltage generator 140 , and a controller 150 .

[0058] The display panel DP includes subpixels SP. The subpixels SP may be connected to the gate driver 120 through first to m-th gate lines GL1 to GLm. The subpixels SP may be connected to the data driver 130 through first to n-th data lines DL1 to DLn.

[0059] The sub-pixels SP may generate light of two or more colors. For example, each of the sub-pixels SP may generate light of red, green, blue, cyan, magenta, yellow, etc.

[0060] Two or more sub-pixels in the sub-pixel SP may constitute one pixel PXL. For example, the pixel PXL may include: Figure 1 In this manner, the pixel PXL can emit light of various colors and various brightnesses according to a combination of lights emitted from the sub-pixels SP included in the pixel PXL.

[0061] The gate driver 120 may be connected to the sub-pixels SP arranged in a row direction through the first to m-th gate lines GL1 to GLm. The gate driver 120 may output gate signals to the first to m-th gate lines GL1 to GLm in response to a gate control signal GCS. In an embodiment, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal, and the like.

[0062] The gate driver 120 may be located on one side of the display panel DP. However, embodiments are not limited thereto. For example, the gate driver 120 may be divided into two or more physically and / or logically separated drivers, and such drivers may be located on one side of the display panel DP and on the other side of the display panel DP opposite to the one side, respectively. Therefore, the gate driver 120 may be located around the display panel DP in various shapes according to embodiments.

[0063] The data driver 130 may be connected to the sub-pixels SP arranged in the column direction via the first to nth data lines DL1 to DLn. The data driver 130 may receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 may operate in response to the data control signal DCS. In an embodiment, the data control signal DCS may include a source start signal, a source shift clock, a source output enable signal, and the like.

[0064] The data driver 130 may receive a voltage from the voltage generator 140. The data driver 130 may apply a data signal having a grayscale voltage corresponding to the image data DATA to the first to n-th data lines DL1 to DLn using the received voltage. When a gate signal is applied to each of the first to m-th gate lines GL1 to GLm, a data signal corresponding to the image data DATA may be applied to the first to n-th data lines DL1 to DLn. Thus, the subpixels SP may generate light corresponding to the data signal, and the display panel DP may display an image.

[0065] In an implementation, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0066] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 may be configured to generate a plurality of voltages and provide the generated voltages to components of the display device DD, such as the gate driver 120, the data driver 130, and the controller 150. The voltage generator 140 may generate the plurality of voltages by receiving an input voltage from outside the display device DD and regulating the received voltage.

[0067] The voltage generator 140 may generate a first power voltage and a second power voltage. The generated first power voltage and second power voltage may be provided to the subpixel SP through the power line PWL. In other embodiments, at least one of the first power voltage and the second power voltage may be provided from outside the display device DD.

[0068] In addition, the voltage generator 140 may provide various voltages and / or signals. For example, the voltage generator 140 may provide one or more initialization voltages applied to the sub-pixel SP. For example, during a sensing operation for sensing electrical characteristics of a transistor and / or a light-emitting element of the sub-pixel SP, a reference voltage (e.g., a predetermined reference voltage) may be applied to the first data line DL1 to the nth data line DLn, and the voltage generator 140 may generate the reference voltage, and the reference voltage may be transmitted to the data driver 130. For example, during a display operation for displaying an image on the display panel DP, a common pixel control signal may be applied to the sub-pixel SP, and the voltage generator 140 may generate the pixel control signal. In an embodiment, the voltage generator 140 may provide a pixel control signal to the sub-pixel SP through the pixel control line PXCL. In Figure 1, the pixel control line PXCL is shown as being connected between the voltage generator 140 and the display panel DP, but embodiments are not limited thereto. For example, the pixel control line PXCL may be connected between the gate driver 120 and the display panel DP. In this case, the pixel control signal may be transmitted from the gate driver 120 to the sub-pixel SP via the pixel control line PXCL.

[0069] The controller 150 may control various operations of the display device DD. The controller 150 may receive input image data IMG and a corresponding control signal CTRL from the outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0070] The controller 150 may convert the input image data IMG into a sub-pixel SP in a row unit and output the image data DATA.

[0071] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 may be mounted on one integrated circuit. Figure 1 As shown in FIG, the data driver 130, the voltage generator 140, and the controller 150 may be included in a driver integrated circuit DIC. In this case, the data driver 130, the voltage generator 140, and the controller 150 may be functionally separate components within one driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be provided as a component separate from the driver integrated circuit DIC.

[0072] Figure 2 is a block diagram of a sub-pixel according to some embodiments. Figure 2 In, arranged in Figure 1 The subpixel SPij in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) among the subpixels SP can be shown as an example.

[0073] refer to Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0074] The light emitting element LD may be connected between a first power supply voltage node VDDN and a second power supply voltage node VSSN. The first power supply voltage node VDDN may be connected to Figure 1The second power supply voltage node VSSN can be connected to one of the power supply lines PWL in the circuit and can receive the first power supply voltage. Figure 1 The first power supply voltage may be higher than the second power supply voltage.

[0075] The light-emitting element LD may be connected between the anode AE and the cathode CE. The anode AE may be connected to a first power supply voltage node VDDN via a sub-pixel circuit SPC. For example, the anode AE may be connected to the first power supply voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC. The cathode CE may be connected to a second power supply voltage node VSSN. The light-emitting element LD may be configured to emit light in response to a current flowing from the anode AE to the cathode CE.

[0076] The sub-pixel circuit SPC can be connected to Figure 1 The i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm is connected to the Figure 1 In response to the gate signal received through the i-th gate line GLi, the sub-pixel circuit SPC can control the light emitting element LD to emit light according to the data signal received through the j-th data line DLj. In an embodiment, the sub-pixel circuit SPC can also be connected to Figure 1 In this case, the sub-pixel circuit SPC may further control the light emitting element LD in response to a pixel control signal received through the pixel control line PXCL.

[0077] For these operations, the sub-pixel circuit SPC may include circuit elements such as a transistor and one or more capacitors.

[0078] The transistors of the sub-pixel circuit SPC may include P-type transistors and / or N-type transistors. In an embodiment, the transistors of the sub-pixel circuit SPC may include metal oxide silicon field effect transistors (MOSFETs). In an embodiment, the transistors of the sub-pixel circuit SPC may include amorphous silicon semiconductors, single crystal silicon semiconductors, polycrystalline silicon semiconductors, oxide semiconductors, etc.

[0079] Figure 3 is a plan view of a display panel according to some embodiments.

[0080] refer to Figure 3 The display panel DP may include a display area DA and a non-display area NDA. The display panel DP displays an image through the display area DA. The non-display area NDA may be located around the display area DA.

[0081] The display panel DP may include sub-pixels SP in the display area DA. The sub-pixels SP may be arranged in a first direction DR1 and in a second direction DR2 intersecting the first direction DR1. For example, the sub-pixels SP may be arranged in a matrix in the first direction DR1 and in the second direction DR2. For another example, the sub-pixels SP may be arranged in a zigzag pattern in the first direction DR1 and in the second direction DR2. The arrangement of the sub-pixels SP may vary depending on the embodiment. The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction.

[0082] Two or more sub-pixels among the plurality of sub-pixels SP may constitute one pixel PXL. Figure 3 , the pixel PXL is shown as including three sub-pixels SP1, SP2, and SP3, but the embodiment is not limited thereto. For example, the pixel PXL may include two sub-pixels. Hereinafter, for ease of description, it is assumed that the pixel PXL includes a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3.

[0083] Each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may generate light of one of various colors, such as red, green, blue, cyan, magenta, yellow, etc. Hereinafter, for clarity and concise description, it is assumed that the first subpixel SP1 is configured to generate red light, the second subpixel SP2 is configured to generate green light, and the third subpixel SP3 is configured to generate blue light.

[0084] Each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may include at least one light-emitting element configured to generate light. In an embodiment, the light-emitting elements of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may generate light of different colors. For example, the light-emitting element of the first subpixel SP1 may generate orange light, the light-emitting element of the second subpixel SP2 may generate green light, and the light-emitting element of the third subpixel SP3 may generate blue light.

[0085] A display panel capable of self-luminescence, such as a light emitting diode (LED) display panel using micrometer- or nanometer-sized light emitting diodes as light emitting elements or an organic light emitting diode (OLED) display panel using organic light emitting diodes as light emitting elements, may be used as the display panel DP.

[0086] Components for controlling the sub-pixels SP may be located in the non-display area NDA. Wiring (eg, Figure 1 The first to m-th gate lines GL1 to GLm, the first to n-th data lines DL1 to DLn, the power lines PWL, and the pixel control lines PXCL may be located in the non-display area NDA.

[0087] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, and the controller 150 of the display panel DP may be located in the non-display area NDA. In an embodiment, the gate driver 120 may be located in the non-display area NDA. In this case, the data driver 130, the voltage generator 140, and the controller 150 may be implemented as Figure 1 The gate driver 120 may be implemented as a single integrated circuit separate from the display panel DP, along with the data driver 130, the voltage generator 140, and the controller 150.

[0088] In an embodiment, the display area DA may have various shapes. The display area DA may have a closed loop shape including straight edges and / or curved edges. For example, the display area DA may have a shape such as a polygon, a circle, a semicircle, or an ellipse.

[0089] In an embodiment, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have a display surface that is at least partially rounded. In an embodiment, the display panel DP may be bendable, foldable, or rollable. In these cases, the display panel DP and / or the substrate of the display panel DP may include a material having flexible properties.

[0090] Figure 4 is a plan view of a pixel according to some embodiments.

[0091] refer to Figure 4 , the pixel PXL may include a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3 arranged in a first direction DR1. However, the arrangement of the pixel PXL is not limited thereto and may vary depending on the embodiment. For example, the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may be arranged in a zigzag pattern.

[0092] The first subpixel SP1 may include a first light emitting area EMA1 and a non-light emitting area NEA surrounding the first light emitting area EMA1. The second subpixel SP2 may include a second light emitting area EMA2 and a non-light emitting area NEA surrounding the second light emitting area EMA2. The third subpixel SP3 may include a third light emitting area EMA3 and a non-light emitting area NEA surrounding the third light emitting area EMA3.

[0093] The first light emitting area EMA1 may be an area where light is emitted from the light emitting element corresponding to the first sub-pixel SP1. The second light emitting area EMA2 may be an area where light is emitted from the light emitting element corresponding to the second sub-pixel SP2. The third light emitting area EMA3 may be an area where light is emitted from the light emitting element corresponding to the third sub-pixel SP3.

[0094] Figure 5 According to some embodiments, Figure 4 A cross-sectional view taken along line II'.

[0095] refer to Figure 5 The pixel circuit layer PCL may be located on a substrate (as used herein, "located on" may mean "above"). The substrate may be made of an insulating material such as glass or resin. For example, the substrate may include a glass substrate. For another example, the substrate may include a polyimide (PI) substrate. For another example, the substrate may include a silicon wafer substrate formed using a semiconductor process.

[0096] In an embodiment, the substrate may be made of a material flexible enough to bend or fold, and may have a single-layer structure or a multi-layer structure. For example, the flexible material may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, the embodiment is not limited thereto.

[0097] The pixel circuit layer PCL may include an insulating layer, a semiconductor pattern, and a conductive pattern. The insulating layer may include a buffer layer, one or more interlayer insulating layers, and one or more passivation layers. The semiconductor pattern and the conductive pattern may be located between the insulating layer. The conductive pattern may include at least one of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0098] The bonding electrode BDE may be located on the pixel circuit layer PCL. The bonding electrode BDE may include a low-melting metal. In an embodiment, the bonding electrode BDE may be composed of multiple layers. For example, the bonding electrode BDE may be composed of a first electrode layer including titanium (Ti), a second electrode layer including gold (Au) and / or tin (Sn), and a third electrode layer including titanium (Ti) stacked in sequence. However, the embodiment is not limited thereto.

[0099] The first electrode ITO1 may be located on the bonding electrode BDE. The first electrode ITO1 may be provided to be included in the first sub-pixel SP1 (see FIG. Figure 4 ) in the sub-pixel circuit SPC (see Figure 2In an embodiment, the first electrode ITO1 may include an anode AE such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the embodiment is not limited thereto. For example, the first electrode ITO1 may include titanium nitride.

[0100] The first light-emitting element LD1 may be located on the first electrode ITO1. The first light-emitting element LD1 may be electrically connected to the first electrode ITO1. Furthermore, the first light-emitting element LD1 may be electrically connected to the second electrode ITO2. In an embodiment, the first light-emitting element LD1 may emit orange light. In this case, the first light-emitting element LD1 may emit light having a dominant wavelength of approximately 580 nm to approximately 620 nm.

[0101] The first light emitting element LD1 may include a first semiconductor layer SCL1, a first active layer AL1, and a second semiconductor layer SCL2. The first semiconductor layer SCL1, the first active layer AL1, and the second semiconductor layer SCL2 may be sequentially stacked on the first electrode ITO1.

[0102] The first semiconductor layer SCL1 may be located on the first electrode ITO1 and may provide holes to the first active layer AL1. The first semiconductor layer SCL1 may include at least one P-type semiconductor layer. For example, the first semiconductor layer SCL1 may include at least one semiconductor material selected from gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a P-type semiconductor layer doped with a first conductive dopant (or P-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), or barium (Ba). However, the material constituting the first semiconductor layer SCL1 is not limited thereto, and various other materials may constitute the first semiconductor layer SCL1. For example, the first semiconductor layer SCL1 may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or P-type dopant).

[0103] The first active layer AL1 may be located on the first semiconductor layer SCL1 and may be a region where electrons and holes recombine. When electrons and holes recombine in the first active layer AL1, their energy levels transition to lower levels, and light having a corresponding wavelength may be generated. The first active layer AL1 may be formed as a single quantum well structure or a multi-quantum well structure. When the first active layer AL1 is formed as a multi-quantum well structure, a unit including a barrier layer, a strain enhancement layer, and a well layer may be repeatedly stacked to form the first active layer AL1. However, embodiments are not limited thereto.

[0104] The second semiconductor layer SCL2 may be located on the first active layer AL1 and may provide electrons to the first active layer AL1. The second semiconductor layer SCL2 may include a semiconductor layer of a different type from the first semiconductor layer SCL1. For example, the second semiconductor layer SCL2 may include at least one N-type semiconductor layer. For example, the second semiconductor layer SCL2 may include at least one semiconductor material selected from gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an N-type semiconductor layer doped with a second conductive dopant (or N-type dopant) such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the second semiconductor layer SCL2 is not limited thereto, and various other materials may constitute the second semiconductor layer SCL2. For example, the second semiconductor layer SCL2 may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or N-type dopant).

[0105] The auxiliary layer may be positioned on the second semiconductor layer SCL2. The auxiliary layer may include a gallium nitride (GaN) semiconductor material not doped with impurities, and may form an N-type semiconductor layer together with the second semiconductor layer SCL2.

[0106] The second electrode ITO2 may be located on the first light emitting element LD1. For example, the second electrode ITO2 may be located on the second semiconductor layer SCL2. The second electrode ITO2 may be provided as a first sub-pixel SP1 (see FIG. Figure 4 ) in the sub-pixel circuit SPC (see Figure 2 The second electrode ITO2 may extend on the first light emitting element LD1 to cover the side surface of the protection layer PL, and may be located on the first insulating layer IL1.

[0107] In an embodiment, the second electrode ITO2 may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO) of at least one of the transparent conductive materials. However, the embodiment is not limited thereto. For example, the second electrode ITO2 may include titanium nitride.

[0108] The protective layer PL may cover the outer peripheral surface of the first light-emitting element LD1. The protective layer PL may reduce or prevent the possibility of a short circuit that may otherwise occur when the first active layer AL1 contacts a conductive material other than the first semiconductor layer SCL1 and the second semiconductor layer SCL2. The protective layer PL may be composed of multiple layers. For example, the protective layer PL may include a first protective layer PL1 and a second protective layer PL2.

[0109] The first protective layer PL1 may be located on the first electrode ITO1. The first protective layer PL1 may extend over the first electrode ITO1 to cover the side surfaces of the first light-emitting element LD1 and may be located on the second electrode ITO2. The first protective layer PL1 may include an insulating material. For example, the first protective layer PL1 may include at least one of zirconium dioxide (ZrO2), aluminum oxide (Al2O3), and silicon dioxide (SiO2). However, embodiments are not limited thereto. The first protective layer PL1 may be composed of a plurality of stacked layers of the above insulating materials.

[0110] The second protective layer PL2 may be located on the pixel circuit layer PCL. The second protective layer PL2 may extend on the pixel circuit layer PCL to cover both the side surfaces of the bonding electrode BDE and the side surfaces of the first electrode ITO1, and may be located on the first protective layer PL1. The second protective layer PL2 may include an insulating material. For example, the second protective layer PL2 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxides (AlO x ) at least one of the metal oxides. However, the embodiment is not limited thereto.

[0111] The reflective layer RFL may be located on the pixel circuit layer PCL. The reflective layer RFL may extend on the pixel circuit layer PCL and may be located on the side surface of the second protective layer PL2. The top surface of the reflective layer RFL may be located on the same line as the top surface of the second protective layer PL2. The reflective layer RFL may reflect incident light, thereby improving light output efficiency. The reflective layer RFL may include a material suitable for reflecting light. For example, the reflective layer RFL may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), or an alloy of two or more materials selected therefrom. However, embodiments are not limited thereto.

[0112] The first insulating layer IL1 may be located between the pixel circuit layer PCL and the second electrode ITO2. The first insulating layer IL1 may cover the reflective layer RFL and the second protection layer PL2. The first insulating layer IL1 may include an inorganic material or an organic material. For example, the inorganic material may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) and aluminum oxides (AlO x). For example, the organic material may include at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin and benzocyclobutene resin.

[0113] The second insulating layer IL2 may be positioned on the second electrode ITO2. The second insulating layer IL2 may be made of substantially the same material as the first insulating layer IL1.

[0114] The distributed Bragg reflector DBR may be located on the second insulating layer IL2. The distributed Bragg reflector DBR may be spaced apart from the second electrode ITO2. The distributed Bragg reflector DBR may serve as a reflective filter. The distributed Bragg reflector DBR may selectively reflect (or transmit) incident light. For example, the distributed Bragg reflector DBR may reflect short-wavelength light in the orange light emitted from the first light emitting element LD1, and may transmit long-wavelength light. Long-wavelength light may refer to light close to red, and short-wavelength light may refer to light close to orange. Because the short-wavelength light reflected from the distributed Bragg reflector DBR is reabsorbed and recycled in the first active layer AL1, light efficiency may be increased. In addition, because the short-wavelength light is filtered in the distributed Bragg reflector DBR and long-wavelength light close to red is emitted, color purity may be increased. Reference will be made later Figure 6 The structure of the distributed Bragg reflector DBR is described in more detail.

[0115] Light emitted from the first light-emitting element LD1 can be incident on the distributed Bragg reflector (DBR) in all directions. The performance of the distributed Bragg reflector (DBR) can vary depending on the incident angle θ (or direction) of the incident light. For example, as the incident angle θ of short-wavelength light incident on the distributed Bragg reflector (DBR) decreases, the reflectivity of the short-wavelength light can increase. For example, as the incident angle θ of short-wavelength light incident on the distributed Bragg reflector (DBR) increases, the reflectivity of the short-wavelength light can decrease. As the incident angle θ of light incident on the distributed Bragg reflector (DBR) increases, the wavelength shift of light reflected from the distributed Bragg reflector (DBR) increases, thereby degrading the function of the distributed Bragg reflector (DBR).

[0116] The color filter CF may be located on the distributed Bragg reflector DBR. For example, the color filter CF may be located directly on the distributed Bragg reflector DBR. The color filter CF may overlap with the first light-emitting element LD1. For example, the color filter CF may overlap with the first light-emitting area EMA1 on the distributed Bragg reflector DBR. The color filter CF may partially overlap with the non-light-emitting area NEA.

[0117] In one or more embodiments, the color filter CF can selectively transmit red light. For example, the color filter CF can be used as an absorption filter that absorbs light of colors other than red. For example, the color filter CF can be used as a reflection filter that reflects light of colors other than red. As the incident angle θ of the short-wavelength light incident on the distributed Bragg reflector DBR increases, not only long-wavelength light close to red but also short-wavelength light close to orange can be transmitted through the distributed Bragg reflector DBR. The color filter CF can absorb or reflect short-wavelength light close to orange that is not filtered in the distributed Bragg reflector DBR. The color filter CF can further improve color purity by transmitting long-wavelength light close to red and filtering short-wavelength light close to orange.

[0118] The lens LA may be located on the distributed Bragg reflector DBR. For example, the lens LA may be located between the distributed Bragg reflector DBR and the color filter CF. The lens LA may overlap with the first light-emitting element LD1. For example, the lens LA may overlap with the first light-emitting area EMA1 on the distributed Bragg reflector DBR. The lens LA may partially overlap with the non-light-emitting area NEA. The lens LA may improve light output efficiency by outputting light emitted from the first light-emitting element LD1 along a desired path. The lens LA may be a microlens, but embodiments are not limited thereto.

[0119] Figure 6 is a cross-sectional view of a distributed Bragg reflector according to some embodiments.

[0120] refer to Figure 6 The distributed Bragg reflector (DBR) may have a structure suitable for transmitting long-wavelength light near red. The distributed Bragg reflector (DBR) may include a first refractive layer RL1 and a second refractive layer RL2 having different refractive indices. For example, the refractive index of the first refractive layer RL1 may be higher than the refractive index of the second refractive layer RL2. The distributed Bragg reflector (DBR) may include at least one multilayer in which the first refractive layer RL1, the second refractive layer RL2, and the first refractive layer RL1 are stacked in sequence. The distributed Bragg reflector (DBR) may have a structure in which n multilayers (1 to n pairs) are stacked. For example, the distributed Bragg reflector (DBR) may include 3 to 60 multilayers (n=3 to 60).

[0121] In one or more embodiments, the first refractive layer RL1 may include titanium dioxide (TiO2), and the second refractive layer RL2 may include silicon dioxide (SiO2). In this case, the multilayer has a TiO2 / SiO2 / TiO2 stacked structure, and the thickness of the multilayer may be approximately 130 nm to approximately 160 nm. In one or more embodiments, the first refractive layer RL1 may include tantalum dioxide (TaO2), and the second refractive layer RL2 may include silicon dioxide (SiO2). In this case, the multilayer has a TaO2 / SiO2 / TaO2 stacked structure, and the thickness of the multilayer may be approximately 150 nm to approximately 180 nm.

[0122] Figure 7 According to some embodiments, Figure 4 A cross-sectional view taken along line II'. Figure 7 , will simplify or omit Figure 5 A description of the overlapping content.

[0123] refer to Figure 7 The second electrode ITO2 may be located on the second semiconductor layer SCL2 of the first light emitting element LD1 and may completely overlap with the first light emitting element LD1.

[0124] The distributed Bragg reflector DBR may be located on the second electrode ITO 2 . For example, the distributed Bragg reflector DBR may be located directly on the second electrode ITO 2 . The distributed Bragg reflector DBR may partially overlap with the first light emitting element LD 1 .

[0125] The first protective layer PL1 may be located on the first electrode ITO1. The first protective layer PL1 may extend on the first electrode ITO1 and may cover the side surfaces of the first light emitting element LD1 and the side surfaces of the second electrode ITO2. The top surface of the first protective layer PL1 may be located on the same line as the top surface of the second electrode ITO2.

[0126] The second protective layer PL2 may be located on the pixel circuit layer PCL. The second protective layer PL2 may extend on the pixel circuit layer PCL and may cover the side surfaces of the bonding electrode BDE, the side surfaces of the first electrode ITO1, and the side surfaces of the first protective layer PL1. The top surface of the second protective layer PL2 may be located on the same line as the top surface of the first protective layer PL1 (e.g., may be flush with the top surface of the first protective layer PL1).

[0127] The reflective layer RFL may be located on the pixel circuit layer PCL. The reflective layer RFL may extend on the pixel circuit layer PCL, may be located on the first protective layer PL1 and the second protective layer PL2, and may be partially located on the second electrode ITO2. In addition, the reflective layer RFL may extend on the second electrode ITO2 and may cover the side surface of the distributed Bragg reflector DBR.

[0128] The first insulating layer IL1 may be located between the pixel circuit layer PCL and the reflective layer RFL. The first insulating layer IL1 may cover the reflective layer RFL. The second insulating layer IL2 may be located on the distributed Bragg reflective layer DBR and the reflective layer RFL.

[0129] The color filter CF may be located on the second insulating layer IL2. The color filter CF may be spaced apart from the distributed Bragg reflector DBR. The lens LA may be located on the second insulating layer IL2. For example, the lens LA may be located between the second insulating layer IL2 and the color filter CF.

[0130] Figure 8 According to some embodiments, Figure 4 The sectional view taken along the line II-II' will be simplified or omitted. Figure 5 Description of the content that the description overlaps.

[0131] refer to Figure 8 The first bonding electrodes BDE1 may be located on the pixel circuit layer PCL. The first bonding electrodes BDE1 may be spaced apart from each other. Each of the first bonding electrodes BDE1 may overlap the first, second, and third emission areas EMA1, EMA2, and EMA3.

[0132] The first electrode ITO1 may be located on the first bonding electrode BDE1. The first electrode ITO1 overlapping the first emission area EMA1 may serve as a first sub-pixel SP1 (see FIG. 1 ). Figure 4 ) in the sub-pixel circuit SPC (see Figure 2 The first electrode ITO1 overlapped with the second light emitting area EMA2 may be used as an anode electrode AE included in the second sub-pixel SP2 (see Figure 4 ) in the sub-pixel circuit SPC. The first electrode ITO1 overlapping the third light emitting area EMA3 may be used as an anode electrode AE included in the third sub-pixel SP3 (see Figure 4). The first electrode ITO1 overlapping the first light-emitting area EMA1 can be electrically connected to the first light-emitting element LD1. The first electrode ITO1 overlapping the second light-emitting area EMA2 can be electrically connected to the second light-emitting element LD2 via a first through-via VIA1 overlapping the second light-emitting area EMA2. The first electrode ITO1 overlapping the third light-emitting area EMA3 can be electrically connected to the third light-emitting element LD3 via a first through-via VIA1 and a second through-via VIA2 overlapping the third light-emitting area EMA3.

[0133] The first light emitting element LD1 may be located on the first electrode ITO1 overlapping the first light emitting region EMA1. The first light emitting element LD1 may emit orange light. The first light emitting element LD1 may include a first semiconductor layer SCL1 (see FIG. 1 ) sequentially stacked between the first electrode ITO1 and the first connection electrode CNE1. Figure 5 ), the first active layer AL1 (see Figure 5 ) and the second semiconductor layer SCL2 (see Figure 5 ).

[0134] The protection layer PL may be on the first electrode ITO 1. The protection layer PL may extend on the first electrode ITO 1 and may cover side surfaces of the first light emitting element LD 1.

[0135] The reflective layer RFL may be located on the pixel circuit layer PCL. The reflective layer RFL may extend on the pixel circuit layer PCL and may cover side surfaces of the first bonding electrode BDE1, the first electrode ITO1, and the protection layer PL.

[0136] The first connection electrode CNE1 may be located on the first light emitting element LD1. The first connection electrode CNE1 may be located on the protection layer PL and the reflective layer RFL.

[0137] The first insulating layer IL1 may be located on the pixel circuit layer PCL. The first insulating layer IL1 may be located on the same layer as the first light emitting element LD1.

[0138] A distributed Bragg reflector (DBR) may be located on the first insulating layer IL1. For example, the distributed Bragg reflector (DBR) may be located entirely on the first insulating layer IL1 (e.g., may cover the entire first insulating layer IL1, or may cover substantially the entire first insulating layer IL1). As described above, the distributed Bragg reflector (DBR) may reflect short-wavelength light emitted from the first light-emitting element LD1 and transmit long-wavelength light.

[0139] The color filter CF may be located on the distributed Bragg reflector DBR. For example, the color filter CF may be located entirely on the distributed Bragg reflector DBR. The color filter CF may transmit red light and may reflect or absorb light other than red light. Therefore, the color filter CF may be located above the first light emitting element LD1 and below the second light emitting element LD2 and the third light emitting element LD3. As described above, the color filter CF may be located at a relatively large incident angle θ (see Figure 5 ) is incident on the distributed Bragg reflector DBR and can filter the unfiltered short wavelength light and can transmit the long wavelength light to improve color purity.

[0140] A first through-hole VIA1 may be provided, penetrating the first insulating layer IL1, the distributed Bragg reflector DBR, and the color filter CF. The first through-hole VIA1, which overlaps with the first light-emitting area EMA1, may be formed on the first connection electrode CNE1 to electrically connect the first connection electrode CNE1 and the second bonding electrode BDE2. The first through-hole VIA1, which overlaps with the second light-emitting area EMA2, may be formed on the first electrode ITO1 to electrically connect the first electrode ITO1 and the second bonding electrode BDE2. The first through-hole VIA1, which overlaps with the third light-emitting area EMA3, may be formed on the first electrode ITO1 to electrically connect the first electrode ITO1 and the second bonding electrode BDE2.

[0141] The second bonding electrodes BDE2 may be located on the color filter CF. The second bonding electrodes BDE2 may be spaced apart from each other. Each of the second bonding electrodes BDE2 may overlap the first, second, and third light emitting areas EMA1, EMA2, and EMA3.

[0142] The second light emitting element LD2 may be located on the second bonding electrode BDE2 overlapping the second light emitting region EMA2. The second light emitting element LD2 may emit green light. The second light emitting element LD2 may include a first semiconductor layer SCL1 (see FIG. 1 ) sequentially stacked between the second bonding electrode BDE2 and the second connection electrode CNE2. Figure 5 ), the second active layer and the second semiconductor layer SCL2 (see Figure 5 ). With the first active layer AL1 (see Figure 5 ) is different, the second active layer can produce green light.

[0143] The protection layer PL may be on the second bonding electrode BDE2 . The protection layer PL may extend on the second bonding electrode BDE2 , and may cover side surfaces of the second light emitting element LD2 .

[0144] The reflective layer RFL may be located on the color filter CF. The reflective layer RFL may extend on the color filter CF and may cover side surfaces of the second bonding electrode BDE2 and the protection layer PL.

[0145] The second connection electrode CNE2 may be located on the second light emitting element LD2. The second connection electrode CNE2 may be located on the protection layer PL and the reflective layer RFL.

[0146] The second insulating layer IL2 may be located on the color filter CF. The second insulating layer IL2 may be located on the same layer as the second light emitting element LD2.

[0147] A second through-hole VIA2 may be provided that penetrates the second insulating layer IL2. The second through-hole VIA2 may be formed on the second bonding electrode BDE2, overlapping the first light-emitting area EMA1, to electrically connect the second bonding electrode BDE2 and the third bonding electrode BDE3. The second through-hole VIA2 may be formed on the second connection electrode CNE2, overlapping the second light-emitting area EMA2, to electrically connect the second connection electrode CNE2 and the third bonding electrode BDE3. The second through-hole VIA2 may be formed on the second bonding electrode BDE2, overlapping the third light-emitting area EMA3, to electrically connect the second bonding electrode BDE2 and the third bonding electrode BDE3.

[0148] The third bonding electrodes BDE3 may be located on the second insulating layer IL2. The third bonding electrodes BDE3 may be spaced apart from each other. Each of the third bonding electrodes BDE3 may overlap the first, second, and third light emitting regions EMA1, EMA2, and EMA3.

[0149] The third light emitting element LD3 may be located on the third bonding electrode BDE3 overlapping the third light emitting region EMA3. The third light emitting element LD3 may emit blue light. The third light emitting element LD3 may include a first semiconductor layer SCL1 (see FIG. 1 ) sequentially stacked between the third bonding electrode BDE3 and the third connection electrode CNE3. Figure 5 ), the third active layer and the second semiconductor layer SCL2 (see Figure 5 ). With the first active layer AL1 (see Figure 5 ) is different, the third active layer can produce blue light.

[0150] The protection layer PL may be on the third bonding electrode BDE3 , extend on the third bonding electrode BDE3 , and cover side surfaces of the third light emitting element LD3 .

[0151] The reflective layer RFL may be located on the second insulating layer IL2 . The reflective layer RFL may extend on the second insulating layer IL2 , and may cover side surfaces of the third bonding electrode BDE3 and the protection layer PL.

[0152] The third connection electrode CNE3 may be located on the third light emitting element LD3. The third connection electrode CNE3 may be located on the protection layer PL and the reflective layer RFL.

[0153] The third insulating layer IL3 may be located on the second insulating layer IL2. The third insulating layer IL3 may be located on the same layer as the third light emitting element LD3.

[0154] A third through-hole VIA3 may be provided that penetrates the third insulating layer IL3. The third through-hole VIA3, which overlaps with the first light-emitting area EMA1, may be formed on the third bonding electrode BDE3 to electrically connect the third bonding electrode BDE3 to the second electrode ITO2. The third through-hole VIA3, which overlaps with the second light-emitting area EMA2, may be formed on the third bonding electrode BDE3 to electrically connect the third bonding electrode BDE3 to the second electrode ITO2. The third through-hole VIA3, which overlaps with the third light-emitting area EMA3, may be formed on the third connection electrode CNE3 to electrically connect the third connection electrode CNE3 to the second electrode ITO2.

[0155] The second electrode ITO2 may be located on the third insulating layer IL3. The second electrode ITO2 may be electrically connected to the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3. For example, the second electrode ITO2 may be electrically connected to the first light-emitting element LD1 via the first connection electrode CNE1 and the first through-via VIA1, the second through-via VIA2, and the third through-via VIA3 that overlap the first light-emitting area EMA1. For example, the second electrode ITO2 may be electrically connected to the second light-emitting element LD2 via the second connection electrode CNE2 and the second through-via VIA2 and the third through-via VIA3 that overlap the second light-emitting area EMA2. For example, the second electrode ITO2 may be electrically connected to the third light-emitting element LD3 via the third connection electrode CNE3 and the third through-via VIA3 that overlaps the third light-emitting area EMA3.

[0156] The lens LA may be located on the second electrode ITO2. The lens LA may overlap the first light emitting area EMA1, the second light emitting area EMA2, and the third light emitting area EMA3, respectively. The lens LA may partially overlap the non-light emitting area NEA.

[0157] Figure 9 is a block diagram of a display system according to some embodiments.

[0158] refer to Figure 9, the display system 1000 may include a processor 1100 and a display device 1200 .

[0159] The processor 1100 may perform various tasks and calculations. In an embodiment, the processor 1100 may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 may be connected to other components of the display system 1000 via a bus system and control other components of the display system 1000.

[0160] The processor 1100 may transmit image data IMG and a control signal CTRL to the display device 1200. The display device 1200 may display an image based on the image data IMG and the control signal CTRL. The display device 1200 may communicate with the reference Figure 1 The display device DD described above is similarly configured. In this case, the image data IMG and the control signal CTRL can be set to Figure 1 Input image data IMG and control signal CTRL.

[0161] The display system 1000 may include a computing system that provides a video display function, such as a smartwatch, a mobile phone, a smartphone, a portable computer, a tablet personal computer, a watch phone, a car display, smart glasses, a portable multimedia player (PMP), a navigation, and an ultra-mobile personal computer (UMPC). In addition, the display system 1000 may include at least one of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, etc.

[0162] Figures 10 to 13 yes Figure 9 A perspective view of an application example of a display system.

[0163] refer to Figure 10 , Figure 9 The display system 1000 may be applied to a smart watch 2000 including a display unit 2100 and a band unit 2200 .

[0164] Smartwatch 2000 may be a wearable electronic device. For example, smartwatch 2000 may have a structure in which a band unit 2200 is mounted on a user's wrist. Here, display system 1000 and / or display device 1200 may be applied to display unit 2100, and image data including time information may be provided to the user.

[0165] refer to Figure 11 , Figure 9 The display system 1000 may be applied to a car display system 3000. Here, the car display system 3000 may include a computing system provided inside and / or outside a vehicle to provide image data.

[0166] For example, the display system 1000 and / or the display device 1200 can be applied to at least one of an infotainment panel 3100, an instrument panel 3200, a co-pilot display 3300, a head-up display 3400, a side-view mirror display 3500, and a rear seat display 3600 provided in a vehicle.

[0167] refer to Figure 12 , Figure 9 The display system 1000 can be applied to smart glasses 4000. The smart glasses 4000 can be a wearable electronic device that can be worn on the user's head. For example, the smart glasses 4000 can be a wearable device for augmented reality.

[0168] Smart glasses 4000 may include a frame 4100 and a lens unit 4200. The frame 4100 may include a housing 4110 supporting the lens unit 4200 and legs 4120 for the user to wear. The legs 4120 may be connected to the housing 4110 via a hinge and may be folded or unfolded relative to the housing 4110.

[0169] A battery, a touch panel, a microphone, a camera, etc. may be embedded in the frame 4100. In addition, a projector for outputting light, a processor for controlling an optical signal, etc. may be embedded in the frame 4100.

[0170] The lens unit 4200 may include an optical member that transmits or reflects light. For example, the lens unit 4200 may include glass, a transparent synthetic resin, or the like.

[0171] In order to allow the user's eyes to recognize visual information, the lens unit 4200 can reflect the image of the light signal transmitted from the projector of the frame 4100 by using the back surface of the lens unit 4200 (e.g., the surface facing the user's eyes). For example, the user can recognize visual information such as the time and date displayed on the lens unit 4200. In this case, the projector and / or the lens unit 4200 can be a type of display device. The display device 1200 can be applied to the projector and / or the lens unit 4200.

[0172] refer to Figure 13 , Figure 9 The display system 1000 can be applied to a head-mounted display device 5000.

[0173] The head-mounted display device 5000 may be a wearable electronic device that can be worn on the user's head. For example, the head-mounted display device 5000 may be a wearable device for virtual reality or mixed reality.

[0174] The head-mounted display device 5000 may include a headband 5100 and a display device storage box 5200. The headband 5100 may be connected to the display device storage box 5200. The headband 5100 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 5000 to the user's head. The horizontal strap may be configured to wrap around the sides of the user's head, and the vertical strap may be configured to wrap around the top of the user's head. However, embodiments are not limited thereto. For example, the headband 5100 may be implemented in the form of an eyeglass frame, a helmet, or the like.

[0175] The display device storage box 5200 may accommodate the display system 1000 and / or the display device 1200 .

[0176] However, aspects of the present disclosure are not limited to those described above, and various other aspects within the spirit and scope of the present disclosure will be understood by those of ordinary skill in the art.

[0177] The embodiments described in detail above are provided to illustrate the present disclosure, but these embodiments are not intended to limit the scope of the present disclosure. Those skilled in the art will appreciate that various changes, substitutions and replacements may be made therein without departing from the scope of the present disclosure as defined by the appended claims and their equivalents.

[0178] The scope of the embodiments according to the present disclosure is not limited by the detailed description of this specification, but should be defined by the appended claims and their equivalents. In addition, all changes or modifications of the present disclosure derived from the claims and their equivalents should be interpreted as being included in the scope of the embodiments according to the present disclosure. The embodiments can be combined to form additional embodiments.

Claims

1. A display device comprising: pixel circuit layer; a bonding electrode, above the pixel circuit layer; a first electrode above the bonding electrode; a light-emitting element, above the first electrode, for emitting light of a first color; a second electrode, above the light-emitting element; a distributed Bragg reflection layer, above the second electrode; as well as The color filter is above the distributed Bragg reflector layer and is configured to transmit light of a second color.

2. The display device according to claim 1, wherein The first color is orange.

3. The display device according to claim 1, wherein The second color is red.

4. The display device according to claim 3, wherein The color filter is configured to absorb or reflect light of a color other than the red color. 5 . The display device according to claim 1 , further comprising a lens between the distributed Bragg reflective layer and the color filter.

6. The display device according to claim 1, further comprising: a first protective layer on the first electrode, on a side surface of the light-emitting element, and on the second electrode; a second protective layer on the pixel circuit layer, on the bonding electrode, on the first electrode, and on the first protective layer; as well as A reflective layer is on the side surface of the second protective layer and on the pixel circuit layer.

7. The display device according to claim 6, wherein: The reflective layer does not overlap with the light emitting element.

8. The display device according to claim 6, further comprising: a first insulating layer, between the pixel circuit layer and the second electrode, and covering the reflective layer and the second protective layer; as well as A second insulating layer is between the second electrode and the distributed Bragg reflective layer.

9. The display device according to claim 1, wherein The distributed Bragg reflector layer includes at least one multilayer in which a first refractive layer, a second refractive layer, and another first refractive layer are sequentially stacked.

10. The display device according to claim 9, wherein The first refractive layer comprises titanium dioxide, Wherein, the second refractive layer comprises silicon dioxide, and Wherein, the thickness of the multilayer is 130nm to 160nm.

11. The display device according to claim 9, wherein The first refractive layer comprises tantalum dioxide, Wherein, the second refractive layer comprises silicon dioxide, and Wherein, the thickness of the multilayer is 150nm to 180nm.

12. The display device according to claim 9, wherein The multilayer comprises 3 to 60 layers.

13. The display device according to claim 1, further comprising: a first protective layer on the first electrode, on a side surface of the light-emitting element, and on a side surface of the second electrode; a second protective layer on a side surface of the first protective layer, on the pixel circuit layer, on the bonding electrode, and on the first electrode; as well as A reflective layer is on a side surface of the distributed Bragg reflective layer, on the pixel circuit layer, on the first protective layer, on the second protective layer, and on the second electrode.

14. The display device according to claim 13, wherein: The reflective layer partially overlaps with the light emitting element.

15. The display device according to claim 13, further comprising: a first insulating layer, between the reflective layer and the pixel circuit layer; as well as A second insulating layer is provided between the color filter, the distributed Bragg reflective layer, and the reflective layer.

16. A display device comprising: a first light emitting element at the same layer as the first insulating layer above the pixel circuit layer and configured to emit light of a first color; a distributed Bragg reflector layer, above the first insulating layer; a color filter over the distributed Bragg reflector layer and configured to transmit red light; a second light emitting element at the same layer as the second insulating layer above the color filter and configured to emit light of a second color; as well as The third light emitting element is located at the same layer as the third insulating layer above the second insulating layer and is configured to emit light of a third color.

17. The display device according to claim 16, wherein: The first color is orange, wherein the second color is green, and wherein the third color is blue.

18. The display device according to claim 16, further comprising: a first electrode, above the pixel circuit layer; a first through hole penetrating the first insulating layer, the distributed Bragg reflective layer, and the color filter; a second through hole, penetrating the second insulating layer; a third through hole, penetrating the third insulating layer; a second electrode, above the third insulating layer; as well as A lens is above the second electrode and overlaps the first light emitting element, the second light emitting element, and the third light emitting element, respectively.

19. The display device according to claim 18, wherein The first light-emitting element is above one of the first electrodes overlapping with the first light-emitting region, and is electrically connected to the second electrode through one of the first through holes overlapping with the first light-emitting region, one of the second through holes overlapping with the first light-emitting region, and one of the third through holes overlapping with the first light-emitting region.

20. The display device according to claim 18, wherein The second light-emitting element is electrically connected to a first electrode among the first electrodes that overlaps with the second light-emitting area through a first through hole among the first through holes that overlaps with the second light-emitting area, and is electrically connected to the second electrode through a second through hole among the second through holes that overlaps with the second light-emitting area and a third through hole among the third through holes that overlaps with the second light-emitting area.

21. The display device according to claim 18, wherein The third light-emitting element is electrically connected to a first electrode among the first electrodes overlapping with the third light-emitting area through a first through hole among the first through holes overlapping with the third light-emitting area and a second through hole among the second through holes overlapping with the third light-emitting area, and is electrically connected to the second electrode through a third through hole among the third through holes overlapping with the third light-emitting area.

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