Display device

Abstract

A first TFT (9A) having a first semiconductor layer (12a) formed of polycrystalline silicon, a second TFT (9B) having a top contact structure, and a third TFT (9C) having a second semiconductor layer (16a) formed of an oxide semiconductor, and a third semiconductor layer (19a) formed of an oxide semiconductor are provided in each of the sub-pixels. The third TFT (9C) has a bottom contact structure and is electrically connected to the third terminal electrode (23c) and the fourth terminal electrode (23d) on the upper side of the second semiconductor layer (16a), and the third TFT (9C) has a bottom contact structure and is electrically connected to the fifth terminal electrode (23e) and the sixth terminal electrode (23f) on the lower side of the third semiconductor layer (19a).

Description

Technical Field

[0001] The present invention relates to a display device. Background Art

[0002] In recent years, self-luminous organic EL displays using organic electroluminescence (EL) elements have attracted attention as an alternative to liquid crystal displays. In these organic EL displays, multiple thin-film transistors (TFTs) are provided for each sub-pixel, the smallest unit of an image. Semiconductor layers that constitute TFTs include, for example, those made of high-mobility polycrystalline silicon and those made of oxide semiconductors such as In-Ga-Zn-O, which have low leakage current.

[0003] For example, Patent Document 1 discloses a semiconductor device comprising a first TFT and a second TFT, wherein the first TFT has a first active layer mainly comprising a first oxide semiconductor, and the second TFT has a second active layer mainly comprising a second oxide semiconductor, wherein the mobility of the second oxide semiconductor is higher than the mobility of the first oxide semiconductor, and the first active layer and the second active layer are arranged on the same insulating layer and in contact with the same insulating layer.

[0004] Prior art literature Patent Literature Patent Document 1: International Publication No. 2016 / 006530 Summary of the Invention Technical problems to be solved by the present invention However, in organic EL display devices having a hybrid structure in which TFTs using polysilicon and TFTs using oxide semiconductors are provided in each subpixel, for example, it has been proposed to use polysilicon for TFTs requiring driving power and oxide semiconductors for TFTs requiring charge retention. Furthermore, the required characteristics of TFTs using oxide semiconductors vary depending on the function of the transistor, making it difficult to achieve characteristics suitable for each function using a single structure, thus leaving room for improvement.

[0005] The present invention has been made in view of this point, and an object of the present invention is to optimize the characteristics of a TFT using an oxide semiconductor in a display device having a hybrid structure.

[0006] Technical solutions to technical problems To achieve the above object, a display device according to the present invention includes: a base substrate; and a thin film transistor layer provided on the base substrate, wherein the thin film transistor layer includes a first thin film transistor, a second thin film transistor, and a third thin film transistor for each sub-pixel constituting a display region, the first thin film transistor including a first semiconductor layer formed of polycrystalline silicon, the second thin film transistor including a second semiconductor layer formed of an oxide semiconductor, and the third thin film transistor including a third semiconductor layer formed of an oxide semiconductor. The first thin film transistor includes: a first semiconductor layer defining a first conductor region and a second conductor region so as to be separated from each other, and defining a first channel region between the first conductor region and the second conductor region; a first gate electrode provided on the first semiconductor layer so as to overlap with the first channel region with a first inorganic insulating film interposed therebetween; and a first terminal electrode and a second terminal electrode, the first terminal electrode and the second terminal electrode being provided so as to be separated from each other on a side opposite to the base substrate relative to the first gate electrode and being electrically connected to the first conductor region and the second conductor region, respectively. The second thin film transistor includes: a second semiconductor layer defining a third conductor region and a fourth conductor region so as to be separated from each other, and defining a first channel region between the first conductor region and the second conductor region. a second channel region is defined between the first and second semiconductor regions; a second gate electrode is provided on the second semiconductor layer in a manner overlapping with the second channel region via a second inorganic insulating film; and a third terminal electrode and a fourth terminal electrode, the third terminal electrode and the fourth terminal electrode being provided in a manner separated from each other on a side opposite to the base substrate than the second gate electrode, and being electrically connected to the third conductor region and the fourth conductor region, respectively, the third thin film transistor comprising: a third semiconductor layer, which defines a fifth conductor region and a sixth conductor region in a manner separated from each other, and between the fifth conductor region and the sixth conductor region. A third channel region is defined; a first relay electrode and a second relay electrode, the first relay electrode and the second relay electrode are arranged on the base substrate side of the third semiconductor layer and are configured in contact with the fifth conductor region and the sixth conductor region, respectively; a third gate is arranged on the third semiconductor layer in a manner overlapping with the third channel region via a third inorganic insulating film; and a fifth terminal electrode and a sixth terminal electrode are arranged in a manner separated from each other on the side opposite to the base substrate than the third gate, and are electrically connected to the first relay electrode and the second relay electrode, respectively.

[0007] Beneficial effects According to the present invention, in a display device having a hybrid structure, it is possible to optimize the characteristics of a TFT using an oxide semiconductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a block diagram showing the overall configuration of an organic EL display device according to a first embodiment of the present invention.

[0009] Figure 2 This is an equivalent circuit diagram of a pixel circuit constituting a TFT layer of the organic EL display device according to the first embodiment of the present invention.

[0010] Figure 3 It is a plan view schematically showing the structure of a TFT layer constituting the organic EL display device according to the first embodiment of the present invention.

[0011] Figure 4 It is a cross-sectional view of the organic EL display device according to the first embodiment of the present invention.

[0012] Figure 5 It is a cross-sectional view of an organic EL layer constituting the organic EL display device according to the first embodiment of the present invention.

[0013] Figure 6 This is a timing chart for explaining the operation of the pixel circuit of the organic EL display device according to the first embodiment of the present invention.

[0014] Figure 7 It is a cross-sectional view showing a part of the process of forming the TFT layer constituting the organic EL display device according to the first embodiment of the present invention.

[0015] Figure 8 It means next Figure 7 A cross-sectional view of a portion of the TFT layer formation process.

[0016] Figure 9 It is a cross-sectional view of an organic EL display device according to a second embodiment of the present invention.

[0017] Figure 10 It is a cross-sectional view showing a part of the process of forming a TFT layer constituting the organic EL display device according to the second embodiment of the present invention.

[0018] Figure 11 It means next Figure 10 A cross-sectional view of a portion of the TFT layer formation process.

[0019] Figure 12 It means next Figure 11 A cross-sectional view of a portion of the TFT layer formation process.

[0020] Figure 13 It is a cross-sectional view of an organic EL display device according to a third embodiment of the present invention.

[0021] Figure 14It is a cross-sectional view showing a part of the process of forming a TFT layer constituting the organic EL display device according to the third embodiment of the present invention.

[0022] Figure 15 It means next Figure 14 A cross-sectional view of a portion of the TFT layer formation process.

[0023] Figure 16 It means next Figure 15 A cross-sectional view of a portion of the TFT layer formation process.

[0024] Figure 17 It means next Figure 16 A cross-sectional view of a portion of the TFT layer formation process. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the present invention will be described in detail based on the drawings. However, the present invention is not limited to the following embodiments.

[0026] First Implementation Method Figures 1 to 8 The first embodiment of the display device of the present invention is shown. In the following embodiments, an organic EL display device including an organic EL element layer is exemplified as a display device including a light-emitting element layer. Figure 1 : is a block diagram showing the overall structure of the organic EL display device 100a of this embodiment. Figure 2 is an equivalent circuit diagram of a pixel circuit of the TFT layer 30a constituting the organic EL display device 100a. Figure 3 3 is a plan view showing a schematic structure of the TFT layer 30a. Figure 4 : is a cross-sectional view of the organic EL display device 100a. Figure 5 3 is a cross-sectional view of the organic EL layer 33 constituting the organic EL display device 100a. Figure 6 This is a timing chart for explaining the operation of the pixel circuit of the organic EL display device 100 a .

[0027] like Figure 1 As shown, the organic EL display device 100a includes: a display area 50 in which a plurality of sub-pixels P are arranged in a matrix; and a gate driver 60, an emission driver 70, and a source driver 80 provided in a frame area around the display area 50. Figure 1 As shown, a display control circuit 150 electrically connected to the gate driver 60 , the emission driver 70 , and the source driver 80 is provided outside the organic EL display device 100 a .

[0028] In addition, if Figure 4As shown, the organic EL display device 100a includes: a resin substrate 10 provided as a base substrate, a TFT layer 30a provided on the resin substrate 10, an organic EL element layer 40 provided on the TFT layer 30a as a light-emitting element layer, and a sealing film 45 provided on the organic EL element layer 40.

[0029] The resin substrate 10 is made of, for example, polyimide resin.

[0030] like Figure 4 As shown, the TFT layer 30a includes: a primer film 11 provided on a resin substrate 10; four first TFTs 9A, one second TFT 9B, two third TFTs 9C, and one capacitor 9h provided on the primer film 11 for each sub-pixel P (see Figure 2 ); and a planarizing film 24 provided on each first TFT 9A, each second TFT 9B, each third TFT 9C and each capacitor 9h.

[0031] like Figure 1 As shown, i first scanning signal lines PS(1) to PS(i), (i+1) second scanning signal lines NS(0) to NS(i), i light emitting control lines EM(1) to EM(i), and j data signal lines D(1) to D(j) are provided in the display area 50 of the TFT layer 30a. In addition, i and j are integers greater than 2, n is an integer greater than 1 and less than i, and m is an integer greater than 1 and less than j. In addition, Figure 1 In the figure, the first scanning signal line PS, the second scanning signal line NS, and the data signal line D are omitted in the display area 50. Here, the first scanning signal lines PS (1) to PS (i) are signal lines for transmitting the control signal for the P-channel transistor, that is, the first scanning signal. In addition, the second scanning signal lines NS (0) to NS (i) are signal lines for transmitting the control signal for the N-channel transistor, that is, the second scanning signal. In addition, the light-emitting control lines EM (1) to EM (i) are signal lines for transmitting the light-emitting control signal. In addition, the first scanning signal lines PS (1) to PS (i), the second scanning signal lines NS (0) to NS (i), and the light-emitting control lines EM (1) to EM (i) are arranged in parallel with each other. In addition, the first scanning signal lines PS (1) to PS (i) and the data signal lines D (1) to D (j) are arranged in a mutually orthogonal manner. In addition, in Figure 6In the timing diagram, the first scanning signals respectively provided to the first scanning signal lines PS(1) to PS(i) are also marked with reference numerals PS(1) to PS(i), the second scanning signals respectively provided to the second scanning signal lines NS(0) to NS(i) are also marked with reference numerals NS(0) to NS(i), the light emitting control signals respectively provided to the light emitting control lines EM(1) to EM(i) are also marked with reference numerals EM(1) to EM(i), and the data signals (data voltages) respectively provided to the data signal lines D(1) to D(j) are also marked with reference numerals D(1) to D(j).

[0032] In addition, in the display area 50 of the TFT layer 30a, there are a power supply line (hereinafter referred to as the "high-level power supply line") that supplies a high-level power supply voltage ELVDD for driving the organic EL element 35 described later, a power supply line (hereinafter referred to as the "low-level power supply line") that supplies a low-level power supply voltage ELVSS for driving the organic EL element 35, and a power supply line (hereinafter referred to as the "initialization power supply line") that supplies an initialization voltage Vini. In addition, in this embodiment, as needed, the high-level power supply line is also marked with the reference numeral ELVDD, the low-level power supply line is also marked with the reference numeral ELVSS, and the initialization power supply line is also marked with the reference numeral Vini. In addition, the high-level power supply voltage ELVDD, the low-level power supply voltage ELVSS, and the initialization voltage Vini are supplied from a power supply circuit not shown. Here, in Figure 3 In the plan view, the first scanning signal line 14g extending in the X direction is represented as the first scanning signal line PS, the light-emitting control line 14e extending in the X direction is represented as the light-emitting control line EM, the second scanning signal line 18d extending in the X direction is represented as the second scanning signal line NS, the initialization power line 18i extending in the X direction is represented as the initialization power line Vini, the data signal line 23g extending in the Y direction is represented as the data signal line D, and the high-level power line 23h extending in the Y direction is represented as the high-level power line ELVDD.

[0033] The undercoat film 11, the first gate insulating film 13 provided as a first inorganic insulating film described later, the first interlayer insulating film 15 provided as a fourth inorganic insulating film, the second gate insulating film 17 provided as a second inorganic insulating film, the third gate insulating film 20 provided as a third inorganic insulating film, and the second interlayer insulating film 22 provided as a third inorganic insulating film are composed of, for example, a single layer or a stacked layer of an inorganic insulating film such as silicon nitride, silicon oxide, or silicon oxynitride. At least the first interlayer insulating film 15 on the second semiconductor layer 16 a side described later, the second gate insulating film 17 on the second semiconductor layer 16 a side, and the third semiconductor layer 19 a side described later, as well as the third gate insulating film 20 on the third semiconductor layer 19 a side are composed of, for example, a silicon oxide film.

[0034] like Figure 4 As shown, the first TFT 9A includes: a first semiconductor layer 12a, which is arranged on the base coating film 11; a first gate 14a, which is arranged on the first semiconductor layer 12a via the first gate insulating film 13; and a first terminal electrode 23a and a second terminal electrode 23b, which are arranged in a manner separated from each other on the second interlayer insulating film 22.

[0035] The first semiconductor layer 12a is formed of polysilicon such as LTPS (low temperature polysilicon), for example. Figure 4 As shown, it includes a first conductor region 12aa and a second conductor region 12ab defined so as to be separated from each other, and a first channel region 122ac defined between the first conductor region 12aa and the second conductor region 12ab.

[0036] like Figure 4 As shown, the first gate 14a is provided so as to overlap the first channel region 12ac of the first semiconductor layer 12a and controls conduction between the first conductor region 12aa and the second conductor region 12ab of the first semiconductor layer 12a.

[0037] like Figure 4 As shown, the first terminal electrode 23a and the second terminal electrode 23b are electrically connected to the first conductor region 12aa and the second conductor region 12ab of the first semiconductor layer 12a respectively via the first contact hole Ha and the second contact hole Hb formed in the stacked film of the first gate insulating film 13, the first interlayer insulating film 15, the second gate insulating film 17, the third gate insulating film 20 and the second interlayer insulating film 22.

[0038] like Figure 4 As shown, the second TFT 9B includes: a second semiconductor layer 16a provided on the first interlayer insulating film 15; a second gate electrode 18a provided on the second semiconductor layer 16a via a second gate insulating film 17; and a third terminal electrode 23c and a fourth terminal electrode 23d provided on the second interlayer insulating film 22 in a manner separated from each other. Figure 4 As shown, the second TFT 9B has a top contact structure, and has a tendency for the threshold value to shift toward the negative side.

[0039] The second semiconductor layer 16a is formed of, for example, an oxide semiconductor such as In-Ga-Zn-O. Figure 4As shown, it includes a third conductive region 16aa and a fourth conductive region 16ab, which are defined so as to be separated from each other; and a second channel region 16ac, which is defined between the third conductive region 16aa and the fourth conductive region 16ab. Here, an In-Ga-Zn-O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc). The ratio (composition ratio) of In, Ga, and Zn is not particularly limited. Furthermore, an In-Ga-Zn-O-based semiconductor can be either amorphous or crystalline. As a crystalline In-Ga-Zn-O-based semiconductor, one with a c-axis aligned substantially perpendicular to the plane is preferred. Alternatively, other oxide semiconductors may be included. Examples of other oxide semiconductors include In-Sn-Zn-O-based semiconductors (e.g., In2O3-SnO2-ZnO; InSnZnO). Here, the In-Sn-Zn-O semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Other oxide semiconductors include In-Al-Zn-O semiconductors, In-Al-Sn-Zn-O semiconductors, Zn-O semiconductors, In-Zn-O semiconductors, Zn-Ti-O semiconductors, Cd-Ge-O semiconductors, Cd-Pb-O semiconductors, CdO (cadmium oxide), Mg-Zn-O semiconductors, In-Ga-Sn-O semiconductors, In-Ga-O semiconductors, Zr- In-Zn-O semiconductors, Hf-In-Zn-O semiconductors, Al-Ga-Zn-O semiconductors, Ga-Zn-O semiconductors, In-Ga-Zn-Sn-O semiconductors, InGaO3 (ZnO)5, magnesium zinc oxide (Mg x Zn 1-x O), cadmium zinc oxide (Cd x Zn 1-x O), etc. In addition, as the Zn-O-based semiconductor, a semiconductor in an amorphous (non-crystalline) state, a semiconductor in a polycrystalline state, a semiconductor in a microcrystalline state in which an amorphous state and a polycrystalline state are mixed, or a semiconductor to which no impurity element is added can be used, to which one or more impurity elements selected from Group I elements, Group XIII elements, Group XIV elements, Group XV elements, and Group XVII elements are added.

[0040] like Figure 4 As shown, the second gate 18a is provided to overlap the second channel region 16ac of the second semiconductor layer 16a and is configured to control conduction between the third conductor region 16aa and the fourth conductor region 16ab of the second semiconductor layer 16a.

[0041] like Figure 4As shown, the third terminal electrode 23c and the fourth terminal electrode 23d are electrically connected to the third conductor region 16aa and the fourth conductor region 16ab of the second semiconductor layer 16a via the third contact hole Hc and the fourth contact hole Hd formed in the stacked film of the second gate insulating film 17, the third gate insulating film 20 and the second interlayer insulating film 22.

[0042] like Figure 4 As shown, the third TFT 9C includes: a third semiconductor layer 19a provided on the second gate insulating film 17; a first relay electrode 18b and a second relay electrode 18c provided on the resin substrate 10 side of the third semiconductor layer 19a in a manner separated from each other; a third gate electrode 21a provided on the third semiconductor layer 19a via the third gate insulating film 20; and a fifth terminal electrode 23e and a sixth terminal electrode 23f provided on the second interlayer insulating film 22 in a manner separated from each other. Figure 4 As shown, the third TFT 9C has a bottom contact structure. For example, in order to form the first relay electrode 18b and the second relay electrode 18c, oxygen ashing during patterning of the second metal film described later by dry etching and trace residues of the second metal film cause the oxide semiconductor to be oxidized, thereby having a tendency for the threshold to easily advance toward the positive side.

[0043] The third semiconductor layer 19a is similar to the second semiconductor layer 16a and is formed of an oxide semiconductor such as In-Ga-Zn-O. Figure 4 As shown, it includes a fifth conductor region 19aa and a sixth conductor region 19ab defined so as to be separated from each other, and a third channel region 19ac defined between the fifth conductor region 19aa and the sixth conductor region 19ab.

[0044] like Figure 4 As shown, the first relay electrode 18b and the second relay electrode 18c are provided on the second gate insulating film 17 and are provided in contact with the lower surfaces of the fifth conductor region 19aa and the sixth conductor region 19ab of the third semiconductor layer 19a, respectively.

[0045] like Figure 4 As shown, the third gate electrode 21a is provided so as to overlap the third channel region 19ac of the third semiconductor layer 19a and is configured to control conduction between the fifth conductor region 19aa and the sixth conductor region 19ab of the third semiconductor layer 19a.

[0046] like Figure 4 As shown, the fifth terminal electrode 23e and the sixth terminal electrode 23f are electrically connected to the first relay electrode 18b and the second relay electrode 18c via a fifth contact hole He and a sixth contact hole Hf formed in the stacked film of the third gate insulating film 20 and the second interlayer insulating film 22, respectively.

[0047] In addition, in the TFT layer 30a, as shown in FIG. Figure 4 As shown, a primer film 11, a first semiconductor film serving as a first semiconductor layer 12a, a first gate insulating film 13, a first metal film serving as a first gate electrode 14a, a first interlayer insulating film 15, a second semiconductor film serving as a second semiconductor layer 16a, a second gate insulating film 17, a second metal film serving as a first relay electrode 18b, a third semiconductor film serving as a third semiconductor layer 19a, a third gate insulating film 20, a third metal film serving as a third gate electrode 21a, a second interlayer insulating film 22, a fourth metal film serving as a first terminal electrode 23a, and a planarizing film 24 are sequentially stacked on a resin substrate 10.

[0048] In this embodiment, a writing control TFT 9c, a driving TFT 9d, a power supply control TFT 9e, and a light emission control TFT 9f are provided as the first TFT 9A, a threshold voltage compensation TFT 9b, and a third TFT 9C are provided as the third TFT 9C (see FIG. 1 ). Figure 2 ). In addition, Figure 2 In the equivalent circuit diagram, circled numbers 1 and 2 represent the first terminal electrode 23a and the second terminal electrode 23b of the write control TFT 9c, the drive TFT 9d, the power supply control TFT 9e and the light emitting control TFT 9f, circled numbers 3 and 4 represent the third terminal electrode 23c and the fourth terminal electrode 23d of the threshold voltage compensation TFT 9b, and circled numbers 5 and 6 represent the fifth terminal electrode 23e and the sixth terminal electrode 23f of the initialization TFT 9a and the anode discharge TFT 9g.

[0049] like Figure 2 As shown, in the initialization TFT 9a, its third gate electrode 21a is electrically connected to the second scanning signal line NS(n-1) of the (n-1)th row, its fifth terminal electrode 23e is connected to the third terminal electrode 23c of the threshold voltage compensation TFT 9b, the first gate electrode 14a of the driving TFT 9d and the capacitor 9h, and its sixth terminal electrode 23f is electrically connected to the initialization power supply line Vini.

[0050] like Figure 2 As shown, in the threshold voltage compensation TFT 9b, its second gate electrode 18a is electrically connected to the second scanning signal line NS of the nth row, its third terminal electrode 23c is electrically connected to the fifth terminal electrode 23e of the initialization TFT 9a, the first gate electrode 14a of the driving TFT 9d and the capacitor 9h, and its fourth terminal electrode 23d is electrically connected to the second terminal electrode 23b of the driving TFT 9d and the first terminal electrode 23a of the light-emitting control TFT 9f.

[0051] like Figure 2 As shown, in the write control TFT 9c, its first gate electrode 14a is electrically connected to the first scanning signal line PS(n) of the nth row, its first terminal electrode 23a is electrically connected to the data signal line D(m) of the mth column, and its second terminal electrode 23b is electrically connected to the first terminal electrode 23a of the drive TFT 9d and the second terminal electrode 23b of the power supply control TFT 9e.

[0052] like Figure 2 As shown, in the driving TFT 9d, its first gate electrode 14a is electrically connected to the fifth terminal electrode 23e of the initialization TFT 9a, the third terminal electrode 23c of the threshold voltage compensation TFT 9b, and the capacitor 9h. Its first terminal electrode 23a is electrically connected to the second terminal electrode 23b of the write control TFT 9c and the second terminal electrode 23b of the power supply control TFT 9e. Its second terminal electrode 23b is electrically connected to the fourth terminal electrode 23d of the threshold voltage compensation TFT 9b and the first terminal electrode 23a of the light emission control TFT 9f. Furthermore, the high-level power supply voltage ELVDD is input to the first terminal electrode 23a of the driving TFT 9d during the period when the organic EL element 35 is emitting light, and the data signal D(m) is input during the period when data is being written to the capacitor 9h.

[0053] like Figure 2 As shown, in the power supply control TFT 9e, its first gate electrode 14a is electrically connected to the light emission control line EM(n) of the n-th row, its first terminal electrode 23a is electrically connected to the high-level power supply line ELVDD and the capacitor 9h, and its second terminal electrode 23b is electrically connected to the second terminal electrode 23b of the write control TFT 9c and the first terminal electrode 23a of the drive TFT 9d.

[0054] like Figure 2 As shown, in the light emission control TFT 9f, its first gate electrode 14a is electrically connected to the light emission control line EM(n) of the n-th row, its first terminal electrode 23a is electrically connected to the fourth terminal electrode 23d of the threshold voltage compensation TFT 9b and the second terminal electrode 23b of the drive TFT 9d, and its second terminal electrode 23b is electrically connected to the sixth terminal electrode 23f of the anode discharge TFT 9g and the first electrode 31 of the organic EL element 35, which will be described later.

[0055] like Figure 2 As shown, in the anode discharge TFT 9g, its third gate electrode 21a is electrically connected to the emission control line EM(n) of the n-th row, its fifth terminal electrode 23e is electrically connected to the initialization power supply line Vini, and its sixth terminal electrode 23f is electrically connected to the second terminal electrode 23b of the emission control TFT 9f and the first electrode 31 of the organic EL element 35.

[0056] The capacitor 9h includes, for example, a first capacitor electrode formed of the same material and provided on the same layer as the third gate electrode 21a; a second capacitor electrode formed of the same material and provided on the same layer as the first terminal electrode 23a; and a second interlayer insulating film 22 provided between the first and second capacitor electrodes. The first capacitor electrode of the capacitor 9h is electrically connected to the high-level power supply line ELVDD and the first terminal electrode 23a of the power supply control TFT 9e, while the second capacitor electrode is electrically connected to the fifth terminal electrode 23e of the initialization TFT 9a, the third terminal electrode 23c of the threshold voltage compensation TFT 9b, and the first gate electrode 14a of the drive TFT 9d.

[0057] The planarizing film 24 has a flat surface in the display region 50 and is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG (spin on glass) material.

[0058] like Figure 4 As shown, the organic EL element layer 40 includes: a plurality of organic EL elements 35, which are arranged in a matrix as a plurality of light-emitting elements corresponding to a plurality of sub-pixels P; and an edge cover 32, which is commonly arranged in a grid shape on all sub-pixels P in a manner that covers the peripheral end portion of the first electrode 31 described later of each organic EL element 35.

[0059] like Figure 4 As shown, the organic EL element 35 includes a first electrode (anode) 31 provided on the planarization film 24 of the TFT layer 30 a , an organic EL layer 33 provided on the first electrode 31 , and a second electrode (cathode) 34 provided on the organic EL layer 33 in each sub-pixel P.

[0060] The first electrode 31 is electrically connected to the second terminal electrode 23b of the light emission control TFT 9f in each subpixel P via a contact hole formed in the planarizing film 24. The first electrode 31 also functions to inject holes (positive holes) into the organic EL layer 33. To improve the efficiency of hole injection into the organic EL layer 33, it is preferable to form the first electrode 31 from a material with a high work function. Examples of materials for the first electrode 31 include metal materials such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), and tin (Sn). Alternatively, the first electrode 31 may be made of an alloy such as astatine (At) / astatine oxide (AtO2). Furthermore, the material constituting the first electrode 31 may be, for example, a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). Furthermore, the first electrode 31 may be formed by stacking multiple layers of the above materials. Examples of compound materials with a large work function include indium tin oxide (ITO) and indium zinc oxide (IZO).

[0061] like Figure 5 As shown, the organic EL layer 33 includes a hole injection layer 1 , a hole transport layer 2 , a light emitting layer 3 , an electron transport layer 4 , and an electron injection layer 5 stacked in this order on the first electrode 31 .

[0062] The hole injection layer 1, also known as the anode buffer layer, has the function of bringing the energy levels of the first electrode 31 and the organic EL layer 33 closer together, thereby improving the efficiency of hole injection from the first electrode 31 to the organic EL layer 33. Examples of materials constituting the hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, and stilbene derivatives.

[0063] The hole transport layer 2 has a function of improving the efficiency of hole transport from the first electrode 31 to the organic EL layer 33. Examples of materials constituting the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, styrylamine derivatives, polyvinylcarbazole, polyparaphenylenevinylene, polysilane, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, zinc sulfide, and zinc selenide.

[0064] The light emitting layer 3 is a region where holes and electrons are injected from the first electrode 31 and the second electrode 34 and recombine when voltage is applied thereto. The light emitting layer 3 is formed of a material with high light emission efficiency. In addition, as materials constituting the light-emitting layer 3, for example, metal oxide compounds [8-hydroxyquinoline metal complexes], naphthalene derivatives, anthracene derivatives, diphenylethylene derivatives, vinylacetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzoxazole derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzothiazole derivatives, styryl derivatives, styrylamine derivatives, distyrylbenzene derivatives, tristyrylbenzene derivatives, perylene derivatives, perinone derivatives (perinone inducers), aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, acridine derivatives, phenoxazole (fenokisone), quinacridone derivatives, rubrene, polyparaphenylenevinylene, polysilane, etc. can be listed.

[0065] The electron transport layer 4 has the function of efficiently transferring electrons to the light-emitting layer 3. Examples of materials constituting the electron transport layer 4 include organic compounds such as oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinodimethane derivatives, dibenzoquinone derivatives, fluorenone derivatives, silole derivatives (silole inducers), and metal oxo compounds (metal oxo compounds).

[0066] The electron injection layer 5 has the function of aligning the energy levels of the second electrode 34 and the organic EL layer 33, thereby improving the efficiency of electron injection from the second electrode 34 to the organic EL layer 33. This function can reduce the driving voltage of the organic EL element 35. The electron injection layer 5 is also called a cathode buffer layer. Examples of materials constituting the electron injection layer 5 include inorganic base compounds such as lithium fluoride (LiF), magnesium fluoride (MgF2), calcium fluoride (CaF2), strontium fluoride (SrF2), and barium fluoride (BaF2), aluminum oxide (Al2O3), and strontium oxide (SrO).

[0067] like Figure 4 As shown, the second electrode 34 is provided in common on all sub-pixels P in a manner covering each organic EL layer 33 and the edge cover 32. In addition, the second electrode 34 has the function of injecting electrons into the organic EL layer 33. In order to improve the efficiency of injecting electrons into the organic EL layer 33, the second electrode 34 is preferably made of a material with a small work function. Figure 2As shown, the second electrode 34 is electrically connected to the low-level power supply line ELVSS. Examples of materials for the second electrode 34 include silver (Ag), aluminum (Al), vanadium (V), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), and lithium fluoride (LiF). Alternatively, the second electrode 34 may be formed from alloys such as magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), astatine (At) / astatine oxide (AtO2), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), or lithium fluoride (LiF) / calcium (Ca) / aluminum (Al). Alternatively, the second electrode 34 may be formed from conductive oxides such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO). Alternatively, the second electrode 34 may be formed by stacking a plurality of layers made of the above-mentioned materials. Examples of materials with a low work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), and lithium fluoride (LiF) / calcium (Ca) / aluminum (Al).

[0068] The edge cover 32 is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG material.

[0069] like Figure 4 As shown, the sealing film 45 includes a first inorganic sealing film 41, an organic sealing film 42 and a second inorganic sealing film 43 which are sequentially stacked on the second electrode 34 and are provided to cover the second electrode 34. The sealing film 45 has the function of protecting the organic EL layer 33 of the organic EL element 35 from moisture and oxygen.

[0070] The first inorganic sealing film 41 and the second inorganic sealing film 43 are formed of an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film.

[0071] The organic sealing film 42 is made of an organic resin material such as acrylic resin, epoxy resin, silicone resin, polyurea resin, parylene resin, polyimide resin, or polyamide resin.

[0072] Next, the operation of the organic EL display device 100 a having the above configuration will be described.

[0073] <Operation of Peripheral Circuits> like Figure 1As shown, the display control circuit 150 receives an externally transmitted input image signal DIN and a timing signal group (horizontal synchronization signal, vertical synchronization signal, etc.) TG, and outputs a digital video signal DV, a gate control signal GCTL for controlling the operation of the gate driver 60, an emission driver control signal EMCTL for controlling the operation of the emission driver 70, and a source control signal SCTL for controlling the operation of the source driver 80. The gate control signal GCTL includes a gate start pulse signal, a gate clock signal, and the like. Furthermore, the emission driver control signal EMCTL includes an emission start pulse signal, an emission clock signal, and the like. Furthermore, the source control signal SCTL includes a source start pulse signal, a source clock signal, a latch strobe signal, and the like.

[0074] The gate driver 60 is electrically connected to the first scanning signal lines PS(1) to PS(i) and the second scanning signal lines NS(0) to NS(i). The gate driver 60 applies a first scanning signal to the first scanning signal lines PS(1) to PS(i) and a second scanning signal to the second scanning signal lines NS(0) to NS(i) based on a gate control signal GCTL output from the display control circuit 150.

[0075] The emission driver 70 is electrically connected to the emission control lines EM(1) to EM(i). The emission driver 70 applies emission control signals to the emission control lines EM(1) to EM(i) based on the emission driver control signals EMCTL output from the display control circuit 150.

[0076] The source driver 80 includes a j-bit shift register (not shown), a sampling circuit, a latch circuit, and j D / A converters. Here, the shift register has j cascade-connected registers. Based on the source clock signal, the pulse of the source start pulse signal supplied to the first-stage register is transmitted from the input end to the output end in sequence. According to the transmission of the pulse, a sampling pulse is output from the register of each stage. In addition, the sampling circuit stores the digital video signal DV based on the sampling pulse. Then, the latch circuit collects and holds a row of digital video signals DV stored in the sampling circuit according to the latch selection signal. In addition, the D / A converter is set to correspond to each data signal line D (1) to D (j), converts the digital video signal DV held by the latch circuit into an analog voltage, and applies the converted analog voltage as the data signal (data voltage) to all data signal lines D (1) to D (j) at the same time.

[0077] As described above, data signals are applied to the data signal lines D(1) to D(j), first scan signals are applied to the first scan signal lines PS(1) to PS(i), second scan signals are applied to the second scan signal lines NS(0) to NS(i), and light emission control signals are applied to the light emission control lines EM(1) to EM(i), whereby an image based on the input image signal DIN is displayed on the display area 50.

[0078] <Pixel Circuit Operation> Next, use Figure 6 The operation of the pixel circuit of the organic EL display device 100a according to this embodiment will be described with reference to the timing chart of FIG. Note that the operation of the pixel circuit is only an example and is not limited thereto.

[0079] First, before time t01, the first scanning signal PS(n) goes high, while the second scanning signal NS(n-1), the second scanning signal NS(n), and the emission control signal EM(n) go low. At this point, the power supply control TFT 9e and the emission control TFT 9f are turned on, while the anode discharge TFT 9g is turned off. Therefore, before time t01, a drive current corresponding to the charge voltage of capacitor 9h is supplied to the organic EL element 35, and the organic EL element 35 emits light in accordance with the magnitude of this drive current.

[0080] At time t01, the emission control signal EM(n) transitions from a low level to a high level, turning off the power supply control TFT 9e and the emission control TFT 9f. As a result, the supply of drive current to the organic EL element 35 is cut off, turning off the organic EL element 35. Furthermore, the transition from a low level to a high level in the emission control signal EM(n) turns on the anode discharge TFT 9g. This initializes the voltage of the first electrode 31 of the organic EL element 35 based on the initialization voltage Vini.

[0081] At time t02, the second scanning signal NS(n-1) changes from a low level to a high level, turning on the initialization TFT 9a. As a result, the gate voltage of the driving TFT 9d is initialized. In other words, the gate voltage of the driving TFT 9d becomes equal to the initialization voltage Vini.

[0082] At time t03, the second scanning signal NS(n-1) changes from high to low, turning the initialization TFT 9a off. Also at time t03, the second scanning signal NS(n) changes from low to high, turning the threshold voltage compensation TFT 9b on.

[0083] When it becomes time t04, the first scan signal PS(n) changes from a high level to a low level, whereby the write control TFT 9c becomes conductive. Here, since the threshold voltage compensation TFT 9b becomes conductive at time t03, the write control TFT 9c becomes conductive at time t04. Thus, via the write control TFT 9c, the drive TFT 9d, and the threshold voltage compensation TFT 9b, the data signal D(m) is input to the second capacitive electrode of the capacitor 9h. Thereby, the capacitor 9h is charged.

[0084] When it becomes time t05, the first scan signal PS(n) changes from a low level to a high level, whereby the write control TFT 9c becomes non-conductive.

[0085] When it becomes time t06, since the second scan signal NS(n) changes from a high level to a low level, the threshold voltage compensation TFT 9b becomes non-conductive.

[0086] When it becomes time t07, the emission control signal EM(n) changes from a high level to a low level, so that the anode discharge TFT 9g becomes non-conductive, and the power supply control TFT 9e and the emission control TFT 9f become conductive. Thus, a drive current corresponding to the charging voltage of the capacitor 9h is supplied to the organic EL element 35. As a result, the organic EL element 35 emits light according to the magnitude of the drive current.

[0087] In this way, in the organic EL display device 100a, in each sub-pixel P, the organic EL element 35 emits light with a luminance corresponding to the drive current to perform image display.

[0088] Next, a method for manufacturing the organic EL display device 100a of the present embodiment will be described. In addition, the method for manufacturing the organic EL display device 100a includes a TFT layer formation process, an organic EL element layer formation process, and a sealing film formation process. Here, Figure 7 is a cross-sectional view showing a part of the process for forming the TFT layer 30a. In addition, Figure 8 is a cross-sectional view showing a part of the process for forming the TFT layer 30a following Figure 7 this.

[0089] <TFT layer formation process> First, for example, by plasma CVD (Chemical Vapor Deposition) method, a silicon oxide film (with a thickness of about 100 nm) is formed on the resin substrate 10 formed on the glass substrate to form the undercoat film 11.

[0090] Next, an amorphous silicon film (about 50 nm thick) is formed on the surface of the substrate on which the base coating film 11 is formed, for example, by a plasma CVD method. After the amorphous silicon film is crystallized by laser annealing or the like to form a first semiconductor film composed of polycrystalline silicon, the first semiconductor film is patterned to form a first semiconductor layer 12a, etc.

[0091] Then, a silicon oxide film (having a thickness of approximately 100 nm) is formed on the substrate surface on which the first semiconductor layer 12 a and the like are formed, for example, by plasma CVD, thereby forming the first gate insulating film 13 .

[0092] Furthermore, after forming a first metal film by, for example, sputtering, forming a molybdenum film (thickness of about 250 nm) on the surface of the substrate on which the first gate insulating film 13 is formed, the first metal film is patterned to form a first gate 14a, a first scanning signal line 14g, a light-emitting control line 14e, etc.

[0093] Next, using the first gate 14a as a mask, impurity ions are doped to make part of the first semiconductor layer 12a conductive, thereby forming a first conductive region 12aa, a second conductive region 12ab, and a first channel region 12ac in the first semiconductor layer 12a.

[0094] Then, for example, by a plasma CVD method, a single layer of silicon oxide film (thickness of about 200 nm) or a stacked film of silicon nitride film (thickness of about 150 nm) and silicon oxide film (thickness of about 50 nm) is stacked in sequence on the surface of the substrate in which a portion of the first semiconductor layer 12 a is made conductive, thereby forming a first interlayer insulating film 15.

[0095] Then, for example, a film such as InGaZnO4 (thickness of about 30 nm) is formed on the surface of the substrate on which the first interlayer insulating film 15 is formed by sputtering to form a second semiconductor film formed of an oxide semiconductor. Then, the second semiconductor film is patterned to form the second semiconductor layer 16 a .

[0096] Next, a silicon oxide film (having a thickness of approximately 100 nm) is formed on the substrate surface on which the second semiconductor layer 16 a and the like are formed, for example, by plasma CVD, thereby forming the second gate insulating film 17 .

[0097] Then, for example, by sputtering, a molybdenum film (thickness of about 250 nm) is formed on the surface of the substrate on which the second gate insulating film 17 is formed, and a second metal film is formed. The second metal film is then patterned, as shown in FIG. Figure 7As shown, the second gate electrode 18a, the first relay electrode 18b, the second relay electrode 18c, the second scanning signal line 18d, the initialization power line 18i, etc. are formed. At this time, the surface of the second gate insulating film 17 exposed from the second gate electrode 18a, the first relay electrode 18b, the second relay electrode 18c, the second scanning signal line 18d, the initialization power line 18i, etc. is formed. Figure 7 As shown by the X mark in FIG, oxygen is absorbed by oxygen ashing during dry etching and oxygen adsorbed in the residue of the second metal film.

[0098] Then, for example, a film of InGaZnO4 (thickness of about 30 nm) is formed on the surface of the substrate on which the second gate 18a is formed, and a third semiconductor film composed of an oxide semiconductor is formed. Then, the third semiconductor film is patterned to form the third semiconductor layer 19a. At this time, the third semiconductor layer 19a is oxidized by diffusion of oxygen from the surface of the second gate insulating film 17 (see Figure 8 ).

[0099] Next, a silicon oxide film (thickness of about 100 nm) is formed on the surface of the substrate on which the third semiconductor layer 19a and the like are formed, for example, by plasma CVD. Figure 8 As shown, a third gate insulating film 20 is formed.

[0100] Then, for example, by sputtering, a single-layer film of a molybdenum film (thickness of about 250 nm) is formed on the surface of the substrate on which the third gate insulating film 20 is formed, or a stacked film of an aluminum film (thickness of about 300 nm) and a titanium film (thickness of about 50 nm) is stacked in sequence, or a stacked film of a titanium film (thickness of about 50 nm), an aluminum film (thickness of about 300 nm) and a titanium film (thickness of about 50 nm) is stacked in sequence to form a third metal film, and then the third metal film is patterned to form a third gate 21 a, etc.

[0101] Furthermore, a silicon oxide film (approximately 300 nm thick) and a silicon nitride film (approximately 150 nm thick) are sequentially deposited, for example, by plasma CVD, on the substrate surface where the third gate electrode 21 a and the like are formed, thereby forming the second interlayer insulating film 22. Furthermore, through heat treatment after the formation of the second interlayer insulating film 22, a portion of the second semiconductor layer 16 a and a portion of the third semiconductor layer 19 a are converted into conductors, thereby forming the third conductor region 16 aa, the fourth conductor region 16 ab, and the second channel region 16 ac in the second semiconductor layer 16 a, and the fifth conductor region 19 ab, and the third channel region 19 ac in the third semiconductor layer 19 a.

[0102] Then, on the surface of the substrate on which the second interlayer insulating film 22 is formed, the first gate insulating film 13, the first interlayer insulating film 15, the second gate insulating film 17, the third gate insulating film 20 and the second interlayer insulating film 22 are appropriately patterned to form the first contact hole Ha, the second contact hole Hb, the third contact hole Hc, the fourth contact hole Hd, the fifth contact hole He and the sixth contact hole Hf.

[0103] Moreover, after forming a fourth metal film on the surface of the substrate having the first contact hole Ha, etc., a titanium film (thickness of about 50 nm), an aluminum film (thickness of about 400 nm) and a titanium film (thickness of about 50 nm) are sequentially formed by, for example, a sputtering method, the fourth metal film is patterned to form a first terminal electrode 23a, a second terminal electrode 23b, a third terminal electrode 23c, a fourth terminal electrode 23d, a fifth terminal electrode 23e, a sixth terminal electrode 23f, a data signal line 23g, a high-level power line 23h, etc.

[0104] Finally, a polyimide-based photosensitive resin film (about 2µm thick) is coated on the surface of the substrate where the first terminal electrode 23a is formed, for example, by spin coating or slit coating, and the coated film is pre-baked, exposed, developed and post-baked to form a planarization film 24.

[0105] As described above, the TFT layer 30 a can be formed.

[0106] <Organic EL Element Layer Formation Step> On the planarizing film 24 of the TFT layer 30 a formed in the above-mentioned TFT layer forming step, a first electrode 31 , an edge mask 32 , an organic EL layer 33 and a second electrode 34 are formed by a known method to form an organic EL element layer 40 .

[0107] <Sealing Film Forming Step> First, on the surface of the substrate on which the organic EL element layer 40 is formed in the above-mentioned organic EL element layer forming process, a mask is used to form an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or an oxynitride silicon film by a plasma CVD method, thereby forming a first inorganic sealing film 41.

[0108] Next, an organic resin material such as acrylic resin is formed on the surface of the substrate on which the first inorganic sealing film 41 is formed, for example, by an inkjet method, to form the organic sealing film 42 .

[0109] Then, an inorganic insulating film such as silicon nitride, silicon oxide, or silicon oxynitride is formed on the substrate surface having the organic sealing film 42 by plasma CVD using a mask to form a second inorganic sealing film 43 , thereby forming a sealing film 45 .

[0110] Finally, after a protective sheet (not shown) is attached to the surface of the substrate on which the sealing film 45 is formed, the glass substrate is peeled off from the lower surface of the resin substrate 10 by irradiating the resin substrate 10 with laser light from the glass substrate side, and a protective sheet (not shown) is attached to the lower surface of the resin substrate 10 from which the glass substrate is peeled off.

[0111] As described above, the organic EL display device 100 a of this embodiment can be manufactured.

[0112] As described above, in the organic EL display device 100a of this embodiment, the threshold voltage compensation TFT 9b, which serves as the second TFT 9B, has a top-contact structure, while the initialization TFT 9a and the anode discharge TFT 9g, which serve as the third TFT 9c, have bottom-contact structures. In the initialization TFT 9a and the anode discharge TFT 9g, which have bottom-contact structures, oxygen is adsorbed on the surface of the second gate insulating film 17 during the formation of the first relay electrode 18b and the second relay electrode 18c, oxidizing the subsequently formed third semiconductor layer 19a. This facilitates the positive shift of the threshold voltages of the initialization TFT 9a and the anode discharge TFT 9g, ensuring sufficient margin for turning off the initialization TFT 9a and the anode discharge TFT 9g. Furthermore, when the emission control signal EM(n) is low, the emission control TFT 9f turns on, allowing current to flow to the organic EL element 35, causing it to emit light. However, if the anode discharge TFT 9g is not fully off at this time, the current intended for the organic EL element 35 flows to the initialization power supply line Vini. Consequently, the threshold voltage of the anode discharge TFT 9g also shifts toward the positive side, ensuring a sufficient turn-off margin. In contrast, in the threshold voltage compensation TFT 9b having a top-contact structure, the formation of the first relay electrode 18b and the second relay electrode 18c prevents oxidation of the second semiconductor layer 16a, allowing the threshold voltage of the second TFT 9b to shift toward the negative side. This allows the voltage of the data signal to be sufficiently written to the first gate electrode 14a of the drive TFT 9d. Therefore, in the organic EL display device 100a having a mixed structure including the first TFT 9A using polysilicon and the second and third TFTs 9B and 9C using oxide semiconductors, the characteristics of the second and third TFTs 9B and 9C using oxide semiconductors can be optimized.

[0113] Second Implementation Method Figures 9 to 12 A second embodiment of the display device of the present invention is shown. Figure 9 1 is a cross-sectional view of an organic EL display device 100b of this embodiment. Figures 1 to 8The same parts are denoted by the same reference numerals, and detailed description thereof is omitted.

[0114] In the above-mentioned first embodiment, an organic EL display device 100a including a TFT layer 30a is illustrated, in which the second semiconductor layer 16a is provided on the resin substrate 10 side and is closer to the second TFT 9B than the third semiconductor layer 19a of the third TFT 9C. However, in the present embodiment, an organic EL display device 100b including a TFT layer 30b in which the second semiconductor layer 16a of the second TFT 9B and the third semiconductor layer 19a of the third TFT 9C are provided on the same layer and made of the same material is illustrated.

[0115] The organic EL display device 100b is similar to the organic EL display device 100a of the first embodiment, and includes: a display area 50 in which multiple sub-pixels P are arranged in a matrix shape; a gate driver 60, an emission driver 70 and a source driver 80 arranged in a frame area around the display area 50.

[0116] Furthermore, a display control circuit 150 electrically connected to the gate driver 60 , the emission driver 70 , and the source driver 80 is provided outside the organic EL display device 100 b , similarly to the organic EL display device 100 a of the first embodiment.

[0117] In addition, if Figure 9 As shown, the organic EL display device 100b includes: a resin substrate 10 provided as a base substrate, a TFT layer 30b provided on the resin substrate 10, an organic EL element layer 40 as a light-emitting element layer provided on the TFT layer 30b, and a sealing film 45 provided on the organic EL element layer 40.

[0118] like Figure 9 As shown, the TFT layer 30b includes: a base coating film 11 arranged on a resin substrate 10; four first TFTs 9A, one second TFT 9B, two third TFTs 9C and one capacitor 9h arranged on the base coating film 11 for each sub-pixel P; and a planarizing film 24 arranged on each first TFT 9A, each second TFT 9B, each third TFT 9C and each capacitor 9h.

[0119] In the display area 50 of the TFT layer 30b, similar to the TFT layer 30a of the first embodiment, i first scanning signal lines PS(1) to PS(i), (i+1) second scanning signal lines NS(0) to NS(i), i light-emitting control lines EM(1) to EM(i), j data signal lines D(1) to D(j), a high-level power line ELVDD, a low-level power line ELVSS and an initialization power line Vini are provided.

[0120] like Figure 9 As shown, the first terminal electrode 23a and the second terminal electrode 23b of the first TFT 9A are electrically connected to the first conductor region 12aa and the second conductor region 12ab of the first semiconductor layer 12a via the first contact hole Ha and the second contact hole Hb formed in the stacked film of the first gate insulating film 13, the first interlayer insulating film 15, the common gate insulating film 25 and the second interlayer insulating film 22, respectively.

[0121] like Figure 9 As shown, the second TFT 9B includes a second semiconductor layer 16a provided on the first interlayer insulating film 15, a second gate electrode 18a provided on the second semiconductor layer 16a via a common gate insulating film 25, and a third terminal electrode 23c and a fourth terminal electrode 23d provided on the second interlayer insulating film 22 in a manner separated from each other. Figure 9 As shown, the second TFT 9B has a top contact structure, and its threshold value tends to shift toward the negative side. Furthermore, the common gate insulating film 25 is provided as a common inorganic insulating film that serves both as a second inorganic insulating film for electrically insulating the second semiconductor layer 16a from the second gate electrode 18a and as a third inorganic insulating film for electrically insulating the third semiconductor layer 19a from the third gate electrode 21a.

[0122] like Figure 9 As shown, the third terminal electrode 23c and the fourth terminal electrode 23d are electrically connected to the third conductor region 16aa and the fourth conductor region 16ab of the second semiconductor layer 16a via the third contact hole Hc and the fourth contact hole Hd formed in the stacked film of the common gate insulating film 25 and the second interlayer insulating film 22, respectively.

[0123] like Figure 9 As shown, the third TFT 9C includes: a third semiconductor layer 19a provided on the first interlayer insulating film 15; a first relay electrode 18b and a second relay electrode 18c provided on the resin substrate 10 side of the third semiconductor layer 19a in a manner separated from each other; a third gate electrode 21a provided on the third semiconductor layer 19a via a common gate insulating film 25; and a fifth terminal electrode 23e and a sixth terminal electrode 23f provided on the second interlayer insulating film 22 in a manner separated from each other. Figure 9 As shown, the third TFT 9C has a bottom contact structure. For example, in order to form the first relay electrode 18b and the second relay electrode 18c, oxygen ashing during patterning of the second metal film by dry etching and trace residues of the second metal film cause the oxide semiconductor to be oxidized, so that the threshold value tends to move toward the positive side.

[0124] like Figure 9As shown, the first relay electrode 18b and the second relay electrode 18c are provided on the first interlayer insulating film 15 and are provided in contact with the lower surfaces of the fifth conductor region 19aa and the sixth conductor region 19ab of the third semiconductor layer 19a, respectively.

[0125] like Figure 9 As shown, the fifth terminal electrode 23e and the sixth terminal electrode 23f are electrically connected to the first relay electrode 18b and the second relay electrode 18c respectively via a fifth contact hole He and a sixth contact hole Hf formed in the stacked film of the common gate insulating film 25 and the second interlayer insulating film 22.

[0126] In addition, in the TFT layer 30b, as shown in FIG. Figure 9 As shown, a primer film 11, a first semiconductor film serving as a first semiconductor layer 12a, etc., a first gate insulating film 13, a first metal film serving as a first gate electrode 14a, etc., a first interlayer insulating film 15, a second metal film serving as a first relay electrode 18b, etc., a second semiconductor film serving as a second semiconductor layer 16a, a third semiconductor layer 19a, etc., a common gate insulating film 25, a third metal film serving as a second gate electrode 18a, a third gate electrode 21a, etc., a second interlayer insulating film 22, a fourth metal film serving as a first terminal electrode 23a, etc., and a planarizing film 24 are sequentially stacked on the resin substrate 10.

[0127] In this embodiment, similar to the TFT layer 30a of the first embodiment, a write control TFT 9c, a drive TFT 9d, a power supply control TFT 9e, and a light emission control TFT 9f are provided as the first TFT 9A, a threshold voltage compensation TFT 9b is provided as the second TFT 9B, and an initialization TFT 9a and an anode discharge TFT 9g are provided as the third TFT 9C.

[0128] The organic EL display device 100 b configured as described above operates similarly to the organic EL display device 100 a of the first embodiment. In each sub-pixel P, the organic EL element 35 emits light at a luminance corresponding to the driving current, thereby displaying an image.

[0129] Next, the manufacturing method of the organic EL display device 100b of this embodiment is described. The manufacturing method of the organic EL display device 100b includes a TFT layer forming step, an organic EL element layer forming step, and a sealing film forming step. Figure 10 3 is a cross-sectional view showing a portion of the formation process of the TFT layer 30b. Figure 11 It means next Figure 10 A cross-sectional view of a portion of the formation process of the TFT layer 30b. Figure 12 It means next Figure 11Cross-sectional view of a part of the process of forming the TFT layer 30b.

[0130] <TFT Layer Formation Process> First, similar to the TFT layer formation process of the first embodiment described above, the first interlayer insulating film 15 is formed.

[0131] Next, for example, by sputtering, after forming a second metal film such as a molybdenum film (with a thickness of about 250 nm) on the surface of the substrate on which the first interlayer insulating film 15 is formed, the second metal film is patterned, as Figure 10 shown, to form the first relay electrode 18b and the second relay electrode 18c. At this time, on the surface of the first interlayer insulating film 15 exposed from the first relay electrode 18b and the second relay electrode 18c, as Figure 10 indicated by the x mark in, oxygen is adsorbed by oxygen ashing during dry etching using a chlorine-based gas or the like and the oxygen of the residue adsorbed on the second metal film.

[0132] Then, after forming a resist pattern R on the surface of the substrate on which the first relay electrode 18b etc. are formed so as to cover between the first relay electrode 18b and the second relay electrode 18c, as Figure 11 shown, a surface treatment T such as dry etching using a fluorine-based gas or the like and wet etching using hydrofluoric acid or the like is performed on the surface of the first interlayer insulating film 15 exposed from the resist pattern R, thereby partially removing the oxygen adsorbed on the surface of the first interlayer insulating film 15.

[0133] Furthermore, for example, by sputtering, after forming an indium gallium zinc oxide 4 (with a thickness of about 30 nm) etc. on the surface of the substrate on which the resist pattern R has been removed by the surface treatment T to form a second semiconductor film made of an oxide semiconductor, by patterning the second semiconductor film, the second semiconductor layer 16a and the third semiconductor layer 19a etc. are formed.

[0134] Next, for example, by plasma CVD method, a silicon oxide film (with a thickness of about 100 nm) is formed on the surface of the substrate on which the second semiconductor layer 16a etc. are formed, thereby as Figure 12 shown, forming the common gate insulating film 25.

[0135] Afterwards, a single-layer film of a molybdenum film (thickness of about 250 nm) is formed on the surface of the substrate on which the common gate insulating film 25 is formed, for example by a sputtering method, or a stacked film of an aluminum film (thickness of about 300 nm) and a titanium film (thickness of about 50 nm) is stacked in sequence, or a stacked film of a titanium film (thickness of about 50 nm), an aluminum film (thickness of about 300 nm), and a titanium film (thickness of about 50 nm) is stacked in sequence, etc. to form a third metal film, and then the third metal film is patterned to form a second gate 18a, a second scanning signal line 18d, an initialization power line 18i, a third gate 21a, etc.

[0136] Furthermore, a silicon oxide film (approximately 300 nm thick) and a silicon nitride film (approximately 150 nm thick) are sequentially deposited, for example, by plasma CVD, on the substrate surface on which the second gate electrode 18 a and the like are formed, thereby forming a second interlayer insulating film 22. Furthermore, through heat treatment after the formation of the second interlayer insulating film 22, a portion of the second semiconductor layer 16 a and a portion of the third semiconductor layer 19 a are converted into conductors, thereby forming a third conductor region 16 aa, a fourth conductor region 16 ab, and a second channel region 16 ac in the second semiconductor layer 16 a, and forming a fifth conductor region 19 aa, a sixth conductor region 19 ab, and a third channel region 19 ac in the third semiconductor layer 19 a.

[0137] Then, on the surface of the substrate on which the second interlayer insulating film 22 is formed, the first gate insulating film 13, the first interlayer insulating film 15, the common gate insulating film 25 and the second interlayer insulating film 22 are appropriately patterned to form the first contact hole Ha, the second contact hole Hb, the third contact hole Hc, the fourth contact hole Hd, the fifth contact hole He and the sixth contact hole Hf.

[0138] Moreover, after forming a fourth metal film by, for example, forming a titanium film (thickness of about 50 nm), an aluminum film (thickness of about 400 nm) and a titanium film (thickness of about 50 nm) in sequence on the surface of the substrate where the first contact hole Ha is formed, the fourth metal film is patterned to form a first terminal electrode 23a, a second terminal electrode 23b, a third terminal electrode 23c, a fourth terminal electrode 23d, a fifth terminal electrode 23e, a sixth terminal electrode 23f, a data signal line 23g, a high-level power supply line 23h, etc.

[0139] Finally, a polyimide-based photosensitive resin film (about 2µm thick) is coated on the surface of the substrate on which the first terminal electrode 23a is formed, for example, by spin coating or slit coating, and then the coated film is pre-baked, exposed, developed and post-baked to form a planarization film 24.

[0140] As described above, the TFT layer 30 b can be formed.

[0141] Thereafter, similarly to the first embodiment, the organic EL element layer forming step and the sealing film forming step are performed, thereby manufacturing the organic EL display device 100 b of this embodiment.

[0142] As described above, in the organic EL display device 100b of this embodiment, the threshold voltage compensation TFT 9b, which serves as the second TFT 9B, has a top-contact structure, while the initialization TFT 9a and the anode discharge TFT 9g, which serve as the third TFT 9c, have a bottom-contact structure. In the initialization TFT 9a and the anode discharge TFT 9g, which have a bottom-contact structure, oxygen is adsorbed on the surface of the first interlayer insulating film 15 during the formation of the first relay electrode 18b and the second relay electrode 18c, causing oxidation of the third semiconductor layer 19a formed subsequently. This facilitates the positive shift of the threshold voltages of the initialization TFT 9a and the anode discharge TFT 9g, ensuring sufficient margin for turning off the initialization TFT 9a and the anode discharge TFT 9g. Furthermore, when the emission control signal EM(n) is low, the emission control TFT 9f turns on, allowing current to flow to the organic EL element 35, causing it to emit light. However, if the anode discharge TFT 9g is not fully off at this time, the current intended for the organic EL element 35 flows to the initialization power supply line Vini. Consequently, the threshold voltage of the anode discharge TFT 9g also shifts positively, ensuring a sufficient turn-off margin. In contrast, in the threshold voltage compensation TFT 9b with a top contact structure, although oxygen temporarily adsorbs on the surface of the first interlayer insulating film 15 during the formation of the first relay electrode 18b and the second relay electrode 18c, oxygen is removed from the surface of the first interlayer insulating film 15 before the second semiconductor layer 16a is formed, preventing oxidation of the second semiconductor layer 16a. This allows the threshold voltage of the second TFT 9b to shift negatively, allowing the voltage of the data signal to be fully written to the first gate electrode 14a of the drive TFT 9d. Therefore, in the organic EL display device 100b having a mixed structure including the first TFT 9A using polysilicon and the second and third TFTs 9B and 9C using oxide semiconductors, the characteristics of the second and third TFTs 9B and 9C using oxide semiconductors can be optimized.

[0143] Third Implementation Method Figures 13 to 17 A third embodiment of the display device of the present invention is shown. Figure 13 2 is a cross-sectional view of an organic EL display device 100 c according to this embodiment.

[0144] In the above-mentioned first embodiment, the organic EL display device 100a is used as an example for description. The organic EL display device 100a includes a TFT layer 30a, in which the second semiconductor layer 16a of the second TFT 9B is arranged on a side closer to the resin substrate 10 than the third semiconductor layer 19a of the third TFT 9C. However, in this embodiment, the organic EL display device 100c is used as an example for description. The organic EL display device 100c includes a TFT layer 30c, in which the third semiconductor layer 19a of the third TFT 9C is arranged on a side closer to the resin substrate 10 than the second semiconductor layer 16a of the second TFT 9B.

[0145] The organic EL display device 100c, similar to the organic EL display device 100a of the first embodiment, includes a display area 50 in which a plurality of sub-pixels P are arranged in a matrix; and a gate driver 60, an emission driver 70, and a source driver 80 provided in a frame region surrounding the display area 50. Furthermore, similar to the organic EL display device 100a of the first embodiment, a display control circuit 150 electrically connected to the gate driver 60, the emission driver 70, and the source driver 80 is provided outside the organic EL display device 100c.

[0146] In addition, if Figure 13 As shown, the organic EL display device 100c includes: a resin substrate 10 provided as a base substrate, a TFT layer 30c provided on the resin substrate 10, an organic EL element layer 40 provided as a light-emitting element layer on the TFT layer 30c, and a sealing film 45 provided on the organic EL element layer 40.

[0147] like Figure 13 As shown, the TFT layer 30c includes: a base coating film 11 arranged on a resin substrate 10; four first TFTs 9A, one second TFT 9B, two third TFTs 9C and one capacitor 9h arranged on the base coating film 11 for each sub-pixel P; and a planarizing film 24 arranged on each first TFT 9A, each second TFT 9B, each third TFT 9C and each capacitor 9h.

[0148] Similar to the TFT layer 30a of the first embodiment, i first scanning signal lines PS(1) to PS(i), (i+1) second scanning signal lines NS(0) to NS(i), i light emitting control lines EM(1) to EM(i), j data signal lines D(1) to D(j), a high-level power line ELVDD, a low-level power line ELVSS and an initialization power line Vini are provided in the display area 50 of the TFT layer 30c.

[0149] like Figure 13As shown, the first terminal electrode 23a and the second terminal electrode 23b of the first TFT 9A are electrically connected to the first conductor region 12aa and the second conductor region 12ab of the first semiconductor layer 12a via the first contact hole Ha and the second contact hole Hb formed in the stacked film of the first gate insulating film 13, the first interlayer insulating film 15, the third gate insulating film 20, the second gate insulating film 17 and the second interlayer insulating film 22, respectively.

[0150] like Figure 13 As shown, the second TFT 9B includes: a second semiconductor layer 16a provided on the third gate insulating film 20; a second gate electrode 18a provided on the second semiconductor layer 16a via the second gate insulating film 17; and a third terminal electrode 23c and a fourth terminal electrode 23d provided on the second interlayer insulating film 22 in a manner separated from each other. Figure 13 As shown, the second TFT 9B has a top contact structure, and the threshold value tends to move toward the negative side.

[0151] like Figure 13 As shown, the third terminal electrode 23c and the fourth terminal electrode 23d are electrically connected to the third conductor region 16aa and the fourth conductor region 16ab of the second semiconductor layer 16a via the third contact hole Hc and the fourth contact hole Hd formed in the stacked film of the second gate insulating film 17 and the second interlayer insulating film 22, respectively.

[0152] like Figure 13 As shown, the third TFT 9C includes: a third semiconductor layer 19a provided on the first interlayer insulating film 15; a first relay electrode 18b and a second relay electrode 18c provided on the resin substrate 10 side of the third semiconductor layer 19a in a manner separated from each other; a third gate electrode 21a provided on the third semiconductor layer 19a via a third gate insulating film 20; and a fifth terminal electrode 23e and a sixth terminal electrode 23f provided on the second interlayer insulating film 22 in a manner separated from each other. Figure 13 As shown, the third TFT 9C has a bottom contact structure. For example, in order to form the first relay electrode 18b and the second relay electrode 18c, oxygen ashing during patterning of the second metal film by dry etching and trace residues of the second metal film cause the oxide semiconductor to be oxidized, so that the threshold value tends to move toward the positive side.

[0153] like Figure 13 As shown, the first relay electrode 18b and the second relay electrode 18c are provided on the first interlayer insulating film 15 and are provided in contact with the lower surfaces of the fifth conductor region 19aa and the sixth conductor region 19ab of the third semiconductor layer 19a, respectively.

[0154] like Figure 13As shown, the fifth terminal electrode 23e and the sixth terminal electrode 23f are electrically connected to the first relay electrode 18b and the second relay electrode 18c respectively via the fifth contact hole He and the sixth contact hole Hf formed in the stacked film of the third gate insulating film 20, the second gate insulating film 17 and the second interlayer insulating film 22.

[0155] In addition, in the TFT layer 30c, as shown in FIG. Figure 13 As shown, a primer film 11, a first semiconductor film serving as a first semiconductor layer 12a, etc., a first gate insulating film 13, a first metal film serving as a first gate electrode 14a, etc., a first interlayer insulating film 15, a second metal film serving as a first relay electrode 18b, etc., a third semiconductor film serving as a third semiconductor layer 19a, etc., a third gate insulating film 20, a third metal film serving as a third gate electrode 21a, etc., a second semiconductor film serving as a second semiconductor layer 16a, etc., a second gate insulating film 17, a fourth metal film serving as a second gate electrode 18a, etc., a second interlayer insulating film 22, a fifth metal film serving as a first terminal electrode 23a, etc., and a planarizing film 24 are sequentially stacked on the resin substrate 10.

[0156] In this embodiment, similar to the TFT layer 30a of the first embodiment, a write control TFT 9c, a drive TFT 9d, a power supply control TFT 9e, and a light emission control TFT 9f are provided as the first TFT 9A, a threshold voltage compensation TFT 9b is provided as the second TFT 9B, and an initialization TFT 9a and an anode discharge TFT 9g are provided as the third TFT 9C.

[0157] The organic EL display device 100 c configured as described above operates in the same manner as the organic EL display device 100 a of the first embodiment. In each sub-pixel P, the organic EL element 35 emits light at a luminance corresponding to the driving current, thereby displaying an image.

[0158] Next, the manufacturing method of the organic EL display device 100c of this embodiment will be described. The manufacturing method of the organic EL display device 100c includes a TFT layer forming step, an organic EL element layer forming step, and a sealing film forming step. Figure 14 3 is a cross-sectional view showing a portion of the formation process of the TFT layer 30c. Figure 15 It means next Figure 14 A cross-sectional view of a portion of the formation process of the TFT layer 30c. Figure 16 It means next Figure 15 A cross-sectional view of a portion of the formation process of the TFT layer 30c. Figure 17 It means next Figure 16 A cross-sectional view showing a portion of the process of forming the TFT layer 30c.

[0159] <TFT Layer Formation Process> First, in the same manner as the TFT layer formation process of the first embodiment described above, the first interlayer insulating film 15 is formed.

[0160] Next, for example, by sputtering, after forming a molybdenum film (with a thickness of about 250 nm) or the like on the surface of the substrate on which the first interlayer insulating film 15 is formed to form the second metal film, the second metal film is patterned, as Figure 14 shown, to form the first relay electrode 18b and the second relay electrode 18c. At this time, on the surface of the first interlayer insulating film 15 exposed from the first relay electrode 18b and the second relay electrode 18c, as Figure 14 indicated by the x mark in, oxygen is adsorbed by oxygen ashing during dry etching using a chlorine-based gas or the like and the oxygen of the residue adsorbed on the second metal film.

[0161] Then, for example, by sputtering, after forming an InGaZnO4 film (with a thickness of about 30 nm) or the like on the surface of the substrate on which the first relay electrode 18b and the like are formed to form the third semiconductor film made of an oxide semiconductor, the third semiconductor film is patterned to form the third semiconductor layer 19a and the like. At this time, the third semiconductor layer 19a is oxidized by the diffusion of oxygen on the surface of the first interlayer insulating film 15 (refer to Figure 15 ).

[0162] Furthermore, for example, by plasma CVD, a silicon oxide film (with a thickness of about 100 nm) is formed on the surface of the substrate on which the third semiconductor layer 19a and the like are formed, thereby forming the third gate insulating film 20.

[0163] Next, for example, by sputtering, after forming a molybdenum film (with a thickness of about 250 nm) or the like on the surface of the substrate on which the third gate insulating film 20 is formed to form the third metal film, the third metal film is patterned, as Figure 15 shown, to form the third gate 21a and the like. At this time, on the surface of the third gate insulating film 20 exposed from the third gate 21a, as Figure 15 indicated by the x mark in, oxygen is adsorbed by oxygen ashing during dry etching using a chlorine-based gas or the like and the oxygen of the residue adsorbed on the third metal film.

[0164] Then, after forming a resist pattern R so as to cover the third gate 21a, as Figure 16 shown, surface treatment T such as dry etching using a fluorine-based gas or the like and wet etching using hydrofluoric acid or the like is performed on the surface of the third gate insulating film 20 exposed from the resist pattern R, thereby partially removing the oxygen adsorbed on the surface of the third gate insulating film 20.

[0165] Furthermore, for example, by sputtering, a second semiconductor film composed of an oxide semiconductor is formed by forming a film of InGaZnO4 (thickness of about 30 nm) on the surface of the substrate after surface treatment T is performed to remove the resist pattern R, and then patterning the second semiconductor film is performed, such as Figure 17 As shown, a second semiconductor layer 16a and the like are formed.

[0166] Next, a silicon oxide film (having a thickness of approximately 100 nm) is formed on the substrate surface on which the second semiconductor layer 16 a and the like are formed, for example, by plasma CVD, thereby forming the second gate insulating film 17 .

[0167] Afterwards, a fourth metal film is formed by forming a single-layer film of molybdenum film (thickness of about 250 nm) on the surface of the substrate on which the second gate insulating film 17 is formed, for example, by using a sputtering method, or a stacked film of aluminum film (thickness of about 300 nm) and titanium film (thickness of about 50 nm) stacked in sequence, or a stacked film of titanium film (thickness of about 50 nm), aluminum film (thickness of about 300 nm) and titanium film (thickness of about 50 nm) stacked in sequence, and then the fourth metal film is patterned to form the second gate 18a, the second scanning signal line 18d, the initialization power line 18i, the third gate 21a, etc.

[0168] Furthermore, a silicon oxide film (approximately 300 nm thick) and a silicon nitride film (approximately 150 nm thick) are sequentially deposited, for example, by plasma CVD, on the substrate surface on which the second gate electrode 18 a and the like are formed, thereby forming a second interlayer insulating film 22. Furthermore, through heat treatment after the formation of the second interlayer insulating film 22, a portion of the second semiconductor layer 16 a and a portion of the third semiconductor layer 19 a are converted into conductors, thereby forming a third conductor region 16 aa, a fourth conductor region 16 ab, and a second channel region 16 ac in the second semiconductor layer 16 a, and forming a fifth conductor region 19 aa, a sixth conductor region 19 ab, and a third channel region 19 ac in the third semiconductor layer 19 a.

[0169] Then, on the surface of the substrate on which the second interlayer insulating film 22 is formed, the first gate insulating film 13, the first interlayer insulating film 15, the third gate insulating film 20, the second gate insulating film 17 and the second interlayer insulating film 22 are appropriately patterned to form the first contact hole Ha, the second contact hole Hb, the third contact hole Hc, the fourth contact hole Hd, the fifth contact hole He and the sixth contact hole Hf.

[0170] Moreover, after forming a fifth metal film by, for example, forming a titanium film (thickness of about 50 nm), an aluminum film (thickness of about 400 nm) and a titanium film (thickness of about 50 nm) in sequence on the surface of the substrate where the first contact hole Ha is formed, the fifth metal film is patterned to form a first terminal electrode 23a, a second terminal electrode 23b, a third terminal electrode 23c, a fourth terminal electrode 23d, a fifth terminal electrode 23e, a sixth terminal electrode 23f, a data signal line 23g, a high-level power supply line 23h, etc.

[0171] Finally, a polyimide-based photosensitive resin film (about 2µm thick) is coated on the surface of the substrate where the first terminal electrode 23a is formed, for example, by spin coating or slit coating, and then the coated film is pre-baked, exposed, developed and post-baked to form a planarization film 24.

[0172] As described above, the TFT layer 30 c can be formed.

[0173] Thereafter, similarly to the first embodiment, the organic EL element layer forming step and the sealing film forming step are performed, thereby manufacturing the organic EL display device 100 c of this embodiment.

[0174] As described above, in the organic EL display device 100c of this embodiment, the threshold voltage compensation TFT 9b provided as the second TFT 9B has a top contact structure, while the initialization TFT 9a and the anode discharge TFT 9g provided as the third TFT 9c have a bottom contact structure. In the initialization TFT 9a and the anode discharge TFT 9g having a bottom contact structure, oxygen is adsorbed on the surface of the first interlayer insulating film 15 during the formation of the first relay electrode 18b and the second relay electrode 18c, causing oxidation of the third semiconductor layer 19a formed subsequently. This facilitates the positive shift of the threshold voltages of the initialization TFT 9a and the anode discharge TFT 9g, ensuring sufficient margin for turning off the initialization TFT 9a and the anode discharge TFT 9g. Furthermore, when the emission control signal EM(n) is low, the emission control TFT 9f turns on, allowing current to flow to the organic EL element 35, causing it to emit light. However, if the anode discharge TFT 9g is not fully turned off at this time, the current intended for the organic EL element 35 flows to the initialization power supply line Vini. Consequently, the threshold voltage of the anode discharge TFT 9g also shifts positively, ensuring a sufficient turn-off margin. In contrast, in the threshold voltage compensation TFT 9b with a top contact structure, oxygen is temporarily adsorbed on the surface of the third gate insulating film 20 during the formation of the third gate electrode 21a. However, this oxygen is removed from the surface of the third gate insulating film 20 before the second semiconductor layer 16a is formed. Consequently, oxidation of the second semiconductor layer 16a is prevented, and the threshold voltage of the second TFT 9b tends to shift negatively. This allows the voltage of the data signal to be sufficiently written to the first gate electrode 14a of the driver TFT 9d. Therefore, in the organic EL display device 100c having a mixed structure including the first TFT 9A using polysilicon and the second and third TFTs 9B and 9C using oxide semiconductors, the characteristics of the second and third TFTs 9B and 9C using oxide semiconductors can be optimized.

[0175] Other Implementation Methods In the above embodiments, an organic EL layer having a five-layer stacked structure of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer is exemplified. However, the organic EL layer may also have a three-layer stacked structure of, for example, a hole injection layer serving as a hole transport layer, a light-emitting layer, and an electron transport layer serving as an electron injection layer.

[0176] In addition, in the above-mentioned embodiments, an organic EL display device in which the first electrode serves as an anode and the second electrode serves as a cathode is exemplified, but the present invention can also be applied to an organic EL display device in which the stacked structure of the organic EL layer is reversed, the first electrode serves as a cathode, and the second electrode serves as an anode.

[0177] In addition, in the above embodiments, an organic EL display device is cited as an example for description as a display device, but the present invention can be applied to a display device having a plurality of light-emitting elements driven by current, for example, a display device having a light-emitting element using a layer containing quantum dots, namely a QLED (Quantum-dot light emitting diode).

[0178] Industrial applicability As described above, the present invention is useful for a flexible display device.

[0179] Description of Reference Numerals Ha: first contact hole; Hb: second contact hole; Hc: third contact hole; Hd: fourth contact hole; He: fifth contact hole; Hf: sixth contact hole; P: sub-pixel; 9A: first TFT (first thin film transistor); 9B: second TFT (second thin film transistor); 9C: third TFT (third thin film transistor); 9a: Initializing TFT (initializing thin film transistor, third thin film transistor); 9b: threshold voltage compensation TFT (threshold voltage compensation thin film transistor, second thin film transistor); 9c: write control TFT (write control thin film transistor, first thin film transistor); 9d: driving TFT (driving thin film transistor, first thin film transistor); 9e: power supply control TFT (power supply control thin film transistor, first thin film transistor); 9f: light-emitting control TFT (light-emitting control thin film transistor, first thin film transistor); 9g: anode discharge TFT (anode discharge thin film transistor, third thin film transistor); 10: Resin substrate (base substrate); 12a: first semiconductor layer; 12aa: first conductor region; 12ab: second conductor region; 12ac: first channel region; 13: first gate insulating film (first inorganic insulating film); 14a: first gate; 15: first interlayer insulating film (fourth inorganic insulating film); 16a: second semiconductor layer; 16aa: third conductor region; 16ab: fourth conductor region; 16ac: second channel region; 17: second gate insulating film (second inorganic insulating film); 18a: second gate; 18b: first relay electrode; 18c: second relay electrode; 19a: third semiconductor layer; 19aa: fifth conductor region; 19ab: sixth conductor region; 19ac: third channel region; 20: a third gate insulating film (a third inorganic insulating film); 21a: third gate; 22: second interlayer insulating film (fifth inorganic insulating film); 23a: first terminal electrode; 23b: second terminal electrode; 23c: third terminal electrode; 23d: fourth terminal electrode; 25: shared gate insulating film (shared inorganic insulating film); 30a, 30b, 30c: TFT layer (thin film transistor layer); 35: Organic EL elements (organic electroluminescent elements, light-emitting elements); 40: organic EL element layer (light-emitting element layer); 45: Sealing film; 50: display area; 100a, 100b, 100c: organic EL display devices.

Claims

1. A display device, characterized in that: It has: base substrate; as well as a thin film transistor layer disposed on the base substrate, In the thin film transistor layer, a first thin film transistor, a second thin film transistor, and a third thin film transistor are provided for each sub-pixel constituting the display area, wherein the first thin film transistor has a first semiconductor layer formed of polycrystalline silicon, the second thin film transistor has a second semiconductor layer formed of an oxide semiconductor, and the third thin film transistor has a third semiconductor layer formed of an oxide semiconductor. The first thin film transistor comprises: a first semiconductor layer defining a first conductor region and a second conductor region in a mutually separated manner, and defining a first channel region between the first conductor region and the second conductor region; a first gate disposed on the first semiconductor layer so as to overlap with the first channel region via a first inorganic insulating film; as well as a first terminal electrode and a second terminal electrode, the first terminal electrode and the second terminal electrode being provided on a side of the base substrate opposite to the first gate electrode in a manner separated from each other and electrically connected to the first conductor region and the second conductor region, respectively; The second thin film transistor comprises: The second semiconductor layer defines a third conductor region and a fourth conductor region in a mutually separated manner, and defines a second channel region between the third conductor region and the fourth conductor region; a second gate disposed on the second semiconductor layer so as to overlap with the second channel region via a second inorganic insulating film; as well as a third terminal electrode and a fourth terminal electrode, the third terminal electrode and the fourth terminal electrode being provided on a side of the base substrate opposite to the second gate electrode in a manner separated from each other and electrically connected to the third conductor region and the fourth conductor region, respectively; The third thin film transistor comprises: a third semiconductor layer defining a fifth conductor region and a sixth conductor region in a manner separated from each other, and defining a third channel region between the fifth conductor region and the sixth conductor region; a first relay electrode and a second relay electrode, the first relay electrode and the second relay electrode being provided on the base substrate side of the third semiconductor layer and being arranged in contact with the fifth conductor region and the sixth conductor region, respectively; a third gate electrode provided on the third semiconductor layer so as to overlap with the third channel region via a third inorganic insulating film; and A fifth terminal electrode and a sixth terminal electrode are provided in a mutually separated manner on a side of the third gate opposite to the base substrate and are electrically connected to the first relay electrode and the second relay electrode, respectively.

2. The display device according to claim 1, wherein As the first thin film transistor, a write control thin film transistor, a drive thin film transistor, a power supply control thin film transistor and a light emission control thin film transistor are provided. As the second thin film transistor, a threshold voltage compensation thin film transistor is provided. As the third thin film transistor, an initialization thin film transistor and an anode discharge thin film transistor are provided.

3. The display device according to claim 1 or 2, characterized in that A fourth inorganic insulating film is provided so as to cover the first gate. The second semiconductor layer is provided on the fourth inorganic insulating film, The third inorganic insulating film is provided so as to cover the second gate. The first relay electrode and the second relay electrode are provided on the second inorganic insulating film. A fifth inorganic insulating film is provided so as to cover the third gate electrode.

4. The display device according to claim 3, wherein: The first terminal electrode and the second terminal electrode are electrically connected to the first conductor region and the second conductor region respectively via a first contact hole and a second contact hole formed in the stacked film of the first inorganic insulating film, the fourth inorganic insulating film, the second inorganic insulating film, the third inorganic insulating film, and the fifth inorganic insulating film. The third terminal electrode and the fourth terminal electrode are electrically connected to the third conductor region and the fourth conductor region respectively via a third contact hole and a fourth contact hole formed in the stacked film of the second inorganic insulating film, the third inorganic insulating film, and the fifth inorganic insulating film. The fifth terminal electrode and the sixth terminal electrode are electrically connected to the first relay electrode and the second relay electrode, respectively, via a fifth contact hole and a sixth contact hole formed in the stacked film of the third inorganic insulating film and the fifth inorganic insulating film.

5. The display device according to claim 1 or 2, characterized in that A fourth inorganic insulating film is provided so as to cover the first gate. The second semiconductor layer, the first relay electrode, and the second relay electrode are provided on the fourth inorganic insulating film. The second inorganic insulating film and the third inorganic insulating film are provided as a common inorganic insulating film. A fifth inorganic insulating film is provided so as to cover the second gate electrode and the third gate electrode.

6. The display device according to claim 5, wherein: The first terminal electrode and the second terminal electrode are electrically connected to the first conductor region and the second conductor region respectively via a first contact hole and a second contact hole formed in the stacked film of the first inorganic insulating film, the fourth inorganic insulating film, the common inorganic insulating film, and the fifth inorganic insulating film. The third terminal electrode and the fourth terminal electrode are electrically connected to the third conductor region and the fourth conductor region respectively through a third contact hole and a fourth contact hole formed in the stacked film of the common inorganic insulating film and the fifth inorganic insulating film. The fifth terminal electrode and the sixth terminal electrode are electrically connected to the first relay electrode and the second relay electrode, respectively, via a fifth contact hole and a sixth contact hole formed in the stacked film of the common inorganic insulating film and the fifth inorganic insulating film.

7. The display device according to claim 1 or 2, characterized in that: A fourth inorganic insulating film is provided so as to cover the first gate. The first relay electrode and the second relay electrode are provided on the fourth inorganic insulating film, The second semiconductor layer is provided on the third inorganic insulating film, The second inorganic insulating film is provided so as to cover the third gate. A fifth inorganic insulating film is provided so as to cover the second gate electrode.

8. The display device according to claim 7, wherein: The first terminal electrode and the second terminal electrode are electrically connected to the first conductor region and the second conductor region respectively via a first contact hole and a second contact hole formed in the stacked film of the first inorganic insulating film, the fourth inorganic insulating film, the third inorganic insulating film, the second inorganic insulating film, and the fifth inorganic insulating film. The third terminal electrode and the fourth terminal electrode are electrically connected to the third conductor region and the fourth conductor region respectively through a third contact hole and a fourth contact hole formed in the stacked film of the second inorganic insulating film and the fifth inorganic insulating film; The fifth terminal electrode and the sixth terminal electrode are electrically connected to the first relay electrode and the second relay electrode, respectively, via a fifth contact hole and a sixth contact hole formed in the stacked film of the third inorganic insulating film, the second inorganic insulating film, and the fifth inorganic insulating film.

9. The display device according to any one of claims 1 to 8, wherein: The display device comprises: a light emitting element layer, which is provided on the thin film transistor layer and has a plurality of light emitting elements arranged corresponding to a plurality of sub-pixels constituting the display area; and A sealing film is provided on the light emitting element layer.

10. The display device according to claim 9, wherein Each of the light-emitting elements is an organic electroluminescent element.

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