Internal spacer pad for gate-all-around devices

Abstract

Semiconductor devices (e.g., gate-around (GAA) devices), process tools for manufacturing GAA devices, and methods of manufacturing GAA devices, as well as internal spacer pads and internal spacers for GAA devices are described. The method includes forming an internal spacer liner within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure has a plurality of recessed layers of semiconductor material (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)), the plurality of recessed layers of semiconductor material and the corresponding plurality of channel layers being alternately arranged in a plurality of stacked pairs. The internal spacer pad includes a crystalline silicon-containing pad formed by a selective epitaxial growth (SEG) process. The crystalline silicon-containing liner may be doped with a dopant (e.g., a p-type dopant or an n-type dopant). One or more operations of the methods described herein are performed in situ in an integrated processing tool system.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to semiconductor devices. More particularly, embodiments of the present disclosure relate to gate-all-around (GAA) devices and methods of forming GAA devices with internal spacer liners. Background Art

[0002] Transistors are key components in most integrated circuits. Because a transistor's drive current, and therefore its speed, is proportional to its gate width, faster transistors typically require larger gate widths. Consequently, there's a trade-off between transistor size and speed. FinFETs (fin-shaped field-effect transistors) have been developed to address the conflicting goals of maximum drive current and minimum transistor size. FinFETs, characterized by a fin-shaped channel region, significantly increase transistor size without significantly increasing the transistor's footprint and are now used in many integrated circuits. However, finFETs also have their drawbacks.

[0003] As the feature size of transistor devices continues to shrink to achieve greater circuit density and higher performance, it is necessary to improve the device structure of transistors to improve electrostatic coupling and reduce negative effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field-effect transistor (FinFET) structures, and horizontal gate-all-around (hGAA) structures. The hGAA device structure consists of several lattice-matched channels that are suspended in a stacked configuration and connected by source / drain regions. The hGAA structure provides good electrostatic control and can find widespread application in complementary metal oxide semiconductor (CMOS) wafer manufacturing.

[0004] One of the challenges of CMOS wafer manufacturing (and GAA formation) is reducing parasitic capacitance. The selective etching process used to form the indentations / cavities for internal spacers is extremely challenging. Furthermore, this selective etching process inevitably results in silicon (Si) loss at the corners of the indentations / cavities within the semiconductor material layer. This silicon (Si) loss reduces the current path and, if the corner silicon (Si) loss is not properly designed, can even lead to current crowding. Furthermore, DC (Direct Current) performance degrades significantly with silicon (Si) loss. The thinner the channel layer, the greater the degradation in DC performance.

[0005] Therefore, there is a need for methods to reduce the amount of silicon (Si) loss in gate-all-around (GAA) devices. Summary of the Invention

[0006] One or more embodiments of the present disclosure relate to a method for manufacturing an electronic device. In some embodiments, the method includes forming a crystalline silicon-containing liner within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure includes a plurality of recessed semiconductor material layers and a corresponding plurality of channel layers, the plurality of recessed semiconductor material layers and the corresponding plurality of channel layers being alternately arranged into a plurality of stacked pairs. In some embodiments, the crystalline silicon-containing liner is formed along the recessed semiconductor material layers and the corresponding plurality of channel layers by a selective epitaxial growth (SEG) process. The method includes forming an internal spacer directly on the crystalline silicon-containing liner, the internal spacer being adjacent to a source region and a drain region.

[0007] Additional embodiments of the present disclosure relate to a method for manufacturing an electronic device. In some embodiments, the method includes forming a crystalline silicon-containing liner within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure includes a plurality of recessed semiconductor material layers and corresponding plurality of channel layers, the plurality of recessed semiconductor material layers and the corresponding plurality of channel layers being alternately arranged into a plurality of stacked pairs. In some embodiments, the crystalline silicon-containing liner is formed along the recessed semiconductor material layers and the corresponding plurality of channel layers by a selective epitaxial growth (SEG) process. The method further includes forming an internal spacer directly on the crystalline silicon-containing liner, the internal spacer being adjacent to a source region and a drain region; etching a portion of the internal spacer; and removing the replacement metal gate and the recessed semiconductor material layers from the semiconductor substrate, and then etching an inner sidewall portion of the crystalline silicon-containing liner.

[0008] Further embodiments of the present disclosure relate to a processing tool. In some embodiments, the processing tool includes: a central transfer station including a robot configured to move a semiconductor substrate; a plurality of process stations, each process station coupled to the central transfer station and providing a processing area separate from a processing area of an adjacent process station, the plurality of process stations including a pre-clean chamber, a selective epitaxial growth (SEG) chamber, and a low-κ silicon oxide (SiOC) dielectric chemical vapor deposition (CVD) chamber; and a controller coupled to the central transfer station and the plurality of process stations. The controller is configured to activate the robot to move the semiconductor substrate between the process stations and control a process cycle for forming a liner comprising crystalline silicon for a gate-all-around (GAA) device. The process cycle includes: pre-cleaning the semiconductor substrate; forming the crystalline silicon-containing liner within a superlattice structure formed on the top surface of the semiconductor substrate by a selective epitaxial growth (SEG) process, the superlattice structure including a plurality of recessed semiconductor material layers and corresponding plurality of channel layers, the plurality of recessed semiconductor material layers and the corresponding plurality of channel layers being alternately arranged into a plurality of stacked pairs, the semiconductor material layers including silicon germanium (SiGe), and the channel layers including silicon (Si), the crystalline silicon-containing liner being formed along the recessed semiconductor material layers and the corresponding plurality of channel layers; and forming an internal spacer directly on the crystalline silicon-containing liner, the internal spacer being adjacent to the source region and the drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to enable a detailed understanding of the above-described features of the present disclosure, a more detailed description of the disclosure, briefly summarized above, may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings depict only typical embodiments of the present disclosure and are therefore not to be considered limiting of the scope of the present disclosure, as the disclosure admits to other equally effective embodiments.

[0010] Figure 1 A process flow diagram illustrating a method of forming an electronic device according to one or more embodiments;

[0011] Figure 2A shows a schematic cross-sectional view of an electronic device according to one or more embodiments;

[0012] Figure 2B shows a schematic cross-sectional view of an electronic device according to one or more embodiments;

[0013] Figure 2C shows a schematic cross-sectional view of an electronic device according to one or more embodiments;

[0014] Figure 2Dshows a schematic cross-sectional view of an electronic device according to one or more embodiments;

[0015] Figure 2E shows a schematic cross-sectional view of an electronic device according to one or more embodiments;

[0016] Figure 2F shows a schematic cross-sectional view of an electronic device according to one or more embodiments;

[0017] Figure 2G shows a schematic cross-sectional view of an electronic device according to one or more embodiments;

[0018] Figure 2H shows a schematic cross-sectional view of an electronic device according to one or more embodiments;

[0019] Figure 2I shows a schematic cross-sectional view of an electronic device according to one or more embodiments;

[0020] Figure 2J shows a schematic cross-sectional view of an electronic device according to one or more embodiments;

[0021] Figure 2K shows a schematic cross-sectional view of an electronic device according to one or more embodiments;

[0022] Figure 2L shows a schematic cross-sectional view of an electronic device in accordance with one or more embodiments; and

[0023] Figure 3 A schematic top view of an example multi-chamber processing system for forming electronic devices is shown in accordance with one or more embodiments.

[0024] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated into other embodiments without further recitation. DETAILED DESCRIPTION

[0025] Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description, and the present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0026] As used in this specification and the appended claims, the term "substrate" refers to a surface or portion of a surface upon which a process is performed. Those skilled in the art will also understand that, unless the context clearly indicates otherwise, reference to a substrate may also refer to only a portion of a substrate. Furthermore, reference to deposited on a substrate may refer to both a bare substrate and a substrate having one or more thin films or features deposited or formed thereon.

[0027] As used herein, "substrate" refers to any substrate, or material surface formed on a substrate, upon which thin film processing is performed during the manufacturing process. For example, depending on the application, substrate surfaces upon which processing may be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material (e.g., metals, metal nitrides, metal alloys, and other conductive materials). Substrates include, but are not limited to, semiconductor wafers and may be referred to as "semiconductor substrates." Substrates may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate (or otherwise create or implant target chemical moieties to impart chemical functionality), anneal, and / or bake the substrate surface. In addition to performing thin film processing directly on the surface of the substrate itself, any of the disclosed thin film processing steps may also be performed on an underlying layer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as indicated above and below. Thus, for example, if a film / layer or portion of a film / layer has already been deposited onto a substrate surface, then the exposed surface of the newly deposited film / layer becomes the substrate surface. What a given substrate surface comprises will depend on the film being deposited and the specific chemistry being used.

[0028] As used in this specification and the appended claims, the terms "precursor," "reactant," "reactant gas," and similar terms are used interchangeably to refer to any gaseous species that can react with a substrate surface.

[0029] As used herein, the term "in situ" refers to processes that are all performed in the same processing chamber or in different processing chambers connected as part of a processing system, such that each process is performed without an intermediate vacuum break. As used herein, the term "ex situ" refers to processes that are performed in at least two different processing chambers, such that one or more processes are performed with an intermediate vacuum break. In some embodiments, processes are performed without breaking vacuum or exposure to ambient air.

[0030] A transistor is a circuit component or element typically formed on a semiconductor device. Depending on the circuit design, a transistor may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, wires, or other components. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source region and the drain region include doped regions of the substrate and exhibit a doping profile suitable for a particular application. The gate is positioned above the channel region and includes a gate dielectric between the gate electrode and the channel region in the substrate.

[0031] As used herein, the term "field-effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Enhancement-mode field-effect transistors typically exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field in the device, which is generated by the voltage difference between the body of the device and the gate. The three terminals of a FET are the source (S), through which carriers enter the channel; the drain (D), through which carriers leave the channel; and the gate (G), which is the terminal that modulates the conductivity of the channel. Traditionally, the current entering the channel at the source (S) is designated as I S , designate the current entering the channel at the drain (D) as I D The drain-to-source voltage is designated as V DS By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., I D ).

[0032] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It features an insulated gate whose voltage determines the device's conductivity. This ability to vary conductivity with applied voltage is used to amplify or switch electronic signals. MOSFETs are based on modulating charge concentration across a metal-oxide-semiconductor (MOS) capacitor between a bulk electrode and a gate electrode, which sits above the bulk and is insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to a separate, highly doped region separated by the bulk region. These regions can be either p-type or n-type, but they are all of the same type and opposite to the bulk region. The source and drain (unlike the bulk) are highly doped, as indicated by the "+" sign following the doping type.

[0033] If the MOSFET is an n-channel, or nMOS FET, then the source and drain are n+ regions, and the bulk is the p region. If the MOSFET is a p-channel, or pMOS FET, then the source and drain are p+ regions, and the bulk is the n region. The source is named because it is the source of charge carriers flowing through the channel (electrons for an n-channel, holes for a p-channel); similarly, the drain is where the charge carriers leave the channel.

[0034] As used herein, the term "fin field-effect transistor (FinFET)" refers to a MOSFET transistor built on a substrate in which the gates are placed on two or three sides of the channel, forming a dual-gate or triple-gate structure. Because the channel region forms a "fin" on the substrate, FinFET devices are given the generic name "FinFET." FinFET devices have fast switching times and high current density.

[0035] As used herein, the term "gate-all-around (GAA)" refers to an electronic device, such as a transistor, in which gate material surrounds the channel region on all sides. The channel region of a GAA transistor can include nanowires or nanoplates, or nanosheets, strip-shaped channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has multiple vertically spaced horizontal nanowires or horizontal strips, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0036] As used herein, the term "nanowire" refers to a nanowire having a diameter of −9 Nanostructures with diameters on the order of meters. A nanowire can also be defined as a structure with a length to width ratio greater than 1000. Alternatively, a nanowire can be defined as a structure with a thickness or diameter limited to tens of nanometers or less and an unlimited length. Nanowires are used in transistors and certain laser applications, and in one or more embodiments are made of semiconducting materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in transistors of logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure having a thickness in a scale ranging from about 0.1 nanometers to about 1000 nanometers.

[0037] Embodiments of the present disclosure are described with reference to the accompanying drawings, which illustrate devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of the present disclosure. The processes shown are merely illustrative of possible uses of the disclosed processes, and skilled artisans will recognize that the disclosed processes are not limited to the applications illustrated.

[0038] Figure 1 A process flow diagram of a method 100 for forming an electronic device (eg, a gate-all-around device (GAA)) according to some embodiments of the present disclosure is shown. Figures 2A-2L Describing method 100, Figures 2A-2L Various stages in fabricating a semiconductor structure according to some embodiments of the present disclosure are described. Figures 2A-2L 1 shows a cross-sectional view of a GAA device according to one or more embodiments. The method 100 may be part of a multi-step manufacturing process for a semiconductor device. Thus, the method 100 may be used in conjunction with a cluster tool such as Figure 3 The processing system 400 may be coupled to any suitable process chamber for manufacturing semiconductor devices, such as a chamber configured for pre-cleaning, etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), selective epitaxial growth (SEG), oxidation, or any other suitable chamber for manufacturing semiconductor devices.

[0039] Figure 2A A semiconductor substrate 200 having a top surface 202 is shown. As used herein, the terms "semiconductor substrate 200" and "substrate 200" may be used interchangeably. The method 100 may optionally include forming Figure 2AOne or more etching processes (operation 102) are performed on the substrate 200 shown (described further below). In some embodiments, the substrate 200 can be a bulk semiconductor substrate. As used herein, the term "bulk semiconductor substrate" refers to a substrate that is entirely composed of semiconductor material. The bulk semiconductor substrate can include any suitable semiconductor material, and / or combination of semiconductor materials used to form a semiconductor structure. For example, the semiconductor layer can include one or more materials, such as crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, semiconductor substrate 200 includes a semiconductor material such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, substrate 200 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). While several examples of materials that can be used to form the substrate are described herein, any material that can serve as a foundation upon which passive and active electronic devices (such as transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic device) can be built falls within the spirit and scope of the present disclosure.

[0040] In some embodiments, the semiconductor material may be a doped material, such as n-doped silicon (n-Si) or p-doped silicon (p-Si). In some embodiments, the substrate may be doped using any suitable process, such as ion implantation. As used herein, the term "n-type" refers to a semiconductor created by doping an intrinsic semiconductor with an electron donor element during fabrication. The term n-type derives from the negative charge of electrons. In an n-type semiconductor, electrons are the majority carriers, and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a greater hole concentration than electrons. In a p-type semiconductor, holes are the majority carriers, and electrons are the minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or a combination thereof. In some embodiments, the substrate may be doped to provide a high dose of the dopant at a first location on the surface of substrate 200 to prevent parasitic bottom device opening.

[0041] At least one superlattice structure 204 is formed on the top surface 202 of the substrate 200. The superlattice structure 204 includes a plurality of semiconductor material layers 226 and a corresponding plurality of channel layers 224, which are alternately arranged into a plurality of stacked pairs. The terms "semiconductor material layers 226" and "dummy semiconductor layers 226" are used interchangeably herein. In some embodiments, the plurality of stacked layers comprises silicon (Si), germanium (Ge), or silicon-germanium (SiGe). In some embodiments, the silicon-germanium (SiGe) may contain germanium (Ge) in an amount ranging from 0 mol% to 50 mol%. In some embodiments, the plurality of semiconductor material layers 226 comprise silicon-germanium (SiGe), and the plurality of channel layers 224 comprise silicon (Si). In some embodiments, the plurality of semiconductor material layers 226 and the corresponding plurality of channel layers 224 may comprise any number of lattice-matched material pairs suitable for forming the superlattice structure 204. In some embodiments, the plurality of semiconductor material layers 226 and the corresponding plurality of channel layers 224 include from about 2 to about 50 lattice-matched material pairs. In some embodiments, the plurality of channel layers 224 can be doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).

[0042] In one or more embodiments, the thickness of the plurality of semiconductor material layers 226 and the plurality of channel layers 224 is in a range from about 2 nanometers to about 50 nanometers (including any subranges and values therebetween), for example, in a range from about 3 nanometers to about 20 nanometers, or in a range from about 2 nanometers to about 15 nanometers.

[0043] Figure 2A Also shown is a replacement gate structure (e.g., dummy gate structure 209) formed and patterned on superlattice structure 204. Dummy gate structure 209 defines the channel region of the transistor device. Dummy gate structure 209 can be formed using any suitable conventional deposition and patterning process known in the art. Dummy gate structure 209 can comprise any suitable material known to those skilled in the art. In some embodiments, dummy gate structure 209 comprises one or more of a sacrificial oxide layer 210 and a dummy gate polysilicon layer 212. In some embodiments, sidewall spacers 214 are formed along the outer sidewalls of dummy gate structure 209. In some embodiments, sidewall spacers 214 comprise a suitable insulating material known in the art, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and the like. In some embodiments, sidewall spacers 214 are formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, or low-pressure chemical vapor deposition.

[0044] refer to Figure 2BIn some embodiments, in operation 104, a source trench 232 and a drain trench 234 are formed on both sides of the superlattice structure 204 and adjacent to the superlattice structure 204. In some embodiments, the source trench 232 is formed near a first end of the superlattice structure 204, and the drain trench 234 is formed near an opposite second end of the superlattice structure 204. Figure 2B In the illustrated embodiment, neither the source trench 232 nor the drain trench 234 is shown at the front of the superlattice structure 204. The other end of the superlattice structure 204 has either the source trench 232 or the drain trench 234. In some embodiments, the source trench 232 and the drain trench 234 include a source region and a drain region, respectively. In other words, in some embodiments, the source region is formed in the source trench 232, while the drain region is formed in the drain trench 234. In some embodiments, the source region and / or the drain region are formed from any suitable semiconductor material, such as, but not limited to, silicon, germanium, silicon germanium, silicon phosphorus, silicon arsenic, or the like. In one or more embodiments, the source region and the drain region can be independently doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga). In some embodiments, the source region and the drain region can be formed using any suitable deposition process, such as an epitaxial deposition process.

[0045] refer to Figure 2CIn operation 106, a portion of the semiconductor material layer 226 is isotropically cavity etched to form a recessed semiconductor material layer 226'. In one or more embodiments, an opening can be formed by isotropically etching below the superlattice structure 204. In some embodiments, the superlattice structure 204 includes alternating silicon (Si) layers (e.g., the plurality of channel layers 224) and silicon germanium (SiGe) layers (e.g., the plurality of semiconductor material layers 226), which are isotropically etched using, for example, a dry etching process, a wet etching process, an RIE process, or a combination thereof, to form a cavity opening below the superlattice structure 204. In some embodiments, the dry etching process includes using a fluorine-based etchant, such as HF, CF4, SF6, CH2F2, CHF3, C2F6, other fluorine-containing etchants, or a combination thereof. In some embodiments, the wet etching process includes using an etchant including nitric acid (HNO3), ammonium hydroxide (NH3OH), ammonium fluoride (NH4F), hydrogen peroxide (H2O2), other suitable etchants, or combinations thereof. In some embodiments, the etching process is controlled by factors such as duration, temperature, pressure, source power, bias voltage, bias power, etchant flow rate, and / or other suitable parameters to remove a desired amount of the semiconductor material layer 226. In some embodiments, the amount of the semiconductor material layer 226 removed in operation 106 is controlled by the duration of the etching process to ensure that a sufficient channel length L is maintained in subsequent processing steps to form a metal gate stack.

[0046] In some embodiments, after the semiconductor material layer cavity etching is performed in operation 106, a pre-cleaning process can be performed in operation 108 before the formation of the internal spacer liner and the internal spacer. The pre-cleaning process can include any suitable pre-cleaning process known to a skilled person. In some embodiments, the pre-cleaning process includes etching a portion of the plurality of semiconductor material layers 226 with diluted hydrofluoric acid (diluted HF) (including diluted HF greater than 100:1, such as 130:1) to etch away native oxide on the substrate to form a hydrophobic surface. In some embodiments, the pre-cleaning process can include conventional plasma etching, or a remote plasma assisted dry etching process, such as SiCoNi available from Applied Materials, Inc., located in Santa Clara, California. TM Etching process. TM During the etching process, the device is exposed to H2, NF3 and / or NH3 plasma species, such as plasma-excited hydrogen and fluorine species. For example, in some embodiments, the device can be exposed to H2, NF3 and NH3 plasma simultaneously. TM The etching process can be performed on SiCoNi TMThe process is performed in a pre-clean chamber that can be integrated into one of a variety of multi-processing platforms, including, for example, the RT-PCR ... ® The company acquired Centura ® 、Dual ACP、Producer ® GT and Endura ® platform.

[0047] The wet etching process may include a hydrofluoric acid (HF) last process, a so-called "HF last" process, in which the surface is HF-etched to hydrogen-terminate the surface. Alternatively, any other liquid-based pre-epitaxial pre-cleaning process may be employed. In some embodiments, the process includes a sublimation etch to remove native oxide. The etching process may be plasma-based or thermal-based. The plasma process may be any suitable plasma (e.g., conductively coupled plasma, inductively coupled plasma, microwave plasma).

[0048] In operation 110, as Figure 2D As shown, after the semiconductor material layer cavity etching is performed in operation 106, and optionally after a pre-cleaning process is performed in operation 108, an internal spacer liner 250 is formed. The internal spacer liner 250 is particularly useful in nMOS FET structures, pMOS FET structures, and GAA devices, and will be described in this context, however, the internal spacer liner 250 is not limited to these applications.

[0049] Embodiments of the present disclosure relate to internal spacer liner technology that improves overall GAA device performance. Some embodiments involve selective internal spacer liner growth prior to internal spacer formation to compensate for silicon (Si) corner losses during pit / cavity etching. Some embodiments advantageously provide fully restored ion / current losses by growing the selective internal spacer liner prior to internal spacer formation.

[0050] Embodiments of the present disclosure relate to internal spacer pad configurations that advantageously have lower overall effective capacitance (C eff ), while having high resistance to dry and wet etching processes. Some embodiments relate to internal spacer liner configurations at 3 nm GAA device size, which advantageously have lower overall effective capacitance (C) compared to conventional internal spacers without internal spacer liner in comparable GAA devices. eff ). It is believed that the presence of the internal spacer liner along the sidewalls improves the wire release process window, which subsequently benefits static random access memory (SRAM) yield.

[0051] In some embodiments, a crystalline silicon-containing liner 250 is formed along the recessed semiconductor material layer 226′ and the corresponding plurality of channel layers 224, and an inner spacer 260 is formed directly on the crystalline silicon-containing liner 250. In some embodiments, the inner spacer 260 is adjacent to the source trench 232 and the drain trench 234.

[0052] refer to Figure 1 and 2D In some embodiments, in operation 110, a selective epitaxial growth (SEG) process is performed to form a crystalline silicon-containing liner 250 along the recessed semiconductor material layer 226' and the corresponding plurality of channel layers 224. The SEG process may include any method for depositing or growing a single crystalline thin film, wherein the lattice structure and orientation of the deposited film are identical to those of the substrate, as known to those skilled in the art. In one or more embodiments, the crystalline silicon-containing liner 250 is selectively formed along the recessed semiconductor material layer 226' and the corresponding plurality of channel layers 224, and is selectively not formed along the sidewall spacers 214.

[0053] The SEG process may be performed until the crystalline silicon-containing liner 250 is formed to a desired thickness. In some embodiments, the thickness of the crystalline silicon-containing liner 250 is in the range of 0.5 nanometers to 3 nanometers, including all subranges and values therebetween. In some embodiments, the thickness of the crystalline silicon-containing liner 250 varies depending on the amount of silicon (Si) loss.

[0054] For example, in some embodiments, when the silicon (Si) loss is about 1 nm, the thickness of the liner 250 comprising crystalline silicon is about 1 nm. In a specific embodiment in which the thickness of the liner 250 comprising crystalline silicon is about 1 nm when the silicon (Si) loss is about 1 nm, the effective capacitance (C eff ) is reduced, measured in femtofarads per micron (fF / μm). In other embodiments, when the silicon (Si) loss is about 1 nanometer, the thickness of the liner 250 comprising crystalline silicon is about 2 nanometers. In a specific embodiment where the thickness of the liner 250 comprising crystalline silicon is about 2 nanometers when the silicon (Si) loss is about 1 nanometer, the effective capacitance (C) of the GAA device is reduced compared to a GAA device without an internal spacer liner. eff ) is reduced and is measured in femtofarads per micron (fF / μm).

[0055] In one or more embodiments, the crystalline silicon-containing liner 250 is doped with a dopant. It has been advantageously discovered that doping the crystalline silicon-containing liner 250 with a p-type dopant or an n-type dopant increases the AC and DC performance of the GAA device. In embodiments where the dopant includes an n-type dopant, the n-type dopant includes, but is not limited to, one or more of phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), or lithium (Li). In embodiments where the dopant includes a p-type dopant, the p-type dopant includes, but is not limited to, one or more of boron (B), aluminum (Al), gallium (Ga), or indium (In). In some embodiments, the p-type dopant includes boron (B) and the n-type dopant includes phosphorus (P).

[0056] The dopant may have any suitable dopant concentration. In some embodiments, the dopant concentration of the dopant is greater than or equal to 10 19 atoms / cm 3 , such as 10 20 atoms / cm 3 , 10 21 atoms / cm 3 or 10 22 atoms / cm 3 .

[0057] refer to Figure 1 and Figure 2E In some embodiments, in operation 112 , an inner spacer 260 is formed directly on the liner 250 comprising crystalline silicon. In some embodiments, the inner spacer 260 is adjacent to the source trench 232 and the drain trench 234 .

[0058] The inner spacer 260 can comprise any suitable insulating material known in the art, such as a low-κ dielectric material. In one or more embodiments, the low-κ dielectric material has a κ value less than or equal to 4.2. In some embodiments, the low-κ dielectric material of the inner spacer 260 comprises one or more of silicon (Si), silicon oxide (SiOx), doped silicon, doped silicon oxide, or a spin-on dielectric. In one or more embodiments, the low-κ dielectric material of the inner spacer 260 comprises one or more of silicon oxycarbide (SiOC) or silicon oxynitride (SiON). In some embodiments, the inner spacer 260 is formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, or isotropic deposition. In some embodiments, the thickness of the inner spacer 260 is in the range of 2 nanometers to 5 nanometers, including all subranges and values therebetween.

[0059] The inner spacer 260 can be deposited on the crystalline silicon-containing liner 250 by any suitable deposition process known to a skilled artisan. In some embodiments, the inner spacer 260 is formed by a thermal chemical vapor deposition process at a temperature in the range of 400° C. to 650° C., including all subranges and values therebetween.

[0060] In some embodiments, the internal spacer 260 is conformally deposited. As used herein, the term "conformal" means that a layer conforms to the contours of a feature or layer. The conformality of a layer is typically quantified by the ratio of the average thickness of the layer deposited on the sidewalls of the feature to the average thickness of the same deposited layer on the field or top surface of the substrate. In some embodiments, the internal spacer 260 is deposited by a thermal chemical vapor deposition process with a conformality in the range of 70% to 90%. The term "conformal in the range of 70% to 90%" as used in this regard means that the ratio of the average thickness of the layer deposited on the sidewalls of the feature to the average thickness of the same deposited layer on the field or top surface of the substrate is in the range of 70% to 90%.

[0061] The inner spacer 260 may be any suitable shape, including but not limited to circular, square, rectangular, or any other polygonal shape.

[0062] In some embodiments, the internal spacer 260 is substantially free of seams and / or voids. As used in this context, the term "substantially free" means that the total composition of the internal spacer 260, on an atomic basis, comprises less than about 5% seams and / or voids, including less than about 4%, less than about 3%, less than about 2%, less than about 1%, less than about 0.5%, and less than about 0.1%.

[0063] refer to Figure 1 and Figure 2F In operation 114, method 100 includes etching a portion of inner spacer 260 to form etched inner spacer 260'. The etching process of operation 114 may include any suitable etching process, including but not limited to the pre-cleaning process, wet etching process, or dry etching process described herein.

[0064] refer to Figure 2G , method 100 includes source / drain epitaxial growth and interlayer dielectric formation processes (operation 116) and replacement metal gate formation and polysilicon removal (operation 118). Figure 2G In the embodiment, the GAA device includes a highly doped epitaxial source / drain junction 270, a protective dielectric layer 272 (e.g., silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof) located on the highly doped epitaxial source / drain junction 270, and an interlayer dielectric 274 formed on the protective dielectric layer 272. Figure 2G The processes and layers shown are well known to those skilled in the art.

[0065] In some embodiments, in operation 118, the dummy gate structure 209 is removed to expose the channel region of the superlattice structure 204. During the removal of the dummy gate structure 209, layers 270, 272, and 274 protect the source trench 232 / drain trench 234. The dummy gate structure 209 can be removed using any conventional etching process, such as a pre-clean process, a wet etching process, or a dry etching process as described herein. In some embodiments, the dummy gate structure 209 includes one or more of a sacrificial oxide layer 210 and a dummy gate polysilicon layer 212, and the entire dummy gate structure 209 is removed by a selective etching process. In embodiments, when the dummy gate structure 209 includes sidewall spacers (such as sidewall spacers 214), the sidewall spacers 214 are not removed in operation 114. Figure 2H The removal of the sacrificial oxide layer 210 is shown. The sacrificial oxide layer 210 may be removed by any suitable etching process, including but not limited to the pre-clean process described herein, a wet etching process, or a dry etching process.

[0066] refer to Figure 2I At operation 120 , method 100 includes removing the recessed semiconductor material layer 226 ′ in the superlattice structure 204 . At operation 120 , the recessed semiconductor material layer 226 ′ is selectively etched between the plurality of channel layers 224 in the superlattice structure 204 . For example, where the superlattice structure 204 is comprised of a silicon (Si) layer and a silicon germanium (SiGe) layer, the silicon germanium (SiGe) is selectively etched to form the channel nanowires. The recessed semiconductor material layer 226 ′ (e.g., comprising silicon germanium (SiGe)) can be removed using any well-known etchant that is selective to the plurality of channel layers 224 (e.g., silicon (Si)), wherein the etchant etches the recessed semiconductor material layer 226 ′ at a significantly higher rate than the plurality of channel layers 224. In some embodiments, a pre-cleaning process, a selective dry etching process, or a wet etching process as described herein can be used. In some embodiments, when the plurality of channel layers 224 are silicon (Si) and the recessed semiconductor material layer 226 ′ is silicon germanium (SiGe), a wet etchant (such as, but not limited to, a carboxylic acid / nitric acid / HF aqueous solution and a citric acid / nitric acid / HF aqueous solution) may be used to selectively remove the silicon germanium (SiGe) layer.

[0067] In one or more embodiments, Figure 2IAs shown, removal of the plurality of semiconductor material layers 226 (and / or the recessed semiconductor material layers 226 ′) leaves gaps between the plurality of channel layers 224 . The gaps between the plurality of channel layers 224 have a thickness of about 3 nanometers to about 20 nanometers, including any subranges and values therebetween. The remaining channel layers 224 form an array of vertical channel nanowires that couple to the source / drain regions in the source trenches 232 and drain trenches 234 . The channel nanowires run parallel to the top surface 202 of the substrate 200 and are aligned with each other to form a single row of channel nanowires.

[0068] refer to Figure 2J In operation 122, the method 100 includes etching a portion of the crystalline silicon-containing liner 250 to form an etched crystalline silicon-containing liner 250'. In one or more embodiments, the portion of the crystalline silicon-containing liner 250 etched in operation 122 is a portion previously formed along the recessed semiconductor material layer 226'. Figure 2I is removed in operation 120. In one or more embodiments, the semiconductor material layer 226' previously formed along the recess (at Figure 2I The portion of the crystalline silicon-containing liner 250 formed along the plurality of channel layers 224 (removed in the illustrated operation 120) may be referred to as an inner sidewall or inner sidewall portion. The portion of the crystalline silicon-containing liner 250 formed along the plurality of channel layers 224 is not etched.

[0069] It has been advantageously discovered that etching the portion of the crystalline silicon-containing liner 250 formed along the inner sidewalls to form the etched crystalline silicon-containing liner 250 ′ in operation 122 reduces the effective capacitance (C ) of the GAA device compared to a GAA device without an inner spacer liner. eff ), measured in femtofarads per micron (fF / μm).

[0070] For example, in some embodiments, when the silicon (Si) loss is about 1 nm, the thickness of the crystalline silicon-containing liner 250 is about 1 nm. In a specific embodiment in which the thickness of the crystalline silicon-containing liner 250 is about 1 nm when the silicon (Si) loss is about 1 nm, and a portion of the crystalline silicon-containing liner 250 formed along the inner sidewall is etched in operation 122 to form an etched crystalline silicon-containing liner 250 ′, the effective capacitance (C ) of the GAA device is reduced compared to a GAA device without an internal spacer liner. eff ) decrease, measured in femtofarads per micron (fF / μm).

[0071] In other embodiments, when the silicon (Si) loss is about 1 nm, the thickness of the crystalline silicon-containing liner 250 is about 2 nm. In a specific embodiment in which the thickness of the crystalline silicon-containing liner 250 is about 2 nm when the silicon (Si) loss is about 1 nm, and a portion of the crystalline silicon-containing liner 250 formed along the inner sidewall is etched in operation 122 to form an etched crystalline silicon-containing liner 250 ′, the effective capacitance (C ) of the GAA device is reduced compared to a GAA device without an internal spacer liner. eff ) decrease, measured in femtofarads per micron (fF / μm).

[0072] refer to Figure 2K At operation 124 , method 100 includes forming an interlayer dielectric (ILD) 276 on each remaining channel layer 224 . In some embodiments, ILD 276 encapsulates the remaining channel layer 224 and covers all portions of channel layer 224 except for portions covered by the etched crystalline silicon-containing liner 250 ′ (e.g., inner sidewalls). ILD 276 can be deposited using conventional chemical vapor deposition methods, such as plasma-enhanced chemical vapor deposition and low-pressure chemical vapor deposition. In one or more embodiments, ILD 276 is formed from any suitable dielectric material described herein, such as, but not limited to, undoped silicon oxide, doped silicon oxide (e.g., BPSG, PSG), silicon nitride, and silicon oxynitride.

[0073] refer to Figure 2L At operation 126 , method 100 includes one or more processes known to those skilled in the art for completing an hGAA device, such as replacement metal gate formation. For example, in one or more embodiments, a high-k dielectric 278 is formed on the ILD 276 . The high-k dielectric 278 can be any suitable high-k dielectric material deposited by any suitable deposition technique known to those skilled in the art. The high-k dielectric 278 of some embodiments includes hafnium oxide. In some embodiments, a conductive material such as titanium nitride (Tin), tungsten (W), cobalt (Co), aluminum (Al), or the like is deposited on the high-k dielectric. The conductive material can be formed using any suitable deposition process, such as, but not limited to, atomic layer deposition (ALD), to ensure that a layer having a uniform thickness is formed around each of the plurality of channel layers 224 .

[0074] like Figure 3 As shown, other embodiments of the present disclosure relate to a processing system 400 and a method (such as method 100) for forming a liner 250 and an inner spacer 260 containing crystalline silicon for an electronic device (such as a GAA device). Examples of processing systems that can be appropriately modified according to the teachings provided herein include those available from Applied Materials, Inc. of Santa Clara, California.® ) purchased Centura ® 、Dual ACP、Producer ® GT and Endura ® Platforms may utilize other processing systems as well. It is contemplated that other processing systems (including those from other manufacturers) may also be adapted to benefit from the aspects described herein.

[0075] The processing system 400 may include a processor available from Applied Materials, Inc. of Santa Clara, California. ® ) purchased from Sym3. In some embodiments, the processing system 400 includes a low-κ silicon oxide carbon (SiOC) dielectric chemical vapor deposition (CVD) chamber. In some embodiments, the processing system 400 includes an advanced unit process solution by combining a low-κ silicon oxide carbon (SiOC) dielectric chemical vapor deposition (CVD) chamber with a Sym3. ® Etch systems (available from Applied Materials, Santa Clara, CA) ® ) are combined to provide an integrated tool solution (e.g., an integrated cyclic CVD deposition and etch processing system).

[0076] In some embodiments, as described herein, one or more operations of the methods of the present disclosure are performed in situ. In some embodiments, as described herein, one or more operations of the methods of the present disclosure are performed ex situ. In some embodiments, one or more operations of method 100 are performed in situ in an integrated processing tool (such as processing system 400). Unless otherwise indicated, the terms "integrated processing tool," "integrated tool system," "cluster tool," "processing tool," and "processing system 400" as used herein may be used interchangeably to refer to a process that is ... Figure 3 Processing system 400 is shown.

[0077] One or more operations of method 100 are performed by an integrated module in situ in an integrated processing tool system, such as processing system 400. Unless otherwise specified, the integrated modules described herein are performed in situ in an integrated processing tool system, such as processing system 400.

[0078] In some embodiments, the processing system 400 includes an integrated module for: performing a pre-cleaning process prior to forming the inner spacer liner and the inner spacer (operation 108 of method 100); selectively forming the liner comprising crystalline silicon (operation 110 of method 100); and forming the inner spacer directly on the liner comprising crystalline silicon (operation 112 of method 100).

[0079] In some embodiments, the processing system 400 includes an integrated module for: performing a cavity etching of a semiconductor material layer (operation 106 of method 100) and then performing a pre-cleaning process prior to forming an inner spacer liner and an inner spacer (operation 108 of method 100); selectively forming a liner comprising crystalline silicon (operation 110 of method 100); and forming an inner spacer directly on the liner comprising crystalline silicon (operation 112 of method 100).

[0080] In some embodiments, the processing system 400 includes an integrated module for: cavity etching a semiconductor material layer (operation 106 of method 100) and then performing a pre-cleaning process prior to forming an inner spacer liner and an inner spacer (operation 108 of method 100); selectively forming a liner comprising crystalline silicon (operation 110 of method 100); and forming an inner spacer directly on the liner comprising crystalline silicon (operation 112 of method 100); and etching a portion of the inner spacer (operation 114 of method 100).

[0081] In some embodiments, the processing system 400 is also particularly useful for 3D memory horizontal wordline applications and forming contacts / sidewall spacers.

[0082] In some embodiments, the operations of the methods described herein are each performed within the same processing chamber. In some embodiments, the operations of the methods described herein are each performed within different processing chambers. In some embodiments, the different processing chambers are connected as part of a processing system. In some embodiments, the operations of the methods described herein are performed without an intermediate vacuum break.

[0083] Figure 3A schematic top view of an example of a multi-chamber processing system 400 according to an embodiment of the present disclosure is illustrated. The processing system 400 generally includes a factory interface 402, load lock chambers 404, 406, transfer chambers 408, 410 with corresponding transfer robots 412, 414, holding chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, 430. As described in detail herein, wafers in the processing system 400 can be processed in and transferred between the various chambers without exposing the wafers to an ambient environment external to the processing system 400 (e.g., an atmospheric ambient environment, such as may be present in a fab). For example, wafers can be processed in and transferred between the various chambers under a low pressure (e.g., less than or equal to about 300 Torr) or vacuum environment without interrupting the low pressure or vacuum environment between various processes performed on the wafers in the processing system 400. Thus, the processing system 400 may provide an integrated solution for several processing operations on a wafer.

[0084] exist Figure 3 In the example shown, the factory interface 402 includes a docking station 440 and a factory interface robot 442 to facilitate wafer transfer. The docking station 440 is configured to receive one or more front-opening unified pods (FOUPs) 444. In some examples, each factory interface robot 442 generally includes a blade 448 disposed at one end of the corresponding factory interface robot 442, which is configured to transfer wafers from the factory interface 402 to the load lock chambers 404, 406.

[0085] The load lock chambers 404 and 406 have respective ports 450 and 452 coupled to the factory interface 402, and have respective ports 454 and 456 coupled to the transfer chamber 408. The transfer chamber 408 further has respective ports 458 and 460 coupled to the holding chambers 416 and 418, and has respective ports 462 and 464 coupled to the processing chambers 420 and 422. Similarly, the transfer chamber 410 has respective ports 466 and 468 coupled to the holding chambers 416 and 418, and has respective ports 470, 472, 474, 476 coupled to the processing chambers 424, 426, 428, 430. Ports 454, 456, 458, 460, 462, 464, 466, 468, 470, 472, 474, and 476 may be, for example, slit valve openings having slit valves. These slit valves are used to pass wafers through the slit valves by the transfer robots 412 and 414 and to provide a seal between the corresponding chambers to prevent gas from passing between the corresponding chambers. Generally, any port is opened for transferring wafers therethrough. Otherwise, the port is closed.

[0086] The load lock chambers 404, 406, transfer chambers 408, 410, holding chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, and 430 can be fluidically coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system can include one or more gas pumps (e.g., turbo pumps, cryopumps, or primary pumps) fluidically coupled to the various chambers, gas sources, various valves, and conduits. In operation, the factory interface robot 442 transfers wafers from a FOUP 444 to a load lock chamber 404 or 406 via port 450 or 452. The gas and pressure control system then evacuates the load lock chamber 404 or 406. The gas and pressure control system further maintains an internal low-pressure or vacuum environment (which may include an inert gas) in the transfer chambers 408, 410 and holding chambers 416, 418. Thus, pumping down the load lock chamber 404 or 406 facilitates transferring wafers between, for example, the atmospheric environment of the factory interface 402 and the low pressure or vacuum environment of the transfer chamber 408 .

[0087] With the wafer in the evacuated load lock chamber 404 or 406, the transfer robot 412 transfers the wafer from the load lock chamber 404 or 406 to the transfer chamber 408 through the port 454 or 456. The transfer robot 412 can then transfer the wafer to and / or between the processing chambers 420 and 422 for processing through the corresponding ports 462 and 464, and transfer the wafer to and / or between the holding chambers 416 and 418 for holding through the corresponding ports 458 and 460, awaiting further transfer. Similarly, the transfer robot 414 can access wafers in the holding chamber 416 or 418 through the port 466 or 468 and can transfer the wafers to any of the processing chambers 424, 426, 428, 430 and / or between any of the processing chambers 424, 426, 428, 430 for processing through the corresponding ports 470, 472, 474, 476, and can transfer the wafers to any of the holding chambers 416, 418 and / or between any of the holding chambers 416, 418 for holding pending further transfer through the corresponding ports 466, 468. The transfer and holding of wafers within and between the various chambers can be performed in a low pressure or vacuum environment provided by the gas and pressure control system.

[0088] Processing chambers 420, 422, 424, 426, 428, and 430 can be any suitable chamber for processing wafers. In one or more embodiments, processing chambers 420, 422, 424, 426, 428, and 430 include a pre-clean chamber, a selective epitaxial growth (SEG) chamber, a low-κ silicon oxide carbon (SiOC) dielectric chemical vapor deposition (CVD) chamber, and an etch chamber. In some embodiments, processing chamber 420 can perform an annealing process, processing chamber 422 can perform a cleaning process, and processing chambers 424, 426, 428, and 430 can perform an epitaxial growth process. In some examples, processing chamber 422 can perform a cleaning process, processing chamber 420 can perform an etching process, and processing chambers 424, 426, 428, and 430 can perform corresponding epitaxial growth processes. Processing chamber 422 can be a SiCoNi™ pre-clean chamber available from Applied Materials, Inc., Santa Clara, California. The processing chamber 420 may be a Selectra™ etch chamber available from Applied Materials, Inc. of Santa Clara, California.

[0089] A system controller 490 is coupled to the processing system 400 to control the processing system 400 or components thereof. For example, the system controller 490 can control the operation of the processing system 400 using direct control of the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, 430 of the processing system 400 or by controlling controllers associated with the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, 430. In operation, the system controller 490 enables data collection and feedback from the respective chambers to coordinate the performance of the processing system 400.

[0090] System controller 490 generally includes a central processing unit (CPU) 492, memory 494, and support circuits 496. CPU 492 can be any general-purpose processor suitable for use in an industrial environment. Memory 494, or non-transitory computer-readable media, is accessible by CPU 492 and can be one or more types of memory, such as random access memory (RAM), read-only memory (ROM), a floppy disk, a hard disk, or any other form of local or remote digital storage. Support circuits 496 are coupled to CPU 492 and can include cache memory, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein can generally be implemented under the control of CPU 492 by CPU 492 executing computer instruction code stored in memory 494 (or memory of a particular process chamber) as, for example, software routines. When the computer instruction code is executed by CPU 492, CPU 492 controls each chamber to perform processes according to the various methods.

[0091] Other processing systems may employ other configurations. For example, more or fewer processing chambers may be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 408 and 410 and holding chambers 416 and 418. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chamber) may be implemented as the transfer device in the processing system.

[0092] The process can generally be stored as a software routine in the memory of the system controller 490. When executed by the processor, the software routine causes the process chamber to perform the process of the present disclosure. The software routine can also be stored and / or executed by a second processor (not shown), which is remote from the hardware controlled by the processor. Some or all of the methods of the present disclosure can also be performed in hardware. Thus, the process can be implemented in software and executed using a computer system, implemented in hardware, such as an application-specific integrated circuit or other type of hardware implementation, or implemented as a combination of software and hardware. The software routine, when executed by the processor, transforms a general-purpose computer into a special-purpose computer (controller) that controls chamber operations to perform the process.

[0093] One or more embodiments of the present disclosure are directed to a non-transitory computer-readable medium comprising instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform a method described herein, such as method 100 .

[0094] Unless otherwise indicated herein or clearly contradicted by context, the use of the terms "a," "an," and "the," and similar designations in the context of describing the materials and methods discussed herein (especially in the context of the following claims) are to be interpreted as encompassing both the singular and the plural. Unless otherwise indicated herein, the recitation of ranges of values herein is merely intended to serve as a shorthand method of individually referring to each individual value falling within the range, and each individual value is incorporated into this specification as if it were individually recited herein. Unless otherwise indicated herein or clearly contradicted by context, all methods described herein can be performed in any suitable order. Unless otherwise requested, the use of any and all examples or exemplary language (e.g., "for example") provided herein is intended solely to better illustrate the materials and methods and does not limit the scope. No language in this specification should be construed to indicate that any unclaimed element is essential to the practice of the disclosed materials and methods.

[0095] References throughout this specification to "one or more embodiments," "certain embodiments," or "one or more embodiments" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the present disclosure. Thus, the appearance of phrases such as "in one or more embodiments," "in certain embodiments," or "in one or more embodiments" in various places throughout this specification are not necessarily referring to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0096] Although the disclosure herein has been described with reference to specific embodiments, it will be understood by those skilled in the art that the embodiments described are merely illustrative of the principles and applications of the disclosure. It will be understood by those skilled in the art that various modifications and variations may be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Therefore, the disclosure may include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method for manufacturing an electronic device, the method comprising: forming a crystalline silicon-containing liner within a superlattice structure formed on a top surface of a semiconductor substrate, the superlattice structure comprising a plurality of recessed semiconductor material layers and a corresponding plurality of channel layers, the plurality of recessed semiconductor material layers and the corresponding plurality of channel layers being alternately arranged into a plurality of stacked pairs, the crystalline silicon-containing liner being formed along the recessed semiconductor material layers and the corresponding plurality of channel layers by a selective epitaxial growth (SEG) process; as well as An inner spacer is formed directly on the crystalline silicon-containing liner, the inner spacer being adjacent to the source region and the drain region.

2. The method of claim 1, further comprising: Before forming the liner containing crystalline silicon, the semiconductor substrate is pre-cleaned.

3. The method of claim 2, wherein pre-cleaning the semiconductor substrate, forming the liner comprising crystalline silicon, and forming the inner spacer are performed in an integrated tool system without a vacuum break. 4 . The method of claim 1 , wherein the liner comprising crystalline silicon is doped with a dopant, the dopant comprising a p-type dopant or an n-type dopant. 5 . The method of claim 4 , wherein the p-type dopant comprises boron (B), and the n-type dopant comprises phosphorus (P). 6 . The method of claim 1 , wherein the thickness of the liner comprising crystalline silicon is in a range of 0.5 nm to 3 nm. The method of claim 1 , wherein the internal spacer comprises a low-κ dielectric material. 8 . The method of claim 1 , wherein the semiconductor material layer comprises silicon germanium (SiGe), and the channel layer comprises silicon (Si).

9. The method of claim 1, further comprising: A portion of the inner spacer and a portion of the crystalline silicon-containing liner are etched.

10. The method of claim 1, wherein the electronic device is a gate-all-around (GAA) device.

11. A method of manufacturing an electronic device, the method comprising: pre-cleaning the semiconductor substrate, and then; forming a liner containing crystalline silicon within a superlattice structure formed on a top surface of the semiconductor substrate, the superlattice structure comprising a plurality of recessed semiconductor material layers and a corresponding plurality of channel layers, the plurality of recessed semiconductor material layers and the corresponding plurality of channel layers being alternately arranged into a plurality of stacked pairs, the liner containing crystalline silicon being formed along the recessed semiconductor material layers and the corresponding plurality of channel layers by a selective epitaxial growth (SEG) process; forming an inner spacer directly on the liner comprising crystalline silicon, the inner spacer being adjacent to the source region and the drain region; etching a portion of the inner spacer; as well as The replacement metal gate and the recessed semiconductor material layer on the semiconductor substrate are removed, and then the inner sidewall portion of the crystalline silicon-containing liner is etched.

12. The method of claim 11, wherein pre-cleaning the semiconductor substrate, forming the liner comprising crystalline silicon, and forming the inner spacer are performed in an integrated tool system without a vacuum break.

13. The method of claim 11, wherein the crystalline silicon-containing liner is doped with a p-type dopant or an n-type dopant. 14 . The method of claim 13 , wherein the p-type dopant comprises boron (B), and the n-type dopant comprises phosphorus (P).

15. The method of claim 11, wherein the thickness of the liner comprising crystalline silicon is in a range of 0.5 nm to 3 nm.

16. The method of claim 11, wherein the internal spacer comprises a low-κ dielectric material. 17 . The method of claim 11 , wherein the semiconductor material layer comprises silicon germanium (SiGe), and the channel layer comprises silicon (Si).

18. The method of claim 11, wherein the electronic device is a gate-all-around (GAA) device.

19. A processing tool, comprising: a central transfer station comprising a robot configured to move a semiconductor substrate; a plurality of process stations, each process station connected to the central transfer station and providing a processing area separate from a processing area of an adjacent process station, the plurality of process stations including a pre-clean chamber, a selective epitaxial growth (SEG) chamber, and a low-κ silicon oxide carbon (SiOC) dielectric chemical vapor deposition (CVD) chamber; as well as a controller connected to the central transfer station and the plurality of process stations, the controller being configured to activate the robot to move the semiconductor substrate between the process stations and control a process cycle for forming a liner comprising crystalline silicon for a gate-all-around (GAA) device, the process cycle comprising: pre-cleaning the semiconductor substrate; The crystalline silicon-containing liner is formed within a superlattice structure formed on the top surface of the semiconductor substrate by a selective epitaxial growth (SEG) process, wherein the superlattice structure includes a plurality of recessed semiconductor material layers and a corresponding plurality of channel layers, wherein the plurality of recessed semiconductor material layers and the corresponding plurality of channel layers are alternately arranged into a plurality of stacked pairs, wherein the semiconductor material layers include silicon germanium (SiGe), and the channel layers include silicon (Si), and the crystalline silicon-containing liner is formed along the recessed semiconductor material layers and the corresponding plurality of channel layers; and an internal spacer is directly formed on the crystalline silicon-containing liner, wherein the internal spacer is adjacent to the source region and the drain region.

20. The processing tool of claim 19, wherein the plurality of process stations further comprises an etch chamber for etching a portion of the inner spacer and a portion of the crystalline silicon-containing liner.

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