MEMS inertial device structure and manufacturing method
By pre-opening a first etching area on the device layer in the MEMS inertial device structure and opening a second etching area on the upper cover at a position corresponding to the substrate test PAD, the problem of the small distance between the device layer and the substrate is solved, the manufacturing yield and etching uniformity are improved, and the reliability of the device is enhanced.
Patent Information
- Application Number
- CN202511000499.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-21
- Publication Date
- 2025-09-30
- Estimated Expiration
- 2045-07-21
AI Technical Summary
During the manufacturing process of MEMS inertial devices, the distance between the device layer and the substrate layer is too small, and there is a risk that the dicing knife will contact the substrate metal wire. In addition, the dicing process window is narrow and the stability requirement is high.
A first etching area is pre-opened on the device layer, and a test PAD is set on the substrate directly above it. After bonding to the device layer through the upper cover, a second etching area is opened on the upper cover to connect with the first etching area when testing is required, exposing the test PAD and preventing the dicing knife from contacting the substrate metal wire.
The manufacturing yield and etching uniformity of MEMS inertial devices are improved, the risk of scratching the device layer and the base metal wire is reduced, and the reliability of the device is enhanced.
Smart Images
Figure CN120483031B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of inertial devices, and in particular to a MEMS inertial device structure and a manufacturing method. Background Art
[0002] During the manufacturing process of MEMS (Micro-Electro-Mechanical System) inertial devices, the device layer must be cut through to expose the test pads on the substrate layer for testing. Currently, the spacing between the device layer and the substrate of MEMS inertial devices is typically less than 10 µm. During operation, this small gap between the device layer and the substrate creates a risk of the dicing blade contacting the substrate metal lines. Furthermore, the narrow dicing process window places extremely high demands on the dicing machine's process stability. Therefore, a MEMS inertial device structure and fabrication method are urgently needed to address these issues. Summary of the Invention
[0003] In order to solve the above problems, on the one hand, the present invention provides a MEMS inertial device structure, including an upper cover plate, a device layer and a substrate bonded in sequence from top to bottom, the device layer having a sensitive etching area and a non-sensitive area, the sensitive etching area being etched to form a sensitive structure of the inertial device, the non-sensitive area being provided with a scribe line, the scribe line being etched to form a first through-etching area, a plurality of test PADs being provided on the substrate, and the first through-etching area being located directly above the plurality of test PADs.
[0004] Furthermore, there are a plurality of first etching regions distributed around the sensitive etching area.
[0005] Furthermore, each of the first cut-through areas is located directly above the corresponding one or more test PADs.
[0006] Furthermore, the first engraved area is a square engraved area, and the width of the square engraved area is not less than 80 μm.
[0007] Furthermore, a second cut-through area is provided on the upper cover plate, and the second cut-through area is connected to the first cut-through area to expose the plurality of test PADs.
[0008] On the other hand, the present invention also provides a method for manufacturing the MEMS inertial device structure as described above, comprising the following steps:
[0009] S1: Patterning the upper cover;
[0010] S2: bonding the device layer to the patterned upper cover plate, etching the scribe lines in the sensitive etching area and the non-sensitive area of the device layer, obtaining the inertial device sensitive structure in the sensitive etching area of the device layer, and forming a first etched through area on the scribe line;
[0011] S3: Bonding the substrate and the device layer to obtain a three-layer bonding structure, wherein the first cut-through area is located directly above the test PAD of the substrate.
[0012] Furthermore, in step S2, etching of the sensitive etching area of the device layer and etching of the scribe lines in the non-sensitive area are performed simultaneously.
[0013] Furthermore, the step S3 also includes, when a test PAD needs to be connected for testing, opening a second cut-through area on the upper cover plate of the three-layer bonding structure, and connecting the second cut-through area with the first cut-through area to expose the test PAD.
[0014] Furthermore, the step S3 further includes thinning the device layer before bonding the substrate to the device layer, thinning the device layer to a thickness of 30-80 μm.
[0015] Furthermore, the step S1 specifically includes: patterning the upper cover wafer through photolithography and etching.
[0016] Due to the adoption of the above technical solution, the present invention has the following beneficial effects compared with the prior art:
[0017] 1) The MEMS inertial device structure and fabrication method provided by the present invention pre-cuts a first through-area on the device layer. After the device layer is bonded to the substrate, the device layer above the substrate can be exposed without scratching, thereby avoiding the risk of the dicing blade contacting the substrate metal wires and improving the MEMS inertial device fabrication yield.
[0018] 2) Compared with the traditional device layer etching, the MEMS inertial device structure and manufacturing method provided by the present invention are only concentrated in the sensitive etching area, and the etching depth and width are relatively large, resulting in uneven distribution of etching gas and poor etching uniformity of the entire wafer. When etching the device layer, the present application adds a first through-area groove in the non-sensitive area, so that the etching gas distribution is more uniform, the etching consistency of the entire wafer is better, the device layer opening is more uniform, the uniformity of the etching structure is improved, and the reliability of the MEMS inertial device is increased. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0020] Figure 1A schematic diagram of the structure of the MEMS inertial device provided by the present invention;
[0021] Figure 2 This is a structural diagram of the upper cover plate in the method for manufacturing the MEMS inertial device provided by the present invention;
[0022] Figure 3 This is a structural diagram of the bonding between the upper cover plate and the device layer in the method for manufacturing the MEMS inertial device provided by the present invention;
[0023] Figure 4 This is a schematic diagram of the graphical representation of the first bonded wafer device layer in the method for manufacturing the MEMS inertial device provided by the present invention;
[0024] Figure 5 A top view of one of the device layers in the method for manufacturing a MEMS inertial device provided by the present invention;
[0025] Figure 6 This is a schematic diagram of bonding the first bonding wafer and the substrate in the method for manufacturing the MEMS inertial device provided by the present invention.
[0026] 1-upper cover; 11-second etching area; 2-device layer; 2a-sensitive etching area; 2b-non-sensitive area; 21-first etching area; 22-dicing street; 3-substrate; 31-test PAD. DETAILED DESCRIPTION
[0027] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention. In the accompanying drawings, the sizes and relative sizes of certain parts may be exaggerated for clarity.
[0028] In the description of the present invention, unless otherwise clearly specified and limited, the terms "connection" and "connected" should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0029] In the description of the present invention, terms such as "up", "down", "left", "right", "front", and "back" and other orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings and are only for the convenience of description and simplification of operation, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, they should not be understood as limiting the present invention.
[0030] Furthermore, in the description of the present invention, the terms "first" and "second" are used solely to distinguish between features in the description and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features being described. Furthermore, features designated as "first" or "second" may explicitly or implicitly include one or more of the features.
[0031] Example 1: As shown in the attached instructions Figure 1-6 As shown, the present invention provides a MEMS inertial device structure, including an upper cover plate 1, a device layer 2 and a substrate 3 bonded in sequence from top to bottom, the device layer 2 having a sensitive etching area 2a and a non-sensitive area 2b, the sensitive etching area 2a being etched to form a sensitive structure of the inertial device, the non-sensitive area 2b being provided with a scribe line 22, the scribe line 22 being etched to form a first through-etched area 21, a plurality of test PADs 31 being provided on the substrate 3, the first through-etched area 21 being located directly above the plurality of test PADs 31.
[0032] Specifically, the inertial device comprises, from top to bottom, an upper cover plate 1, a device layer 2, and a substrate 3. The substrate 3 is equipped with multiple test pads (i.e., test pads). During the inertial device manufacturing process, the test pads need to be connected to external circuits for testing. This testing is a routine part of inertial device testing and will not be detailed here. Therefore, holes are required in the device layer 2 and upper cover plate 1 to expose the test pads, facilitating testing of the test pads on the substrate 3. The spacing between the device layer 2 and substrate 3 is typically less than 10 µm. Before bonding the substrate 3 to the device layer 2, a first through-hole area 21 is pre-cut into the device layer 2, and then the upper cover plate 1 is bonded. Before the test, no hole is opened in the upper cover 1, and the upper cover 1 can protect the test PAD and prevent the test PAD from being damaged. When testing is required, a hole can be opened in the upper cover 1 as needed to expose the test PAD for testing. The gap between the upper cover 1 and the test PAD is large, which avoids the risk of scratching the metal wire of the substrate 3 when the hole is opened in the device layer 2, and can improve the yield rate of inertial device manufacturing.
[0033] In an optimized embodiment, there are multiple first etching regions 21 distributed around the sensitive etching area. The first etching regions 21 are configured to correspond to the test PADs, and the sizes of the first etching regions 21 can be the same or different. The term "multiple" refers to two or more.
[0034] Specifically, the first cut-through region 21 runs through the thickness direction of the device layer 2 , and each of the first cut-through regions 21 may be located directly above one test PAD, or directly above multiple test PADs.
[0035] In an optimized embodiment, the first engraved area 21 is a square engraved area, and the width of the square engraved area is not less than 80 μm.
[0036] Specifically, the sensitive etched area has a depth-to-width ratio of 30:1 and can be etched using a Bosch etching process or a DRIE (deep silicon etching) process. The device layer patterning is specifically performed by coating, exposing, and developing the scribe line 22 on the device layer 2 to form a minimum 80 µm area (the resist removal area). The sensitive etched area of the device layer 2 is then DRIE (deep silicon etching) to form a silicon-etched through area. Specifically, the silicon-etched through area on the scribe line 22 forms a first etching through region 21. The sensitive etched area of the device layer 2 forms an etching pattern, thereby obtaining the sensitive structure of the inertial device. The traditional etching of the device layer 2 is only concentrated in the sensitive etching area, and the etching depth and width are relatively large, which makes the etching gas distribution uneven and the etching uniformity of the entire wafer poor. When etching the device layer 2, the present application adds two first etching areas 21 to open grooves in the non-sensitive area, and the sensitive etching area and the non-sensitive area are etched synchronously, so that the etching gas distribution is more uniform, the etching consistency of the entire wafer is better, the device layer 2 openings are more uniform, the uniformity of the etching structure is improved, and the reliability of the MEMS inertial device is increased.
[0037] In an optimized implementation manner, the device layer 2 is a low-resistance silicon wafer device layer.
[0038] In an optimized embodiment, the thickness of the device layer 2 is 30-80 μm. Before the substrate 3 and the device layer 2 are bonded, the device layer 2 may be thinned.
[0039] In an optimized embodiment, the upper cover plate 1 is provided with a second cut-through area 11, which is connected to the first cut-through area 21 to expose the multiple test PADs 31. Preferably, the second cut-through area 11 is located directly above the first cut-through area 21, and the second cut-through area 11 is connected to the first cut-through area 21. The bonding areas corresponding to the first cut-through area 21 and the second cut-through area 11 are also connected, so as to facilitate the exposure of the test PADs 31 on the substrate 3 for line testing.
[0040] In an optimized embodiment, the second perforated area 11 is provided on the upper cover 1 and extends through the thickness of the upper cover 1. The second perforated area 11 can be a circular through-hole, with one second perforated area 11 corresponding to one or more test PADs. The second perforated area 11 can also be a rectangular through-hole, with one second perforated area 11 corresponding to one or more test PADs. The second perforated area 11 is provided corresponding to the first perforated area 21, and is located directly above the first perforated area 21. The second perforated area 11 is connected to the first perforated area 21, exposing the test PAD on the substrate 3 for wiring.
[0041] Specifically, there are multiple second engraved areas 11 and they are respectively arranged in a one-to-one correspondence with the first engraved areas 21.
[0042] Specifically, the second engraved area 11 is opened on the dicing street of the upper cover plate 1 .
[0043] Example 2: The present invention further provides a method for manufacturing a MEMS inertial device structure. The MEMS inertial device structure is as described in Example 1, and the manufacturing method includes the following steps:
[0044] S1: Patterning the upper cover plate 1;
[0045] S2: Bonding the device layer 2 to the patterned upper cover plate 1 to obtain a first bonded wafer, wherein the scribe lines in the sensitive etching area and the non-sensitive area of the device layer 2 are etched to obtain the inertial device sensitive structure in the sensitive etching area of the device layer 2, and forming a first etched through area 21 on the scribe line;
[0046] S3: Bond the substrate 3 to the device layer 2 to obtain a three-layer bonded structure, recorded as the second bonded wafer, wherein the substrate 3 is bonded to the side of the device layer 2 away from the upper cover plate 1 , and the first engraved area 21 is located directly above the test PAD of the substrate 3 .
[0047] The first engraved area 21 on the device layer 2 is opened before the substrate 3 is bonded to the device layer 2. The first engraved area 21 of the device layer 2 can be opened before it is bonded to the upper cover plate 1, or opened after it is bonded to the upper cover plate 1. The opening of the first engraved area 21 is completed before the substrate 3 is bonded to the device layer 2.
[0048] In an optimized embodiment, step S3 further includes, when a test PAD needs to be connected for testing, opening a second cut-through area 11 on the upper cover plate 1 of the three-layer bonding structure, and connecting the second cut-through area 11 with the first cut-through area 21 to expose the test PAD 31. The second cut-through area 11 may have the same or different dimensions as the first cut-through area 21, and the second cut-through area 11 is located directly above the first cut-through area 21.
[0049] Specifically, the second cut-through area 11 on the upper cover plate 1 is opened before or after the substrate 3 is bonded to the first bonding wafer, and the manufacturing method of the MEMS inertial device includes the following two methods.
[0050] As one of the specific embodiments, a method for manufacturing a MEMS inertial device includes the following steps:
[0051] S100: Patterning the upper cover plate 1;
[0052] S200: Bonding the device layer 2 to the patterned upper cover plate 1, and etching the scribe lines 22 in the sensitive etching area and the non-sensitive area of the device layer 2, obtaining the inertial device sensitive structure in the sensitive etching area of the device layer 2, and forming a first etched through area 21 on the scribe line to obtain a first bonded wafer;
[0053] S300 : Bonding the substrate 3 to the first bonding wafer to obtain a second bonding wafer, wherein the substrate 3 is bonded to a side of the device layer 2 away from the upper cover 1 , and the first cut-through area 21 is located directly above the test PAD 31 of the substrate 3 .
[0054] S400 : A second through hole 11 is formed on the upper cover plate 1 , and the second through hole 11 is connected to the first through hole 21 to expose the test PAD of the substrate 3 .
[0055] After bonding the substrate 3 to the device layer 2 of the first bonding wafer, if the test PAD needs to be exposed for testing, a second cut-through area 11 is opened on the upper cover plate 1 at a position corresponding to the first cut-through area 21. The first cut-through area 21 runs through the thickness of the device layer 2, and the second cut-through area 11 runs through the thickness of the upper cover plate 1. The second cut-through area 11 is connected to the first cut-through area 21. The test PAD of the substrate 3 is located directly below the first cut-through area 21, which facilitates external connection of the test PAD for testing. The upper cover plate 1 is not opened before testing, and the upper cover plate 1 can form a protection for the test PAD.
[0056] As one of the specific embodiments, a method for manufacturing a MEMS inertial device includes the following steps:
[0057] S100: Patterning the upper cover plate 1;
[0058] S200: Bonding the device layer 2 to the patterned upper cover plate 1, and forming a first cut-through area 21 on the device layer 2 and a second cut-through area 11 on the upper cover plate 1, wherein the second cut-through area 11 is connected to the first cut-through area 21, thereby obtaining a first bonded wafer;
[0059] S300 : Bonding the substrate 3 to the first bonding wafer to obtain a second bonding wafer, wherein the substrate 3 is bonded to a side of the device layer 2 away from the upper cover 1 , and the first cut-through area 21 is located directly above the test PAD 31 of the substrate 3 .
[0060] Before bonding the substrate 3 to the first bonding wafer, the second cut-through area 11 is formed on the upper cover plate 1 to accommodate the thinner device layer 2 and further prevent scratches on the substrate's metal wires when opening holes in the upper cover plate 1. The device layer 2 is bonded to the patterned upper cover plate 1, and a first cut-through area 21 is formed on the device layer 2. A second cut-through area 11 is also formed on the upper cover plate 1. The first cut-through area 21 corresponds to the second cut-through area 11, and the second cut-through area is connected to the first cut-through area.
[0061] In an optimized embodiment, the second carved area 11 and the first carved area 21 are aligned vertically to form a through hole. Preferably, the width of the second carved area 11 is the same as that of the first carved area 21.
[0062] In an optimized embodiment, there are multiple first etching regions 21 distributed around the sensitive etching area. Multiple test PADs are provided on the substrate 3, and each first etching region 21 is located directly above one or more corresponding test PADs to meet different wiring requirements.
[0063] In the optimized implementation method, in step S2, the etching of the sensitive etching area of the device layer 2 and the etching of the dicing road in the non-sensitive area are carried out simultaneously, so that the etching gas distribution is more uniform, the etching consistency of the whole wafer is better, the device layer 2 opening is more uniform, the uniformity of the etching structure is improved, and the reliability of the MEMS inertial device is increased.
[0064] In an optimized implementation manner, before bonding the substrate 3 to the device layer 2, the device layer 2 is thinned to a thickness of 30-80 μm.
[0065] In an optimized implementation manner, the upper cover plate 1 and the device layer 2 are bonded by silicon-oxygen bonding; and the substrate 3 and the device layer 2 are bonded by gold-silicon bonding.
[0066] The preparation method of the present invention is explained below through specific examples.
[0067] S100: The upper cover plate 1 is patterned by photolithography and etching, as shown in the attached manual. Figure 2 As shown, the upper cover plate 1 is an upper cover plate wafer.
[0068] S200: A layer of silicon oxide is grown on the upper cover wafer and bonded to another low-resistance silicon wafer through silicon-oxygen bonding. The low-resistance silicon wafer is thinned to the required device thickness of 50 µm, as shown in the attached manual. Figure 3As shown, the low-resistance silicon wafer is the device layer; after the upper cover wafer is patterned, bosses are formed around the upper cover wafer, and a groove is formed in the middle. A layer of silicon oxide is grown on the boss and bonded to the device layer. After the device layer is bonded to the upper cover wafer, the groove of the upper cover wafer forms a accommodating chamber.
[0069] The scribe line in the device layer and the sensitive etching area are patterned by photolithography and DRIE (deep silicon etching). Specifically, the device layer is located at the scribe line position in the X and Y directions. After resist coating, exposure, and development, a minimum size of 80 μm area (stripping area) is formed. The sensitive etching area of the device is subjected to DRIE (deep silicon etching) to form an inertial device sensitive structure. A first through-etching area 21 is formed on the scribe line, as shown in the attached manual. Figure 4 shown.
[0070] As the instruction manual Figure 5 , which is a top view of one of the device layers obtained by the above method, specifically a schematic diagram of X and Y dicing lanes of adjacent chip device layers, wherein the X direction refers to the horizontal direction and the Y direction refers to the vertical direction.
[0071] S300: The first bonded wafer and the substrate 3 are bonded to form a three-layer bonded structure through gold-silicon bonding to obtain a second bonded wafer, as shown in the attached manual. Figure 6 As shown, the first bonded wafer is located above the substrate 3, and from bottom to top are the substrate 3, the device layer 2 and the upper cover 1 wafer. The first cut-through area is located directly above the test PAD of the substrate, and the width of the first cut-through area is not less than the width of the test PAD.
[0072] S400: As the instruction manual Figure 1 As shown, the second bonded wafer only needs to cut through the upper cover plate 1 wafer along the wafer scribing area of the upper cover plate 1 to form a second cut-through area 11. The position of the second cut-through area 11 corresponds to the position of the first cut-through area 21. The second cut-through area 11 is located directly above the first cut-through area 21. The test PAD can be exposed through the first cut-through area 21 and the second cut-through area 11 to complete the test.
[0073] Those skilled in the art will appreciate that the present invention can be implemented in many other specific forms without departing from the spirit and scope of the present invention. Although embodiments of the present invention have been described, it should be understood that the present invention should not be limited to these embodiments, and those skilled in the art can make changes and modifications within the spirit and scope of the present invention as defined by the appended claims.
Claims
1. A MEMS inertial device structure, comprising an upper cover plate, a device layer, and a substrate bonded sequentially from top to bottom, characterized in that: The device layer has a sensitive etching area and a non-sensitive area, the sensitive etching area is etched to form a sensitive structure of the inertial device, the non-sensitive area is provided with a scribe line, the scribe line is etched to form a first through-etching area, a plurality of test PADs are provided on the substrate, and the first through-etching area is located directly above the plurality of test PADs.
2. The MEMS inertial device structure according to claim 1, characterized in that: There are a plurality of first etching regions distributed around the sensitive etching area.
3. The MEMS inertial device structure according to claim 2, characterized in that: Each of the first cut-through areas is located directly above the corresponding one or more test PADs.
4. The MEMS inertial device structure according to claim 1, characterized in that: The first engraved area is a square engraved area, and the width of the square engraved area is not less than 80 μm.
5. The MEMS inertial device structure according to claim 1, characterized in that: A second cut-through area is provided on the upper cover plate, and the second cut-through area is connected to the first cut-through area to expose the plurality of test PADs.
6. A method for manufacturing a MEMS inertial device structure according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1: Patterning the upper cover; S2: bonding the device layer to the patterned upper cover plate, etching the scribe lines in the sensitive etching area and the non-sensitive area of the device layer, obtaining the inertial device sensitive structure in the sensitive etching area of the device layer, and forming a first etched through area on the scribe line; S3: Bonding the substrate and the device layer to obtain a three-layer bonding structure, wherein the first cut-through area is located directly above the test PAD of the substrate.
7. The method for manufacturing a MEMS inertial device structure according to claim 6, wherein: In the step S2, etching of the sensitive etching area of the device layer and etching of the scribe lines in the non-sensitive area are performed simultaneously.
8. The method for manufacturing a MEMS inertial device structure according to claim 6, wherein: The step S3 further includes, when a test PAD needs to be connected for testing, opening a second cut-through area on the upper cover plate of the three-layer bonding structure, and connecting the second cut-through area with the first cut-through area to expose the test PAD.
9. The method for manufacturing a MEMS inertial device structure according to claim 6, wherein: The step S3 further includes thinning the device layer before bonding the substrate to the device layer, thinning the device layer to a thickness of 30-80 μm.
10. The method for manufacturing a MEMS inertial device structure according to claim 6, wherein: The step S1 specifically includes: patterning the upper cover wafer through photolithography and etching.