A front-end detection circuit for a box-type transformer

Abstract

The application discloses a front-end detection circuit of a box-type transformer, which comprises a main control unit, wherein the main control unit comprises a plurality of field effect tubes, a plurality of diodes, a plurality of resistors, a capacitor, an inverter and a counter; a gate of a field effect tube Q1 in the plurality of field effect tubes is connected with a gate of a field effect tube Q2 and an IN-7 end, a source is connected with an anode of a diode D2 and a drain of a field effect tube Q3, a drain is connected with a drain of the field effect tube Q2 and one end of the capacitor C1; a source of the field effect tube Q2 is connected with one end of the resistor R11; a first pin of the counter U2 and the other end of the resistor R11 are connected with a power supply; a second pin is connected with a cathode of a diode D1, a cathode of the diode D2 and one end of the resistor R4; a ninth pin is connected with an output end of the inverter U1 and one end of the resistor R5; a third pin, a fourth pin, a fifth pin, a sixth pin, a tenth pin, an eleventh pin, a twelfth pin and a thirteenth pin are connected with an input end of the row resistor R6; a gate of the field effect tube Q3 is connected with the third pin of the counter U2; and an input end of the inverter U1 is connected with one end of the resistor R12 and an IN-6 end.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of transformer front-end detection, and particularly relates to a front-end detection circuit of a box-type transformer. BACKGROUND

[0002] In order to meet the needs of intensive industrial loads, multiple box-type transformers are deployed in clusters. Different specifications of transformers have different cooling requirements, and their cooling methods and cooling parameters are also different. In the prior art, in order to prevent the temperature of the transformer from being too high, a detection circuit is configured separately according to the cooling parameters of the multiple box-type transformers deployed in clusters. However, this method increases the redundancy of the lower-level circuit. Therefore, the present application provides a front-end detection circuit of a box-type transformer, which can cyclically detect multiple target feedback target detection signals, and feed back the cooling parameters of the detection unit when any target obtains a target detection signal, so as to achieve the purpose of multiple targets sharing the detection unit and reduce the redundancy of the lower-level circuit. SUMMARY

[0003] In view of the above technical problems, the present application provides a front-end detection circuit of a box-type transformer, which comprises a main control unit, the main control unit comprises a plurality of field effect tubes, a plurality of diodes, a plurality of resistors, a capacitor, an inverter, and a counter, a gate of a field effect tube Q1 in the plurality of field effect tubes is connected to a gate of a field effect tube Q2 and an IN-7 end, a source of the field effect tube Q1 is connected to an anode of a diode D2 and a drain of a field effect tube Q3, a drain of the field effect tube Q1 is connected to a drain of the field effect tube Q2 and one end of the capacitor C1, a source of the field effect tube Q2 is connected to one end of a resistor R11, a first pin of the counter U2 and the other end of the resistor R11 are connected to a power supply, a second pin of the counter U2 is connected to a cathode of the diode D1, a cathode of the diode D2, and one end of a resistor R4, a ninth pin of the counter U2 is connected to an output end of the inverter U1 and one end of a resistor R5, a third pin, a fourth pin, a fifth pin, a sixth pin, a tenth pin, an eleventh pin, a twelfth pin, and a thirteenth pin of the counter U2 are connected to an input end of a row resistor R6, a gate of the field effect tube Q3 is connected to the third pin of the counter U2, an input end of the inverter U1 is connected to one end of a resistor R12 and an IN-6 end, an anode of the diode D1 is connected to an IN-10 end, the other end of the capacitor C1, a source of the field effect tube Q3, the other end of the resistor R4, the other end of the resistor R5, the other end of the resistor R12, and an output end of the row resistor R6 are connected to the ground.

[0004] Further, the feedback unit further comprises a plurality of switches, a plurality of resistors, a diode and a flip-flop, one end of a switch S1 of the plurality of switches is connected to an IN-8 terminal, the other end is connected to an OUT-1 terminal, the positive electrode is connected to the positive electrode of a switch S2, the positive electrode of a switch S3, the positive electrode of a switch S4, the anode of a diode D5, one end of a resistor R1, one end of a resistor R3, one end of a resistor R13 and an IN-9 terminal; one end of the switch S2 is connected to the other end of the resistor R13, and the other end is connected to an OUT-3 terminal; one end of the switch S3 is connected to the other end of the resistor R1, and the other end is connected to an OUT-2 terminal; one end of the switch S4 is connected to the third pin of a flip-flop U3 and one end of a resistor R15, and the other end is connected to an IN-4 terminal; the first pin and the fourth pin of the flip-flop U3 are connected to a power supply; the cathode of the diode D5 is connected to an OUT-5 terminal; the negative electrode of the switch S1, the negative electrode of the switch S2, the negative electrode of the switch S3, the negative electrode of the switch S4, the other end of the resistor R3 and the other end of the resistor R15 are connected to the ground.

[0005] Further, the detection unit further comprises a plurality of operational amplifiers, a plurality of resistors, a plurality of diodes, a field effect transistor and a capacitor, one end of a resistor R8 and an IN-1 terminal are connected to the non-inverting input terminal of an operational amplifier U4 of the plurality of operational amplifiers, the output terminal, the non-inverting input terminal of an operational amplifier U7 and the inverting input terminal of an operational amplifier U8 are connected to the inverting input terminal of the operational amplifier U4; one end of a resistor R2 and an IN-2 terminal are connected to the non-inverting input terminal of an operational amplifier U5 of the plurality of operational amplifiers, the output terminal, the inverting input terminal of the operational amplifier U7 are connected to the inverting input terminal of the operational amplifier U5; one end of a resistor R14 and an IN-3 terminal are connected to the non-inverting input terminal of an operational amplifier U6 of the plurality of operational amplifiers, the output terminal, the non-inverting input terminal of the operational amplifier U8 are connected to the inverting input terminal of the operational amplifier U6; the output terminal of the operational amplifier U7 is connected to the anode of a diode D3; the output terminal of the operational amplifier U8 is connected to the anode of a diode D4; the gate of a field effect transistor Q4 is connected to an IN-5 terminal, the source is connected to the cathode of the diode D3, the cathode of the diode D4, one end of a capacitor C2 and an OUT-4 terminal; the other end of the resistor R2, the other end of the resistor R8, the other end of the resistor R14, the other end of the capacitor C2 and the drain of the field effect transistor Q4 are connected to the ground.

[0006] Further, the main control unit further comprises a resistor, one end of the resistor R7 is connected to the gate of the field effect transistor Q1, and the other end is connected to the ground.

[0007] Further, the feedback unit further comprises a plurality of resistors, one end of a resistor R10 of the plurality of resistors is connected to the fifth pin of a flip-flop U3; one end of a resistor R16 is connected to the second pin and the sixth pin of the flip-flop U3; the other end of the resistor R10 and the other end of the resistor R16 are connected to the ground.

[0008] Further, the detection unit further comprises a resistor, one end of the resistor R9 is connected to the gate of the field effect transistor Q4, and the other end is connected to the ground.

[0009] Further, the resistor R4 is a variable resistor.

[0010] Further, the resistor R1 and the resistor R13 are variable resistors.

[0011] The advantages of this invention compared to the prior art are:

[0012] This invention can cyclically detect multiple targets by feeding back target detection signals, and when any target obtains a target detection signal, it feeds back its own cooling parameters to the detection unit, so as to achieve the purpose of multiple targets sharing the detection unit and reducing the redundant settings of the lower-level circuit. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the main control unit structure provided by the present invention.

[0015] Figure 2 This is a schematic diagram of the feedback unit structure provided by the present invention.

[0016] Figure 3 This is a schematic diagram of the detection unit structure provided by the present invention. Detailed Implementation

[0017] To make the objectives and advantages of the present invention clearer, the present invention will be specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or more specific embodiments of the present invention and does not strictly limit the scope of protection specifically claimed by the present invention.

[0018] This invention discloses a front-end detection circuit for a box-type transformer, such as... Figure 1As shown, the system includes a main control unit, which comprises several field-effect transistors (FETs), several diodes, several resistors, capacitors, an inverter, and a counter. The gate of FET Q1 is connected to the gate of FET Q2 and the IN-7 terminal; its source is connected to the drain of FET Q3 and the anode of diode D2; and its drain is connected to the drain of FET Q2 and one end of capacitor C1. The source of FET Q2 is connected to one end of resistor R11. The first pin of counter U2 and the other end of resistor R11 are connected to the power supply; the second pin is connected to the cathodes of diodes D1 and D2 and resistor R4. One end, pin 9 is connected to the output of inverter U1 and one end of resistor R5; pins 3, 4, 5, 6, 10, 11, 12, and 13 are connected to the input of resistor array R6; the gate of MOSFET Q3 is connected to the third pin of counter U2; the input of inverter U1 is connected to one end of resistor R12 and IN-6; the anode of diode D1 is connected to IN-10; the other end of capacitor C1, the source of MOSFET Q3, the other end of resistor R4, the other end of resistor R5, the other end of resistor R12, and the output of resistor array R6 are grounded.

[0019] like Figure 2 As shown, specifically, it also includes a feedback unit, which includes several switches, several resistors, diodes, and triggers. Among the switches, one end of switch S1 is connected to the IN-8 terminal, and the other end is connected to the OUT-1 terminal. Its positive terminal is connected to the positive terminals of switches S2, S3, and S4, the anode of diode D5, one end of resistor R1, one end of resistor R3, one end of resistor R13, and the IN-9 terminal. One end of switch S2 is connected to the other end of resistor R13, and the other end is connected to the OUT-3 terminal. One end of switch S3 is connected to the other end of resistor R1, and the other end is connected to the OUT-2 terminal. One end of switch S4 is connected to the third pin of trigger U3, one end of resistor R15, and the other end is connected to the IN-4 terminal. The first and fourth pins of trigger U3 are connected to the power supply. The cathode of diode D5 is connected to the OUT-5 terminal. The negative terminals of switches S1, S2, S3, and S4, the other ends of resistor R3 and resistor R15 are grounded.

[0020] like Figure 3As shown, specifically, it also includes a detection unit, which includes several operational amplifiers, several resistors, several diodes, field-effect transistors, and capacitors. Among the several operational amplifiers, the non-inverting input of operational amplifier U4 is connected to one end of resistor R8 and the IN-1 terminal, and the inverting input is connected to the output terminal; the non-inverting input of operational amplifier U7 and the inverting input of operational amplifier U8 are also included. The non-inverting input of operational amplifier U5 is connected to one end of resistor R2 and the IN-2 terminal, and the inverting input is connected to the output terminal and the inverting input of operational amplifier U7. The non-inverting input of operational amplifier U6 is connected to one end of resistor R14 and the IN-3 terminal, and the inverting input is connected to the output terminal and the non-inverting input of operational amplifier U8. The output terminal of operational amplifier U7 is connected to the anode of diode D3; the output terminal of operational amplifier U8 is connected to the anode of diode D4; the gate of field-effect transistor Q4 is connected to the IN-5 terminal, and the source is connected to the cathodes of diodes D3 and D4, one end of capacitor C2, and the OUT-4 terminal; the other ends of resistors R2, R8, R14, and C2, and the drain of field-effect transistor Q4 are grounded.

[0021] like Figure 1 As shown, specifically, the main control unit also includes a resistor, with one end of the resistor R7 connected to the gate of the field-effect transistor Q1 and the other end grounded.

[0022] like Figure 2 As shown, specifically, the feedback unit further includes several resistors, one end of resistor R10 is connected to the fifth pin of trigger U3; one end of resistor R16 is connected to the second and sixth pins of trigger U3; and the other ends of resistor R10 and resistor R16 are grounded.

[0023] like Figure 3 As shown, specifically, the detection unit also includes a resistor, R9, with one end connected to the gate of the field-effect transistor Q4 and the other end grounded.

[0024] like Figure 1 As shown, specifically, the resistor R4 is an adjustable resistor.

[0025] like Figure 2 As shown, specifically, resistors R1 and R13 are adjustable resistors.

[0026] See Figure 1IN-7 inputs the start detection signal, and IN-6 inputs the main control unit reset signal. The start detection and reset signals are fed back from the terminal or manually. After the circuit is powered on, the power signal passes through resistor R11, the source of MOSFET Q2, and the drain of MOSFET Q2, giving capacitor C1 a certain potential. The signal at IN-7 is synchronously fed back to the gates of MOSFETs Q1 and Q2. Resistor R7 is used to discharge the parasitic capacitance of the gates of MOSFETs Q1 and Q2. When IN-7 receives the start detection signal, if the voltage difference between the gate and source of MOSFET Q2 is higher than the conduction threshold, MOSFET Q2 is turned off; if the voltage difference between the gate of MOSFET Q1 and the source of MOSFET Q2 is higher than the conduction threshold, MOSFET Q1 is turned on. The signal at terminal C1 passes through the drain and source of MOSFET Q1, diode D2, and resistor R4 to ground, causing resistor R4 to be at a high level. This causes the potential at terminal C1 to decrease, and the signal at resistor R4 is fed back to pin 2 of counter U2. Pin 8 of counter U2 receives the clock signal. Each time the clock signal is at its rising edge, pin 3 of counter U2 receives the signal from pin 2. Simultaneously, the signals at pins 3, 4, 5, 6, 10, 11, and 12 of counter U2 shift downwards. Adjusting the resistance of resistor R4 ensures that after MOSFET Q1 is turned on, the rate of potential decrease at terminal C1 remains high throughout one clock cycle, maintaining the high level signal at resistor R4. This ensures that the initial detection signal is obtained at IN-7 while the clock signal is at its rising edge. On the rising edge of the clock signal, pin 3 of counter U2 receives the signal from pin 2 of counter U2, causing pin 3 of flip-flop U3 to output a high level. Simultaneously, the signal from pin 3 of counter U2 is fed back to the gate of field-effect transistor Q3. The voltage difference between the gate and source of field-effect transistor Q3 exceeds the conduction threshold, turning on Q3. The signal at capacitor C1 passes through the drain and source of field-effect transistors Q1 and Q3, and then back to ground, causing resistor R4 to go low. Subsequently, on each rising edge of the clock signal, pins 4, 5, 6, 10, 11, 12, and 13 of counter U2 output high levels sequentially, and any one of these pins is high. When the signal level is low, the signal at this pin is the target detection signal. The signal loop terminal is set according to the number of targets detected in the loop (number of transformers). The signal at the signal loop terminal is synchronously fed back to IN-10. The range of the number of targets detected in the loop is 2-8, and the settings of the signal loop terminal correspond to pins 4, 5, 6, 10, 11, 12, and 13 of counter U2, respectively. If the number of targets detected in the loop is 8, the signal loop terminal is set to pin 13 of counter U2, so that the signal at pin 13 of counter U2 can be synchronously fed back to the IN-10 terminal. When pin 13 of counter U2 outputs a high level (i.e., when the target detection signal is output), the signal passes through diode D1 and resistor R4 to the ground terminal. The signal at the resistor R4 terminal is fed back to pin 2 of counter U2.When the clock signal is on its rising edge again, pin 3 of counter U2 receives the signal from pin 2 of counter U2 again to complete the cyclic detection. When a reset is required, the feedback of the initial detection signal stops, allowing IN-6 to receive a reset signal feedback. The reset signal is fed back to the input of inverter U1. Resistor R12 acts as a pull-down resistor for the input of inverter U1, turning inverter U1 off. Resistor R5 acts as a pull-down resistor for the output of inverter U1 and pin 9 of counter U2, making pin 9 of counter U2 low and resetting the main control unit. This allows the main control unit to cyclically feed back target detection signals to multiple targets based on the set signal loop for cyclic detection, reducing redundant settings in lower-level circuits.

[0027] See Figure 2 , Figure 3The number of feedback units is set according to the number of targets detected in the loop. Each target detection signal is input to the corresponding feedback unit IN-9. IN-8 receives the temperature signal from the temperature sensor. The signals from OUT-1, OUT-2, OUT-3, and OUT-5 of each feedback unit are input to the detection units IN-1, IN-2, IN-3, and IN-5, respectively. When any feedback unit receives a target detection signal, the signal travels through resistor R3 to the ground terminal. Simultaneously, the positive terminals of switches S1, S2, S3, and S4 synchronously receive this signal feedback. When switch S4 is closed, the temperature signal is fed back to detection unit IN-1 via switch S1 and OUT-1. Resistor R8 is a pull-down resistor for the non-inverting input of operational amplifier U4. One target detection signal is fed back to detection unit IN-2 via resistor R1, switch S3, and OUT-2. The signal at IN-2 is then fed to ground via resistor R2. The other signal is fed back to detection unit IN-3 via resistor R13, switch S2, and OUT-3. The signal at IN-3 is then fed to ground via resistor R14. Adjusting resistor R1 sets the cooling start signal, and adjusting resistor R13 sets the cooling stop signal. Adjust each resistor as needed according to the cooling method of the target. The values ​​of resistors R1 and R13 in the feedback unit are specified. IN-4 receives a temperature over-limit signal. When IN-4 receives this signal, it is fed back to pin 3 of trigger U3 via switch S4. Resistor R15 is a pull-down resistor for pin 3 of trigger U3. Pin 5 of trigger U3 receives a high level feedback. When pin 5 of trigger U3 is high, pin 6 of trigger U3 is low. Resistor R10 and R16 are pull-down resistors for pin 5 and pin 6 of trigger U3, respectively. When IN-4 receives the temperature over-limit signal again, pins 5 and 6 of trigger U3... Pin level substitution: when pin 5 of trigger U3 is low, pin 6 of trigger U3 is high. The signal acquisition of pin 5 / pin 6 of trigger U3 is selected according to the control type of the corresponding actuator control signal. When there is an upper-level connection or control, the pull-down resistor is enabled; otherwise, it is pulled down through resistors R10 and R16. In this way, when any feedback unit obtains the target detection signal, it feeds back its own cooling reference signal to the detection unit, achieving the purpose of multiple detection targets sharing the detection unit. At the same time, it allows each feedback unit to make its own selection according to the control type of its corresponding actuator control signal.

[0028] See Figure 3IN-1 inputs the transformer temperature signal, IN-2 inputs the cooling start signal, and IN-3 inputs the cooling stop signal. The cooling reference signal can be fed back from the power supply signal. When the cooling reference signal is fed back from the power supply signal, resistor R2 is the pull-down resistor for the non-inverting input of op-amp U5, and resistor R14 is the pull-down resistor for the non-inverting input of op-amp U6. When these two signals are fed back from the feedback unit, resistors R2 and R14 are the voltage divider resistors for the target detection signal. The cooling start signal and cooling stop signal are set by adjusting the resistance values ​​of resistors R1 and R13 in the feedback unit. The inverting input and output of op-amp U5 are connected for negative feedback. Op-amp U5 follows the cooling start signal. The inverting input of op-amp U6 and its output are connected with negative feedback. Op-amp U6 follows the cooling stop signal. The inverting input of op-amp U4 and its output are connected with negative feedback. Op-amp U4 follows the transformer temperature signal. The output signal of op-amp U4 is synchronously fed back to the non-inverting input of op-amp U7 and the inverting input of op-amp U8. The output signal of op-amp U5 is fed back to the inverting input of op-amp U7, and the output signal of op-amp U6 is fed back to the non-inverting input of op-amp U8. When the transformer temperature is higher than the set cooling start signal, op-amp U7 outputs; when the transformer temperature is lower than the set cooling stop signal, op-amp U8 outputs. To prevent damage when there is no signal input to IN-1, IN-2, and IN-3, op-amp U... 7 / Op-amp U8 erroneously outputs due to signal interference. The signal from the output terminal of op-amp U7 passes through diode D3, the source of MOSFET Q4, and the drain of MOSFET Q4 to ground. The signal from the output terminal of op-amp U8 passes through diode D4, the source of MOSFET Q4, and the drain of MOSFET Q4 to ground. This causes the source of MOSFET Q4 to be at a low level when op-amp U7 / op-amp U8 erroneously outputs due to signal interference. When any feedback unit receives the target detection signal, IN-2, IN-3, and IN-5 on the detection unit receive signal feedback. The signal at IN-5 is fed back to the gate of MOSFET Q4. The voltage difference between the gate and source of MOSFET Q4 is higher than the conduction threshold, and MOSFET Q4... 4. With the resistor R9 cut off, the parasitic capacitance of the gate of the field-effect transistor Q4 is discharged. At this time, when the amplitude of the transformer temperature signal is higher than the amplitude of the cooling start signal or lower than the amplitude of the cooling stop signal, causing the op-amp U7 / op-amp U8 to output, the source terminal signal of the field-effect transistor Q4 is at a high level. The capacitor C2 is used to prevent the source terminal signal of the field-effect transistor Q4 from changing abruptly. The source terminal signal of the field-effect transistor Q4 is a temperature over-limit signal. The signal is output to the feedback unit IN-4 through OUT-4. In this way, when any feedback unit obtains the target detection signal, it detects the transformer temperature based on the feedback cooling reference signal and feeds back the temperature over-limit signal, so that the corresponding actuator performs the cooling operation.

[0029] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No markings in the claims should be construed as limiting the scope of the claims.

Claims

1. A front-end detection circuit for a box-type transformer, characterized in that, The system includes a main control unit, a feedback unit, and a detection unit. The main control unit includes several field-effect transistors (FETs), several diodes, several resistors, capacitors, inverters, and a counter. Among the FETs, the gate of FET Q1 is connected to the gate of FET Q2 and the IN-7 terminal; its source is connected to the drain of FET Q3 and the anode of diode D2; its drain is connected to the drain of FET Q2 and one end of capacitor C1; the source of FET Q2 is connected to one end of resistor R11; the first pin of counter U2 and the other end of resistor R11 are connected to the power supply; the second pin is connected to the cathodes of diodes D1 and D2 and one end of resistor R4; the ninth pin is connected to the output of inverter U1 and one end of resistor R5; the third to sixth pins and the tenth to thirteenth pins are connected to the input of resistor array R6; the gate of FET Q3 is connected to the third pin of counter U2; the input of inverter U1 is connected to one end of resistor R12 and the IN-6 terminal; the anode of diode D1 is connected to the IN-10 terminal. The feedback unit includes several switches, several resistors, diodes, and a trigger. Switch S1 has one end connected to IN-8 and the other end connected to OUT-1. Its positive terminal is connected to the positive terminals of switches S2, S3, and S4, the anode of diode D5, one end of resistor R1, one end of resistor R3, one end of resistor R13, and the IN-9 terminal. Switch S2 has one end connected to the other end of resistor R13 and the other end connected to OUT-3. Switch S3 has one end connected to the other end of resistor R1 and the other end connected to OUT-2. Switch S4 has one end connected to the third pin of trigger U3, one end of resistor R15, and the other end connected to IN-4. The first and fourth pins of trigger U3 are connected to the power supply. The cathode of diode D5 is connected to the OUT-5 terminal. The detection unit includes several operational amplifiers, several resistors, several diodes, field-effect transistors, and capacitors. Among the operational amplifiers, operational amplifier U4's non-inverting input is connected to one end of resistor R8 and IN-1, its inverting input is connected to the output terminal, operational amplifier U7's non-inverting input is connected to the inverting input of operational amplifier U8, and operational amplifier U8's inverting input is connected to the non-inverting input; operational amplifier U5's non-inverting input is connected to one end of resistor R2 and IN-2, its inverting input is connected to the output terminal, and operational amplifier U7's inverting input is connected to the inverting input; operational amplifier U6's non-inverting input is connected to one end of resistor R14 and IN-3, its inverting input is connected to the output terminal, and operational amplifier U8's non-inverting input is connected to the non-inverting input; operational amplifier U7's output terminal is connected to the anode of diode D3; operational amplifier U8's output terminal is connected to the anode of diode D4; the gate of field-effect transistor Q4 is connected to the IN-5 terminal, and its source is connected to diode D...

3. Cathode, diode D4 cathode, one end of capacitor C2, OUT-4 terminal; resistors R2, R3, R4, R5, R8, R12, R14, R15, capacitors C1, and the other end of capacitor C2 are grounded; the drain of MOSFET Q4, the source of MOSFET Q3, and the output terminal of resistor array R6 are grounded; the negative terminals of switches S1, S2, S3, and S4 are grounded; the signals from OUT-1 to OUT-5 are input to IN-1 to IN-5 terminals; the reset signal, start detection signal, temperature signal, target detection signal, and loop signal are input to IN-6 to IN-10 terminals respectively.

2. The front-end detection circuit of the box-type transformer according to claim 1, characterized in that, The main control unit also includes a resistor R7, one end of which is connected to the gate of the field-effect transistor Q1, and the other end is grounded.

3. The front-end detection circuit of the box-type transformer according to claim 1, characterized in that, The feedback unit also includes resistors R10 and R16. One end of resistor R10 is connected to the fifth pin of trigger U3; one end of resistor R16 is connected to the second and sixth pins of trigger U3; and the other ends of resistors R10 and R16 are grounded.

4. The front-end detection circuit of the box-type transformer according to claim 1, characterized in that, The detection unit also includes a resistor R9, one end of which is connected to the gate of the field-effect transistor Q4, and the other end is grounded.

5. The front-end detection circuit of the box-type transformer according to claim 1, characterized in that, The resistor R4 is an adjustable resistor.

6. The front-end detection circuit of the box-type transformer according to claim 1, characterized in that, The resistors R1 and R13 are adjustable resistors.

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