Universal hardware architecture suitable for boundary scan test and use method thereof

Abstract

The invention discloses a universal hardware architecture suitable for a boundary scan test and a use method thereof. The framework comprises at least three switching type connectors which are used for the boundary scan test and are located between a to-be-tested plate and a simulation test card, and the switching type connectors comprise a first switching type connector, a second switching type connector and a third switching type connector; the first switching type connector is formed by connecting at least one switching wire and at least one switching card through a golden finger; the second switching type connector is formed by connecting at least two switching wires and at least one switching card through golden fingers; the second switching type connector is formed by connecting at least one switching line and at least two switching cards through golden fingers. According to the method, hardware does not need to be repeatedly designed, the hardware development difficulty of the boundary scan test system is remarkably reduced, the jig delivery time is shortened, design errors are effectively avoided, and compared with a customized board card, the cost is effectively reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of boundary scan testing, and in particular relates to a universal hardware architecture suitable for boundary scan testing and a method for using the same. Background Art

[0002] In the field of boundary scan test fixtures, the types of connectors to be tested on the DUT are limited. Common ones include: MCIO x4, MCIO x8, MCIO x16, MCIO x20, SLIM x4 (SLIM is the abbreviation of SLIMLINESAS, the same below), SLIM x8, PCIEx1, PCIE x4, PCIE x8, PCIE x16, USB3.0, SATA-Express, M.2, OCP, RISER, SFP, etc. Different types of connectors to be tested need to be switched out through an adapter card and finally connected to the IO resources of the boundary scan chip of the boundary scan simulation test card (DUMMY card), thereby forming an interconnection relationship in which IO can be sent and received or level reading can be effectively read, and boundary scan testing of the DUT is performed.

[0003] Different boards under test (DUTs) have different connector types, locations, and quantities. To meet the boundary scan testing requirements of different DUTs, the traditional method requires a customized boundary scan test system for each DUT, which involves redesigning the schematic, drawing the PCB board, and making the board. This boundary scan design customized for specific DUT testing is not universal and will also affect the delivery time of the boundary scan test fixture. Every hasty design may also lead to design errors.

[0004] Currently, the market only offers customized solutions for boundary scan testing of different DUTs, and a universal hardware system and design methodology have yet to be established. If the boundary scan test hardware system could eliminate the need for repetitive schematic and PCB design, and standardize the previously designed DUMMY cards, adapter cables, and adapter card hardware to meet the testing requirements of different DUTs, forming a universal system, there would be no need to redesign the hardware. Boundary scan engineers would only need to flexibly combine the boards and adapter cables used in the original DUT project, eliminating the need for repeated hardware design. This would significantly reduce the difficulty of hardware development for boundary scan test systems, save manpower and material resources, shorten fixture delivery times, and effectively avoid design errors. Furthermore, universal boards and adapter cables can be used in mass production, effectively reducing costs compared to customized boards.

[0005] Therefore, in view of the above technical problems and defects, it is urgent to design and develop a universal hardware architecture suitable for boundary scan testing and its use method. Summary of the Invention

[0006] In order to overcome the shortcomings and difficulties of the above-mentioned prior art, the purpose of the present invention is to provide a universal hardware architecture suitable for boundary scan testing and its use method, which does not require repeated hardware design, significantly reduces the difficulty of hardware development of the boundary scan test system, saves manpower and material resources, shortens the fixture delivery time, and effectively avoids design errors. In addition, universal boards and adapters can be used in mass production, which effectively reduces costs compared to customized boards.

[0007] The first object of the present invention is to provide a universal hardware architecture suitable for boundary scan testing; the second object of the present invention is to provide a method for using universal hardware suitable for boundary scan testing;

[0008] The first object of the present invention is achieved as follows: the architecture includes at least three adapter type connectors for boundary scan testing and located between the board to be tested and the analog test card, including a first adapter type connector, a second adapter type connector, and a third adapter type connector;

[0009] The first adapter type connector is composed of at least one adapter wire and at least one adapter card connected by gold fingers; the second adapter type connector is composed of at least two adapter wires and at least one adapter card connected by gold fingers; the second adapter type connector is composed of at least one adapter wire and at least two adapter cards connected by gold fingers.

[0010] Furthermore, the simulation test card is provided with at least one test unit; the test unit is provided with at least four electrically connected resistor groups, including a first resistor group; a second resistor group, a third resistor group and a fourth resistor group.

[0011] Furthermore, the simulation test card is provided with at least four SLIM x8 connectors; the chip model of the SLIM x8 connector is 10M25DAF484C8G.

[0012] Furthermore, the adapter card is provided with at least two rows of connectors, including a first differential gold finger connector and a second differential gold finger connector;

[0013] The differential sending signal pin ends in the first differential gold finger connector are staggeredly connected to the pin ends in the gold finger; the differential receiving signal pin ends in the second differential gold finger connector are sequentially connected to the pin ends in the gold finger.

[0014] The second object of the present invention is achieved as follows: the method of use is applied to the universal hardware architecture; the method of use comprises the steps of:

[0015] Determine whether the number of pins m1+v1 of the DUT connector under test J1_1 is not greater than the number of pins of the SLIM x8 connector or the gold finger, that is, m1+v1≤74; when the condition is not met, that is, m1+v1≥75, the transfer condition of the first transfer type connector is not met; when 38<m1+v1≤74, adopt the SLIM x8 interface transfer, which is suitable for the transfer of the first transfer type connector; among them, 38 is the number of pins of the SLIM x4 connector, and 38 is the limit of the number of pins of the connector under test; when the number of pins of the DUT connector under test m2+v2≥75, the transfer condition of the first transfer type connector is not met, and the transfer condition of the second transfer type connector is suitable.

[0016] Furthermore, the method of use further includes the steps of: determining whether the number of pins m2+v2 of the connector under test J2_1 of the DUT satisfies 74+1≤m2+v2≤74+38, that is, 75≤m2+v2≤112, wherein 38 represents the number of pins of the SLIM x4 connector, and 74 represents the number of pins of the SLIM x8 connector; under the above conditions, the gold fingers 2_5 and 2_4 of the adapter cable 2_2 are SLIM x8 to SLIM x4, respectively; the connector J2_3 of the adapter card 2_1 uses a SLIM x4 connector; the adapter cable 2_2 is a SLIM x8 to SLIM x4 adapter cable; the adapter cable 2_1 is fully equipped and uses a SLIM x8 to SLIM x8 adapter cable;

[0017] Determine whether the number of pins m2 + v2 on the DUT's connector (under test) J2_1 satisfies 74 + 39 ≤ m2 + v2 ≤ 74 + 74, that is, 113 ≤ m2 + v2 ≤ 148. 74 represents the number of pins on the SLIM x8 connector. Connector J2_3 on riser card 2_1 uses a SLIM x8 connector, and adapter cable 2_2 uses a SLIM x8 to SLIM x8 adapter cable. Adapter cable 2_1 is fully populated and uses a SLIM x8 to SLIM x8 adapter cable.

[0018] Furthermore, the method further comprises the steps of: determining whether the number of gold finger pins m3+v3 of the connector to be tested J3_1 satisfies 1≤m3+v3≤38, which is suitable for the transfer condition of the third transfer type connector, wherein 38 represents the number of SLIM x4 pins;

[0019] The third adapter type connector transfers the IO resources of the DUMMY card's SLIM x8 to two SLIM x4 gold fingers via adapter cable 3_1. The number of pins on the SLIM x8 is 74, while the number of pins on the SLIM x4 is 38. The total number of pins on the two SLIM x4s is 38 × 2 = 76, which is greater than 74.

[0020] The processing method for adapter cable 3_1 is as follows: The SLIM x4 gold finger 3_3 of adapter cable 3_1 is fully populated. 2×p is the maximum number of SLIM x4 gold fingers 3_3 on adapter cable 3_1. The number of I / O resources of fully populated gold fingers 3_3 is 2×p = 38. When the number of pins on J3_1 is 1≤2×m3≤2×p=38, the pin numbers of the DUT connectors to be tested, such as SLIM x4, MCIO x4, PCIE x1, PCIE x4, USB3.0, SATA-EXPRESS, and SFP, are 38, 38, 18, 32, 9, 29, and 20, respectively, and can all be transferred.

[0021] The SLIM x4 gold finger 3_5 of adapter cable 3_2 is not fully populated. The number of IO resources of the partially populated gold finger 3_5 is 2×q=74-38=36. The pin counts of the DUT connectors to be tested, such as PCIE x1, PCIE x4, USB3.0, SATA-EXPRESS, and SFP, are 18, 32, 9, 29, and 20, respectively. All of them can be transferred. However, the SLIM x4 and MCIO x4 connectors to be tested have 38 pins and cannot be fully connected to the DUMMY card's IO.

[0022] SLIM x4 gold fingers 3_5 are not fully populated. The arrangement principle is based on the pin definition order A1, B1, A2, B2.... The first 1 to 36 pins are allocated I / O resources, and pins 37 and 38 are not allocated I / O resources.

[0023] Furthermore, the method of use further comprises the steps of:

[0024] The gold finger 3_1 of the adapter card 3_1 and the gold finger 3_2 of the adapter card 3_2 are respectively determined by the type of the DUT connector J1_1 to be tested. If the pin definition of the connector is standard, the designed DUT connector adapter card to be tested is also universal.

[0025] The present invention provides a universal hardware architecture suitable for boundary scan testing, the architecture including at least three adapter-type connectors for boundary scan testing and located between a board to be tested and a simulation test card, including a first adapter-type connector, a second adapter-type connector, and a third adapter-type connector; the first adapter-type connector is composed of at least one adapter wire and at least one adapter card connected via a gold finger; the second adapter-type connector is composed of at least two adapter wires and at least one adapter card connected via a gold finger; and the second adapter-type connector is composed of at least one adapter wire and at least two adapter cards connected via a gold finger. Furthermore, a method for using the universal hardware architecture is provided. Without the need to redesign hardware, boundary scan engineers only need to flexibly combine and use the boards and adapter wire resources used in the original DUT project, eliminating the need for repeated hardware design. This significantly reduces the difficulty of hardware development for the boundary scan test system, saves manpower and material resources, shortens fixture delivery time, and effectively avoids design errors. Furthermore, the universal boards and adapter wires can be mass-produced, effectively reducing costs compared to customized boards. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 Schematic diagram of the hardware transfer type ①②③ system framework of a boundary scan test system of a universal hardware architecture suitable for boundary scan testing of the present invention;

[0028] Figure 2 Schematic diagram of the implementation framework of hardware transfer type ① of a boundary scan test system of a universal hardware architecture suitable for boundary scan testing of the present invention;

[0029] Figure 3 Schematic diagram of the implementation framework of hardware transfer type ② of a boundary scan test system of a universal hardware architecture suitable for boundary scan testing of the present invention;

[0030] Figure 4 Schematic diagram of the implementation framework of hardware transfer type ③ of a boundary scan test system of a universal hardware architecture suitable for boundary scan testing of the present invention;

[0031] Figure 5 Schematic diagram of the specific implementation framework of the hardware transfer types ①②③ of a boundary scan test system of a universal hardware architecture suitable for boundary scan testing of the present invention;

[0032] Figure 6 A schematic diagram of a universal hardware architecture suitable for boundary scan testing according to the present invention, wherein each DUMMY card is connected to multiple SLIM x8 connectors;

[0033] Figure 7 This is a schematic diagram of a specific implementation framework of a boundary scan test system hardware DDR5 connector under test according to an embodiment of the present invention, which is a universal hardware architecture suitable for boundary scan testing;

[0034] Figure 8 A schematic diagram of the smallest universal test unit framework of an embodiment of a universal hardware architecture suitable for boundary scan testing of the present invention;

[0035] Figure 9 A schematic diagram of a transfer mode framework of an adapter card of a universal hardware architecture suitable for boundary scan testing according to the present invention;

[0036] Figure 10 This is a second schematic diagram of an adapter framework of an adapter card of a universal hardware architecture suitable for boundary scan testing according to the present invention. DETAILED DESCRIPTION

[0037] In order to better understand the purpose, technical solutions and advantages of the present invention, the present invention is further described below with reference to the accompanying drawings and specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0038] The present invention may also be implemented or applied through other different specific examples, and the details in this specification may also be modified and changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0039] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.

[0040] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of such features. Secondly, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that ordinary technicians in this field can implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0041] The present invention will be further described below with reference to the accompanying drawings. Figures 1-10 As shown, the present invention provides a universal hardware architecture suitable for boundary scan testing, the architecture comprising at least three adapter type connectors for boundary scan testing and located between a board to be tested and an analog test card, including a first adapter type connector, a second adapter type connector, and a third adapter type connector;

[0042] The first adapter type connector is composed of at least one adapter wire and at least one adapter card connected by gold fingers; the second adapter type connector is composed of at least two adapter wires and at least one adapter card connected by gold fingers; the second adapter type connector is composed of at least one adapter wire and at least two adapter cards connected by gold fingers.

[0043] The simulation test card is provided with at least one test unit;

[0044] The test unit is provided with at least four electrically connected resistor groups, including a first resistor group, a second resistor group, a third resistor group and a fourth resistor group.

[0045] The simulation test card is provided with at least four SLIM x8 connectors;

[0046] The SLIM x8 connector chip model is 10M25DAF484C8G.

[0047] The adapter card is provided with at least two rows of connectors, including a first differential gold finger connector and a second differential gold finger connector;

[0048] The differential sending signal pin ends in the first differential gold finger connector are staggeredly connected to the pin ends in the gold finger; the differential receiving signal pin ends in the second differential gold finger connector are sequentially connected to the pin ends in the gold finger.

[0049] Specifically, in an embodiment of the present invention, a general hardware system suitable for boundary scan testing and a design method thereof are proposed. Designing a general hardware system suitable for boundary scan testing, applicable to general boards under test, is a challenge that needs to be overcome. The problem can be summarized into two main points:

[0050] The design of the adapter system, including all DUMMY cards, adapter cables, and adapter cards for the boundary scan hardware system, must meet the universal requirements of the hardware system. This allows the hardware components to be combined and used for different DUT boundary scan test projects without redesigning the board. Test coverage requirements must be met to ensure that all connectors under test are tested.

[0051] Table 1 Statistics of common DUT connector types and pin numbers in embodiments of the present invention

[0052] Serial number DUT connector under test Number of pins Serial number DUT connector under test Number of pins 1 MICOx4 38 11 USB 3.0 9 2 MCIOx8 74 12 SATA-Express 29 3 MCIOx16 124 13 M.2 75 4 MCIOx20 148 14 OCP 140 5 SLIMx4 38 15 RISER 280 6 SLIMx8 74 16 SFP 20 7 PCIEx1 18 17 DDR5 288 8 PCIEx4 32 9 PCIEx8 49 10 PCIEx16 82

[0053] As shown in Table 1, boundary scan testing targets the DUT's connectors under test. Each connector under test has different pin counts. To test these connectors, a universal design approach is needed to ensure that DUMMY cards, adapter cables, and adapter cards are universal across different DUT projects while achieving full test coverage.

[0054] As shown in Table 1, the number of pins on the connectors under test of different DUTs varies. Therefore, universal design not only needs to consider universality but also the full utilization of pin resources as much as possible, especially the adapter card. This involves the fixed position installation of the fixture and the docking of the connector under test of the DUT, which requires the effective implementation of the fixture space.

[0055] like Figure 1 As shown, in adapter type ①, the connector J1_3 of the DUMMY card is connected to the gold finger 1_3 at one end of the adapter cable 1_1, the gold finger 1_2 at the other end of the adapter cable 1_1 is connected to the connector J1_2 of the adapter card 1_1, and the gold finger 1_1 of the adapter card 1_1 is connected to the connector under test J1_1 of the DUT.

[0056] In adapter type ②, connector J2_4 on the DUMMY card connects to gold finger 2_3 on one end of adapter cable 2_1, and gold finger 2_2 on the other end of adapter cable 2_1 connects to connector J2_2 on adapter card 2_1. Furthermore, connector J2_5 on the analog test card connects to gold finger 2_5 on one end of adapter cable 2_2, and gold finger 2_4 on the other end of adapter cable 2_2 connects to connector J2_3 on adapter card 2_1. Connectors J2_2 and J2_3 on adapter card 2_1 are combined to gold finger 2_1 on adapter card 2_1, which then interfaces with connector J2_1 on the DUT under test.

[0057] In adapter type ③, connector J3_5 on the DUMMY card connects to gold finger 3_4 on one end of adapter cable 3_1. The resources on adapter cable 3_1 are split into two paths, connected to gold finger 3_3 and gold finger 3_5 on the other end of adapter cable 3_1. Gold fingers 3_3 and 3_5 on adapter cable 3_1 connect to connector J3_3 on adapter card 3_1 and connector J3_4 on adapter card 3_2, respectively. Gold fingers 3_1 on adapter card 3_1 and gold fingers 3_2 on adapter card 3_2 connect to connectors J3_1 and J3_2 on the DUT, respectively.

[0058] The purpose of considering three types of transfers is to improve the transfer efficiency of the DUT's connector resources and reduce the waste of transfer resources under the premise of ensuring universal transfer of the hardware system. At the same time, it ensures that the connectors transferred out by the transfer card, such as: J1_2, J2_2 and J2_3, J3_3, J3_4, save transfer space as much as possible and avoid structural interference when installing the transfer card on the fixture.

[0059] like Figure 2 As shown, the first is the DUMMY card, which has a boundary scan chip (BS chip). The reference FPGA model is 10M25DAF484C8G. The boundary scan test requires the IO pin resources of the chip. During the design, some pin resources are divided into two parts, one of which is IO_A1_1 to IO_A1_n, and the other is IO_B1_1 to IO_B1_n, corresponding to the A and B rows of the connector J1_3 respectively (the actual pins of the J1_3 connector are two symmetrical rows);

[0060] The specific conversion method inside the DUMMY card is as follows: IO_A1_1 to IO_A1_n pass through resistors R_A1_1_1 to R_A1_1_n, and then pass through resistors R_A1_3_1 to R_A1_3_n, respectively, before connecting to pins A1_3_1 to A1_3_n of connector J1_3. IO_B1_1 to IO_B1_n pass through resistors R_B1_1_1 to R_B1_1_n, and then pass through resistors R_B1_3_1 to R_B1_3_n, respectively, before connecting to pins B1_3_1 to B1_3_n of connector J1_3.

[0061] Connect one leg of resistors R_A1_2_1 to R_A1_2_n and R_B1_2_1 to R_B1_2_n to the GND pin of the JTAG connector CON1. Connect the other legs of resistors R_A1_2_1 to R_A1_2_n and R_B1_2_1 to R_B1_2_n to the remote chip pins of resistors R_A1_1_1 to R_A1_1_n and R_B1_1_1 to R_B1_1_n, respectively. Connect the other legs of resistors R_A1_3_1 to R_A1_3_n and R_B1_3_1 to R_B1_3_n to the remote connector pins.

[0062] One leg of resistors R_AB1_1 to R_AB1_n is connected to the remote connector pins of resistors R_A1_3_1 to R_A1_3_n, respectively, and the other leg is connected to the remote connector pins of resistors R_B1_3_1 to R_B1_3_n, respectively.

[0063] Next, connect adapter cable 1_1. Pins A1_3_1 to A1_3_n and B1_3_1 to B1_3_n of connector J1_3 of the DUMMY card are connected to pins a1_3_1 to a1_3_n and b1_3_1 to b1_3_n of gold finger 1_3 of adapter cable 1_1, respectively. Inside adapter cable 1_1, pins a1_3_1 to a1_3_n and b1_3_1 to b1_3_n of gold finger 1_3 are connected to pins a1_2_1 to a1_2_n and b1_2_1 to b1_2_n of gold finger 1_2, respectively.

[0064] Next is riser card 1_1. Pins a1_2_1 to a1_2_n and b1_2_1 to b1_2_n of gold finger 1_2 on riser cable 1_1 are connected to pins A1_2_1 to A1_2_m1 and B1_2_1 to B1_2_v1 of connector J1_2 on riser card 1_1, respectively. Inside riser card 1_1, pins A1_2_1 to A1_2_m1 and B1_2_1 to B1_2_v1 of connector J1_2 are connected to pins a1_1_1 to a1_1_m1 and b1_1_1 to b1_1_v1 of gold finger 1_1, respectively.

[0065] Finally, the DUT connector J1_1 is connected to the test. The gold finger 1_1 pins a1_1_1 to a1_1_m1 and b1_1_1 to b1_1_v1 of the adapter card 1_1 are connected to the pins S1_1_1 to S1_1_m1 and T1_1_1 to T1_1_v1 of the test connector J1_1 respectively.

[0066] Depend on Figure 2It can be seen that the number of pins on the DUT connector under test J1_1 is m1+v1. When the number of pins on the DUT connector under test is an even number, v1=m1. When the number of pins on the DUT connector under test is an odd number, v1=m1-1. The connector J1_2 on the adapter card 1_1 is in two symmetrical rows, AB. The DUT pins are connected to the connector J1_2 and are filled in the order of A1, B1, A2, B2, A3, B3, ...An, Bn according to J1_2. The unfilled pins are left empty. The number of pins on the DUT connector under test is not greater than the number of connected pins, 2n, that is, m1+v1≤2n, to ensure that the pins on the DUT connector under test can all be connected to the pins on the DUMMY card BS chip.

[0067] The above test type ① involves a 1-to-1 connection of the connector.

[0068] like Figure 3 As shown, combined Figure 2 and Figure 3 As shown, when the number of pins of the DUT connector to be tested is large, that is, the number of pins of the connector to be tested m2+v2>2n, Figure 2 The transfer method of transfer type ① no longer meets the transfer requirements of the DUT test connector J2_1, so transfer type ② is proposed.

[0069] First, the DUMMY card. During design, the chip pin resources are also divided into two parts. The first part is IO_A2_1 to IO_A2_n and IO_A2_(n+1) to IO_A2_2n. The second part is IO_B2_1 to IO_B2_n and IO_B2_(n+1) to IO_B2_2n. One connector is needed to complete the two-segment transfer. The transfer method is still the same as transfer type 1. Following the first connector transfer, the first section is IO_A2_1 to IO_A2_n and IO_B2_1 to IO_B2_n. The second section is IO_A2_(n+1) to IO_A2_2n and IO_B2_(n+1) to IO_B2_2n. The first section corresponds to connector J2_4, and the second section corresponds to connector J2_5.

[0070] The specific transfer method inside the DUMMY card is as follows: For the first transfer, IO_A2_1 to IO_A2_n pass through resistors R_A2_1_1 to R_A2_1_n, and then pass through resistors R_A2_3_1 to R_A2_3_n, and then connect to pins A2_3_1 to A2_3_n of connector J2_4. IO_B2_1 to IO_B2_n pass through resistors R_B2_1_1 to R_B2_1_n, and then pass through resistors R_B2_3_1 to R_B2_3_n, and then connect to pins B2_3_1 to B2_3_n of connector J2_4.

[0071] One leg of resistors R_A2_2_1 to R_A2_2_n and R_B2_2_1 to R_B2_2_n are also connected to the GND of the JTAG connector CON2. The other legs of resistors R_A2_2_1 to R_A2_2_n and R_B2_2_1 to R_B2_2_n are connected to the far chip pins of resistors R_A2_1_1 to R_A2_1_n and R_B2_1_1 to R_B2_1_n, respectively. They are also connected to the far connector pins of resistors R_A2_3_1 to R_A2_3_n and R_B2_3_1 to R_B2_3_n, respectively.

[0072] One pin of resistors R_AB2_1 to R_AB2_n is connected to the remote connector pins of resistors R_A2_3_1 to R_A2_3_n, respectively, and the other pin is connected to the remote connector pins of resistors R_B2_3_1 to R_B2_3_n, respectively.

[0073] Second-stage transfer: IO_A2_(n+1) to IO_A2_2n pass through resistors R_A2_1_(n+1) to R_A2_1_2n, then through resistors R_A2_3_(n+1) to R_A2_3_2n, before connecting to pins A2_3_(n+1) to A2_3_2n of connector J2_5. IO_B2_(n+1) to IO_B2_2n pass through resistors R_B2_1_(n+1) to R_B2_1_2n, then through resistors R_B2_3_(n+1) to R_B2_3_2n, before connecting to pins B2_3_(n+1) to B2_3_2n of connector J2_5.

[0074] One leg of resistors R_A2_2_(n+1) to R_A2_2_2n and R_B2_2_(n+1) to R_B2_2_2n are also connected to the GND pin of JTAG connector CON2. The other legs of resistors R_A2_2_(n+1) to R_A2_2_2n and R_B2_2_(n+1) to R_B2_2_2n are connected to resistors R_A2_1_(n+1) to R_A2_1_2n and R_B2_1_(n+1) to R_B2_1_2n, respectively. _2n far chip pin ends, and are respectively connected to the far connector pins of resistors R_A2_3_(n+1) to R_A2_3_2n and R_B2_3_(n+1) to R_B2_3_2n; one leg of resistors R_AB2_(n+1) to R_AB2_2n is connected to the near connector pins of resistors R_A2_3_(n+1) to R_A2_3_2n, and the other leg is connected to the near connector pins of resistors R_B2_3_(n+1) to R_B2_3_2n.

[0075] Next is adapter cable 2_1. Pins A2_3_1 to A2_3_n and B2_3_1 to B2_3_n of connector J2_4 on the DUMMY card are connected to pins a2_3_1 to a2_3_n and b2_3_1 to b2_3_n of gold finger 2_3 on adapter cable 2_1, respectively. Inside adapter cable 2_1, pins a2_3_1 to a2_3_n and b2_3_1 to b2_3_n of gold finger 2_3 are connected to pins a2_2_1 to a2_2_n and b2_2_1 to b2_2_n of gold finger 2_2, respectively.

[0076] Pins A2_3_(n+1) to A2_3_2n and B2_3_(n+1) to B2_3_2n of connector J2_5 of the DUMMY card are connected to pins a2_3_(n+1) to a2_3_2n and b2_3_(n+1) to b2_3_2n of gold finger 2_5 of adapter cable 2_2, respectively. Inside adapter cable 2_2, pins a2_3_(n+1) to a2_3_2n and b2_3_(n+1) to b2_3_2n of gold finger 2_5 are connected to pins a2_2_(n+1) to a2_2_2n and b2_2_(n+1) to b2_2_2n of gold finger 2_4, respectively.

[0077] Next, we have riser card 2_1. Pins a2_2_1 to a1_2_n and b2_2_1 to b2_2_n of gold finger 2_2 on riser cable 2_1 are connected to pins A2_2_1 to A2_2_n and B2_2_1 to B2_2_n of connector J2_2 on riser card 2_1, respectively. Inside riser card 2_1, pins A2_2_1 to A2_2_n and B2_2_1 to B2_2_n of connector J2_2 are connected to pins a2_1_1 to a2_1_n and b2_1_1 to b2_1_n of gold finger 2_1, respectively. This first stage of the transition is a full-match transition.

[0078] Pins a2_2_(n+1) to a1_2_2n and b2_2_(n+1) to b2_2_2n of gold finger 2_4 on adapter cable 2_2 are connected to pins A2_2_(n+1) to A2_2_2n and B2_2_(n+1) to B2_2_2n of connector J2_3 on adapter card 2_1, respectively. Inside adapter card 2_1, pins A2_2_1 to A2_2_m2 and B2_2_1 to B2_2_v2 of connector J2_3 are connected to pins a2_1_(n+1) to a2_1_m2 and b2_1_(m+1) to b2_1_v2 of gold finger 2_1, respectively.

[0079] Finally, the DUT's connector under test J2_1 is connected. Pins a2_1_1 to a2_1_m2 of the gold finger 2_1 of the adapter card 2_1 are connected to pins S2_1_1 to S2_1_m2 of the connector under test J2_1, respectively. Pins b2_1_1 to b2_1_v2 of the gold finger 2_1 of the adapter card 2_1 are connected to pins T2_1_1 to T2_1_v2 of the connector under test J2_1, respectively.

[0080] Follow the principle of first arranging the pin resources of the riser card 2_1 connector J2_2, and then arranging the resources of the riser card 2_1 connector J2_3, and arrange them in the order of A1, B1, A2, B2, A3, B3, ... A2n, B2n. Then the pins of J2_2 and the DUT connector to be tested will be fully matched, and J2_3 will be connected to the remaining pins of the DUT connector to be tested.

[0081] When the number of pins m2+v2 of the DUT connector J2_1 to be tested is an even number, v2=m2; when the number of pins m2+v2 of the DUT connector J2_1 to be tested is an odd number, v2=m2-1.

[0082] The resources of adapter cables 2_1 and 2_2 are combined through connectors J2_2 and J2_3 on adapter card 2_1, and then transferred to the only gold finger 2_1 on adapter card 2_1. Gold finger 2_1 connects to the DUT connector under test J2_1, thereby allocating the pins of all DUT connectors under test to the BS chip IO resources. If the DUT has more connectors under test, and the two connectors J2_4 and J2_5 on the DUMMY card still cannot allocate enough, three or more connectors can be used using the same method to meet general hardware design requirements.

[0083] like Figure 4 As shown, combined Figure 2 and Figure 4 As shown, when the number of pins of the DUT connector is small, that is, the number of pins of the DUT connector J3_1 to be tested m3≤p, and the number of pins of the DUT connector J3_2 to be tested m4≤q, the transfer type ③ is suitable;

[0084] First, the DUMMY card. During design, the chip pin resources are divided into two parts. The first part is IO_A3_1 to IO_A3_(n / 2) and IO_B3_1 to IO_B3_(n / 2). The second part is IO_A4_1 to IO_A4_(n / 2) and IO_B4_1 to IO_B4_(n / 2).

[0085] Part 1: IO_A3_1 to IO_A3_(n / 2) pass through resistors R_A3_1_1 to R_A3_1_(n / 2), then through resistors R_A3_3_1 to R_A3_3_(n / 2), before connecting to pins A3_3_1 to A3_3_(n / 2) of connector J3_5. IO_B3_1 to IO_B3_(n / 2) pass through resistors R_B3_1_1 to R_B3_1_(n / 2), then through resistors R_B3_3_1 to R_B3_3_(n / 2), before connecting to pins B3_3_1 to B3_3_(n / 2) of connector J3_5.

[0086] One leg of resistors R_A3_2_1 to R_A3_2_(n / 2) and R_B3_2_1 to R_B3_2_(n / 2) are also connected to the GND pin of the JTAG connector CON3. The other legs of resistors R_A3_2_1 to R_A3_2_(n / 2) and R_B3_2_1 to R_B3_2_(n / 2) are connected to the remote chip pins of resistors R_A3_1_1 to R_A3_1_(n / 2) and R_B3_1_1 to R_B3_1_(n / 2), respectively. They are also connected to the remote connector pins of resistors R_A3_3_1 to R_A3_3_(n / 2) and R_B3_3_1 to R_B3_3_(n / 2), respectively.

[0087] One leg of resistors R_AB3_1 to R_AB3_(n / 2) is connected to the remote connector pins of resistors R_A3_3_1 to R_A3_3_(n / 2), and the other leg is connected to the remote connector pins of resistors R_B3_3_1 to R_B3_3_(n / 2).

[0088] Part 2: IO_A4_1 to IO_A4_(n / 2) pass through resistors R_A4_1_1 to R_A4_1_(n / 2), and then pass through resistors R_A4_3_1 to R_A4_3_(n / 2) before being connected to pins A4_3_1 to A2_3_(n / 2) of connector J3_5. IO_B4_1 to IO_B4_(n / 2) pass through resistors R _B4_1_1 to R_B4_1_(n / 2), and then pass through resistors R_B4_3_1 to R_B4_3_(n / 2), and then connect to pins B4_3_1 to B2_3_(n / 2) of connector J3_5 respectively; one leg of resistors R_A4_2_1 to R_A4_2_(n / 2) and R_B4_2_1 to R_B4_2_(n / 2) are also all connected to JT Connect the GND pin of AG connector CON3. The other legs of resistors R_A4_2_1 to R_A4_2_(n / 2) and R_B4_2_1 to R_B4_2_(n / 2) are connected to the remote chip pins of resistors R_A4_1_1 to R_A4_1_(n / 2) and R_B4_1_1 to R_B4_1_(n / 2), respectively. They are also connected to the remote connector pins of resistors R_A4_3_1 to R_A4_3_(n / 2) and R_B4_3_1 to R_B4_3_(n / 2), respectively. Resistors R_AB4_1 to R_AB4_(n / 2) each have one leg connected to the remote connector pins of resistors R_A4_3_1 to R_A4_3_(n / 2), and the other leg connected to the remote connector pins of resistors R_B4_3_1 to R_B4_3_(n / 2), respectively.

[0089] Next, connect pins A3_3_1 to A3_3_(n / 2) and B3_3_1 to B3_3_(n / 2) of connector J3_5 on the DUMMY card to pins a3_3_1 to a3_3_(n / 2) and b3_3_1 to b3_3_(n / 2) of gold finger 3_4 on adapter cable 3_1, respectively.

[0090] Pins A4_3_1 to A4_3_(n / 2) and B4_3_1 to B4_3_(n / 2) of the DUMMY card connector J3_5 are connected to pins a4_3_1 to a4_3_(n / 2) and b4_3_1 to b4_3_(n / 2) of the gold finger 3_4 of the adapter cable 3_1, respectively. Inside the adapter cable 3_1, pins a3_3_1 to a3_3 _p and b3_3_1 to b3_3_p are connected to pins a3_2_1 to a3_2_p and b3_2_1 to b3_2_p of gold finger 3_3 respectively; pins a4_3_1 to a4_3_q and b4_3_1 to b4_3_q of gold finger 3_4 are connected to pins a4_2_1 to a4_2_q and b4_2_1 to b4_2_q of gold finger 3_5 respectively;

[0091] Then, the riser cards 3_1 and 3_2 are connected. Pins a3_2_1 to a3_2_(n / 2) and b3_2_1 to b3_2_(n / 2) of the gold fingers 3_3 of the riser cable 3_1 are connected to pins A3_2_1 to A3_2_(n / 2) and B3_2_1 to B3_2_(n / 2) of the connector J3_3 of the riser card 3_1, respectively.

[0092] Pins a4_2_1 to a4_2_(n / 2) and b4_2_1 to b4_2_(n / 2) of the gold finger 3_5 of the adapter cable 3_1 are connected to pins A4_2_1 to A4_2_(n / 2) and B4_2_1 to B4_2_(n / 2) of J3_4 of the adapter card 3_2, respectively. Inside the adapter card 3_1, pins A3_2_1 to A3_2_m3 and B3_2_1 to B3_2_v3 of J3_3 are connected to pins a3_1_1 to a3_2_m3 and b4_1_1 to b4_2_v3 of the gold finger 3_1, respectively. Inside the adapter card 3_2, pins A4_2_1 to A4_2_m4 and B4_2_1 to B4_2_v4 of J3_4 are connected to pins Pins a4_1_1 to a4_2_m4 and b4_1_1 to b4_2_v4 of gold finger 3_2; finally, the DUT connectors under test J3_1 and J3_2. Pins a3_1_1 to a3_1_m3 and b3_1_1 to b3_1_v3 of gold finger 3_1 of adapter card 3_1 are connected to pins S3_1_1 to S3_1_m3 and T3_1_1 to T3_1_v3 of DUT connector under test J3_1, respectively. Pins a4_1_1 to a4_1_m4 and b4_1_1 to b4_1_v4 of gold finger 3_2 of adapter card 3_2 are connected to pins S4_1_1 to S4_1_m4 and T4_1_1 to T4_1_v4 of DUT connector under test J3_2, respectively.

[0093] In order to ensure that each pin of the DUT can be allocated to the IO resources of the DUMMY card, the number of pins of the DUT connector J3_1 to be tested is m3+v3, which must satisfy m3+v3≤2×p, and the number of pins of the DUT connector J3_2 to be tested is m4+v4, which must satisfy m4+v4≤2×q.

[0094] In adapter type ③, adapter cable 3_1 has one gold finger 3_4 at one end and two gold fingers, gold finger 3_3 and gold finger 3_5, at the other end. This splits the IO resources of gold finger 3_4 into two. These are then connected to the DUT's test connectors J3_1 and J3_2, respectively, through adapter cards 3_1 and 3_2. This ensures maximum utilization of IO test resources while meeting the requirements of a common hardware system.

[0095] like Figure 5 As shown, combined Figure 1 and Figure 5 As shown, Figure 5 Compared to Figure 1 For more details, please explain the adapter cables and adapter cards required for the transfer, as well as the specific types of connectors and gold fingers.

[0096] Figures 2 to 4 Combined with Figure 5 As shown, Figure 5 Detailed display of three common implementation methods of transfer types ①②③, Figure 2 correspond Figure 5 The transfer type shown is ①, Figure 2 The DUMMY card connector J1_3, the adapter cable 1_1 gold finger 1_3 and gold finger 1_2, and the connector J1_2 correspond to Figure 5 SLIM x8 connector, SLIM x8 gold finger and SLIM x8 gold finger, and SLIM x8 connector,

[0097] The conditions for applying transfer type ① are analyzed as follows:

[0098] Taking the SLIM x8 gold finger and connector transfer implementation as an example, first of all, it is necessary to meet the pin number m1+v1 of the DUT test connector J1_1 is not greater than the pin number of the SLIM x8 connector or gold finger, that is, m1+v1≤74. When the condition is not met, that is, m1+v1≥75, the transfer condition of transfer type ① is not met (transfer type ② will be considered later). When m1+v1≤74 is met, but the number of pins of the test connector m1+v1 is very small, for example, m1+v1=20, although m1+v1≤74 is met, the general design requirements can be met, but it will cause excessive IO resource transfer waste, and the test connector adopts SLIM x8 interface transfer, which requires a larger implementation space and is not suitable for transfer type ① (this scenario will be considered later for transfer type ③ implementation); when 38<m1+v1≤74 (38 is the number of SLIM x4 connector pins, and 38 is the limit of the number of pins of the test connector), SLIM is used. x8 interface transfer, it is believed that it will not cause excessive waste of IO resources, and this is suitable for the implementation of transfer type ① of the present invention.

[0099] As shown in Table 1, the connectors to be tested of the DUT are MCIO x8, SLIM x8, and PCIE x8. The number of pins of these connectors are 74, 74, and 49 respectively, which all satisfy 38<m1+v1≤74, and are suitable for transfer test of transfer type ①.

[0100] In addition, the gold finger 1_1 of the adapter card 1_1 is determined by the type of the DUT connector J1_1 and is compatible with the DUT connector test docking requirements. If the pin definition of the connector is standard, the designed DUT connector adapter card is also universal.

[0101] Figure 3 correspond Figure 5 The transfer type shown is ②, Figure 3 The DUMMY card connector J2_4 and connector J2_5, the adapter cable 2_1 gold finger 2_3 and gold finger 2_2, the adapter cable 2_2 gold finger 2_5 and gold finger 2_4, the adapter card 2_1 connector J2_2 and J2_3, respectively correspond to Figure 5 DUMMY card SLIM x8 connector and SLIM x8 connector, adapter cable 2_1 gold finger SLIM x8 and gold finger SLIM x8, adapter cable 2_2 gold finger SLIM x8 and gold finger SLIM x8 (or gold finger SLIM x4), adapter card 2_1 connector SLIM x8 and connector SLIM x8 (or connector SLIM x4);

[0102] The conditions for applying transfer type ② are analyzed as follows: when the number of pins on the DUT connector to be tested, m2+v2, is ≥ 75, the transfer condition of transfer type ① is not met, and transfer type ② of the present invention is suitable. Transfer type ② is divided into two scenarios. Transfer type ② scenario 1: The number of pins on the DUT connector to be tested, m2+v2, satisfies 74+1≤m2+v2≤74+38, that is, 75≤m2+v2≤112, where 38 represents the number of pins on the SLIM x4 connector and 74 represents the number of pins on the SLIM x8 connector.

[0103] Under this condition, the gold fingers 2_5 and 2_4 of adapter cable 2_2 are SLIM x8 to SLIM x4 respectively. The connector J2_3 of adapter card 2_1 will use the SLIM x4 connector. Adapter cable 2_2 is a SLIM x8 to SLIM x4 adapter cable. In addition, adapter cable 2_1 is fully equipped and uses a SLIM x8 to SLIM x8 adapter cable.

[0104] As shown in Table 1, the connectors under test of the DUT are PCIE x16 and M.2, with 82 and 75 pins respectively, satisfying 75≤m2≤112. The number of pins of these connectors meets the transfer conditions of transfer type ② Scenario 1, so the transfer method of transfer type ② Scenario 1 is adopted;

[0105] Adapter Type ② Scenario 2: The number of pins on the DUT's connector J2_1 (m2 + v2) satisfies 74 + 39 ≤ m2 + v2 ≤ 74 + 74, that is, 113 ≤ m2 + v2 ≤ 148, where 74 represents the number of pins on the SLIM x8 connector. To accommodate the above adapter, connector J2_3 on riser card 2_1 uses a SLIM x8 connector, and adapter cable 2_2 uses a SLIM x8 to SLIM x8 adapter cable. In addition, adapter cable 2_1 is fully populated and also uses a SLIM x8 to SLIM x8 adapter cable.

[0106] As shown in Table 1, the DUT's connectors under test are MCIO x16, MCIO x20, and OCP, with pin counts of 124, 148, and OCP, respectively. (The number of pins is 113 ≤ m2 ≤ 148.) These connectors meet the requirements for transfer type 2, scenario 2, and therefore are transferred using the method for transfer type 2, scenario 2. Similarly, when the DUT connector has a larger pin count, such as a riser connector with 280 pins, the method for transfer type 2 can still be expanded and implemented, requiring four SLIM x8 transfer cables. Furthermore, the gold finger 2_1 of transfer card 2_1 is determined by the type of the DUT's connector under test, J2_1, and is compatible with the DUT's connector under test test requirements. If the connector pin definition is standard, the designed DUT connector under test transfer card is also universal.

[0107] Figure 4 correspond Figure 5 The transfer type shown is ③, Figure 4 The DUMMY card connector J3_5, the adapter cable 3_1 gold finger 3_4, gold finger 3_3 and gold finger 3_5, the adapter card 3_1 connector J3_3, the adapter card 3_2 connector J3_4, respectively correspond to Figure 5 DUMMY card SLIM x8 connector, SLIM x8 gold finger, SLIM x4 gold finger and SLIM x4 gold finger of adapter cable 3_1, SLIM x4 connector of adapter card 3_1, SLIM x4 connector of adapter card 3_2,

[0108] The conditions for applying transfer type ③ are analyzed as follows: when the number of gold finger pins m3+v3 of the connector under test J3_1 satisfies 1≤m3+v3≤38, 38 represents the number of SLIM x4 pins, that is, the number of pins m3+v3 of the connector under test is very small. At this time, if a SLIM x8 connector is used for transfer, although it meets the requirements of general design, it will cause excessive waste of IO resource transfer and require a larger implementation space. In this case, transfer type ③ is suitable; the important content of transfer type ③ is to transfer the IO resources of the SLIM x8 of the DUMMY card to two SLIM x4 gold fingers through the transfer line 3_1. There is a problem that needs to be considered here. The number of pins of SLIM x8 is 74, while the number of pins of SLIM x4 is 38. The total number of pins of the two SLIM x4 is 38×2=76>74. Therefore, if you want to make full use of SLIM x4 resources, so the adapter cable 3_1 and adapter cable 3_2 cannot achieve full IO resource transfer at the same time. In this case, the processing method of adapter cable 3_1 is as follows: the SLIM x4 gold finger 3_3 of adapter cable 3_1 is fully configured, 2×p is the fully configured number of adapter cable 3_1, and p corresponds to Figure 4 The IO resource quantity of the fully equipped gold finger 3_3 is 2×p=38. When the pin quantity of J3_1 is 1≤2×m3≤2×p=38, such as SLIM x4, MCIO x4, PCIE x1, PCIE x4, USB3.0, SATA-EXPRESS, SFP, the pin quantities of these DUT connectors to be tested are 38, 38, 18, 32, 9, 29, and 20 respectively, and they can all be transferred; the SLIM x4 gold finger 3_5 of the adapter cable 3_2 is not fully equipped, and q corresponds to Figure 40, SATA-EXPRESS, SFP, these DUT connectors have 18, 32, 9, 29, and 20 pins, respectively, which can all be transferred. However, the connectors SLIM x4 and MCIO x4 to be tested have 38 pins, which cannot all be connected to the IO of the DUMMY card. The SLIM x4 gold finger 3_5 is not fully populated. The arrangement principle is to allocate IO resources to the first 1 to 36 pins according to the pin definition order A1, B1, A2, B2..., and the 37th and 38th pins are not allocated IO resources. The adapter cable 3_1 is processed in the above manner to make full use of the IO resources transferred from the SLIM x8 connector of the DUMMY card, completing the allocation of 1 SLIM x8 gold finger to 2 SLIM x4 gold fingers. According to the actual pin situation of the connector to be tested on the DUT, the fully populated and partially populated SLIM The x4 gold fingers can be used flexibly. In addition, the gold fingers 3_1 of the adapter card 3_1 and the gold fingers 3_2 of the adapter card 3_2 are determined by the type of the DUT connector J1_1, respectively, and are also compatible with the test docking requirements of the DUT connector. If the pin definition of the connector is standard, the designed DUT connector adapter card is also universal.

[0109] In summary, the pin count of the SLIM x8 connector is moderate for common DUT connections. Therefore, based on adapter type ①, consider adapter type ②, where the DUT connector has more pins than the SLIM x8, and adapter type ③, where the DUT connector has significantly fewer pins than the SLIM x8.

[0110] Table 2 Statistics of adapter card configurations of DUT connectors of different types and pin numbers according to embodiments of the present invention

[0111]

[0112]

[0113] Table 2 lists the common DUT connector types to be tested, the pin count of each connector, and the adapter form. Except for the DDR5 connector, all other connectors to be tested have adapter forms based on the pin count of each connector to ensure consistency between the adapter card and the adapter end of the adapter cable. The adapter cards described in the three adapter types only have two connectors: SLIM x4 and SLIM x8, thus supporting universal adapter requirements.

[0114] like Figure 6 As shown, Figures 2 to 5 and Figure 6As shown, the DUMMY card connector implemented in the present invention uniformly adopts a SLIM x8 connector. The reference chip is 10M25DAF484C8G, which can be transferred to 4 SLIM x8s, and the IO resources are fully equipped. If a chip with more pins is selected, more SLIM x8 connectors can be transferred, which can be flexibly used for the transfer types ①②③.

[0115] The present invention is not limited to the above-mentioned connectors to be tested. There are many other DUT connectors to be tested that are not listed here. They can be implemented in the same way. Figures 2 to 5 From the implementation content of the three types of connectors to be tested, it can be seen that the system's adapter cables only include the SLIM x8 to SLIM x8 adapter cable and the SLIM x8 to SLIM x4 adapter cable. Combined with the implementation content, it can be seen that the SLIM x8 to SLIM x8 adapter cable will be used in test types ① and ②. In addition, the adapter type ③, the SLIM x8 to 2 SLIMx4 adapter cable 3_1, can provide up to 2 SLIM x8 to SLIM x4 resources and is compatible with 2 connectors to be tested. Combined with the implementation content, it can be seen that the SLIM x8 to 2 SLIM x4 adapter cable must be used in test type ③ and will be used in test type ② in scenario 1, so as to achieve the purpose of making full use of IO resources as much as possible. The system hardware type is simple and the hardware is universal, which will be suitable for general boundary scan test scenarios.

[0116] like Figure 7 As shown, the DDR5 connector to be tested is usually formed in a DIMM group, which is not convenient to transfer through an adapter cable. Therefore, a DDR5 DUMMY card is provided. The gold fingers of the DDR5 DUMMY card are directly connected to the connector of the DDR5 adapter card. Finally, the gold fingers of the DDR5 adapter card are connected to the DDR5 connector to be tested of the DUT.

[0117] Table 3 Statistics of common hardware types for other system designs

[0118]

[0119] As shown in Table 3, combined Figures 2 to 7 As can be seen from the implementation of the connector under test, in addition to the adapter card for the DUT connector under test in Table 2, the BSI hardware system only includes a DUMMY card, a DDR5 DUMMY card, a SLIM x8 to SLIM x8 adapter cable, and a SLIM x8 to two SLIM x4 adapter cables. Therefore, the hardware types are few and can be flexibly combined, making it suitable for all boundary scan test automation test projects and universal.

[0120] like Figure 8 As shown, Figure 8 Originated from Figure 2, taking the connection relationship between DUMMY card IO_A1_1 and IO_B1_1 as an example, the specific connection relationship will not be repeated. Figures 2 to 4 and Figure 8 As shown, transfer types ①②③ are all made by Figure 8 In order to achieve universal design of coverage, the resistance design in the minimum universal test unit is very important.

[0121] The resistors are divided into 4 groups. The first group is R_A1_1_1 and R_B1_1_1, the second group is R_A1_2_1 and R_B1_2_1, the third group is R_A1_3_1 and R_B1_3_1, and the fourth group is R_AB1_1. To achieve universal hardware system, it is also necessary to consider achieving the best test effect. In practical applications, according to actual test needs, the resistors of the smallest universal test unit can be flexibly adjusted to determine whether to use chips or not, and the chip resistance value can be flexibly adjusted to achieve the purpose of comprehensive test coverage and achieve the purpose of eliminating the need for secondary circuit board design for the hardware system.

[0122] In order to achieve the goal of testing everything that needs to be tested, the following adjustments need to be made to the resistance of the minimum common test unit:

[0123] Test type 1: When the DUT test board connector pins A1_1_1 and B1_1_1 are both ordinary signal pins, these signals can be connected to the IO resources of the DUMMY card to implement the transceiver test. To implement the test, all resistors in Group 1 and Group 4 are disconnected, and all resistors in Group 2 and Group 3 are connected through 0Ω resistors or small resistor patches, such as small 33 ohm resistor patches. This can implement the transceiver test between the DUMMY card IO_A1_1 and IO_B1_1 and the DUT chip pins corresponding to the DUT connector pins A1_1_1 and B1_1_1, thereby detecting whether the connection between the DUT test connector pins A1_1_1 and B1_1_1 and the internal chip pins is faulty.

[0124] Test type 2: Implements AC differential signaling, that is, the transceiver test between TX and RX signals. For this signal test, ordinary DUMMY cards do not support the 1149.6 protocol and cannot be tested by directly connecting to the DUMMY card IO resources. To effectively test this, a 0Ω resistor needs to be attached to the fourth resistor group R_AB1_1 (in a short-circuit state), and all resistor positions in the other three groups need to be left unattached (in a disconnected state). This allows the DUT's internal chip to transmit and receive differential signals, thereby testing the DUT's internal connection between the differential signal pins A1_1_1 and B1_1_1 of the test board connector for faults.

[0125] Test type 3: When the DUT connector pins A1_1_1 and B1_1_1 are GND signal pins, for effective testing, all resistors in Groups 2 and 4 are disconnected. All resistors in Groups 1 and 3 are connected through 0Ω resistors or resistors of a certain value, such as 500Ω. The FPGA has a default weak pull-up. This allows the DUMMY IO_A1_1 and IO_B1_1 to read a valid level of 0, respectively. This tests whether the internal GND connections of DUT connector pins A1_1_1 and B1_1_1 are faulty.

[0126] Test type 4: When the DUT connector pins A1_1_1 and B1_1_1 are power signals, in order to achieve the purpose of effective testing, the fourth group of resistors is not mounted and remains disconnected. The second and third groups of resistors are used to complete the voltage division of the power signals of the DUT connector pins A1_1_1 and B1_1_1, respectively. For example, the DUT connector pins A1_1_1 and B1_1_1 are 12V and 3.3V power signals, respectively. Assume that the high level standard received by the DUMMY card IO_A1_1 and IO_B1_1 is 3.3V.

[0127] The 12V power supply can be divided by 10kΩ and 36.4kΩ, that is, the second resistor R_A1_2_1 and the third resistor R_A1_3_1 are 10kΩ and 36.4kΩ respectively. The larger the resistance, the better the current limiting protection. The first resistor R_A1_1_1 can be 0 ohm or a certain resistance value, such as 100Ω.

[0128] The 3.3V power supply does not require voltage division. That is, the second group of resistors and R_B1_2_1 and the third group of resistors R_B1_3_1 are 10kΩ and 0Ω respectively. The purpose of pulling 10kΩ down to GND is to ensure that the high level read by the DUMM end is a valid level. The first group of resistors R_B1_1_1 has a certain resistance, such as 1kΩ, to prevent the 3.3V power supply from being directly connected to the IO of the DUMMY card, thereby respectively realizing the effective level test of the internal power supply of the DUT test connector pins A1_1_1 and B1_1_1. Similarly, the DUT test board connector pins A1_1_1 and B1_1_1 may be pull-up and pull-down signals with a certain resistance inside the DUT, not pure power or GND signals. You only need to flexibly adjust the voltage divider resistors and implement it according to the GND and power pin test method.

[0129] Note 1: Sometimes the DUMMY card link is relatively long. Therefore, connecting to a common GND through the JTAG connector may cause test instability. It is necessary to be able to flexibly obtain GND directly from the DUT's connector to share the GND with the DUMMY card to ensure test stability. This can be achieved as follows: when the DUT's internal GND pin is connected to the DUT's internal GND pin, the first resistor group A1_1_1 is not patched and remains disconnected to prevent a direct short circuit between the DUT's connector pin GND and the DUMMY card's IO_A1_1. The fourth resistor group is not patched, and 0Ω resistors are applied to the second resistor group A1_2_1 and the second resistor group A1_3_1. The DUT's connector is directly connected to the DUMMY to achieve a more stable test result.

[0130] The above demonstrates the flexibility of the minimum test unit in adapting to various test scenarios. By using resistor patches, it can flexibly adapt to various test types and adjust stability. This extends to the entire test system, which is built entirely from the smallest universal test units. Each minimum unit in the system can flexibly adapt to various test types through resistor patches, thus meeting general test requirements and achieving the full test effect of boundary scan.

[0131] After the PCB hardware of the entire system is designed once, it can be universally applied to the boundary scan test items of different DUTs without the need to re-print the board. All test results that should be tested are completed through the resistor patch of the above minimum resistance test unit. When designing later, the resistors of the DUMMY card can be flexibly patched.

[0132] As shown in Figure 9, combined Figures 1 to 9 In the embodiment of the present invention, the connector J1 that connects the adapter card 1 to the connecting line end adopts a SLIM x4 or SLIM x8 connector, both of which are connectors with symmetrical rows A and B. The DUT connector that connects to the gold finger 1 may be a connector with symmetrical rows A and B, or an asymmetrical connector. The a3 and a4 pins of the gold finger 1 of the adapter card 1 are differential transmission signals TX1_DP and TX1_DN respectively, and the b3 and b4 pins are differential reception signals RX1_DP and RX1_DN. It can be seen that the pins can be directly matched in order to achieve Figure 8 The measurable condition of the smallest universal test unit resistor R_AB1_1 being shorted.

[0133] like Figure 10 As shown, combined Figures 1 to 10When considering AC differential signal testing, the differential transmit and receive signal pins of some connectors under test are not distributed in the symmetrical A and B rows. For example, the distribution of AC differential transmit and receive signals in rows A and B of the PCIE connector under test is misplaced. Some connectors under test do not even distinguish between rows A and B, such as the M.2 connector. The above scenarios cannot be directly achieved. Figure 8 The minimum universal test unit resistance R_AB1_1 is short-circuited to meet the test condition. Therefore, for the test of the specific DUT connector to be tested, the pins are corrected by designing an adapter card to achieve the test condition.

[0134] Figure 10 , the a1 and a2 pins of the gold finger 2 are differential transmission signals TX1_DP and TX1_DN respectively, and the b3 and b4 pins of the gold finger 2 are differential receiving signals RX1_DP and RX1_DN respectively. Figure 9 and Figure 10 As shown, if according to Figure 9 The docking method of the pin sequence will not be able to achieve Figure 8 The testable condition of shorting the resistance R_AB1_1 of the smallest universal test unit realizes differential loopback testing. Therefore, when designing the adapter card, connect the a1 and a2 pins of gold finger 2 to A3 and A4 of connector J2, respectively, and connect the b3 and a3 pins of gold finger 2 to B3 and B4 of connector J2. Other differential signals are implemented in the same way. In this way, the differential loopback test conditions are achieved and it is compatible with universal systems. Other common signals can be flexibly connected to the pins of connector J2 in a 1-to-1 manner.

[0135] After the adapter card is compatible with the general hardware system design, for different DUT tests, when encountering the same definition of the test connector, the adapter card can be directly combined and used without redesign.

[0136] To achieve the above-mentioned objectives, the present invention further provides a method for using universal hardware suitable for boundary scan testing, the method being applied to the universal hardware architecture; the method comprising the steps of: determining whether the number of pins m1+v1 of the DUT connector to be tested J1_1 is not greater than the number of pins of the SLIM x8 connector or the gold finger, that is, m1+v1≤74; when the condition is not satisfied, that is, when m1+v1≥75, then the transfer condition of the first transfer type connector is not satisfied; when 38<m1+v1≤74, adopting the SLIM x8 interface transfer, which is suitable for transfer of the first transfer type connector; wherein 38 is the number of pins of the SLIM x4 connector, and 38 is the limit for the number of pins of the connector to be tested being small; when the number of pins of the DUT connector to be tested m2+v2≥75, then the transfer condition of the first transfer type connector is not satisfied, and the transfer condition of the second transfer type connector is suitable.

[0137] The method of use further includes the steps of: determining whether the number of pins m2+v2 of the connector to be tested J2_1 of the DUT satisfies 74+1≤m2+v2≤74+38, that is, 75≤m2+v2≤112, wherein 38 represents the number of pins of the SLIM x4 connector, and 74 represents the number of pins of the SLIM x8 connector; under the above conditions, the gold fingers 2_5 and 2_4 of the adapter cable 2_2 are SLIM x8 to SLIM x4 respectively, the connector J2_3 of the adapter card 2_1 adopts a SLIM x4 connector, and the adapter cable 2_2 is a SLIM x8 to SLIM x4 adapter cable; the adapter cable 2_1 is fully equipped and adopts a SLIM x8 to SLIM x8 adapter cable; determining whether the number of pins m2+v2 of the connector to be tested J2_1 of the DUT satisfies 74+39≤m2+v2≤74+74, that is, 113≤m2+v2≤148; wherein 74 represents the number of pins of the SLIM x8 connector pin count. Connector J2_3 on riser card 2_1 uses a SLIM x8 connector, and adapter cable 2_2 uses a SLIM x8 to SLIM x8 adapter cable. Adapter cable 2_1 is fully populated and uses a SLIM x8 to SLIM x8 adapter cable.

[0138] The method of use further includes the steps of: determining whether the number of gold finger pins m3+v3 of the connector to be tested J3_1 satisfies 1≤m3+v3≤38, and is suitable for the transfer condition of the third transfer type connector, wherein 38 represents the number of SLIM x4 pins; an important content of the transfer of the third transfer type connector is to transfer the IO resources of the SLIM x8 of the DUMMY card to two SLIM x4 gold fingers through the transfer line 3_1, the number of pins of SLIM x8 is 74, and the number of pins of SLIM x4 is 38, and the sum of the number of pins of the two SLIM x4 is 38×2=76>74; the processing method of the transfer line 3_1 is as follows: the SLIM x4 gold finger 3_3 of the transfer line 3_1 is fully equipped, 2×p is the fully equipped number of the transfer line 3_1, and the IO resource number of the fully equipped gold finger 3_3 is 2×p=38. When the number of pins of J3_1 is 1≤2×m3≤2×p=38, SLIM x4, MCIO x4, PCIE x1, PCIE x4, USB3.0, SATA-EXPRESS, SFP, the number of pins of these DUT connectors to be tested are 38, 38, 18, 32, 9, 29, 20 respectively, and all can be transferred;

[0139] The SLIM x4 gold finger 3_5 of adapter cable 3_2 is not fully populated. The number of IO resources of the partially populated gold finger 3_5 is 2×q=74-38=36. The pin counts of the DUT connectors to be tested, such as PCIE x1, PCIE x4, USB3.0, SATA-EXPRESS, and SFP, are 18, 32, 9, 29, and 20, respectively. All of them can be transferred. However, the SLIM x4 and MCIO x4 connectors to be tested have 38 pins and cannot be fully connected to the DUMMY card's IO.

[0140] SLIM x4 gold fingers 3_5 are not fully populated. The arrangement principle is based on the pin definition order A1, B1, A2, B2.... The first 1 to 36 pins are allocated I / O resources, and pins 37 and 38 are not allocated I / O resources.

[0141] The method of use further includes the steps of: the gold finger 3_1 of the adapter card 3_1 and the gold finger 3_2 of the adapter card 3_2 are respectively determined by the type of the DUT test connector J1_1. If the pin definition of the connector is standard, the designed DUT test connector adapter card is also universal.

[0142] The present invention provides a universal hardware architecture suitable for boundary scan testing, the architecture including at least three adapter-type connectors for boundary scan testing and located between a board to be tested and a simulation test card, including a first adapter-type connector, a second adapter-type connector, and a third adapter-type connector; the first adapter-type connector is composed of at least one adapter wire and at least one adapter card connected via a gold finger; the second adapter-type connector is composed of at least two adapter wires and at least one adapter card connected via a gold finger; and the second adapter-type connector is composed of at least one adapter wire and at least two adapter cards connected via a gold finger. Furthermore, a method for using the universal hardware architecture is provided. Without the need to redesign hardware, boundary scan engineers only need to flexibly combine and use the boards and adapter wire resources used in the original DUT project, eliminating the need for repeated hardware design. This significantly reduces the difficulty of hardware development for the boundary scan test system, saves manpower and material resources, shortens fixture delivery time, and effectively avoids design errors. Furthermore, the universal boards and adapter wires can be mass-produced, effectively reducing costs compared to customized boards.

[0143] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A general hardware architecture suitable for boundary scan testing, characterized in that: The architecture includes at least three adapter type connectors for boundary scan testing and located between the board to be tested and the analog test card, including a first adapter type connector, a second adapter type connector, and a third adapter type connector; The first adapter type connector is composed of at least one adapter wire and at least one adapter card connected by gold fingers; the second adapter type connector is composed of at least two adapter wires and at least one adapter card connected by gold fingers; the second adapter type connector is composed of at least one adapter wire and at least two adapter cards connected by gold fingers.

2. A universal hardware architecture suitable for boundary scan testing according to claim 1, characterized in that: The simulation test card is provided with at least one test unit; The test unit is provided with at least four electrically connected resistor groups, including a first resistor group, a second resistor group, a third resistor group and a fourth resistor group.

3. A universal hardware architecture suitable for boundary scan testing according to claim 1 or 2, characterized in that: The simulation test card is provided with at least four SLIM x8 connectors; The SLIM x8 connector chip model is 10M25DAF484C8G.

4. The universal hardware architecture suitable for boundary scan testing according to claim 1, characterized in that: The adapter card is provided with at least two rows of connectors, including a first differential gold finger connector and a second differential gold finger connector; The differential sending signal pin ends in the first differential gold finger connector are staggeredly connected to the pin ends in the gold finger; the differential receiving signal pin ends in the second differential gold finger connector are sequentially connected to the pin ends in the gold finger.

5. A method for using universal hardware suitable for boundary scan testing, characterized in that: The method of use is applied to the universal hardware architecture according to any one of claims 1 to 4; the method of use comprises the steps of: Determine whether the number of pins m1+v1 of the DUT connector J1_1 under test is not greater than the number of pins of the SLIM x8 connector or the gold finger connector, that is, m1+v1≤74; if the condition is not met, that is, m1+v1≥75, the transfer condition of the first transfer type connector is not met; When 38 < m1 + v1 ≤ 74, the SLIM x8 interface adapter is used, which is suitable for adapters of the first adapter type connector; wherein 38 is the number of pins of the SLIM x4 connector, and 38 is the limit of the number of pins of the connector to be tested; When the number of pins of the DUT connector to be tested, m2+v2, is ≥75, the transfer condition of the first transfer type connector is not met, but the transfer condition of the second transfer type connector is met.

6. The method for using universal hardware suitable for boundary scan testing according to claim 5, characterized in that: The method of use further comprises the steps of: Determine whether the number of pins m2+v2 on the DUT's connector (under test) J2_1 satisfies 74+1≤m2+v2≤74+38, that is, 75≤m2+v2≤112. 38 represents the number of pins on the SLIM x4 connector, and 74 represents the number of pins on the SLIM x8 connector. Under these conditions, gold fingers 2_5 and 2_4 on adapter cable 2_2 are SLIM x8 to SLIM x4 connectors, connector J2_3 on adapter card 2_1 uses a SLIM x4 connector, adapter cable 2_2 is a SLIM x8 to SLIM x4 adapter cable, and adapter cable 2_1 is fully populated and uses a SLIM x8 to SLIM x8 adapter cable. Determine whether the number of pins m2 + v2 on the DUT's connector under test, J2_1, satisfies 74 + 39 ≤ m2 + v2 ≤ 74 + 74, that is, 113 ≤ m2 + v2 ≤ 148. 74 represents the number of pins on the SLIM x8 connector. Connector J2_3 on riser card 2_1 uses a SLIM x8 connector, and adapter cable 2_2 uses a SLIM x8 to SLIM x8 adapter cable. Adapter cable 2_1 is fully populated and uses a SLIM x8 to SLIMx8 adapter cable.

7. The method for using universal hardware suitable for boundary scan testing according to claim 5, characterized in that: The method of use further comprises the steps of: Determine whether the number of gold finger pins m3+v3 of the connector under test J3_1 satisfies 1≤m3+v3≤38, which is suitable for the transfer condition of the third transfer type connector, where 38 represents the number of SLIM x4 pins; The third adapter type connector transfers the IO resources of the DUMMY card's SLIM x8 to two SLIM x4 gold fingers via adapter cable 3_1. The number of pins on the SLIM x8 is 74, while the number of pins on the SLIM x4 is 38. The total number of pins on the two SLIM x4s is 38 × 2 = 76, which is greater than 74. The processing method for adapter cable 3_1 is as follows: The SLIM x4 gold finger 3_3 of adapter cable 3_1 is fully populated. 2×p is the maximum number of SLIM x4 gold fingers 3_3 on adapter cable 3_1. The number of I / O resources of fully populated gold fingers 3_3 is 2×p = 38. When the number of pins on J3_1 is 1≤2×m3≤2×p=38, the pin numbers of the DUT connectors to be tested, such as SLIM x4, MCIO x4, PCIE x1, PCIE x4, USB3.0, SATA-EXPRESS, and SFP, are 38, 38, 18, 32, 9, 29, and 20, respectively, and can all be transferred. The SLIM x4 gold finger 3_5 of adapter cable 3_2 is not fully populated. The number of IO resources of the partially populated gold finger 3_5 is 2×q=74-38=36. The pin counts of the DUT connectors to be tested, such as PCIE x1, PCIE x4, USB3.0, SATA-EXPRESS, and SFP, are 18, 32, 9, 29, and 20, respectively. All of them can be transferred. However, the SLIM x4 and MCIO x4 connectors to be tested have 38 pins and cannot be fully connected to the DUMMY card's IO. SLIM x4 gold fingers 3_5 are not fully populated. The arrangement principle is based on the pin definition order A1, B1, A2, B2.... The first 1 to 36 pins are allocated I / O resources, and pins 37 and 38 are not allocated I / O resources.

8. The method for using universal hardware suitable for boundary scan testing according to claim 7, characterized in that: The method of use further comprises the steps of: The gold finger 3_1 of the adapter card 3_1 and the gold finger 3_2 of the adapter card 3_2 are respectively determined by the type of the DUT connector J1_1 to be tested. If the pin definition of the connector is standard, the designed DUT connector adapter card to be tested is also universal.

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