LDO circuit

Abstract

The invention provides an LDO circuit. The LDO circuit comprises a chopping stabilization error amplifier, a first transistor and a feedback loop. The chopping stabilization error amplifier comprises an in-phase input end, an inverted input end, a current bias end, a first voltage bias end, a second voltage bias end, a third voltage bias end, a clock end, a power supply end, a reference ground end and an output end. The inverted input end of the chopping stabilization error amplifier is connected with reference voltage, the current bias end is connected with external bias current, the first to third voltage bias ends are correspondingly connected with three bias voltages respectively, the clock end is connected with a chopping clock source, the power end is connected with a power supply, and the reference ground end is grounded; the grid electrode of the first transistor is connected with the output end of the chopping stabilization error amplifier, the source electrode of the first transistor is connected with a power supply, and the drain electrode of the first transistor serves as the output end of the LDO circuit and is connected to the in-phase input end of the chopping stabilization error amplifier through the feedback loop. According to the invention, flicker noise can be reduced.

Description

Technical Field

[0001] The present application relates to the field of power management technology, and in particular to an LDO circuit. Background Art

[0002] With the rapid development of modern communication technology, the performance requirements of communication systems are becoming increasingly stringent. Phase noise performance in modern communication systems continues to receive significant attention. Excellent phase noise performance can improve the dynamic range and sensitivity of RF systems, reduce bit error rates, and enhance carrier frequency tracking accuracy. Among the factors influencing RF system noise, noise generated by power modules is a significant factor. Implementing a power supply system with low flicker noise is a challenge in CMOS (Complementary Metal-Oxide-Semiconductor) processes. This is because the interface between the transistor gate oxide and the silicon substrate creates numerous silicon "dangling bonds," which generate additional energy states. When charge carriers move through this interface, some are randomly trapped and then released, manifesting as random flicker noise in the current. At low frequencies below tens of kHz, this flicker noise dominates the transistor noise and significantly contributes to the output noise.

[0003] Generally speaking, the direct way to suppress flicker noise is to increase the length and width of the main noise contributing devices. This method can reduce the flicker noise voltage in principle, but it requires a larger chip area. Summary of the Invention

[0004] The purpose of this application is to provide an LDO circuit that can solve at least one of the technical problems mentioned in the above-mentioned prior art.

[0005] One aspect of the present application provides an LDO circuit. The LDO circuit includes a chopper-stabilized error amplifier, a first transistor, and a feedback loop. The chopper-stabilized error amplifier includes a non-inverting input terminal, an inverting input terminal, a current bias terminal, a first voltage bias terminal, a second voltage bias terminal, a third voltage bias terminal, a clock terminal, a power supply terminal, a reference ground terminal, and an output terminal. The inverting input terminal of the chopper-stabilized error amplifier is connected to a reference voltage, the current bias terminal is connected to an external bias current, the first voltage bias terminal, the second voltage bias terminal, and the third voltage bias terminal are connected to three bias voltages respectively, the clock terminal is connected to a chopper clock source, the power supply terminal is connected to a power supply, and the reference ground terminal is grounded; the gate of the first transistor is connected to the output terminal of the chopper-stabilized error amplifier, the source of the first transistor is connected to the power supply, and the drain of the first transistor serves as the output terminal of the LDO circuit and is connected to the non-inverting input terminal of the chopper-stabilized error amplifier through the feedback loop.

[0006] Furthermore, the feedback loop includes a first resistor and a second resistor, wherein the first resistor and the second resistor are connected in series between the drain of the first transistor and the ground, and the connection point between the first resistor and the second resistor is connected to the non-inverting input of the chopper-stabilized error amplifier as a feedback node.

[0007] Furthermore, the LDO circuit further includes a first capacitor, wherein two ends of the first capacitor are respectively connected to a connection point between the first resistor and the second resistor and a connection point between the drain of the first transistor and the first resistor.

[0008] Furthermore, the LDO circuit also includes a pre-amplifier, which includes a transistor, wherein the inverting input terminal of the chopper-stabilized error amplifier is connected to the reference voltage through the pre-amplifier; and the feedback node is connected to the non-inverting input terminal of the chopper-stabilized error amplifier through the pre-amplifier.

[0009] Furthermore, the preamplifier has a non-inverting input terminal, an inverting input terminal, a current bias terminal, a power supply terminal, a reference ground terminal, a non-inverting output terminal and an inverting output terminal. The inverting input terminal of the chopper-stabilized error amplifier is connected to the inverting output terminal of the preamplifier, and the inverting input terminal of the preamplifier is connected to the reference voltage; the feedback node is connected to the non-inverting input terminal of the preamplifier, and the non-inverting output terminal of the preamplifier is connected to the non-inverting input terminal of the chopper-stabilized error amplifier; the current bias terminal of the preamplifier is connected to an external bias current, the power supply terminal of the preamplifier is connected to the power supply, and the reference ground terminal of the preamplifier is grounded.

[0010] Furthermore, the preamplifier includes a third transistor to a sixth transistor, a fifth resistor, a sixth resistor and a second capacitor, the base of the third transistor serves as the non-inverting input terminal of the preamplifier, the collector of the third transistor is connected to the power supply terminal of the preamplifier through the fifth resistor, and the collector of the third transistor serves as the inverting output terminal of the preamplifier; the base of the fourth transistor serves as the inverting input terminal of the preamplifier, the collector of the fourth transistor is connected to the power supply terminal of the preamplifier through the sixth resistor, and the fourth transistor as the in-phase output terminal of the pre-amplifier; the collector of the fifth transistor is connected to the emitter of the third transistor and the emitter of the fourth transistor, the base of the fifth transistor is connected to the base of the sixth transistor, the emitter of the fifth transistor is connected to the emitter of the sixth transistor and serves as the reference ground terminal of the pre-amplifier; the collector and base of the sixth transistor are short-circuited, and the collector of the sixth transistor serves as the current bias terminal of the pre-amplifier; the two ends of the second capacitor are respectively connected between the collector and emitter of the sixth transistor.

[0011] Furthermore, the LDO circuit further includes a voltage buffer, which includes a triode, wherein the output end of the chopper-stabilized error amplifier is connected to the gate of the first transistor through the voltage buffer.

[0012] Furthermore, the voltage buffer includes a first transistor, a second transistor, a third resistor and a fourth resistor, and the output end of the chopper-stabilized error amplifier is connected to the gate of the first transistor through the first transistor and the second transistor, wherein the output end of the chopper-stabilized error amplifier is connected to the base of the first transistor, the collector of the first transistor is connected to the base of the second transistor and is connected to the power supply through the third resistor, and the emitter of the first transistor is grounded; the collector of the second transistor is connected to the power supply, and the emitter of the second transistor is connected to the gate of the first transistor and is grounded through the fourth resistor.

[0013] Furthermore, the chopper-stabilized error amplifier includes a second transistor to a fifteenth transistor, a first chopper switch module, a second chopper switch module and a third chopper switch module, and each of the first chopper switch module, the second chopper switch module and the third chopper switch module has a first left port, a second left port, a first right port, a second right port, a power supply terminal, a clock terminal and an inverted clock terminal.The first left side port and the second left side port of the first chopping switch module are respectively connected to the non-inverting input terminal and the inverting input terminal of the chopper-stabilized error amplifier, and the first right side port and the second right side port of the first chopping switch module are respectively connected to the gate of the third transistor and the gate of the second transistor; the power supply terminal, the clock terminal and the inverted clock terminal of the first chopping switch module, the second chopping switch module and the third chopping switch module are respectively connected to the power supply, the chopping clock source and the inverted chopping clock source; the first left side port and the second left side port of the second chopping switch module are respectively connected to the source of the ninth transistor and the source of the eighth transistor, and the second chopping switch The first right side port and the second right side port of the switch module are connected to the drain of the tenth transistor and the drain of the eleventh transistor respectively; the first left side port of the third chopping switch module is connected to the drain of the second transistor and the drain of the fourth transistor, the second left side port of the third chopping switch module is connected to the drain of the third transistor and the drain of the fifth transistor, the first right side port and the second right side port of the third chopping switch module are connected to the source of the sixth transistor and the source of the seventh transistor respectively; the source of the second transistor and the source of the third transistor are connected to the drain of the twelfth transistor; the gate of the fourth transistor and the gate of the fifth transistor are connected to the chopper stabilization error The first voltage bias terminal of the chopper-stabilized error amplifier is connected to the first voltage bias terminal of the chopper-stabilized error amplifier, the source of the fourth transistor and the source of the fifth transistor are grounded; the gate of the sixth transistor and the gate of the seventh transistor are connected to the second voltage bias terminal of the chopper-stabilized error amplifier, the drain of the sixth transistor is connected to the drain of the eighth transistor, the gate of the tenth transistor and the gate of the eleventh transistor, the drain of the seventh transistor is connected to the drain of the ninth transistor and the output terminal of the chopper-stabilized error amplifier; the gate of the eighth transistor and the gate of the ninth transistor are connected to the third voltage bias terminal of the chopper-stabilized error amplifier; the source of the tenth transistor is connected to the drain of the eighth transistor, the gate of the tenth transistor and the gate of the eleventh transistor, and the drain of the seventh transistor is connected to the drain of the ninth transistor and the output terminal of the chopper-stabilized error amplifier. The source of the eleventh transistor is connected to the power supply; the gate of the twelfth transistor is connected to the gate of the thirteenth transistor, the drain of the thirteenth transistor and the current bias terminal of the chopper-stabilized error amplifier, and the source of the twelfth transistor and the source of the thirteenth transistor are connected to the power supply; the gate of the fourteenth transistor and the gate of the fifteenth transistor are connected to the clock terminal of the chopper-stabilized error amplifier, the source of the fourteenth transistor is connected to the power supply, the drain of the fourteenth transistor and the drain of the fifteenth transistor are connected together and connected to the inverting clock terminal of the chopper-stabilized error amplifier; the source of the fifteenth transistor is grounded.

[0014] Furthermore, each of the first chopping switch module, the second chopping switch module, and the third chopping switch module includes a sixteenth transistor to a nineteenth transistor, wherein the gate of the sixteenth transistor and the gate of the eighteenth transistor are connected together and serve as the clock terminal of the chopping switch module, the source of the sixteenth transistor and the source of the seventeenth transistor are connected together and serve as the first left port of the chopping switch module, and the drain of the sixteenth transistor and the drain of the nineteenth transistor are connected together and serve as the first right port of the chopping switch module; the gate of the seventeenth transistor and the gate of the nineteenth transistor are connected together and serve as the inverting clock terminal of the chopping switch module, the drain of the seventeenth transistor and the drain of the eighteenth transistor are connected together and serve as the second right port of the chopping switch module; and the source of the eighteenth transistor and the source of the nineteenth transistor are connected together and serve as the second left port of the chopping switch module.

[0015] The LDO circuit of this application can effectively remove flicker noise from the power supply system, preventing high noise from entering the oscillator and other core modules of the RF system through the power supply, thereby reducing system noise and improving system phase noise performance. This low-flicker noise LDO circuit can be integrated with the RF module on the same chip, achieving a high level of integration and significantly contributing to the improvement of RF system noise performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic structural diagram of an LDO circuit according to an embodiment of the present application.

[0017] Figure 2 This is a schematic diagram of the internal structure of a pre-amplifier according to an embodiment of the present application.

[0018] Figure 3 Schematic diagram of the internal structure of a chopper-stabilized error amplifier according to an embodiment of the present application.

[0019] Figure 4 This is a schematic diagram of the internal structure of a chopper switch module according to an embodiment of the present application. DETAILED DESCRIPTION

[0020] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of devices consistent with certain aspects of the present application, as detailed in the appended claims.

[0021] The LDO (Low Dropout Regulator) circuit of the present application will be described in detail below with reference to the accompanying drawings. The features of the following embodiments and implementations may be combined with each other unless there is a conflict.

[0022] Figure 1 The schematic diagram of the structure of the LDO circuit 100 according to one embodiment of the present application is disclosed. Figure 1 As shown, an LDO circuit 100 according to an embodiment of the present application includes a chopper-stabilized error amplifier I2 , a first transistor M1 , and a feedback loop.

[0023] The chopper-stabilized error amplifier I2 includes a non-inverting input terminal VP, an inverting input terminal VN, a current bias terminal IBIAS, a first voltage bias terminal VBIAS1, a second voltage bias terminal VBIAS2, a third voltage bias terminal VBIAS3, a clock terminal CLK, a power supply terminal VDD, a reference ground terminal VSS, and an output terminal VO.

[0024] The inverting input terminal VN of the chopper-stabilized error amplifier I2 is connected to the reference voltage VREF, the current bias terminal IBIAS is connected to the external bias current, the first voltage bias terminal VBIAS1, the second voltage bias terminal VBIAS2, and the third voltage bias terminal VBIAS3 are connected to three bias voltages respectively, the clock terminal CLK is connected to the chopper clock source, the power supply terminal VDD is connected to the power supply, and the reference ground terminal VSS is grounded.

[0025] The first transistor M1 is a PMOS transistor. The gate of the first transistor M1 is connected to the output terminal VO of the chopper-stabilized error amplifier I2. The source of the first transistor M1 is connected to the power supply. The drain of the first transistor M1 serves as the output terminal of the LDO circuit 100 and is connected to the non-inverting input terminal VP of the chopper-stabilized error amplifier I2 through a feedback loop.

[0026] In some embodiments, the feedback loop of the present application may include a first resistor R1 and a second resistor R2. The first resistor R1 and the second resistor R2 are connected in series between the drain of the first transistor M1 and ground, and the connection point between the first resistor R1 and the second resistor R2 serves as a feedback node FB connected to the non-inverting input terminal VP of the chopper-stabilized error amplifier I2.

[0027] Optionally, the LDO circuit 100 of the present application may further include a first capacitor C1 , wherein two ends of the first capacitor C1 are respectively connected to the connection point between the first resistor R1 and the second resistor R2 and the connection point between the drain of the first transistor M1 and the first resistor R1 .

[0028] In some embodiments, the LDO circuit 100 of the present application may further include a pre-amplifier I1. The pre-amplifier I1 includes a bipolar junction transistor (BJT). The pre-amplifier I1 is a differential amplifier with a BJT structure, and its main function is to provide gain and reduce system noise. The inverting input terminal VIN of the chopper-stabilized error amplifier I2 is connected to the reference voltage VREF through the pre-amplifier I1; the feedback node FB is connected to the non-inverting input terminal VP of the chopper-stabilized error amplifier I2 through the pre-amplifier I1.

[0029] The LDO circuit 100 of the present application uses a BJT structure pre-amplifier I1 and a chopper-stabilized error amplifier I2 structure to shift the low-frequency flicker noise spectrum to a high frequency. After filtering, a low-noise output power supply is obtained, thereby improving the noise performance of the system and achieving the purpose of reducing output noise.

[0030] Preamplifier I1 has a non-inverting input terminal VIP, an inverting input terminal VIN, a current bias terminal IBIAS, a power supply terminal VDD, a reference ground terminal VSS, a non-inverting output terminal VON, and an inverting output terminal VOP. The inverting input terminal VN of the chopper-stabilized error amplifier I2 is connected to the inverting output terminal VON of the preamplifier I1, and the inverting input terminal VIN of the preamplifier I1 is connected to a reference voltage VREF. The feedback node FB is connected to the non-inverting input terminal VIP of the preamplifier I1, and the non-inverting output terminal VOP of the preamplifier I1 is connected to the non-inverting input terminal VP of the chopper-stabilized error amplifier I2. The current bias terminal IBIAS of the preamplifier I1 is connected to an external bias current, the power supply terminal VDD of the preamplifier I1 is connected to the power supply, and the reference ground terminal VSS of the preamplifier I1 is grounded.

[0031] Figure 2 The internal structure diagram of the pre-amplifier I1 according to one embodiment of the present application is disclosed. Figure 2 As shown, in some embodiments, the pre-amplifier I1 includes a third transistor Q3 to a sixth transistor Q6, a fifth resistor R5, a sixth resistor R6, and a second capacitor C2.

[0032] The base of the third transistor Q3 serves as the non-inverting input terminal VIP of the pre-amplifier I1, the collector of the third transistor Q3 is connected to the power supply terminal VDD of the pre-amplifier I1 through the fifth resistor R5, and the collector of the third transistor Q3 serves as the inverting output terminal VON of the pre-amplifier I1.

[0033] The base of the fourth transistor Q4 serves as the inverting input terminal VIN of the preamplifier I1, the collector of the fourth transistor Q4 is connected to the power supply terminal VDD of the preamplifier I1 through the sixth resistor R6, and the collector of the fourth transistor Q4 serves as the non-inverting output terminal VOP of the preamplifier I1.

[0034] The collector of the fifth transistor Q5 is connected to the emitter of the third transistor Q3 and the emitter of the fourth transistor Q4. The base of the fifth transistor Q5 is connected to the base of the sixth transistor Q6. The emitter of the fifth transistor Q5 is connected to the emitter of the sixth transistor Q6 and serves as the reference ground VSS of the pre-amplifier I1.

[0035] The collector and the base of the sixth transistor Q6 are short-circuited, and the collector of the sixth transistor Q6 serves as the current bias terminal IBIAS of the pre-amplifier I1.

[0036] Two ends of the second capacitor C2 are respectively connected between the collector and the emitter of the sixth transistor Q6.

[0037] Continue to refer to Figure 1 As shown, the LDO circuit 100 of the present application may further include a voltage buffer, which includes a transistor. The output terminal VO of the chopper-stabilized error amplifier I2 is connected to the gate of the first transistor M1 through the voltage buffer.

[0038] In some embodiments, the voltage buffer includes a first transistor Q1, a second transistor Q2, a third resistor R3, and a fourth resistor R4. An output terminal VO of the chopper-stabilized error amplifier I2 is connected to the gate of the first transistor M1 through the first transistor Q1 and the second transistor Q2, wherein the output terminal VO of the chopper-stabilized error amplifier I2 is connected to the base of the first transistor Q1, the collector of the first transistor Q1 is connected to the base of the second transistor Q2 and is connected to a power supply through the third resistor R3, and the emitter of the first transistor Q1 is grounded; the collector of the second transistor Q2 is connected to the power supply, and the emitter of the second transistor Q2 is connected to the gate of the first transistor M1 and is grounded through the fourth resistor R4.

[0039] Figure 3 The internal structure diagram of the chopper-stabilized error amplifier I2 according to one embodiment of the present application is disclosed. Figure 3 As shown, in some embodiments, the chopper-stabilized error amplifier I2 of the present application may include a second transistor M2 to a fifteenth transistor M15, a first chopping switch module I3, a second chopping switch module I4, and a third chopping switch module I5. Each of the first chopping switch module I3, the second chopping switch module I4, and the third chopping switch module I5 has a first left-side port PL1, a second left-side port PL2, a first right-side port PR1, a second right-side port PR2, a power supply terminal VDD, a clock terminal CLK, and an inverted clock terminal nCLK.

[0040] The first left port PL1 and the second left port PL2 of the first chopper switch module I3 are respectively connected to the non-inverting input terminal VP and the inverting input terminal VN of the chopper-stabilized error amplifier I2, and the first right port PR1 and the second right port PR2 of the first chopper switch module I3 are respectively connected to the gate of the third transistor M3 and the gate of the second transistor M2.

[0041] The power supply terminal VDD, the clock terminal CLK and the inverted clock terminal nCLK of the first chopping switch module I3, the second chopping switch module I4 and the third chopping switch module I5 are connected to the power supply, the chopping clock source and the inverted chopping clock source respectively.

[0042] The first left port PL1 and the second left port PL2 of the second chopping switch module I4 are respectively connected to the source of the ninth transistor M9 and the source of the eighth transistor M8, and the first right port PR1 and the second right port PR2 of the second chopping switch module I4 are respectively connected to the drain of the tenth transistor M10 and the drain of the eleventh transistor M11.

[0043] The first left port PL1 of the third chopping switch module I5 is connected to the drain of the second transistor M2 and the drain of the fourth transistor M4, the second left port PL2 of the third chopping switch module I5 is connected to the drain of the third transistor M3 and the drain of the fifth transistor M5, and the first right port PR1 and the second right port PR2 of the third chopping switch module I5 are respectively connected to the source of the sixth transistor M6 and the source of the seventh transistor M7.

[0044] The second transistor M2 and the third transistor M3 are PMOS transistors, and the source of the second transistor M2 and the source of the third transistor M3 are connected to the drain of the twelfth transistor M12.

[0045] The fourth transistor M4 and the fifth transistor M5 are NMOS transistors, the gates of the fourth transistor M4 and the fifth transistor M5 are connected to the first voltage bias terminal VBIAS1 of the chopper-stabilized error amplifier I2, and the sources of the fourth transistor M4 and the fifth transistor M5 are grounded.

[0046] The sixth transistor M6 and the seventh transistor M7 are NMOS transistors. The gates of the sixth transistor M6 and the seventh transistor M7 are connected to the second voltage bias terminal VBIAS2 of the chopper-stabilized error amplifier I2. The drain of the sixth transistor M6 is connected to the drain of the eighth transistor M8, the gate of the tenth transistor M10, and the gate of the eleventh transistor M11. The drain of the seventh transistor M7 is connected to the drain of the ninth transistor M9 and the output terminal VO of the chopper-stabilized error amplifier I2.

[0047] The eighth transistor M8 and the ninth transistor M9 are PMOS transistors. The gates of the eighth transistor M8 and the ninth transistor M9 are connected to the third voltage bias terminal VBIAS3 of the chopper-stabilized error amplifier I2.

[0048] The tenth transistor M10 and the eleventh transistor M11 are PMOS transistors, and the source of the tenth transistor M10 and the source of the eleventh transistor M11 are connected to a power supply.

[0049] The twelfth transistor M12 and the thirteenth transistor M13 are PMOS transistors. The gate of the twelfth transistor M12 is connected to the gate of the thirteenth transistor M13, the drain of the thirteenth transistor M13, and the current bias terminal IBIAS of the chopper-stabilized error amplifier I2. The source of the twelfth transistor M12 and the source of the thirteenth transistor M13 are connected to the power supply.

[0050] The fourteenth transistor M14 is a PMOS transistor, and the fifteenth transistor M15 is an NMOS transistor. The gate of the fourteenth transistor M14 and the gate of the fifteenth transistor M15 are connected to the clock terminal CLK of the chopper-stabilized error amplifier I2. The source of the fourteenth transistor M14 is connected to a power supply. The drain of the fourteenth transistor M14 and the drain of the fifteenth transistor M15 are connected together and connected to the inverting clock terminal nCLK of the chopper-stabilized error amplifier I2.

[0051] A source of the fifteenth transistor M15 is grounded.

[0052] Chopper-stabilized error amplifier I2 implements chopper stabilization via three chopper switch modules. Each chopper switch module controls the signal flow of two paths (PL1, PL2, PR1, and PR2). Within one clock cycle, the signal is exchanged between PL1 and PR1, between PL2 and PR2, and between PL1 and PR2 and between PL2 and PR1, thereby modulating and demodulating the signal and noise. The useful signal undergoes two modulations, returning its spectrum to its original position. The flicker noise signal undergoes only one modulation, modulating its spectrum to a high frequency (the clock frequency) and filtering it out, thereby removing the more influential flicker noise from the signal.

[0053] Figure 4 The internal structure diagram of the chopper switch module of one embodiment of the present application is disclosed. Figure 4 As shown, in some embodiments, each of the first chopping switch module I3, the second chopping switch module I4, and the third chopping switch module I5 includes sixteenth to nineteenth transistors M16 to M19.

[0054] The gate of the sixteenth transistor M16 and the gate of the eighteenth transistor M18 are connected together and serve as the clock terminal CLK of the chopping switch module, the source of the sixteenth transistor M16 and the source of the seventeenth transistor M17 are connected together and serve as the first left port PL1 of the chopping switch module, and the drain of the sixteenth transistor M16 and the drain of the nineteenth transistor M19 are connected together and serve as the first right port PR1 of the chopping switch module.

[0055] The gate of the seventeenth transistor M17 and the gate of the nineteenth transistor M19 are connected together and serve as the inverting clock terminal nCLK of the chopper switch module. The drain of the seventeenth transistor M17 and the drain of the eighteenth transistor M18 are connected together and serve as the second right port PR2 of the chopper switch module.

[0056] The source of the eighteenth transistor M18 and the source of the nineteenth transistor M19 are connected together and serve as the second left port PL2 of the chopper switch module.

[0057] The working principle of the LDO circuit 100 of the present application will be described below.

[0058] The LDO circuit 100 of the present application uses pre-amplification and chopper stabilization technology to stabilize the output voltage VOUT of the LDO circuit 100 to a multiple of the input reference voltage VREF through a feedback loop and a first resistor R1 and a second resistor R2. The quantitative relationship can be expressed as:

[0059]

[0060] The LDO circuit 100 of the present application uses a pre-amplifier I1 to increase the first-stage gain and reduce the output noise level. The chopper-stabilized error amplifier I2 shifts the noise spectrum generated by the previous stage and itself to a high frequency and filters it, suppressing flicker noise. The first transistor Q1 and the second transistor Q2 provide a buffering effect, pushing the internal pole to a higher position to ensure loop stability. The first transistor M1 acts as a pass transistor to control the output current and voltage.

[0061] The LDO circuit 100 of this application can effectively remove flicker noise from the power supply system, preventing high noise from entering the core modules of the RF system, such as the oscillator, through the power supply, thereby reducing system noise and improving system phase noise performance. This low-flicker noise LDO circuit 100 can be integrated with the RF module on the same chip, achieving a high level of integration and significantly contributing to the improvement of the RF system's noise performance.

[0062] The above is a detailed introduction to the LDO circuit provided in the embodiment of the present application. This article uses specific examples to illustrate the LDO circuit in the embodiment of the present application. The description of the above embodiment is only used to help understand the core idea of the present application and is not intended to limit the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the spirit and principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications should also fall within the scope of protection of the claims attached to the present application.

Claims

1. An LDO circuit, characterized in that: The invention comprises a chopper-stabilized error amplifier, a first transistor and a feedback loop, wherein the chopper-stabilized error amplifier comprises a non-inverting input terminal, an inverting input terminal, a current bias terminal, a first voltage bias terminal, a second voltage bias terminal, a third voltage bias terminal, a clock terminal, a power supply terminal, a reference ground terminal and an output terminal, wherein: The inverting input terminal of the chopper-stabilized error amplifier is connected to a reference voltage, the current bias terminal is connected to an external bias current, the first voltage bias terminal, the second voltage bias terminal, and the third voltage bias terminal are connected to three bias voltages respectively, the clock terminal is connected to a chopper clock source, the power terminal is connected to a power supply, and the reference ground terminal is grounded; The gate of the first transistor is connected to the output end of the chopper-stabilized error amplifier, the source of the first transistor is connected to the power supply, and the drain of the first transistor serves as the output end of the LDO circuit and is connected to the non-inverting input end of the chopper-stabilized error amplifier through the feedback loop.

2. The LDO circuit according to claim 1, wherein: The feedback loop includes a first resistor and a second resistor, wherein, The first resistor and the second resistor are connected in series between the drain of the first transistor and the ground, and a connection point between the first resistor and the second resistor is connected to the non-inverting input of the chopper-stabilized error amplifier as a feedback node.

3. The LDO circuit according to claim 2, wherein: Also includes a first capacitor, wherein, Two ends of the first capacitor are respectively connected to a connection point between the first resistor and the second resistor and a connection point between the drain of the first transistor and the first resistor.

4. The LDO circuit according to claim 2, wherein: It also includes a pre-amplifier, which includes a triode, wherein: The inverting input terminal of the chopper-stabilized error amplifier is connected to a reference voltage through the pre-amplifier; The feedback node is connected to the non-inverting input of the chopper-stabilized error amplifier through the pre-amplifier.

5. The LDO circuit according to claim 4, wherein: The preamplifier has a non-inverting input terminal, an inverting input terminal, a current bias terminal, a power supply terminal, a reference ground terminal, a non-inverting output terminal and an inverting output terminal. The inverting input terminal of the chopper-stabilized error amplifier is connected to the inverting output terminal of the pre-amplifier, and the inverting input terminal of the pre-amplifier is connected to the reference voltage; The feedback node is connected to the non-inverting input of the pre-amplifier, and the non-inverting output of the pre-amplifier is connected to the non-inverting input of the chopper-stabilized error amplifier; The current bias terminal of the preamplifier is connected to an external bias current, the power supply terminal of the preamplifier is connected to the power supply, and the reference ground terminal of the preamplifier is grounded.

6. The LDO circuit according to claim 5, wherein: The pre-amplifier includes a third transistor to a sixth transistor, a fifth resistor, a sixth resistor and a second capacitor. The base of the third transistor serves as the non-inverting input terminal of the pre-amplifier, the collector of the third transistor is connected to the power supply terminal of the pre-amplifier through the fifth resistor, and the collector of the third transistor serves as the inverting output terminal of the pre-amplifier; The base of the fourth transistor serves as the inverting input terminal of the pre-amplifier, the collector of the fourth transistor is connected to the power supply terminal of the pre-amplifier through the sixth resistor, and the collector of the fourth transistor serves as the non-inverting output terminal of the pre-amplifier; The collector of the fifth transistor is connected to the emitter of the third transistor and the emitter of the fourth transistor, the base of the fifth transistor is connected to the base of the sixth transistor, and the emitter of the fifth transistor is connected to the emitter of the sixth transistor and serves as the reference ground of the pre-amplifier; The collector and base of the sixth transistor are short-circuited, and the collector of the sixth transistor serves as the current bias terminal of the pre-amplifier; Two ends of the second capacitor are respectively connected between the collector and the emitter of the sixth transistor.

7. The LDO circuit according to claim 1, wherein: It also includes a voltage buffer, which includes a triode, wherein: The output terminal of the chopper-stabilized error amplifier is connected to the gate of the first transistor through the voltage buffer.

8. The LDO circuit according to claim 7, wherein: The voltage buffer includes a first transistor, a second transistor, a third resistor and a fourth resistor. The output end of the chopper-stabilized error amplifier is connected to the gate of the first transistor through the first transistor and the second transistor, wherein the output end of the chopper-stabilized error amplifier is connected to the base of the first transistor, the collector of the first transistor is connected to the base of the second transistor and is connected to the power supply through the third resistor, and the emitter of the first transistor is grounded; the collector of the second transistor is connected to the power supply, and the emitter of the second transistor is connected to the gate of the first transistor and is grounded through the fourth resistor.

9. The LDO circuit according to claim 1, wherein: The chopper-stabilized error amplifier includes second to fifteenth transistors, a first chopping switch module, a second chopping switch module, and a third chopping switch module. Each of the first chopping switch module, the second chopping switch module, and the third chopping switch module has a first left port, a second left port, a first right port, a second right port, a power supply terminal, a clock terminal, and an inverted clock terminal. The first left port and the second left port of the first chopper switch module are respectively connected to the non-inverting input terminal and the inverting input terminal of the chopper-stabilized error amplifier, and the first right port and the second right port of the first chopper switch module are respectively connected to the gate of the third transistor and the gate of the second transistor; The power supply terminal, clock terminal and inverted clock terminal of the first chopping switch module, the second chopping switch module and the third chopping switch module are connected to the power supply, the chopping clock source and the inverted chopping clock source respectively; The first left port and the second left port of the second chopping switch module are connected to the source of the ninth transistor and the source of the eighth transistor, respectively, and the first right port and the second right port of the second chopping switch module are connected to the drain of the tenth transistor and the drain of the eleventh transistor, respectively; The first left port of the third chopping switch module is connected to the drain of the second transistor and the drain of the fourth transistor, the second left port of the third chopping switch module is connected to the drain of the third transistor and the drain of the fifth transistor, and the first right port and the second right port of the third chopping switch module are connected to the source of the sixth transistor and the source of the seventh transistor, respectively; The source of the second transistor and the source of the third transistor are connected to the drain of the twelfth transistor; The gate of the fourth transistor and the gate of the fifth transistor are connected to the first voltage bias terminal of the chopper-stabilized error amplifier, and the source of the fourth transistor and the source of the fifth transistor are grounded; a gate of the sixth transistor and a gate of the seventh transistor connected to the second voltage bias terminal of the chopper-stabilized error amplifier, a drain of the sixth transistor connected to the drain of the eighth transistor, the gate of the tenth transistor, and the gate of the eleventh transistor, and a drain of the seventh transistor connected to the drain of the ninth transistor and the output terminal of the chopper-stabilized error amplifier; The gate of the eighth transistor and the gate of the ninth transistor are connected to the third voltage bias terminal of the chopper-stabilized error amplifier; The source of the tenth transistor and the source of the eleventh transistor are connected to the power supply; The gate of the twelfth transistor is connected to the gate of the thirteenth transistor, the drain of the thirteenth transistor and the current bias terminal of the chopper-stabilized error amplifier, and the source of the twelfth transistor and the source of the thirteenth transistor are connected to the power supply; The gate of the fourteenth transistor and the gate of the fifteenth transistor are connected to the clock terminal of the chopper-stabilized error amplifier, the source of the fourteenth transistor is connected to the power supply, and the drain of the fourteenth transistor and the drain of the fifteenth transistor are connected together and connected to the inverting clock terminal of the chopper-stabilized error amplifier; A source of the fifteenth transistor is grounded.

10. The LDO circuit according to claim 9, wherein: Each of the first chopping switch module, the second chopping switch module and the third chopping switch module includes sixteenth to nineteenth transistors, wherein: The gate of the sixteenth transistor and the gate of the eighteenth transistor are connected together and serve as a clock terminal of the chopping switch module, the source of the sixteenth transistor and the source of the seventeenth transistor are connected together and serve as a first left port of the chopping switch module, and the drain of the sixteenth transistor and the drain of the nineteenth transistor are connected together and serve as a first right port of the chopping switch module; The gate of the seventeenth transistor and the gate of the nineteenth transistor are connected together and serve as the inverting clock terminal of the chopping switch module, and the drain of the seventeenth transistor and the drain of the eighteenth transistor are connected together and serve as the second right side port of the chopping switch module; The source of the eighteenth transistor and the source of the nineteenth transistor are connected together and serve as the second left port of the chopper switch module.

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