A dynamic reference voltage amplification integrated circuit

Abstract

The application relates to the technical field of integrated circuits, and provides a dynamic reference voltage amplification integrated circuit, which comprises a dynamic reference voltage circuit and a double-path output amplification circuit, the dynamic reference voltage circuit comprises ports VB, VINF1 and VREF1, the double-path output amplification circuit comprises ports VINF2, VREF2, VIA and VRA, the port VB is an input port of external bias voltage vb, the ports VINF1 and VINF2 are input ports of input voltage vinf, the port VREF1 is connected with the port VREF2, the port VRA is an output port of amplified dynamic reference voltage vr, the dynamic reference voltage circuit is adapted to generate corresponding reference voltage vref according to the input voltage vinf, and the double-path output amplification circuit is adapted to amplify and output the input voltage vinf and the dynamic reference voltage vref. The application can generate corresponding reference voltage according to the input voltage, that is, output dynamic reference voltage, so that a sufficient voltage difference is kept between the input voltage and the reference voltage, and the power consumption of the system and the demand of the power supply voltage for the normal operation of the system are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, and in particular, to a dynamic reference voltage amplification integrated circuit. BACKGROUND

[0002] In the process of integrated circuit data reading, the input voltage value needs to be compared with the relevant reference voltage value to determine the data information carried by the input voltage. However, when the input voltage value is very close to the reference voltage value, the accuracy of reading the data information is easily affected by the circuit noise or the circuit leakage current, thereby increasing the interference in the process of integrated circuit data reading and seriously reducing the accuracy of reading the data information. SUMMARY

[0003] The problem solved by the present application is how to effectively expand the voltage difference between the input voltage and the reference voltage to improve the anti-interference ability of integrated circuit data reading and ensure the accuracy of reading the data information.

[0004] To solve the above problem, the present application provides a dynamic reference voltage amplification integrated circuit including a dynamic reference voltage circuit and a dual-path output amplification circuit.

[0005] The dynamic reference voltage circuit can generate a corresponding reference voltage according to the input voltage, so as to maintain a sufficient voltage difference between the input voltage and the reference voltage. The dynamic reference voltage circuit outputs a dynamically changing reference voltage.

[0006] The dual-path output amplification circuit can amplify and output the input voltage and the reference voltage. Based on the relevant circuit structure design, the dual-path output amplification circuit uses a relevant capacitor voltage to amplify the input voltage and the reference voltage, without the need to input a offset voltage at the input port of the amplification circuit, thereby reducing the power consumption of the system and the demand for power supply voltage for normal operation of the system, and further ensuring the voltage difference range between the input voltage and the reference voltage.

[0007] The dynamic reference voltage circuit includes ports VB, VINF1 and VREF1.

[0008] The dual-path output amplification circuit includes ports VINF2, VREF2, VIA and VRA.

[0009] The port VB is an input port of the circuit external bias voltage vb.

[0010] The ports VINF1 and VINF2 are both input ports of the input voltage vinf.

[0011] The port VREF1 is connected with the port VREF2, and is used for transmitting the dynamic reference voltage vref.

[0012] The port VIA is an output port of the amplified input voltage vi.

[0013] Port VRA is an output port of the amplified dynamic reference voltage vr.

[0014] Further, the dynamic reference voltage circuit comprises a bias circuit and a reference voltage circuit.

[0015] The bias circuit is connected to the reference voltage circuit, and the bias circuit provides a corresponding high-stability bias voltage for the reference voltage circuit, so that the reference voltage circuit is in a normal working state.

[0016] Further, the bias circuit comprises MOS tubes M1 to M5, resistors R1 to R2, and a port VB.

[0017] Further, the source of the MOS tube M1 is connected to the port VB, the gate of the MOS tube M1 is connected to the gate of the MOS tube M4, and the drain of the MOS tube M1 is connected to the source of the MOS tube M2. The source of the MOS tube M2 is connected to the gate of the MOS tube M1, the gate of the MOS tube M2 is connected to the drain of the MOS tube M2, and the drain of the MOS tube M2 is connected to the drain of the MOS tube M3. The drain of the MOS tube M3 is connected to the gate of the MOS tube M2, the gate of the MOS tube M3 is connected to the gate of the MOS tube M5, and the source of the MOS tube M3 is connected to the upper end of the resistor R1, and the lower end of the resistor R1 is grounded.

[0018] Further, the source of the MOS tube M4 is connected to the gate of the MOS tube M8, the gate of the MOS tube M4 is connected to the drain of the MOS tube M1, and the drain of the MOS tube M4 is connected to the drain of the MOS tube M5. The drain of the MOS tube M5 is connected to the drain of the MOS tube M4, the gate of the MOS tube M5 is connected to the drain of the MOS tube M5, and the source of the MOS tube M5 is connected to the upper end of the resistor R2, and the lower end of the resistor R2 is grounded.

[0019] Further, the reference voltage circuit comprises MOS tubes M6 to M10, a resistor R3, a port VINF1, and a port VREF1.

[0020] Further, the drain of the MOS tube M7 is connected to the port VINF1, the gate of the MOS tube M7 is connected to the drain of the MOS tube M6, and the source of the MOS tube M7 is connected to the gate of the MOS tube M10. The drain of the MOS tube M6 is connected to the source of the MOS tube M7, the gate of the MOS tube M6 is connected to the gate of the MOS tube M3, and the source of the MOS tube M6 is connected to the upper end of the resistor R3, and the lower end of the resistor R3 is grounded.

[0021] Further, the source of the MOS transistor M8 is connected to the power supply VDD, the gate of the MOS transistor M8 is connected to the source of the MOS transistor M4, and the drain of the MOS transistor M8 is connected to the source of the MOS transistor M9. The source of the MOS transistor M9 is connected to the drain of the MOS transistor M8, the gate of the MOS transistor M9 is connected to the drain of the MOS transistor M9, and the drain of the MOS transistor M9 is connected to the drain of the MOS transistor M10. The drain of the MOS transistor M10 is connected to the port VREF1, the gate of the MOS transistor M10 is connected to the source of the MOS transistor M7, and the source of the MOS transistor M10 is connected to the ground.

[0022] Further, the double-path output amplification circuit comprises an input control circuit, a transfer amplification circuit, and an output circuit.

[0023] The input control circuit is connected to the transfer amplification circuit, the port VINF2 receives the input voltage vinf, and the port VREF2 receives the dynamic reference voltage vref. The input control circuit controls whether the input voltage vinf and the dynamic reference voltage vref are input into the transfer amplification circuit.

[0024] The transfer amplification circuit is connected to the output circuit, the transfer amplification circuit inputs the preliminarily amplified input voltage vinf and the dynamic reference voltage vref into the output circuit, and the output circuit outputs the completely amplified input voltage vinf and the dynamic reference voltage vref through the port.

[0025] Further, the input control circuit comprises MOS transistors M11 to M14, a resistor R4, a port VINF2, and a port VREF2.

[0026] Further, the source of the MOS transistor M11 is connected to the source of the MOS transistor M13, the gate of the MOS transistor M11 is connected to the external control voltage V4, and the drain of the MOS transistor M11 is connected to the drain of the MOS transistor M12. The drain of the MOS transistor M12 is connected to the port VREF2, the gate of the MOS transistor M12 is connected to the external control voltage V4, and the source of the MOS transistor M12 is connected to the source of the MOS transistor M14. The drain of the MOS transistor M13 is connected to the port VINF2, the gate of the MOS transistor M13 is connected to the external control voltage V3, and the source of the MOS transistor M13 is connected to the source of the MOS transistor M11. The drain of the MOS transistor M14 is connected to the drain of the MOS transistor M12, the gate of the MOS transistor M14 is connected to the external control voltage V3, the source of the MOS transistor M14 is connected to the upper end of the resistor R4, and the lower end of the resistor R4 is connected to the gate of the MOS transistor M20.

[0027] Further, the transfer amplification circuit comprises MOS transistors M15 to M26 and capacitors C1 to C2.

[0028] Further, the drain of the MOS transistor M15 is connected to a power supply VD1, the gate of the MOS transistor M15 is connected to an external control voltage V1, and the source of the MOS transistor M15 is connected to the drain of the MOS transistor M18. The drain of the MOS transistor M16 is connected to the source of the MOS transistor M19, the gate of the MOS transistor M16 is connected to the external control voltage V1, and the source of the MOS transistor M16 is connected to a low potential VSS.

[0029] Further, the drain of the MOS transistor M17 is connected to the drain of the MOS transistor M21, the gate of the MOS transistor M17 is connected to the gate of the MOS transistor M21, and the source of the MOS transistor M17 is connected to the source of the MOS transistor M18. The source of the MOS transistor M18 is connected to the source of the MOS transistor M17, the gate of the MOS transistor M18 is connected to an external control voltage V2, and the drain of the MOS transistor M18 is connected to the upper end of a capacitor C1. The source of the MOS transistor M19 is connected to the lower end of the capacitor C1, the gate of the MOS transistor M19 is connected to the external control voltage V2, and the drain of the MOS transistor M19 is connected to the source of the MOS transistor M20.

[0030] Further, the source of the MOS transistor M20 is connected to the drain of the MOS transistor M19, the gate of the MOS transistor M20 is connected to the gate of the MOS transistor M24, and the drain of the MOS transistor M20 is connected to the drain of the MOS transistor M24. The drain of the MOS transistor M21 is connected to the source of the MOS transistor M27, the gate of the MOS transistor M21 is connected to the source of the MOS transistor M13, and the source of the MOS transistor M21 is connected to the drain of the MOS transistor M22. The drain of the MOS transistor M22 is connected to the source of the MOS transistor M21, the gate of the MOS transistor M22 is connected to the external control voltage V2, and the source of the MOS transistor M22 is connected to the upper end of a capacitor C2. The drain of the MOS transistor M23 is connected to the lower end of the capacitor C2, the gate of the MOS transistor M23 is connected to the external control voltage V2, and the source of the MOS transistor M23 is connected to the source of the MOS transistor M24. The source of the MOS transistor M24 is connected to the source of the MOS transistor M23, the gate of the MOS transistor M24 is connected to the lower end of a resistor R4, and the drain of the MOS transistor M24 is connected to the source of the MOS transistor M29.

[0031] Further, the source of the MOS transistor M25 is connected to the low potential VSS, the gate of the MOS transistor M25 is connected to the external control voltage V1, and the drain of the MOS transistor M25 is connected to the source of the MOS transistor M22. The source of the MOS transistor M26 is connected to the drain of the MOS transistor M23, the gate of the MOS transistor M26 is connected to the external control voltage V1, and the drain of the MOS transistor M26 is connected to the power supply VD1.

[0032] Further, the output circuit includes MOS transistors M27 to M30, capacitors C3 to C4, a port VIA, and a port VRA.

[0033] Further, the drain of the MOS transistor M27 is connected to the power supply VD2, the gate of the MOS transistor M27 is connected to the external control voltage V4, the source of the MOS transistor M27 is connected to the upper end of the capacitor C3 and the port VIA. The drain of the MOS transistor M28 is connected to the lower end of the capacitor C3, the gate of the MOS transistor M28 is connected to the drain of the MOS transistor M28, and the source of the MOS transistor M28 is grounded. The drain of the MOS transistor M29 is connected to the power supply VD2, the gate of the MOS transistor M29 is connected to the external control voltage V4, and the source of the MOS transistor M29 is connected to the upper end of the capacitor C4 and the port VRA. The drain of the MOS transistor M30 is connected to the lower end of the capacitor C4, the gate of the MOS transistor M30 is connected to the drain of the MOS transistor M30, and the source of the MOS transistor M30 is grounded.

[0034] Compared with the prior art, the present application has the following advantages:

[0035] The application provides a dynamic reference voltage amplification integrated circuit, which comprises a dynamic reference voltage circuit and a double-path output amplification circuit, wherein an input voltage vinf can be received through a port VINF1 in the dynamic reference voltage circuit and a port VINF2 in the double-path output amplification circuit, the received dynamic reference voltage vref is transmitted to the port VREF2 through the port VREF1 and the port VREF2, and the input voltage vinf and the dynamic reference voltage vref are amplified by the double-path output amplification circuit and output through the port VIA and the port VRA respectively. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 It is a schematic diagram of the overall principle structure of the application.

[0037] Figure 2 It is a schematic diagram of the principle structure of the dynamic reference voltage circuit of the application.

[0038] Figure 3 It is a schematic diagram of the principle structure of the double-path output amplification circuit of the application.

[0039] REFERENCE SIGNS:

[0040] 1 - dynamic reference voltage circuit; 2 - dual output amplification circuit; 11 - biasing circuit; 12 - reference voltage circuit; 21 - input control circuit; 22 - transfer amplification circuit; 23 - output circuit. DETAILED DESCRIPTION

[0041] In order to make the above objectives, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0042] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "arrange", "mount", "connect", "connect" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected; it can be directly connected, or indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0043] In the description of the present application, the description of the terms "embodiment", "one embodiment" and "one embodiment" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or embodiment are included in at least one embodiment or embodiment of the present application. In the present application, the illustrative description of the above terms does not necessarily refer to the same embodiment or embodiment. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or embodiments in a suitable manner.

[0044] As shown in Figure 1 A dynamic reference voltage amplification integrated circuit includes a dynamic reference voltage circuit 1 and a dual output amplification circuit 2.

[0045] It should be noted that the dynamic reference voltage circuit 1 is adapted to generate a corresponding reference voltage vref according to the input voltage vinf, so that the input voltage and the reference voltage maintain a sufficient voltage difference.

[0046] The dynamic reference voltage circuit 1 outputs a dynamically changing reference voltage vref.

[0047] The dual output amplification circuit 2 can amplify and output the input voltage vinf and the reference voltage vref.

[0048] Based on the design of the related circuit structure, the dual output amplification circuit 2 uses the related capacitance voltage to amplify the input voltage and the reference voltage, without inputting the offset voltage at the input port of the amplification circuit, which reduces the power consumption of the system and the demand for power supply voltage for normal operation of the system, and further ensures the voltage difference range between the input voltage and the reference voltage.

[0049] The dynamic reference voltage circuit 1 comprises ports VB, VINF1 and VREF1.

[0050] The dual-output amplification circuit 2 comprises ports VINF2, VREF2, VIA and VRA.

[0051] The port VB is an input port of the external bias voltage vb. The ports VINF1 and VINF2 are input ports of the input voltage vinf. The ports VREF1 and VREF2 are connected and used for transmitting the dynamic reference voltage vref. The port VIA is an output port of the amplified input voltage vi. The port VRA is an output port of the amplified dynamic reference voltage vr.

[0052] As shown in Figure 1 , the dynamic reference voltage circuit 1 comprises a bias circuit 11 and a reference voltage circuit 12.

[0053] It should be noted that the bias circuit 11 is connected with the reference voltage circuit 12, and the bias circuit 11 provides corresponding high-stability bias voltage for the reference voltage circuit, so that the reference voltage circuit 12 is in a normal working state.

[0054] As shown in Figure 1 , the dual-output amplification circuit 2 comprises an input control circuit 21, a transfer amplification circuit 22 and an output circuit 23.

[0055] It should be noted that the input control circuit 21 is connected with the transfer amplification circuit 22, the port VINF2 receives the input voltage vinf, and the port VREF2 receives the dynamic reference voltage vref. The input control circuit 21 controls whether the input voltage vinf and the dynamic reference voltage vref are input into the transfer amplification circuit 22.

[0056] The transfer amplification circuit 22 is connected with the output circuit 23, the transfer amplification circuit 22 inputs the preliminarily amplified input voltage vinf and the dynamic reference voltage vref into the output circuit 23, and the output circuit 23 outputs the completely amplified input voltage vinf and the dynamic reference voltage vref through the port.

[0057] In an embodiment of the present application, as shown in Figure 2 , the bias circuit 11 comprises MOS tubes M1 to M5, resistors R1 to R2 and the port VB.

[0058] The source of the MOS transistor M1 is connected to the port VB, the gate of the MOS transistor M1 is connected to the gate of the MOS transistor M4, and the drain of the MOS transistor M1 is connected to the source of the MOS transistor M2. The source of the MOS transistor M2 is connected to the gate of the MOS transistor M1, the gate of the MOS transistor M2 is connected to the drain of the MOS transistor M2, and the drain of the MOS transistor M2 is connected to the drain of the MOS transistor M3. The drain of the MOS transistor M3 is connected to the gate of the MOS transistor M2, the gate of the MOS transistor M3 is connected to the gate of the MOS transistor M5, and the source of the MOS transistor M3 is connected to the upper end of the resistor R1, and the lower end of the resistor R1 is grounded.

[0059] The source of the MOS transistor M4 is connected to the gate of the MOS transistor M8, the gate of the MOS transistor M4 is connected to the drain of the MOS transistor M1, and the drain of the MOS transistor M4 is connected to the drain of the MOS transistor M5. The drain of the MOS transistor M5 is connected to the drain of the MOS transistor M4, the gate of the MOS transistor M5 is connected to the drain of the MOS transistor M5, and the source of the MOS transistor M5 is connected to the upper end of the resistor R2, and the lower end of the resistor R2 is grounded.

[0060] It should be noted that the connection structure of the MOS transistors M1, M3, M4 and M5 makes the source of the MOS transistor M1 have a virtual break characteristic, that is, the source current of the MOS transistor M1 is irrelevant to the source voltage of the MOS transistor M1, but is related to the source current of the MOS transistor M4. The connection structure of the MOS transistors M1, M3, M4 and M5 makes the source of the MOS transistor M4 have a virtual short characteristic, that is, the source voltage of the MOS transistor M4 is irrelevant to the source current of the MOS transistor M4, but follows the change of the source voltage of the MOS transistor M1.

[0061] Since the source of the MOS transistor M1 is connected to the port VB, and the source of the MOS transistor M4 is connected to the gate of the MOS transistor M8, the gate voltage of the MOS transistor M8 is exactly equal to the external bias voltage vb input by the port VB, and is not affected by the voltage jitter of the power supply VDD and the related branch leakage current, effectively improving the accuracy and anti-interference ability of the dynamic reference voltage circuit 1. The related circuit connection structure of the MOS transistor M2 can effectively suppress the reverse current in the branch, and the resistors R1 and R2 serve as branch current limiting.

[0062] In an embodiment of the present application, as shown in Figure 2 The reference voltage circuit 12 includes MOS transistors M6 to M10, a resistor R3, a port VINF1 and a port VREF1.

[0063] The drain of the MOS transistor M7 is connected to the port VINF1, the gate of the MOS transistor M7 is connected to the drain of the MOS transistor M6, and the source of the MOS transistor M7 is connected to the gate of the MOS transistor M10. The drain of the MOS transistor M6 is connected to the source of the MOS transistor M7, the gate of the MOS transistor M6 is connected to the gate of the MOS transistor M3, and the source of the MOS transistor M6 is connected to the upper end of the resistor R3, and the lower end of the resistor R3 is grounded.

[0064] The source of the MOS transistor M8 is connected to the power supply VDD, the gate of the MOS transistor M8 is connected to the source of the MOS transistor M4, and the drain of the MOS transistor M8 is connected to the source of the MOS transistor M9. The source of the MOS transistor M9 is connected to the drain of the MOS transistor M8, the gate of the MOS transistor M9 is connected to the drain of the MOS transistor M9, and the drain of the MOS transistor M9 is connected to the drain of the MOS transistor M10. The drain of the MOS transistor M10 is connected to the port VREF1, the gate of the MOS transistor M10 is connected to the source of the MOS transistor M7, and the source of the MOS transistor M10 is grounded.

[0065] It should be noted that the gate of the MOS transistor M6 is connected to the gate of the MOS transistor M5, and based on the connection structure of the related circuit of the MOS transistor M5, the drain-source branch current of the MOS transistor M6 is in a mirror relationship with the drain-source branch current of the MOS transistor M5. Under the action of the drain-source branch current of the MOS transistor M6, the MOS transistor M7 is biased to be turned on. The port VINF1 is connected to the drain of the MOS transistor M7, and after the MOS transistor M7 is turned on, the input voltage vinf is transmitted to the gate of the MOS transistor M10 through the port VINF and the MOS transistor M7.

[0066] The MOS transistor M10 is biased to work in the saturation region, so that the gate voltage of the MOS transistor M10 is in a linear inverse proportion relationship with the drain voltage thereof. The MOS transistor M8 is biased to work in the linear region and serves as an active load of the MOS transistor M10. The MOS transistor M9 is used to suppress the reverse leakage current and has a small on-voltage drop. The node voltage of the drain of the MOS transistor M10 and the drain of the MOS transistor M9 serves as a dynamic reference voltage vref, which is output through the port VREF1. Based on the circuit connection structure of the reference voltage circuit 12, the relationship expression between the input voltage vinf and the dynamic reference voltage vref is shown in formula (1).

[0067]

[0068] wherein, V DD is the power supply VDD voltage value, W 10 is the conductive channel width of the MOS transistor M10, W8 is the channel width of the MOS transistor M8, K is a manufacturing process parameter, L8 is the conductive channel length of the MOS transistor M8, V TH10 is the threshold voltage of the MOS transistor M10, μ n is the electron mobility, C OX is the unit area capacitance value of the oxide layer, V GS8 is the gate-source voltage of the MOS transistor M8, V TH8 is the threshold voltage of the MOS transistor M8.

[0069] As can be seen from the expression (1), the input voltage vinf is in linear inverse proportion to the dynamic reference voltage vref, and as the input voltage vinf changes continuously, the dynamic reference voltage vref can always maintain a large enough voltage difference with the input voltage vinf, thereby improving the anti-interference ability of the circuit for reading data.

[0070] In one embodiment of the present application, as shown in Figure 3 the input control circuit 21 comprises MOS transistors M11 to M14, a resistor R4, a port VINF2 and a port VREF2.

[0071] The source of the MOS transistor M11 is connected to the source of the MOS transistor M13, the gate of the MOS transistor M11 is connected to an external control voltage V4, and the drain of the MOS transistor M11 is connected to the drain of the MOS transistor M12. The drain of the MOS transistor M12 is connected to the port VREF2, the gate of the MOS transistor M12 is connected to the external control voltage V4, and the source of the MOS transistor M12 is connected to the source of the MOS transistor M14. The drain of the MOS transistor M13 is connected to the port VINF2, the gate of the MOS transistor M13 is connected to an external control voltage V3, and the source of the MOS transistor M13 is connected to the source of the MOS transistor M11. The drain of the MOS transistor M14 is connected to the drain of the MOS transistor M12, the gate of the MOS transistor M14 is connected to the external control voltage V3, and the source of the MOS transistor M14 is connected to the upper end of the resistor R4, and the lower end of the resistor R4 is connected to the gate of the MOS transistor M20.

[0072] It should be noted that the input voltage vinf is input into the dual-output amplification circuit 2 through the port VINF2, and the dynamic reference voltage vref is input into the dual-output amplification circuit 2 through the port VREF2.

[0073] The MOS transistors M11 to M14 are used to control the transmission paths of the input voltage vinf and the dynamic reference voltage vref. When the MOS transistor M11 is turned on, the dynamic reference voltage vinf is transmitted to the gate of the MOS transistor M17. When the MOS transistor M12 is turned on, the dynamic reference voltage vref is transmitted to the gate of the MOS transistor M20. When the MOS transistor M13 is turned on, the dynamic reference voltage vinf is transmitted to the gate of the MOS transistor M17. When the MOS transistor M14 is turned on, the dynamic reference voltage vref is transmitted to the gate of the MOS transistor M20.

[0074] In one embodiment of the present application, as shown in Figure 3 the transfer amplification circuit 22 comprises MOS transistors M15 to M26 and capacitors C1 to C2.

[0075] The drain of the MOS transistor M15 is connected to a power supply VD1, the gate of the MOS transistor M15 is connected to an external control voltage V1, and the source of the MOS transistor M15 is connected to the drain of the MOS transistor M18. The drain of the MOS transistor M16 is connected to the source of the MOS transistor M19, the gate of the MOS transistor M16 is connected to the external control voltage V1, and the source of the MOS transistor M16 is connected to a low potential VSS.

[0076] The drain of the MOS transistor M17 is connected to the drain of the MOS transistor M21, the gate of the MOS transistor M17 is connected to the gate of the MOS transistor M21, and the source of the MOS transistor M17 is connected to the source of the MOS transistor M18. The source of the MOS transistor M18 is connected to the source of the MOS transistor M17, the gate of the MOS transistor M18 is connected to an external control voltage V2, and the drain of the MOS transistor M18 is connected to the upper end of a capacitor C1. The source of the MOS transistor M19 is connected to the lower end of the capacitor C1, the gate of the MOS transistor M19 is connected to the external control voltage V2, and the drain of the MOS transistor M19 is connected to the source of the MOS transistor M20.

[0077] The source of the MOS transistor M20 is connected to the drain of the MOS transistor M19, the gate of the MOS transistor M20 is connected to the gate of the MOS transistor M24, and the drain of the MOS transistor M20 is connected to the drain of the MOS transistor M24. The drain of the MOS transistor M21 is connected to the source of the MOS transistor M27, the gate of the MOS transistor M21 is connected to the source of the MOS transistor M13, and the source of the MOS transistor M21 is connected to the drain of the MOS transistor M22. The drain of the MOS transistor M22 is connected to the source of the MOS transistor M21, the gate of the MOS transistor M22 is connected to the external control voltage V2, and the source of the MOS transistor M22 is connected to the upper end of a capacitor C2. The drain of the MOS transistor M23 is connected to the lower end of the capacitor C2, the gate of the MOS transistor M23 is connected to the external control voltage V2, and the source of the MOS transistor M23 is connected to the source of the MOS transistor M24. The source of the MOS transistor M24 is connected to the source of the MOS transistor M23, the gate of the MOS transistor M24 is connected to the lower end of a resistor R4, and the drain of the MOS transistor M24 is connected to the source of the MOS transistor M29.

[0078] The source of the MOS transistor M25 is connected to the low potential VSS, the gate of the MOS transistor M25 is connected to the external control voltage V1, and the drain of the MOS transistor M25 is connected to the source of the MOS transistor M22. The source of the MOS transistor M26 is connected to the drain of the MOS transistor M23, the gate of the MOS transistor M26 is connected to the external control voltage V1, and the drain of the MOS transistor M26 is connected to the power supply VD1.

[0079] It should be noted that the MOS transistors M17 and M24 are P-channel MOS transistors, and the MOS transistors M15, M16, M18, M19, M20, M21, M22, M23, M25, and M26 are N-channel MOS transistors.

[0080] MOS transistor M15 and M16 are state reset control switches of capacitor C1, MOS transistor M25 and M26 are state reset control switches of capacitor C2. MOS transistor M18 and M19 are charge and discharge control switches of capacitor C1, MOS transistor M22 and M23 are charge and discharge control switches of capacitor C2. MOS transistor M17, M21, M20 and M24 are used to receive and transfer input voltage vinf and dynamic reference voltage vref according to the working state of the circuit. Capacitor C1 and C2 are used to amplify input voltage vinf and dynamic reference voltage vref respectively.

[0081] In one embodiment of the present application, as shown in Figure 3 Output circuit 23 includes MOS transistor M27 to M30, capacitor C3 to C4, port VIA, and port VRA.

[0082] The drain of MOS transistor M27 is connected to power supply VD2, the gate of MOS transistor M27 is connected to external control voltage V4, and the source of MOS transistor M27 is connected to the upper end of capacitor C3 and port VIA. The drain of MOS transistor M28 is connected to the lower end of capacitor C3, the gate of MOS transistor M28 is connected to the drain of MOS transistor M28, and the source of MOS transistor M28 is grounded. The drain of MOS transistor M29 is connected to power supply VD2, the gate of MOS transistor M29 is connected to external control voltage V4, and the source of MOS transistor M29 is connected to the upper end of capacitor C4 and port VRA. The drain of MOS transistor M30 is connected to the lower end of capacitor C4, the gate of MOS transistor M30 is connected to the drain of MOS transistor M30, and the source of MOS transistor M30 is grounded.

[0083] It should be noted that MOS transistor M27 is a branch control switch of power supply VD2. Capacitor C3 is used to amplify input voltage vinf. MOS transistor M28 is an active load at the output end. The voltage at the node of the upper end of capacitor C3 and the drain of MOS transistor M27 is the amplified voltage vi of input voltage vinf and is output through port VIA. MOS transistor M29 is a branch control switch of power supply VD2. Capacitor C4 is used to amplify dynamic reference voltage vref. MOS transistor M30 is an active load at the output end. The voltage at the node of the upper end of capacitor C4 and the drain of MOS transistor M29 is the amplified voltage vr of dynamic reference voltage vref and is output through port VRA.

[0084] It should be noted that the working process of two-way output amplification circuit 2 is divided into three stages.

[0085] Stage 1: external control voltages V4 and V1 are high, and external control voltages V3 and V2 are low. MOS transistors M11, M12, M15, M16, M25, M26, M27 and M29 are in the on state, and the other MOS transistors are in the off state.

[0086] The branch formed by the connection of power supply VDD, M15, Cl, M16, low potential VSS is conducted, so that the capacitor Cl is in a reset state. The branch formed by the connection of power supply VDD, M26, C2, M25, low potential VSS is conducted, so that the capacitor C2 is in a reset state.

[0087] The dynamic reference voltage vref is connected to M11 through port VREF2 to form a branch, enters the gate of M17 and M21, and makes M17 and M21 conductive. The dynamic reference voltage vref is connected to M12 and resistor R4 through port VREF2 to form a branch, enters the gate of M20 and M24, and makes M20 and M24 conductive.

[0088] Port VIA is connected to power supply VD2 through M27, and the voltage output by port VIA is equal to the voltage of power supply VD2. Port VRA is connected to power supply VD2 through M29, and the voltage output by port VRA is equal to the voltage of power supply VD2.

[0089] Stage 2: The external control voltages V4 and V2 are high, and the external control voltages V3 and V1 are low. MOS transistors M11, M12, M17, M18, M19, M20, M21, M22, M23, M24, M27, and M29 are in a conductive state, and the other MOS transistors are in a cut-off state.

[0090] The dynamic reference voltage vref is connected to M11 through port VREF2 to form a branch, enters the gate of M17 and M21, and makes M17 and M21 conductive. The dynamic reference voltage vref is connected to M12 and resistor R4 through port VREF2 to form a branch, enters the gate of M20 and M24, and makes M20 and M24 conductive.

[0091] Power supply VD2, M29, M20, M19, and capacitor Cl form a path A1, and power supply VD2 charges capacitor Cl through path A1. Power supply VD2, M27, M21, M22, and capacitor C2 form a path A2, and power supply VD2 charges capacitor C2 through path A2. Power supply VD2 charges capacitor C3 through M27, and power supply VD2 charges capacitor C4 through M29.

[0092] Stage 3: The external control voltages V3 and V2 are high, and the external control voltages V4 and V1 are low. MOS transistors M13, M14, M17, M18, M19, M20, M21, M22, M23, and M24 are in a conductive state, and the other MOS transistors are in a cut-off state.

[0093] The input voltage vinf is input to the gates of M17 and M21 through a branch formed by connecting port VINF2 with M13, and is input to port VIA through the drain node of M17 and M21. Capacitors C1 and C3 amplify the input voltage vinf, so that the voltage output by port VIA is the amplified voltage vi. The input voltage vref is input to the gates of M20 and M24 through a branch formed by connecting port VREF2 with M14, and is input to port VRA through the drain node of M20 and M24. Capacitors C2 and C4 amplify the input voltage vref, so that the voltage output by port VRA is the amplified voltage vr.

[0094] Although the present disclosure is disclosed as above, the protection scope of the present disclosure is not limited to this. Various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the present disclosure, and these changes and modifications shall fall within the protection scope of the present disclosure.

Claims

1. A dynamic reference voltage amplifier integrated circuit, Its features are, Includes: a dynamic reference voltage circuit (1) and a dual-output amplifier circuit (2); The dynamic reference voltage circuit (1) includes ports VB, VINF1 and VREF1; The dual-output amplifier circuit (2) includes ports VINF2, VREF2, VIA and VRA; Port VB is the input port for the external bias voltage vb; ports VINF1 and VINF2 are both input ports for the input voltage vinf; ports VREF1 and VREF2 are connected and used to transmit the dynamic reference voltage vref; port VIA is the output port for amplifying the input voltage vi; port VRA is the output port for amplifying the dynamic reference voltage vr. The dynamic reference voltage circuit (1) is suitable for generating a corresponding reference voltage vref based on the input voltage vif; The dual-output amplifier circuit (2) is suitable for amplifying and outputting the input voltage vinf and the dynamic reference voltage vref; The dual-output amplifier circuit (2) includes an input control circuit (21), a transfer amplifier circuit (22), and an output circuit (23); The input control circuit (21) is connected to the transfer amplifier circuit (22). Port VINF2 receives the input voltage vinf, and port VREF2 receives the dynamic reference voltage vref. The input control circuit (21) controls whether the input voltage vinf and the dynamic reference voltage vref are input into the transfer amplifier circuit (22). The transfer amplifier circuit (22) is connected to the output circuit (23). The transfer amplifier circuit (22) inputs the initially amplified input voltage vinf and dynamic reference voltage vref into the output circuit (23). The output circuit (23) outputs the fully amplified input voltage vinf and dynamic reference voltage vref through the port. The input control circuit (21) includes MOSFETs M11 to M14, resistor R4, port VINF2, and port VREF2; The transfer amplifier circuit (22) includes MOSFETs M15 to M26 and capacitors C1 to C2; The output circuit (23) includes MOSFETs M27 to M30, capacitors C3 to C4, port VIA, and port VRA; The source of MOSFET M13 is connected to the gate of MOSFET M17, and the gate of MOSFET M17 is connected to the gate of MOSFET M21. The upper end of resistor R4 is connected to the source of MOSFET M14, and the lower end of resistor R4 is connected to the gate of MOSFET M20. The gate of MOSFET M20 is connected to the gate of MOSFET M24. The drain of MOSFET M17 is connected to the drain of MOSFET M21, and the drain of MOSFET M21 is connected to the source of MOSFET M27. The drain of MOSFET M20 is connected to the drain of MOSFET M24, and the drain of MOSFET M24 is connected to the source of MOSFET M29.

2. The dynamic reference voltage amplifier integrated circuit according to claim 1, characterized in that, The dynamic reference voltage circuit (1) includes a bias circuit (11) and a reference voltage circuit (12); The bias circuit (11) is connected to the reference voltage circuit (12). The bias circuit (11) provides a corresponding high-stability bias voltage to the reference voltage circuit (12) so that the reference voltage circuit (12) is in normal working condition.

3. The dynamic reference voltage amplifier integrated circuit according to claim 2, characterized in that, The bias circuit (11) includes MOSFETs M1 to M5, resistors R1 to R2, and port VB; The source of MOSFET M1 is connected to port VB, the gate of MOSFET M1 is connected to the gate of MOSFET M4, and the drain of MOSFET M1 is connected to the source of MOSFET M2. The source of MOSFET M2 is connected to the gate of MOSFET M1, the gate of MOSFET M2 is connected to the drain of MOSFET M2, and the drain of MOSFET M2 is connected to the drain of MOSFET M3. The drain of MOSFET M3 is connected to the gate of MOSFET M2, the gate of MOSFET M3 is connected to the gate of MOSFET M5, and the source of MOSFET M3 is connected to the upper end of resistor R1. The lower end of resistor R1 is grounded. The source of MOSFET M4 is connected to the gate of MOSFET M8, the gate of MOSFET M4 is connected to the drain of MOSFET M1, and the drain of MOSFET M4 is connected to the drain of MOSFET M5. The drain of MOSFET M5 is connected to the drain of MOSFET M4, the gate of MOSFET M5 is connected to the drain of MOSFET M5, and the source of MOSFET M5 is connected to the upper end of resistor R2. The lower end of resistor R2 is grounded.

4. The dynamic reference voltage amplifier integrated circuit according to claim 2, characterized in that, The reference voltage circuit (12) includes MOSFETs M6 to M10, resistor R3, port VINF1, and port VREF1; The drain of MOSFET M7 is connected to port VINF1, the gate of MOSFET M7 is connected to the drain of MOSFET M6, and the source of MOSFET M7 is connected to the gate of MOSFET M10. The drain of MOSFET M6 is connected to the source of MOSFET M7, the gate of MOSFET M6 is connected to the gate of MOSFET M3, the source of MOSFET M6 is connected to the upper end of resistor R3, and the lower end of resistor R3 is grounded. The source of MOSFET M8 is connected to the power supply VDD, the gate of MOSFET M8 is connected to the source of MOSFET M4, and the drain of MOSFET M8 is connected to the source of MOSFET M9. The source of MOSFET M9 is connected to the drain of MOSFET M8, the gate of MOSFET M9 is connected to the drain of MOSFET M9, and the drain of MOSFET M9 is connected to the drain of MOSFET M10. The drain of MOSFET M10 is connected to port VREF1, the gate of MOSFET M10 is connected to the source of MOSFET M7, and the source of MOSFET M10 is grounded.

5. The dynamic reference voltage amplifier integrated circuit according to claim 1, characterized in that, The source of MOSFET M11 is connected to the source of MOSFET M13, the gate of MOSFET M11 is connected to the external control voltage V4, and the drain of MOSFET M11 is connected to the drain of MOSFET M12. The drain of MOSFET M12 is connected to port VREF2, the gate of MOSFET M12 is connected to the external control voltage V4, and the source of MOSFET M12 is connected to the source of MOSFET M14. The drain of MOSFET M13 is connected to port VINF2, the gate of MOSFET M13 is connected to the external control voltage V3, and the source of MOSFET M13 is connected to the source of MOSFET M11. The drain of MOSFET M14 is connected to the drain of MOSFET M12, the gate of MOSFET M14 is connected to the external control voltage V3, and the source of MOSFET M14 is connected to the upper end of resistor R4. The lower end of resistor R4 is connected to the gate of MOSFET M20.

6. The dynamic reference voltage amplifier integrated circuit according to claim 1, characterized in that, The drain of MOSFET M15 is connected to power supply VD1, the gate of MOSFET M15 is connected to external control voltage V1, and the source of MOSFET M15 is connected to the drain of MOSFET M18; the drain of MOSFET M16 is connected to the source of MOSFET M19, the gate of MOSFET M16 is connected to external control voltage V1, and the source of MOSFET M16 is connected to a low potential VSS. The drain of MOSFET M17 is connected to the drain of MOSFET M21, the gate of MOSFET M17 is connected to the gate of MOSFET M21, and the source of MOSFET M17 is connected to the source of MOSFET M18. The source of MOSFET M18 is connected to the source of MOSFET M17, the gate of MOSFET M18 is connected to the external control voltage V2, and the drain of MOSFET M18 is connected to the upper end of capacitor C1. The source of MOSFET M19 is connected to the lower end of capacitor C1, the gate of MOSFET M19 is connected to the external control voltage V2, and the drain of MOSFET M19 is connected to the source of MOSFET M20. The source of MOSFET M20 is connected to the drain of MOSFET M19, the gate of MOSFET M20 is connected to the gate of MOSFET M24, and the drain of MOSFET M20 is connected to the drain of MOSFET M24. The drain of MOSFET M21 is connected to the source of MOSFET M27, the gate of MOSFET M21 is connected to the source of MOSFET M13, and the source of MOSFET M21 is connected to the drain of MOSFET M22. The drain of MOSFET M22 is connected to the source of MOSFET M21, the gate of MOSFET M22 is connected to the external control voltage V2, and the source of MOSFET M22 is connected to the upper end of capacitor C2. The drain of MOSFET M23 is connected to the lower end of capacitor C2, the gate of MOSFET M23 is connected to the external control voltage V2, and the source of MOSFET M23 is connected to the source of MOSFET M24. The source of MOSFET M24 is connected to the source of MOSFET M23, the gate of MOSFET M24 is connected to the lower end of resistor R4, and the drain of MOSFET M24 is connected to the source of MOSFET M29. The source of MOSFET M25 is connected to a low potential VSS, the gate of MOSFET M25 is connected to an external control voltage V1, and the drain of MOSFET M25 is connected to the source of MOSFET M22; the source of MOSFET M26 is connected to the drain of MOSFET M23, the gate of MOSFET M26 is connected to an external control voltage V1, and the drain of MOSFET M26 is connected to the power supply VD1.

7. The dynamic reference voltage amplifier integrated circuit according to claim 1, characterized in that, The drain of MOSFET M27 is connected to power supply VD2, the gate of MOSFET M27 is connected to external control voltage V4, and the source of MOSFET M27 is connected to the upper end of capacitor C3 and connected to port VIA; the drain of MOSFET M28 is connected to the lower end of capacitor C3, the gate of MOSFET M28 is connected to the drain of MOSFET M28, and the source of MOSFET M28 is grounded; the drain of MOSFET M29 is connected to power supply VD2, the gate of MOSFET M29 is connected to external control voltage V4, and the source of MOSFET M29 is connected to the upper end of capacitor C4 and connected to port VRA; the drain of MOSFET M30 is connected to the lower end of capacitor C4, the gate of MOSFET M30 is connected to the drain of MOSFET M30, and the source of MOSFET M30 is grounded.

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