Oscillator circuit and microcontroller

Abstract

The invention discloses an oscillator circuit and a microcontroller, and the oscillator circuit comprises a pre-voltage-stabilizing circuit which converts a first power supply voltage into a second power supply voltage, and the second power supply voltage is smaller than the first power supply voltage; the bias circuit is used for providing bias current based on the second power supply voltage; the clock signal generation circuit is used for outputting a square wave signal based on the bias current; and the clock signal output circuit is used for outputting a first clock signal working in a power domain corresponding to the first power supply voltage and a second clock signal working in a power domain corresponding to the second power supply voltage based on the square wave signal. Through the pre-voltage-stabilizing circuit, the first power supply voltage is converted into the second power supply voltage and then is output to the subsequent circuit, so that the problem that the low-speed oscillator cannot output the clock signal when the kernel power supply is closed or the power supply voltage drops to the level that the logic circuit cannot work normally is avoided; and the bias circuit can generate a bias current based on the second power supply voltage, and does not depend on an external bias current source.

Description

Technical Field

[0001] This invention belongs to the field of chip technology, specifically relating to an oscillator circuit and a microcontroller. Background Technology

[0002] In microcontroller unit (MCU) design, low power consumption has become one of the key metrics for measuring system performance. To support functions such as standby, wake-up, or time-hold, MCUs typically require a low-frequency clock source that can continue operating even when the system master clock is off. This type of clock source is generally provided by a low-frequency oscillator (LFO), whose core function is to generate a periodic signal (i.e., oscillation) through internal circuitry, thereby outputting a stable low-frequency clock signal.

[0003] However, traditional low-speed oscillator circuits typically rely on external bias current sources to maintain stable oscillation output. This not only increases the number of peripheral components and system cost, but also makes it difficult to further reduce static power consumption. Furthermore, when the core power is turned off or the supply voltage drops to a level where the logic circuit cannot function properly, the low-speed oscillator often cannot continue to output a valid clock signal. Summary of the Invention

[0004] In view of the above problems, embodiments of the present invention are proposed to provide an oscillator circuit and microcontroller that overcome or at least partially solve the above problems.

[0005] In a first aspect, embodiments of the present invention provide an oscillator circuit, the oscillator circuit comprising: A pre-regulatory circuit is used to receive a first power supply voltage, convert the first power supply voltage into a second power supply voltage, and then output it; the second power supply voltage is less than the first power supply voltage. A bias circuit is used to provide a bias current based on the second power supply voltage; A clock signal generating circuit is used to output a square wave signal based on the bias current; A clock signal output circuit is used to output a first clock signal operating in the power domain corresponding to the first power supply voltage and a second clock signal operating in the power domain corresponding to the second power supply voltage, based on the square wave signal.

[0006] Optionally, the bias circuit includes a first resistor and a current mirror; The first resistor is connected to the current mirror and is used to generate a reference current based on the second power supply voltage; The current mirror is used to provide the bias current based on the reference current.

[0007] Optionally, the current mirror includes a first MOSFET and a second MOSFET; One end of the first resistor is connected to the second power supply voltage, and the other end is connected to the input terminal of the first MOSFET, the control terminal of the first MOSFET, and the control terminal of the second MOSFET, respectively. The control terminal of the first MOSFET is connected to both the input terminal of the first MOSFET and the control terminal of the second MOSFET, and the output terminal of the first MOSFET is grounded. The output terminal of the second MOSFET is grounded; the input terminal of the second MOSFET is connected to the clock signal generation circuit to provide bias current.

[0008] Optionally, both the first MOS transistor and the second MOS transistor are NMOS transistors; the control terminals of the first MOS transistor and the second MOS transistor are both gates; the input terminals of the first MOS transistor and the second MOS transistor are both drains; and the output terminals of the first MOS transistor and the second MOS transistor are both sources.

[0009] Optionally, the pre-regulator circuit includes a first depletion-type NMOS transistor, a second depletion-type NMOS transistor, a second resistor, a first bipolar transistor, a second bipolar transistor, and a third bipolar transistor; The drain of the first depletion-type NMOS transistor and the drain of the second depletion-type NMOS transistor are connected to the first power supply voltage, and the gate of the first depletion-type NMOS transistor and the gate of the second depletion-type NMOS transistor are connected. One end of the second resistor is connected to the source of the second depletion-type NMOS transistor, and the other end is connected to the gate of the first depletion-type NMOS transistor, the gate of the second depletion-type NMOS transistor, and the collector of the first bipolar transistor, respectively. The base of the first bipolar transistor is connected to the base of the second bipolar transistor, and the emitter of the first bipolar transistor is connected to the emitter of the second bipolar transistor. The collector of the second bipolar transistor is connected to the base of the second bipolar transistor and the emitter of the third bipolar transistor, respectively; The collector of the third bipolar transistor is connected to the base of the third bipolar transistor and the source of the first depletion-type NMOS transistor, respectively. The bias circuit is connected at a node between the collector of the third bipolar transistor and the source of the first depletion-type NMOS transistor, and the voltage of the node is the second power supply voltage.

[0010] Optionally, the clock signal generating circuit includes a first capacitor, a second capacitor, a crystal oscillator, and a driving circuit; One end of the first capacitor is connected to one end of the crystal oscillator, and the other end of the first capacitor is grounded; One end of the second capacitor is connected to the other end of the crystal oscillator, and the other end of the second capacitor is grounded; The first input terminal of the driving circuit is connected to the bias circuit, the second input terminal is connected to one end of the crystal oscillator, and the output terminal is connected to the other end of the crystal oscillator and the clock signal output circuit, respectively, for outputting a square wave signal based on the bias current.

[0011] Optionally, the driving circuit includes a current source circuit, a feedback circuit, and a shaping circuit; The current source circuit is connected to the bias circuit and the feedback circuit respectively, and is used to adjust the current value output to the feedback circuit based on the first power supply voltage, the bias current and the digital signal. The feedback circuit is connected to the shaping circuit and is used to output a voltage signal to the shaping circuit; The shaping circuit is connected to the pre-regulatory circuit and is used to shape the voltage signal based on the power supply voltage of the second power supply to form a square wave signal and output it.

[0012] Optionally, the clock signal output circuit includes a first inverter, a second inverter, a delay circuit, a NAND gate, a level conversion circuit, a third inverter, and a fourth inverter; The input terminal of the first inverter is connected to the clock signal generating circuit, and the output terminal of the first inverter is connected to the second inverter and the delay circuit respectively; used to output an inverted square wave signal. The output of the second inverter is connected to the first input of the NAND gate, and is used to output a square wave signal after double inversion; The output terminal of the delay circuit is connected to the second input terminal of the NAND gate, and is used to output a delayed signal after a preset delay time based on the inverted square wave signal. The delayed signal is high level. The NAND gate is used to output a clock signal based on the square wave signal after the second inversion and the delayed signal; The third inverter is connected to the NAND gate and is used to invert the clock signal and output a second clock signal that operates in the power domain corresponding to the second power supply voltage. The level conversion circuit is connected to the output of the NAND gate and is used to convert the power domain of the clock signal into the power domain corresponding to the first power supply voltage. The fourth inverter is connected to the level conversion circuit and is used to invert the clock signal operating in the power domain corresponding to the first power supply voltage, and then output the first clock signal operating in the power domain corresponding to the first power supply voltage.

[0013] Optionally, the delay circuit includes a plurality of D flip-flops connected in series; The clock input of the first-stage D flip-flop is connected to the output of the first inverter, the data input of the first-stage D flip-flop is connected to the inverted output of the first-stage D flip-flop, and the inverted output of the first-stage D flip-flop is connected to the clock input of the next-stage D flip-flop. The clock input of the last stage D flip-flop is connected to the inverted output of the previous stage D flip-flop. The data input of the last stage D flip-flop receives a high level. The output of the last stage D flip-flop is connected to the second input of the NAND gate, which is used to output a delayed signal after a preset delay time. The delayed signal is a high level.

[0014] In a second aspect, embodiments of the present invention provide a microcontroller including an oscillator circuit as described in any of the preceding claims.

[0015] In an embodiment of the present invention, the oscillator circuit includes a pre-regulator circuit for receiving a first power supply voltage, converting the first power supply voltage into a second power supply voltage, and then outputting it; the second power supply voltage is less than the first power supply voltage; a bias circuit for providing a bias current based on the second power supply voltage; a clock signal generation circuit for outputting a square wave signal based on the bias current; and a clock signal output circuit for outputting a first clock signal operating in the power domain corresponding to the first power supply voltage and a second clock signal operating in the power domain corresponding to the second power supply voltage, based on the square wave signal. This embodiment of the present invention, through the pre-regulator circuit, converts the first power supply voltage into a second power supply voltage before outputting it to subsequent circuits, avoiding the problem that the low-speed oscillator cannot output a clock signal when the core power is off or the supply voltage drops to a level where the logic circuit cannot function properly. Furthermore, the bias circuit can generate a bias current based on the second power supply voltage, without relying on an external bias current source.

[0016] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of an oscillator circuit according to an embodiment of the present invention; Figure 2This is a schematic diagram of the pre-stabilized voltage circuit according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the bias circuit according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the clock signal generation circuit according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the driving circuit according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the clock signal output circuit according to an embodiment of the present invention.

[0018] Reference numerals: Pre-regulator circuit 10, first depletion-type NMOS transistor 11, second depletion-type NMOS transistor 12, second resistor 13, first bipolar transistor 14, second bipolar transistor 15, third bipolar transistor 16, bias circuit 20, first resistor 21, current mirror 22, first MOS transistor 221, second MOS transistor 222, clock signal generation circuit 30, first capacitor 31, second capacitor 32, crystal oscillator 33, drive circuit 34, current source circuit 341, feedback circuit 342, shaping circuit 343, clock signal output circuit 40, first inverter 41, second inverter 42, delay circuit 43, D flip-flop 431, NAND gate 44, level conversion circuit 45, third inverter 46, fourth inverter 47. Detailed Implementation

[0019] Embodiments of the present invention will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0020] In microcontroller unit design, low power consumption has become one of the key metrics for measuring system performance. To support functions such as standby, wake-up, or time-hold, MCUs typically require a low-frequency clock source that can continue operating even when the system master clock is off. This type of clock source is generally provided by a low-speed oscillator, whose core function is to generate a periodic signal (i.e., oscillation) through internal circuitry, thereby outputting a stable low-frequency clock signal.

[0021] However, traditional low-speed oscillator circuits typically rely on external bias current sources to maintain stable oscillation output. This not only increases the number of peripheral components and system cost, but also makes it difficult to further reduce static power consumption. Furthermore, when the core power is turned off or the supply voltage drops to a level where the logic circuit cannot function properly, the low-speed oscillator often cannot continue to output a valid clock signal.

[0022] One of the core concepts of this invention is that by using a pre-regulating circuit, the first power supply voltage is converted into a second power supply voltage and then output to the subsequent circuit. This avoids the problem that the low-speed oscillator cannot output a clock signal when the core power supply is turned off or the supply voltage drops to a level where the logic circuit cannot work properly. Furthermore, the bias circuit can generate a bias current based on the second power supply voltage, without relying on an external bias current source.

[0023] Reference Figure 1 The diagram illustrates a structural schematic of an oscillator circuit according to an embodiment of the present invention, which may specifically include the following structure: The pre-regulator circuit 10 is used to receive the first power supply voltage, convert the first power supply voltage into a second power supply voltage, and then output it; the second power supply voltage is less than the first power supply voltage.

[0024] The first power supply voltage can be the VCC power supply, which is the main power supply. After the first power supply voltage passes through the pre-regulator circuit 10, it outputs the second power supply voltage. The second power supply voltage can be the VDD voltage, which is close to the core voltage, and has a certain driving capability. The VDD voltage, which is close to the core voltage, is output through the pre-regulator circuit 10. It can also work normally in the low-power mode when there is no core voltage.

[0025] Bias circuit 20 is used to provide bias current based on the second power supply voltage.

[0026] The bias circuit 20 is connected to the pre-regulator circuit 10. Based on the second power supply voltage output by the pre-regulator circuit 10, the bias circuit 20 generates a self-biasing current and outputs the self-biasing current. By generating the self-biasing current through the bias circuit 20, no external bias is required, which can reduce the increase in power consumption caused by calling other resources, thereby reducing the power consumption of the overall circuit.

[0027] The clock signal generation circuit 30 is used to output a square wave signal based on the bias current.

[0028] The clock signal generating circuit 30 is connected to the bias circuit 20. The clock signal generating circuit 30 outputs a square wave signal based on the bias current provided by the bias circuit 20 and the power supply of the first power supply voltage VCC.

[0029] The clock signal output circuit 40 is used to output a first clock signal operating in the power domain corresponding to the first power supply voltage and a second clock signal operating in the power domain corresponding to the second power supply voltage, based on a square wave signal.

[0030] The clock signal output circuit 40 is connected to the clock signal generating circuit 30. The clock signal output circuit 40 receives the square wave signal output by the clock signal generating circuit 30 and outputs a first clock signal and a second clock signal based on the square wave signal. The first clock signal operates in the power domain corresponding to the first power supply voltage and is a square wave signal that jumps between 0 V and VCC. The second clock signal operates in the power domain corresponding to the second power supply voltage and is a square wave signal that jumps between 0 V and VDD.

[0031] In an embodiment of the present invention, the oscillator circuit includes a pre-regulator circuit for receiving a first power supply voltage, converting the first power supply voltage into a second power supply voltage, and then outputting it; the second power supply voltage is less than the first power supply voltage; a bias circuit for providing a bias current based on the second power supply voltage; a clock signal generation circuit for outputting a square wave signal based on the bias current; and a clock signal output circuit for outputting a first clock signal operating in the power domain corresponding to the first power supply voltage and a second clock signal operating in the power domain corresponding to the second power supply voltage, based on the square wave signal. This embodiment of the present invention, through the pre-regulator circuit, converts the first power supply voltage into a second power supply voltage before outputting it to subsequent circuits, avoiding the problem that the low-speed oscillator cannot output a clock signal when the core power is off or the supply voltage drops to a level where the logic circuit cannot function properly. Furthermore, the bias circuit can generate a bias current based on the second power supply voltage, without relying on an external bias current source.

[0032] Reference Figure 2 The diagram shows a pre-regulator circuit 10 according to an embodiment of the present invention, which may specifically include the following structure: The pre-regulator circuit 10 includes a first depletion-type NMOS transistor 11, a second depletion-type NMOS transistor 12, a second resistor 13, a first bipolar transistor 14, a second bipolar transistor 15, and a third bipolar transistor 16.

[0033] The drain of the first depletion-type NMOS transistor 11 and the drain of the second depletion-type NMOS transistor 12 are connected to the first power supply voltage, and the gate of the first depletion-type NMOS transistor 11 and the gate of the second depletion-type NMOS transistor 12 are connected.

[0034] When the gate-source voltage is 0, the channel of a depletion-type NMOS transistor already exists, and the device is in the on state. Only when a negative gate-source voltage is applied will the carriers in the channel be depleted, causing the current to decrease or even be cut off. When the pre-regulator circuit 10 is powered on, the first depletion-type NMOS transistor 11 and the second depletion-type NMOS transistor 12 are always on.

[0035] One end of the second resistor 13 is connected to the source of the second depletion-type NMOS transistor 12, and the other end is connected to the gate of the first depletion-type NMOS transistor 11, the gate of the second depletion-type NMOS transistor 12, and the collector of the first bipolar transistor 14, respectively.

[0036] The second resistor 13 is a current-limiting resistor. The function of the second resistor 13 is to prevent the pre-regulatory circuit 10 from consuming a large current.

[0037] The base of the first bipolar transistor 14 is connected to the base of the second bipolar transistor 15, and the emitter of the first bipolar transistor 14 is connected to the emitter of the second bipolar transistor 15.

[0038] The collector of the second bipolar transistor 15 is connected to the base of the second bipolar transistor 15 and the emitter of the third bipolar transistor 16.

[0039] The collector of the third bipolar transistor 16 is connected to the base of the third bipolar transistor 16 and the source of the first depletion-type NMOS transistor 11, respectively.

[0040] The first bipolar transistor 14, the second bipolar transistor 15, and the third bipolar transistor 16 can be identical NPN bipolar transistors with the same base-emitter voltage VBE. When the pre-regulator circuit 10 is powered on, the first depletion-type NMOS transistor 11 and the second depletion-type NMOS transistor 12 are always turned on, and the base voltages of the first bipolar transistor 14 and the second bipolar transistor 15 rise. Therefore, the pre-regulator circuit does not require a startup circuit.

[0041] The first bipolar transistor 14, the second bipolar transistor 15, and the third bipolar transistor 16 are located between the cutoff region and the amplification region. The current of the first bipolar transistor 14 is limited by the second resistor 13. The base and collector of the second bipolar transistor 15 and the third bipolar transistor 16 are shorted, so they are in the amplification region with the same current. However, the VBE of the first bipolar transistor 14 and the second bipolar transistor 15 are the same, so they are at the edge threshold of the operating region. Thus, the second bipolar transistor 15 and the third bipolar transistor 16 obtain a VCE that is approximately Von. At the node AVDD between the collector of the third bipolar transistor 16 and the source of the first depletion-type NMOS transistor 11, a voltage value less affected by VCC is obtained. This realizes the conversion of the first power supply voltage VCC into a second power supply voltage VDD that is close to the core voltage, so that the subsequent circuit can provide clock output under the condition of no core voltage. The circuit achieves low power consumption and does not rely on other references, current sources, amplifiers, LDOs, etc.

[0042] The bias circuit 20 is connected to node AVDD between the collector of the third bipolar transistor 16 and the source of the first depletion-type NMOS transistor 11. The voltage of node AVDD is the second power supply voltage.

[0043] At node AVDD, which is less affected by VCC, a second power supply voltage VDD is obtained between the collector of the third bipolar transistor 16 and the source of the first depletion-type NMOS transistor 11. The bias circuit 20 is connected to this node AVDD and receives the second power supply voltage VDD.

[0044] Reference Figure 3 The diagram shows a schematic of the bias circuit according to an embodiment of the present invention, which may specifically include the following structure: The bias circuit 20 includes a first resistor 21 and a current mirror 22.

[0045] The first resistor 21 is connected to the current mirror 22 and is used to generate a reference current based on the second power supply voltage VDD.

[0046] The current mirror 22 is used to provide a bias current IBIAS based on the reference current.

[0047] One end of the first resistor 21 is connected to the output terminal of the pre-regulator circuit 10, that is, to the node AVDD between the collector of the third bipolar transistor 16 and the source of the first depletion-type NMOS transistor 11. Based on the second power supply voltage VDD output by the pre-regulator circuit 10, a reference current is generated. The current mirror 22 is connected to the first resistor 21 and is used to replicate the reference current generated by the first resistor 21 to form a bias current IBIAS, which provides a stable and controllable bias current IBIAS for the clock signal generation circuit 30.

[0048] In this embodiment of the invention, the current mirror 22 includes a first MOS transistor 221 and a second MOS transistor 222.

[0049] One end of the first resistor 21 is connected to the second power supply voltage, and the other end is connected to the input terminal of the first MOSFET 221, the control terminal of the first MOSFET 221, and the control terminal of the second MOSFET 222, respectively.

[0050] The control terminal of the first MOSFET 221 is connected to the input terminal of the first MOSFET 221 and the control terminal of the second MOSFET 222, respectively, and the output terminal of the first MOSFET 221 is grounded.

[0051] The output terminal of the second MOSFET 222 is grounded; the input terminal of the second MOSFET 222 is connected to the clock signal generation circuit 30 to provide bias current IBIAS.

[0052] The first MOSFET 221 and the second MOSFET 222 form a current mirror structure. The branch containing the first MOSFET 221 is the reference branch, and the branch containing the second MOSFET 222 is the output branch. Both the first MOSFET 221 and the second MOSFET 222 operate in the saturation region. The first MOSFET 221 uses the second power supply voltage to apply a voltage to the first resistor 21 to obtain a reference current. The second MOSFET 222 replicates the reference current to obtain a bias current IBIAS, which is output as a current source and sent to the clock signal generation circuit as a reference bias current.

[0053] In this embodiment of the invention, the first MOS transistor 221 and the second MOS transistor 222 are both NMOS transistors; the control terminal of the first MOS transistor 221 and the control terminal of the second MOS transistor 222 are both gates; the input terminal of the first MOS transistor 221 and the input terminal of the second MOS transistor 222 are both drains; and the output terminal of the first MOS transistor 221 and the output terminal of the second MOS transistor 222 are both sources.

[0054] For example, both the first MOSFET 221 and the second MOSFET 222 are NMOS transistors. The first MOSFET 221 applies a voltage to the first resistor 21 using the second power supply voltage to obtain a reference current. The second MOSFET 222 replicates the reference current to obtain a bias current IBIAS, which is output as a current source and used as a reference bias current by the clock signal generation circuit. This achieves a self-biased current source, eliminating the need for external bias and reducing the power consumption caused by calling other resources, thus reducing the overall power consumption of the circuit.

[0055] Reference Figure 4 The diagram shows a schematic of the clock signal generation circuit according to an embodiment of the present invention, which may specifically include the following structure: The clock signal generating circuit 30 includes a first capacitor 31, a second capacitor 32, a crystal oscillator 33, and a driving circuit 34.

[0056] One end of the first capacitor 31 is connected to one end of the crystal oscillator 33, and the other end of the first capacitor 31 is grounded.

[0057] One end of the second capacitor 32 is connected to the other end of the crystal oscillator 33, and the other end of the second capacitor 32 is grounded.

[0058] The first input terminal of the driving circuit 34 is connected to the bias circuit 20, the second input terminal is connected to one end of the crystal oscillator 33, and the output terminal is connected to the other end of the crystal oscillator 33 and the clock signal output circuit 40, respectively, for outputting a square wave signal based on the bias current.

[0059] The first capacitor 31 and the second capacitor 32 are load capacitors, a common structure in crystal oscillator circuits. XIN and XOUT are external I / O pins connected to crystal oscillator 33. The function of crystal oscillator 33 is as follows: At the moment of enable, the circuit generates weak noise (including broadband signals), among which signals near the resonant frequency are selected by the crystal; crystal frequency selection, at the parallel resonant frequency (f... p At point f, the crystal is equivalent to a high-impedance inductor (ideally purely inductive), forming an LC resonant circuit with the load capacitance. p The frequency generates strong feedback; positive feedback amplification, and the drive circuit 34 (amplifier) ​​will amplify f. p The signal is amplified by 180° and then phase-shifted by 180° by the crystal. The output signal is in phase with the input signal, forming positive feedback. This cycle repeats, and the signal amplitude increases exponentially (amplitude condition is met). During the amplitude stabilization phase, when the signal amplitude increases to a certain value, the amplifier enters the nonlinear region, automatically limits the gain, and finally achieves stable oscillation, with the frequency locked at the nominal frequency of the crystal (32.768KHz).

[0060] The driving circuit 34 is powered by the first power supply voltage VCC. Its first input terminal is connected to the bias circuit 20. The first input terminal receives the bias current IBIAS output from the drain of the second MOSFET 222. Under the power supply voltage VCC, the driving circuit 34 outputs a square wave signal based on the bias current. This enables the generation of a square wave signal in low-power mode without core voltage and without external bias current, so that the clock signal output circuit 40 outputs a clock signal based on the square wave signal.

[0061] Reference Figure 5 The diagram shows a schematic of the driving circuit according to an embodiment of the present invention, which may specifically include the following structure: The driving circuit 34 includes a current source circuit 341, a feedback circuit 342, and a shaping circuit 343.

[0062] The current source circuit 341 is connected to the bias circuit 20 and the feedback circuit 342 respectively, and is used to adjust the current value output to the feedback circuit 342 based on the first power supply voltage, the bias current and the digital signal.

[0063] Feedback circuit 342 is connected to shaping circuit 343 and is used to output voltage signal to shaping circuit 343.

[0064] The shaping circuit 343 is connected to the pre-regulatory circuit 10. Based on the power supply of the second power supply voltage, it shapes the voltage signal to form a square wave signal and outputs it.

[0065] The current source circuit 341 controls the current magnitude using the digital signal ISEL<0:3>. The four control bits of ISEL<0:3> control current sources of 100nA, 200nA, 400nA, and 800nA respectively, thereby allowing the gain of the feedback network 342 to be controlled in 100nA steps. The reference current of the current source circuit 341 comes from the bias current IBIAS. The current source circuit 341 is powered by the first power supply voltage VCC. The digital signal is controlled by the digital circuit. When the digital circuit is not active, the default value can be used.

[0066] The current source circuit 341 can control the magnitude of the output current, thus enabling controllable current source magnitude. M10 is controlled by LOSC_E. When the LOSC circuit is enabled, LOSC_E is high, M10 is turned on, and M30 is turned off. M23, M22, M25, M28, M29, and M31 form a current mirror structure. M22, M25, M28, M29, and M31 form a current mirror with a ratio of 6:1:2:4:8, controlled by ISEL<0:3> for on / off states. The five current mirror branches are connected at one point to supply the feedback circuit 342. When LOSC_E is 0, M10 is turned off, and M30 is turned on, making the current in the current mirror circuit zero.

[0067] The shaping circuit 343 includes two inverters consisting of PM5 and NM0, and PM2 and NM3. PM2 and NM3 form the last stage driver for the clock output, which is powered by the second power supply voltage VDD provided by the pre-regulator circuit 10, and outputs a square wave signal with an amplitude range near the core voltage.

[0068] When operating, LOSC_E is high and LOSC_ENN is low. I58, I59, and M10 are turned on, while M30 and NM1 are turned off. The feedback network 342, composed of M19, M20, M21, and M46, starts working. The sine wave output on LOUT is shaped by two inverters, PM5 and NM0, and PM2 and NM3, to output a square wave at the frequency corresponding to the crystal oscillator. When not operating, LOSC_E is low and LOSC_ENN is high. I58, I59, and M10 are turned off, while M30 and NM1 are turned on. The current source 341 is turned off, and the input and output channels of the feedback network 342 are closed.

[0069] I58 and I59 are transmission gate circuits composed of parallel NMOS and PMOS transistors, equivalent to controllable switches. XIN and XOUT are the interfaces at both ends of the driver circuit 34, and also the interfaces at both ends of the crystal oscillator 33. The XOUT signal is fed back to XIN after passing through the crystal oscillator 33, forming a feedback loop. The waveforms at XIN and XOUT are inverted. Because the output waveform is a sine wave, it needs to be shaped by an inverter before being transmitted to other modules.

[0070] The current source circuit 341 serves to control the magnitude of the current source, and can control the gain of the feedback network 342 in 100nA steps. The reference current of the current source circuit 341 comes from the bias current IBIAS. The shaping circuit 343 is powered by the second power supply voltage VDD provided by the pre-regulator circuit 10, and outputs a square wave signal with an amplitude range near the core voltage, so that the clock signal output circuit 40 outputs a clock signal based on the square wave signal.

[0071] Reference Figure 6 The diagram illustrates the structure of a clock signal output circuit according to an embodiment of the present invention, which may specifically include the following structure: The clock signal output circuit 40 includes a first inverter 41, a second inverter 42, a delay circuit 43, a NAND gate 44, a level conversion circuit 45, a third inverter 46, and a fourth inverter 47.

[0072] The input terminal of the first inverter 41 is connected to the clock signal generating circuit 30, and the output terminal of the first inverter 41 is connected to the second inverter 42 and the delay circuit 43 respectively; it is used to output the inverted square wave signal.

[0073] The output of the second inverter 42 is connected to the first input of the NAND gate 44 to output a square wave signal after double inversion.

[0074] The output of the delay circuit 43 is connected to the second input of the NAND gate 44, and is used to output a delayed signal after a preset delay time based on the inverted square wave signal. The delayed signal is high level.

[0075] NAND gate 44 is used to output a clock signal based on a square wave signal after double inversion and a delayed signal.

[0076] The third inverter 46 is connected to the NAND gate 44 and is used to invert the clock signal and output a second clock signal that operates in the power domain corresponding to the second power supply voltage.

[0077] The level conversion circuit 45 is connected to the output of the NAND gate 44 and is used to convert the power domain of the clock signal into the power domain corresponding to the first power supply voltage.

[0078] The fourth inverter 47 is connected to the level conversion circuit 45 and is used to invert the clock signal operating in the power domain corresponding to the first power supply voltage and output the first clock signal operating in the power domain corresponding to the first power supply voltage.

[0079] The delay circuit 43 maintains a high-level output delay signal after the preset delay time ends. That is, the signal received at the second input terminal of the NAND gate 44 remains high after the preset delay time ends. The signal received at the first input terminal of the NAND gate 44 is a square wave signal. The square wave signal output by the second inverter 42 after two inversions is the square wave signal itself. For example, the high level remains high after two inversions. When all inputs of the NAND gate 44 are high, the output is low. As long as one input is low, the output is high. Since the signal received at the second input terminal of the NAND gate 44 remains high, when the square wave signal received at the second input terminal is high, the NAND gate 44 outputs a low level, and when the square wave signal received at the second input terminal is low, the NAND gate 44 outputs a high level. Therefore, an inverter is needed to shape and invert the signal of the NAND gate 44 so that the level of the output signal is consistent with the square wave signal. The third inverter 46 outputs the first square wave clock signal in the VCC domain, and the fourth inverter 47 outputs the second square wave clock signal in the VDD domain.

[0080] Since the frequency of the initial waveform during the start-up phase of the crystal oscillator 33 does not reach 32.768kHz, the square wave output after a delay is the waveform with the accurate frequency. Therefore, after the preset delay time, the delay circuit 43 needs to input a high-level delay signal to the second input terminal of the NAND gate 44 so that the NAND gate 44 outputs a 32.768kHz square wave clock signal. After passing through the third inverter 46, the square wave clock signal is output as the first square wave clock signal in the VCC domain. After passing through the level conversion circuit 45 and the fourth inverter 47, the output is the second square wave clock signal in the VDD domain, thus realizing the square wave clock signal output in the dual power supply domain.

[0081] In this embodiment of the invention, the delay circuit 43 includes a plurality of D flip-flops 431 connected in series.

[0082] The clock input of the first-stage D flip-flop 431 is connected to the output of the first inverter 41, the data input of the first-stage D flip-flop 431 is connected to the inverted output of the first-stage D flip-flop 431, and the inverted output of the first-stage D flip-flop 431 is connected to the clock input of the next-stage D flip-flop 431.

[0083] The clock input of the last stage D flip-flop 431 is connected to the inverted output of the previous stage D flip-flop 431. The data input of the last stage D flip-flop 431 receives a high level. The output of the last stage D flip-flop 431 is connected to the second input of the NAND gate 44, which is used to output a delayed signal after the preset delay time. The delayed signal is a high level.

[0084] The delay circuit 43 utilizes superimposed D flip-flops 431 to take only the rising edge of the inverted square wave signal (XOUT signal). After passing through N D flip-flops 431, it outputs a square wave with a frequency of XOUT / 2n. This square wave is then passed through the last stage D flip-flop 431, with its first rising edge serving as the enable signal, thus obtaining a fixed delay time. The data input terminal TIEH of the last stage D flip-flop 431 is a high-level signal. Therefore, after a fixed delay time, the delayed signal output by the last stage D flip-flop 431 becomes a high-level signal and remains high before being transmitted to the second input terminal of the NAND gate 44. Since the initial waveform frequency of the crystal oscillator 33 during its oscillation phase has not reached 32.768kHz, the output square wave after a delay time will be the waveform with the accurate frequency. Therefore, the delay circuit 43 needs to perform a preset delay time, which can be a power of n of one clock cycle.

[0085] In an embodiment of the present invention, the oscillator circuit includes a pre-regulator circuit for receiving a first power supply voltage, converting the first power supply voltage into a second power supply voltage, and then outputting it; the second power supply voltage is less than the first power supply voltage; a bias circuit for providing a bias current based on the second power supply voltage; a clock signal generation circuit for outputting a square wave signal based on the bias current; and a clock signal output circuit for outputting a first clock signal operating in the power domain corresponding to the first power supply voltage and a second clock signal operating in the power domain corresponding to the second power supply voltage, based on the square wave signal. This embodiment of the present invention, through the pre-regulator circuit, converts the first power supply voltage into a second power supply voltage before outputting it to subsequent circuits, avoiding the problem that the low-speed oscillator cannot output a clock signal when the core power is off or the supply voltage drops to a level where the logic circuit cannot function properly. Furthermore, the bias circuit can generate a bias current based on the second power supply voltage, without relying on an external bias current source.

[0086] It achieves low power consumption and provides clock output without core voltage. The pre-regulator circuit 10 achieves low power consumption and does not rely on other references, current sources, amplifiers, LDOs, etc. It can be used in IC design to reduce the operating power consumption of MCU and expand the application scenarios of the chip. The bias circuit 20 realizes a self-biased current source. It does not require external bias and generates self-biased current by relying on the circuit. It can optimize the circuit, reduce the power consumption increase caused by calling other resources, and reduce the overall power consumption of the circuit.

[0087] In the embodiments of the present invention, the components in the circuit can be replaced by circuits with the same function, the current source can be replaced by a bipolar transistor, the pre-regulator circuit can be replaced by an LDO, and the delay circuit can be charged by an RC circuit to obtain the delay time.

[0088] This invention also provides a microcontroller, including the oscillator circuit described above.

[0089] In an embodiment of the present invention, the oscillator circuit includes a pre-regulator circuit for receiving a first power supply voltage, converting the first power supply voltage into a second power supply voltage, and then outputting it; the second power supply voltage is less than the first power supply voltage; a bias circuit for providing a bias current based on the second power supply voltage; a clock signal generation circuit for outputting a square wave signal based on the bias current; and a clock signal output circuit for outputting a first clock signal operating in the power domain corresponding to the first power supply voltage and a second clock signal operating in the power domain corresponding to the second power supply voltage, based on the square wave signal. This embodiment of the present invention, through the pre-regulator circuit, converts the first power supply voltage into a second power supply voltage before outputting it to subsequent circuits, avoiding the problem that the low-speed oscillator cannot output a clock signal when the core power is off or the supply voltage drops to a level where the logic circuit cannot function properly. Furthermore, the bias circuit can generate a bias current based on the second power supply voltage, without relying on an external bias current source.

[0090] The terms "first" and "second" in the specification and claims of this invention may explicitly or implicitly include one or more of those features. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0091] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0092] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0093] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0094] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. An oscillator circuit, characterized in that, The oscillator circuit includes: A pre-regulatory circuit is used to receive a first power supply voltage, convert the first power supply voltage into a second power supply voltage, and then output it; the second power supply voltage is less than the first power supply voltage. A bias circuit is used to provide a bias current based on the second power supply voltage; A clock signal generating circuit is used to output a square wave signal based on the bias current; A clock signal output circuit is used to output a first clock signal operating in the power domain corresponding to the first power supply voltage and a second clock signal operating in the power domain corresponding to the second power supply voltage, based on the square wave signal.

2. The oscillator circuit according to claim 1, characterized in that, The bias circuit includes a first resistor and a current mirror; The first resistor is connected to the current mirror and is used to generate a reference current based on the second power supply voltage; The current mirror is used to provide the bias current based on the reference current.

3. The oscillator circuit according to claim 2, characterized in that, The current mirror includes a first MOSFET and a second MOSFET; One end of the first resistor is connected to the second power supply voltage, and the other end is connected to the input terminal of the first MOSFET, the control terminal of the first MOSFET, and the control terminal of the second MOSFET, respectively. The control terminal of the first MOSFET is connected to both the input terminal of the first MOSFET and the control terminal of the second MOSFET, and the output terminal of the first MOSFET is grounded. The output terminal of the second MOSFET is grounded; the input terminal of the second MOSFET is connected to the clock signal generation circuit to provide bias current.

4. The oscillator circuit according to claim 3, characterized in that, Both the first MOS transistor and the second MOS transistor are NMOS transistors; the control terminals of the first MOS transistor and the second MOS transistor are both gates; the input terminals of the first MOS transistor and the second MOS transistor are both drains; and the output terminals of the first MOS transistor and the second MOS transistor are both sources.

5. The oscillator circuit according to claim 1, characterized in that, The pre-regulator circuit includes a first depletion-type NMOS transistor, a second depletion-type NMOS transistor, a second resistor, a first bipolar transistor, a second bipolar transistor, and a third bipolar transistor; The drain of the first depletion-type NMOS transistor and the drain of the second depletion-type NMOS transistor are connected to the first power supply voltage, and the gate of the first depletion-type NMOS transistor and the gate of the second depletion-type NMOS transistor are connected. One end of the second resistor is connected to the source of the second depletion-type NMOS transistor, and the other end is connected to the gate of the first depletion-type NMOS transistor, the gate of the second depletion-type NMOS transistor, and the collector of the first bipolar transistor, respectively. The base of the first bipolar transistor is connected to the base of the second bipolar transistor, and the emitter of the first bipolar transistor is connected to the emitter of the second bipolar transistor. The collector of the second bipolar transistor is connected to the base of the second bipolar transistor and the emitter of the third bipolar transistor, respectively; The collector of the third bipolar transistor is connected to the base of the third bipolar transistor and the source of the first depletion-type NMOS transistor, respectively. The bias circuit is connected at a node between the collector of the third bipolar transistor and the source of the first depletion-type NMOS transistor, and the voltage of the node is the second power supply voltage.

6. The oscillator circuit according to claim 1, characterized in that, The clock signal generating circuit includes a first capacitor, a second capacitor, a crystal oscillator, and a driving circuit. One end of the first capacitor is connected to one end of the crystal oscillator, and the other end of the first capacitor is grounded; One end of the second capacitor is connected to the other end of the crystal oscillator, and the other end of the second capacitor is grounded; The first input terminal of the driving circuit is connected to the bias circuit, the second input terminal is connected to one end of the crystal oscillator, and the output terminal is connected to the other end of the crystal oscillator and the clock signal output circuit, respectively, for outputting a square wave signal based on the bias current.

7. The oscillator circuit according to claim 6, characterized in that, The driving circuit includes a current source circuit, a feedback circuit, and a shaping circuit; The current source circuit is connected to the bias circuit and the feedback circuit respectively, and is used to adjust the current value output to the feedback circuit based on the first power supply voltage, the bias current and the digital signal. The feedback circuit is connected to the shaping circuit and is used to output a voltage signal to the shaping circuit; The shaping circuit is connected to the pre-regulatory circuit and is used to shape the voltage signal based on the power supply voltage of the second power supply to form a square wave signal and output it.

8. The oscillator circuit according to claim 1, characterized in that, The clock signal output circuit includes a first inverter, a second inverter, a delay circuit, a NAND gate, a level conversion circuit, a third inverter, and a fourth inverter; The input terminal of the first inverter is connected to the clock signal generating circuit, and the output terminal of the first inverter is connected to the second inverter and the delay circuit respectively. Used to output the inverted square wave signal; The output of the second inverter is connected to the first input of the NAND gate to output a square wave signal after double inversion. The output terminal of the delay circuit is connected to the second input terminal of the NAND gate, and is used to output a delayed signal after a preset delay time based on the inverted square wave signal. The delayed signal is high level. The NAND gate is used to output a clock signal based on the square wave signal after the second inversion and the delayed signal; The third inverter is connected to the NAND gate and is used to invert the clock signal and output a second clock signal that operates in the power domain corresponding to the second power supply voltage. The level conversion circuit is connected to the output of the NAND gate and is used to convert the power domain of the clock signal into the power domain corresponding to the first power supply voltage. The fourth inverter is connected to the level conversion circuit and is used to invert the clock signal operating in the power domain corresponding to the first power supply voltage, and then output the first clock signal operating in the power domain corresponding to the first power supply voltage.

9. The oscillator circuit according to claim 8, characterized in that, The delay circuit includes multiple D flip-flops connected in series; The clock input of the first-stage D flip-flop is connected to the output of the first inverter, the data input of the first-stage D flip-flop is connected to the inverted output of the first-stage D flip-flop, and the inverted output of the first-stage D flip-flop is connected to the clock input of the next-stage D flip-flop. The clock input of the last stage D flip-flop is connected to the inverted output of the previous stage D flip-flop. The data input of the last stage D flip-flop receives a high level. The output of the last stage D flip-flop is connected to the second input of the NAND gate, which is used to output a delayed signal after a preset delay time. The delayed signal is a high level.

10. A microcontroller, characterized in that, Includes the oscillator circuit as described in any one of claims 1-9 above.

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