Data block management method and device, electronic equipment and storage medium

Abstract

The invention discloses a data block management method and device, electronic equipment and a storage medium, and the method comprises the steps: determining a first target data block corresponding to a target command when the target command is received; wherein the target command is used for indicating that the first target data block is marked as an invalid data block; if the length of the first target data block is smaller than a preset value, storing the address range of the first target data block into a target global variable; wherein if a first target address range overlapped with the address range of the first target data block exists in the target global variable, the address range of the first target data block is merged to the target address range; and when a second target address range of which the length is greater than or equal to a preset value exists in the target global variable, deleting an address mapping relationship corresponding to the second target address range in the address mapping table. The influence of invalid operation of the data block on the performance of the solid state disk is avoided.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a data block management method, device, electronic device, and storage medium. Background Art

[0002] In related technology, when a user deletes a file in an operating system, the operating system issues a trim command (an operation that marks a corresponding data block as invalid) to the solid-state drive (SSD). The SSD then updates the trim table, marks the corresponding data block as invalid, and deletes the mapping relationship corresponding to the data block in the address mapping table. However, frequent updates to the address mapping table for small-scale trim commands can increase read and write latency within the SSD, impacting its performance.

[0003] Therefore, how to avoid the impact of invalid data block operations on the performance of the solid-state drive is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The present application provides a data block management method, device, electronic device and storage medium, which avoid the impact of invalid data block operations on the performance of solid-state drives.

[0005] This application provides a data block management method, including:

[0006] When a target command is received, determining a first target data block corresponding to the target command; wherein the target command is used to instruct to mark the first target data block as an invalid data block;

[0007] If the length of the first target data block is less than a preset value, the address range of the first target data block is stored in the target global variable; wherein, if the target global variable contains a first target address range that overlaps with the address range of the first target data block, the address range of the first target data block is merged into the target address range;

[0008] When a second target address range exists in the target global variable and its length is greater than or equal to the preset value, the address mapping relationship corresponding to the second target address range in the address mapping table is deleted.

[0009] The present application also provides a data block management device, comprising:

[0010] a determining unit, configured to, upon receiving a target command, determine a first target data block corresponding to the target command; wherein the target command is configured to instruct to mark the first target data block as an invalid data block;

[0011] a storage unit configured to store the address range of the first target data block in a target global variable when the length of the first target data block is less than a preset value; wherein, if the target global variable contains a first target address range that overlaps with the address range of the first target data block, merging the address range of the first target data block into the target address range;

[0012] The first deleting unit is configured to delete the address mapping relationship corresponding to the second target address range in the address mapping table when the target global variable has a second target address range whose length is greater than or equal to a preset value.

[0013] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned data block management methods when executing the computer program.

[0014] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned data block management methods are implemented.

[0015] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned data block management methods when executed by a processor.

[0016] The data block management method provided by the present application effectively solves the performance problems caused by frequent updates of the address mapping table in the related art by introducing a target global variable to cache trim commands in a small range. When the length of the data block corresponding to the received target command is less than the preset value, its address range is stored in the target global variable, and the overlapping address ranges are merged. When the cached address range reaches the preset value, the corresponding mapping relationships in the address mapping table are deleted in batches. This process not only reduces the number of modifications to the address mapping table, but also avoids the performance loss caused by repeated trim operations, and optimizes the trim processing flow. In this way, the present application significantly improves the response speed and overall performance of the solid-state hard disk when processing small-scale continuous trim or repeated trim operations. The present application also discloses a data block management device and an electronic device, a computer-readable storage medium and a computer program product, which can also achieve the above-mentioned technical effects.

[0017] It should be understood that the foregoing general description and the following detailed description are merely illustrative and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 is a flow chart showing a data block management method according to an exemplary embodiment;

[0020] Figure 2 is a flow chart showing another data block management method according to an exemplary embodiment;

[0021] Figure 3 A structural diagram of a data block management system in an application embodiment provided by this application;

[0022] Figure 4 This is a flowchart of the front-end Trim operation in an application embodiment provided by this application;

[0023] Figure 5 This is a flowchart of the back-end Trim operation in an application embodiment provided by this application;

[0024] Figure 6 is a structural diagram of a data block management device according to an exemplary embodiment;

[0025] Figure 7 The figure is a structural diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0026] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0027] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0028] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0029] The embodiments of the present application provide a data block management method, and the method is described in detail in conjunction with the execution process of the data block management method.

[0030] See also Figure 1 , according to an exemplary embodiment, a flow chart of a data block management method is shown, as shown in FIG. Figure 1 As shown, including:

[0031] S101: When a target command is received, determining a first target data block corresponding to the target command; wherein the target command is used to instruct to mark the first target data block as an invalid data block;

[0032] The target command refers to the trim command sent by the operating system or upper-layer application to the SSD, which notifies the SSD which data blocks are no longer needed and can be marked as invalid. The first target data block refers to the data block specified by the target command to be marked as invalid, usually expressed as a logical block address (LBA) range.

[0033] In a specific implementation, when the SSD's front-end trim module receives a trim command, it first parses the command to determine the specific data block range to which the command corresponds. For example, the trim command may indicate that the data blocks from LBA 1000 to LBA 2000 are invalid data blocks, in which case these data blocks are the first target data blocks.

[0034] S102: Determine whether the length of the first target data block is less than a preset value; if so, proceed to S103;

[0035] The preset value is used to determine whether the length of the data block is large enough to determine whether caching is required. The preset value may be the maximum length of the address mapping relationship modified by the hardware unit at a single time, such as 256MB.

[0036] In this step, after determining the range of the first target data block, the length of the first target data block, i.e., the size of the first target data block, is calculated. If the length is less than a preset value, the process proceeds to S103; otherwise, the trim information of the data block is directly passed to the back-end trim module for processing.

[0037] It can be seen that by judging the length of the data block, small data blocks and large data blocks can be effectively distinguished, so that small data blocks can be cached, avoiding frequent updates of the address mapping table and reducing unnecessary operations.

[0038] As a feasible implementation, after determining the first target data block corresponding to the target command, the method further includes: if the length of the first target data block is greater than or equal to a preset value, deleting the address mapping relationship corresponding to the first target data block in the address mapping table.

[0039] In a specific implementation, if the length of the first target data block is greater than or equal to a preset value, the back-end trim module directly deletes the address mapping relationship corresponding to the first target data block in the address mapping table. This processing method is an optimization strategy for large data blocks. When the length of a data block reaches or exceeds the preset value, it means that the range of the data block is large, and directly processing it can avoid the additional overhead caused by caching and merging operations. By directly deleting the address mapping relationship, the first target data block is marked as invalid, and the garbage collection mechanism of the SSD can identify and process these invalid data blocks more quickly, thereby improving the overall performance and response speed of the SSD. This method is particularly suitable for processing a large range of trim operations, which can effectively reduce the burden on the back-end trim module, while avoiding performance bottlenecks caused by frequent caching and merging of small data blocks.

[0040] As a feasible implementation method, after deleting the address mapping relationship corresponding to the first target data block in the address mapping table, it also includes: if there is a first target address range in the target global variable that overlaps with the address range of the first target data block, then deleting the address range in the first target address range that overlaps with the address range of the first target data block.

[0041] In a specific implementation, after deleting the address mapping relationship corresponding to the first target data block in the address mapping table, it is necessary to further process the relevant information in the target global variable. Specifically, if the target global variable contains a first target address range that overlaps with the address range of the first target data block, the portion of the first target address range that overlaps with the address range of the first target data block needs to be deleted. This operation is intended to ensure that the address range information in the target global variable remains accurate and up-to-date, avoiding redundant or erroneous information caused by overlap.

[0042] For example, suppose the address range of the first target data block is from LBA 1000 to LBA 2000, and the target global variable already has an address range from LBA 1500 to LBA 2500 cached. After deleting the mapping relationship of the first target data block in the address mapping table, it is necessary to check the address range in the target global variable and delete the portion that overlaps with the address range of the first target data block, that is, the portion from LBA 1500 to LBA 2000. In this way, the remaining address range in the target global variable will be from LBA 2001 to LBA 2500.

[0043] This implementation is beneficial in that it ensures that the address range information in the target global variable remains accurate and consistent. By promptly removing overlapping address ranges, duplicate processing of the same area in subsequent trim operations is avoided, improving SSD trim performance and overall efficiency. This also reduces potential errors caused by address range conflicts or redundancies, further enhancing system stability and reliability.

[0044] S103: Storing the address range of the first target data block into a target global variable; wherein, if the target global variable contains a first target address range that overlaps with the address range of the first target data block, merging the address range of the first target data block into the target address range;

[0045] The target global variable is a global variable used to cache trim information and stores the address range of data blocks that need to be marked as invalid.

[0046] In this step, if the length of the first target data block is less than a preset value, its address range is stored in the target global variable. The address range may include a starting address and a length. If another address range already exists in the target global variable that overlaps with the address range of the first target data block, the two address ranges are merged. After the merger, the address range information in the target global variable is updated.

[0047] For example, suppose the target global variable already caches the address range from LBA 500 to LBA 1000, and now a new trim command is received indicating that the data block from LBA 900 to LBA 1500 is invalid. Because these two address ranges overlap (LBA 900 to LBA 1000), they are merged into the address range from LBA 500 to LBA 1500.

[0048] It can be seen that by caching and merging address ranges, the execution times of the backend trim module are reduced, and repeated processing of data blocks in the same area is avoided, thereby improving the trim performance of the SSD.

[0049] S104: When a second target address range exists in the target global variable and its length is greater than or equal to the preset value, the address mapping relationship corresponding to the second target address range in the address mapping table is deleted.

[0050] The address mapping table is a table inside the SSD that records the mapping relationship between logical block addresses (LBA) and physical block addresses (PBA), also known as the L2P (Logic to Physical mapping) table.

[0051] In this step, if the target global variable contains a second target address range whose length is greater than or equal to the preset value, the front-end trim module transfers the second target address range to the back-end trim module for processing. The back-end trim module deletes the address mapping relationship corresponding to the second target address range from the address mapping table. This means that these data blocks are officially marked as invalid, and subsequent garbage collection operations on the SSD can ignore these areas.

[0052] For example, assuming that the address range of the cache in the target global variable is from LBA 500 to LBA 1500, and its size is 1MB, which has reached the preset value, the mapping relationship from LBA 500 to LBA 1500 in the address mapping table is deleted.

[0053] It can be seen that by deleting address mapping relationships in batches, the frequent modification operations on the address mapping table are reduced, the performance of the SSD is improved, and the write amplification phenomenon is reduced, thereby extending the service life of the SSD.

[0054] The data block management method provided in the embodiment of the present application effectively solves the performance problem caused by frequent updates of the address mapping table in the related art by introducing a target global variable to cache the trim commands in a small range. When the length of the data block corresponding to the received target command is less than the preset value, its address range is stored in the target global variable, and the overlapping address ranges are merged. When the cached address range reaches the preset value, the corresponding mapping relationship in the address mapping table is deleted in batches. This process not only reduces the number of modifications to the address mapping table, but also avoids the performance loss caused by repeated trim operations, and optimizes the trim processing flow. In this way, the embodiment of the present application significantly improves the response speed and overall performance of the solid-state hard disk when processing small-scale continuous trim or repeated trim operations.

[0055] On the basis of the above embodiment, as a feasible implementation method, the target global variable is used to store a preset number of address ranges. After determining the first target data block corresponding to the target command, it also includes: if the length of the first target data block is less than the preset value and there is no first target address range in the target global variable that overlaps with the address range of the first target data block, then determine whether the number of address ranges currently stored in the target global variable reaches the preset number; if so, determine the third target address range stored earliest in the target global variable, delete the address mapping relationship corresponding to the third target address range in the address mapping table, delete the third target address range in the target global variable, and execute the step of storing the address range of the first target data block in the target global variable; if not, execute the step of storing the address range of the first target data block in the target global variable.

[0056] In this embodiment, the target global variable is used to store a preset number of address ranges. For example, a maximum of two address ranges may be preset. After determining the first target data block corresponding to the target command, if the length of the first target data block is less than a preset value and no address range in the target global variable overlaps with the address range of the first target data block, it is necessary to further determine whether the number of address ranges currently stored in the target global variable has reached the preset number.

[0057] If the number of address ranges in the target global variable has reached a preset number (for example, two address ranges have already been stored), the oldest stored third target address range needs to be determined. Next, the address mapping relationship corresponding to the third target address range in the address mapping table is deleted, and the third target address range is deleted from the target global variable. After these operations are completed, the address range of the first target data block is stored in the target global variable.

[0058] If the number of address ranges in the target global variable has not reached a preset number, the address range of the first target data block is directly stored in the target global variable.

[0059] This implementation is beneficial in that it limits the number of address ranges stored in the target global variable, preventing the global variable from growing unchecked, thereby conserving storage resources. Furthermore, by prioritizing the oldest address ranges, adhering to the first-in, first-out (FIFO) principle, it ensures fairness and efficiency in trim operations. Furthermore, this method dynamically adjusts the address ranges in the global variable, avoiding processing delays caused by an excessive number of address ranges, further improving the SSD's trim performance and overall responsiveness.

[0060] As a preferred embodiment, key SSD performance indicators, including but not limited to write amplification, garbage collection frequency, and cache hit rate, are monitored. Trim command patterns are collected, including command size, frequency, and time distribution, as well as their impact on SSD performance. An adaptive algorithm is employed to analyze the collected data and dynamically adjust the capacity of the target global variable based on the SSD's real-time performance and workload. For example, if a large number of small Trim commands are predicted, the algorithm may increase the capacity of the target global variable to more effectively cache these commands.

[0061] First, by introducing an adaptive algorithm to dynamically adjust the SSD's Trim command handling strategy, cache efficiency can be significantly improved. Because the algorithm adjusts the cache strategy based on the SSD's actual workload and performance metrics, limited cache resources can be more effectively utilized, reducing performance bottlenecks caused by inappropriate caching. Second, it significantly reduces write amplification. By reducing unnecessary write operations, the SSD's write amplification rate is lowered, which helps reduce wear on the flash memory cells and thus extend the SSD's lifespan. Furthermore, the introduction of the adaptive algorithm improves SSD responsiveness. The algorithm predicts future Trim command patterns and makes corresponding cache adjustments in advance, enabling the SSD to process upcoming commands more quickly and improving real-time data processing. Furthermore, this dynamic adjustment mechanism enhances system stability and reliability. In the face of changing workloads, the system can automatically adjust its strategy to adapt to these changes, maintaining stable performance and reducing the risk of system instability caused by sudden load changes.

[0062] The embodiment of the present application discloses a data block management method. Compared with the previous embodiment, this embodiment further explains and optimizes the technical solution. Specifically:

[0063] See also Figure 2 , a flowchart of another data block management method according to an exemplary embodiment is shown, such as Figure 2 As shown, including:

[0064] S201: When a target command is received, determining a first target data block corresponding to the target command; wherein the target command is used to instruct to mark the first target data block as an invalid data block;

[0065] S202: Determine whether the length of the first target data block is less than a preset value; if so, proceed to S203;

[0066] S203: updating the bit value of the bit corresponding to the first target data block in the invalid operation table to a first preset value; wherein the invalid operation table is used to record invalid operations to be performed, the data block corresponding to the bit value of the first preset value is the data block to be executed with the invalid operation, and the data block corresponding to the bit value of the second preset value is the valid data block;

[0067] The invalid operation table, also known as the trim table, is used to record data blocks for which invalid operations are to be performed. It uses bits to mark the status of data blocks. A first preset value indicates that a data block is in the state of a pending invalid operation, for example, a bit value of "1." A second preset value indicates that a data block is in the state of a pending invalid operation, for example, a bit value of "0."

[0068] In a specific implementation, if the length of the first target data block is less than a preset value, the bit value of the corresponding bit of the first target data block in the invalid operation table is updated to a first preset value (e.g., "1"), which indicates that the data block has been marked as a pending invalid operation.

[0069] By updating the bit values in the invalidation operation table, it is possible to clearly mark which data blocks require subsequent processing, providing a basis for subsequent batch invalidation operations while avoiding repeated processing of the same data block.

[0070] S204: Storing the address range of the first target data block into the target global variable; wherein, if the target global variable contains a first target address range that overlaps with the address range of the first target data block, merging the address range of the first target data block into the target address range;

[0071] S205: When a second target address range exists in the target global variable and its length is greater than or equal to the preset value, deleting the address mapping relationship corresponding to the second target address range in the address mapping table;

[0072] S206: Determine a second target data block corresponding to the second target address range, and update the bit value of the bit corresponding to the second target data block in the invalidation operation table to a second preset value.

[0073] In this step, after deleting the address mapping relationship corresponding to the second target address range in the address mapping table, the second target data block corresponding to the second target address range is determined, and the bit value of the bit corresponding to these data blocks in the invalid operation table is updated to a second preset value (for example, "0"), indicating that these data blocks have been processed as invalid data blocks.

[0074] By updating the bit value in the invalid operation table to the second preset value, it is possible to clearly mark which data blocks have been processed as invalid, thereby avoiding repeated processing and further optimizing the trim performance and management efficiency of the SSD.

[0075] Based on the above embodiment, as a feasible implementation method, the following is also included:

[0076] When a read instruction for the third target data block is received, the bit value of the bit corresponding to the third target data block in the invalid operation table is queried. If the bit value of the bit corresponding to the third target data block is the first preset value, empty data is directly returned.

[0077] The third target data block refers to the data block to be read as specified by the read instruction. In a specific implementation, when the SSD receives a read instruction for the third target data block, it first queries the invalidation table for the bit value corresponding to the third target data block. If the bit value is a first preset value, it indicates that the data block has been marked for pending invalidation, meaning that the contents of the data block have been marked invalid. In this case, the SSD directly returns empty data rather than attempting to read the actual invalid data.

[0078] This mechanism avoids reading invalid data, saving time and resources for read operations and improving SSD read efficiency. At the same time, it also ensures that read operations do not interfere with ongoing invalid operations, improving overall system stability.

[0079] On the basis of the above embodiment, as a feasible implementation method, it also includes: when a write instruction for the fourth target data block is received, the target global variable is queried, and if there is a fourth target address range in the target global variable that overlaps with the address range of the fourth target data block, the address range in the fourth target address range that overlaps with the address range of the fourth target data block is deleted, and the bit value of the bit corresponding to the fifth target data block in the invalid operation table is updated to a second preset value; wherein, the address range corresponding to the fifth target data block is the address range in the fourth target address range that overlaps with the address range of the fourth target data block.

[0080] Among them, the fourth target data block refers to the area where data needs to be written as specified by the write instruction. In a specific implementation, when the SSD receives a write instruction for the fourth target data block, it first queries the target global variable to check whether there is a fourth target address range that overlaps with the address range of the fourth target data block. If there is an overlap, it means that this part of the data block has been marked as waiting for an invalid operation. In this case, it is necessary to delete the part of the fourth target address range that overlaps with the address range of the fourth target data block, and update the bit value of the corresponding bit of the fifth target data block in the invalid operation table to the second preset value, indicating that these data blocks no longer need to perform invalid operations, and then perform the write operation.

[0081] This mechanism avoids interfering with invalidated data blocks during write operations, ensuring the correctness and efficiency of write operations. Furthermore, by updating the bit values in the invalidation table, repeated processing of the same area can be avoided, further optimizing SSD trim performance and management efficiency.

[0082] The following describes an application embodiment provided by this application. In the firmware implementation of a multi-core SSD product, different cores can be set to handle front-end and back-end trim operations respectively. Specifically, the front-end trim control module runs on Core[0], which receives IO (Input / Output) commands, while the back-end trim module runs on Core[1]. This design can improve the efficiency of trim operations and the overall performance of the SSD.

[0083] The structural diagram of a data block management system in an application embodiment provided by this application is as follows: Figure 3 As shown, in the front-end trim process, the host sends trim commands to the NVMe (Non-Volatile Memory Express) hardware, instructing it to mark certain data blocks as invalid. The front-end trim module receives these commands and interacts with the trim table / global cache to update the corresponding information. If the trim command processed by the front-end trim module is less than 256MB, it will not immediately pass the trim information to the back-end trim module, but will cache it. The front-end trim module interacts with the 512-bit write NAND (flash memory), which may involve direct operations on the physical storage media.

[0084] In the backend trim module, the backend trim module interacts with the L2P table (logical-to-physical address mapping table) and the hardware unit. It is responsible for updating the L2P table based on the trim table to reflect the valid status of the data block. This process involves modifying the physical address to ensure that the mapping between the logical and physical addresses of the data block is up to date. The dotted lines in the figure indicate the separation of data flow and operations between the frontend and backend trim modules.

[0085] Front-end Trim operation is as follows Figure 4 As shown, including:

[0086] 1. Receiving Trim instructions: The front-end Trim module of the SSD firmware first receives Trim instructions from the host. These instructions are used to inform the SSD which data blocks are no longer needed and can be marked as invalid.

[0087] 2. Parameter Check and Buffer Request: The front-end Trim module performs parameter checks to ensure that the received Trim command parameters are valid. If the check passes, it sends a request to the buffer manager to request a trim buffer.

[0088] 3. DMA (Direct Memory Access) transfer and TRIM table modification: Start DMA to transfer TRIM ENTRY data and modify the TRIM table for all TRIM Ranges.

[0089] 4. Caching TRIM information: If the TRIM range is less than 256MB, the front-end Trim module records this information in a global variable to accumulate it to 256MB. If more than two TRIM ranges are already cached in the global variable, the older one is passed to the back-end Trim module to process the L2P table modification. For non-4K-aligned TRIM ranges, no caching is performed; instead, data blocks within the non-4K-aligned TRIM range are directly written to zero.

[0090] 5. Scheduling back-end Trim: If the TRIM range information parsed by the front-end Trim module reaches 256MB, the front-end Trim module will schedule the back-end Trim module to update the L2P table once.

[0091] 6. Save global variables: When the SSD is powered off, the multiple TRIM range information recorded in the global variables needs to be saved to the NVMe hardware so that it can be restored when it is powered on next time.

[0092] 7. Release resources: If the cached TRIM Range reaches 256MB or above, a backend trim message is sent and resources (BUFFER and context) are released based on resource usage.

[0093] Backend Trim operation is as follows Figure 5 As shown, including:

[0094] 1. Processing TRIM information: After the back-end Trim module receives the message carrying the TRIM start position and length from the front-end Trim module, it reads the message content and TRIM table, and modifies the content of the L2P table through the hardware unit according to the TRIM table. It can complete the modification of up to 65536 PBAs at a time.

[0095] 2. Set the TRIM flag: After completing the modification of the L2P table, the back-end Trim module clears the corresponding bit in the TRIM table and sends a completion message to the front-end Trim module. The front-end Trim module determines whether to set the trim_finish flag based on the completion message.

[0096] 3. Processing write commands: When the firmware (FW) receives a write command, if the TRIM flag is trim_no_finish, it needs to check the TRIM table. If the TRIM table is found to overlap with the write range, it needs to clear the corresponding bit in the TRIM table.

[0097] 4. Processing read commands: When the FW receives a read command, if the TRIM flag is trim_no_finish, it checks the TRIM table. If the corresponding bit in the TRIM table is 1, the read data is returned as unmap (unmapping, which in the SSD context means marking the data block as invalid and removing it from the file system).

[0098] 5. Throughout the entire operation, read / write / trim operations for each LBA are mutually exclusive and can be implemented through locking to ensure data consistency and atomicity of operations. This collaborative working mechanism of front-end and back-end trim ensures that the SSD can process trim commands efficiently and accurately, optimizing storage performance and extending the life of the SSD.

[0099] A data block management device provided in an embodiment of the present application is introduced below. The data block management device described below and the data block management method described above can be referenced to each other.

[0100] See also Figure 6 , according to an exemplary embodiment, a structural diagram of a data block management device is shown, such as Figure 6 As shown, including:

[0101] The determining unit 100 is configured to, upon receiving a target command, determine a first target data block corresponding to the target command; wherein the target command is configured to instruct to mark the first target data block as an invalid data block;

[0102] The storage unit 200 is configured to store the address range of the first target data block in a target global variable when the length of the first target data block is less than a preset value; wherein, if the target global variable contains a first target address range that overlaps with the address range of the first target data block, the address range of the first target data block is merged into the target address range;

[0103] The first deleting unit 300 is configured to delete the address mapping relationship corresponding to the second target address range in the address mapping table when the target global variable has a second target address range whose length is greater than or equal to a preset value.

[0104] The data block management device provided in the embodiment of the present application effectively solves the performance problem caused by frequent updates of the address mapping table in the related art by introducing a target global variable to cache trim commands in a small range. When the length of the data block corresponding to the received target command is less than the preset value, its address range is stored in the target global variable, and the overlapping address ranges are merged. When the cached address range reaches the preset value, the corresponding mapping relationship in the address mapping table is deleted in batches. This process not only reduces the number of modifications to the address mapping table, but also avoids the performance loss caused by repeated trim operations, and optimizes the trim processing flow. In this way, the embodiment of the present application significantly improves the response speed and overall performance of the solid-state hard disk when processing small-scale continuous trim or repeated trim operations.

[0105] Based on the above embodiment, as a preferred implementation, it further includes:

[0106] The second deleting unit is configured to delete the address mapping relationship corresponding to the first target data block in the address mapping table when the length of the first target data block is greater than or equal to a preset value.

[0107] Based on the above embodiment, as a preferred implementation, it further includes:

[0108] The third deleting unit is configured to delete the address range overlapping with the address range of the first target data block in the first target address range when the first target address range overlapping with the address range of the first target data block exists in the target global variable.

[0109] Based on the above embodiment, as a preferred implementation, the preset value is the maximum length of the address mapping relationship modified by the hardware unit in a single time.

[0110] Based on the above embodiment, as a preferred implementation, the target global variable is used to store a preset number of address ranges, and the device further includes:

[0111] a determination unit configured to, when the length of the first target data block is less than a preset value and the target global variable does not contain a first target address range that overlaps with the address range of the first target data block, determine whether the number of address ranges currently stored in the target global variable has reached a preset number; if so, initiate a work process of the fourth deletion unit; if not, initiate a work process of the storage unit 200;

[0112] The fourth deletion unit is used to determine the third target address range stored earliest in the target global variable, delete the address mapping relationship corresponding to the third target address range in the address mapping table, delete the third target address range in the target global variable, and execute the step of storing the address range of the first target data block in the target global variable.

[0113] Based on the above embodiment, as a preferred implementation, it further includes:

[0114] a first updating unit, configured to update, when the length of the first target data block is less than a preset value, a bit value corresponding to the first target data block in the invalid operation table to a first preset value; wherein the invalid operation table is configured to record invalid operations to be performed, a data block corresponding to a bit value having a first preset value as the data block to be subjected to the invalid operation, and a data block corresponding to a bit value having a second preset value as the valid data block;

[0115] The first updating unit is used to determine the second target data block corresponding to the second target address range after deleting the address mapping relationship corresponding to the second target address range in the address mapping table, and update the bit value of the bit corresponding to the second target data block in the invalid operation table to a second preset value.

[0116] Based on the above embodiment, as a preferred implementation, it further includes:

[0117] a read operation unit, configured to, upon receiving a read instruction for the third target data block, query a bit value of a bit corresponding to the third target data block in the invalid operation table, and directly return empty data if the bit value of the bit corresponding to the third target data block is a first preset value;

[0118] A write operation unit is used to query the target global variable when receiving a write instruction for the fourth target data block. If there is a fourth target address range in the target global variable that overlaps with the address range of the fourth target data block, delete the address range in the fourth target address range that overlaps with the address range of the fourth target data block, and update the bit value of the bit corresponding to the fifth target data block in the invalid operation table to a second preset value; wherein, the address range corresponding to the fifth target data block is the address range in the fourth target address range that overlaps with the address range of the fourth target data block.

[0119] Regarding the apparatus in the above embodiment, the specific manner in which each unit performs operations has been described in detail in the embodiment of the method, and will not be elaborated on here.

[0120] An embodiment of the present application further provides an electronic device, Figure 7 FIG. 1 is a structural diagram of an electronic device according to an exemplary embodiment. Figure 7As shown, the electronic equipment includes:

[0121] Communication interface 1, capable of exchanging information with other devices such as network devices;

[0122] The processor 2 is connected to the communication interface 1 to implement information exchange with other devices and is used to execute the data block management method provided by one or more of the above technical solutions when running a computer program. The computer program is stored in the memory 3.

[0123] Of course, in actual application, the various components in the electronic device are coupled together through the bus system 4. It can be understood that the bus system 4 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 4 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, Figure 7 Various buses are labeled as bus system 4.

[0124] The memory 3 in the embodiment of the present application is used to store various types of data to support the operation of the electronic device. Examples of such data include: any computer program used to operate on the electronic device.

[0125] It is understood that the memory 3 can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory can be a magnetic disk or a magnetic tape. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus random access memory (DRRAM).The memory 3 described in the embodiments of the present application is intended to include but is not limited to these and any other suitable types of memories.

[0126] The method disclosed in the above-mentioned embodiment of the present application can be applied to processor 2 or implemented by processor 2. Processor 2 may be an integrated circuit chip with signal processing capabilities. During the implementation process, each step of the above-mentioned method can be completed by the integrated logic circuit of the hardware in processor 2 or instructions in the form of software. The above-mentioned processor 2 can be a general-purpose processor, DSP, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 2 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the embodiment of the present application can be directly embodied as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in memory 3. Processor 2 reads the program in memory 3 and completes the steps of the above-mentioned method in combination with its hardware.

[0127] When the processor 2 executes the program, the corresponding processes in each method of the embodiment of the present application are implemented. For the sake of brevity, they are not repeated here.

[0128] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above-mentioned data block management method embodiments when running.

[0129] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0130] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by the processor 2, the steps of any of the above-mentioned data block management method embodiments are implemented.

[0131] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, which stores a computer program. When the computer program is executed by the processor 2, it implements the steps of any of the above-mentioned data block management method embodiments.

[0132] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0133] The above is a detailed introduction to a data block management system, method, apparatus and equipment, medium and product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the present application.

Claims

1. A data block management method, characterized in that: include: When a target command is received, determining a first target data block corresponding to the target command; wherein the target command is used to instruct to mark the first target data block as an invalid data block; If the length of the first target data block is less than a preset value, the address range of the first target data block is stored in a target global variable; wherein, if the target global variable contains a first target address range that overlaps with the address range of the first target data block, the address range of the first target data block is merged into the target address range; When a second target address range exists in the target global variable and its length is greater than or equal to the preset value, the address mapping relationship corresponding to the second target address range in the address mapping table is deleted.

2. The data block management method according to claim 1, characterized in that: After determining the first target data block corresponding to the target command, the method further includes: If the length of the first target data block is greater than or equal to the preset value, the address mapping relationship corresponding to the first target data block in the address mapping table is deleted.

3. The data block management method according to claim 2, characterized in that: After deleting the address mapping relationship corresponding to the first target data block in the address mapping table, the method further includes: If a first target address range that overlaps with the address range of the first target data block exists in the target global variable, the address range in the first target address range that overlaps with the address range of the first target data block is deleted.

4. The data block management method according to claim 1, characterized in that: The preset value is the maximum length of the address mapping relationship modified by the hardware unit in a single time.

5. The data block management method according to claim 1, characterized in that: The target global variable is used to store a preset number of address ranges. After determining the first target data block corresponding to the target command, the method further includes: If the length of the first target data block is less than a preset value and there is no first target address range in the target global variable that overlaps with the address range of the first target data block, determining whether the number of address ranges currently stored in the target global variable reaches the preset number; If so, determining the third target address range stored earliest in the target global variable, deleting the address mapping relationship corresponding to the third target address range in the address mapping table, deleting the third target address range in the target global variable, and performing the step of storing the address range of the first target data block in the target global variable; If not, the step of storing the address range of the first target data block into the target global variable is performed.

6. The data block management method according to claim 1, characterized in that: Before storing the address range of the first target data block into the target global variable, the method further includes: Updating the bit value of the bit corresponding to the first target data block in the invalid operation table to a first preset value; wherein the invalid operation table is used to record invalid operations to be performed, the data block corresponding to the bit value of the first preset value is the data block to be executed with the invalid operation, and the data block corresponding to the bit value of the second preset value is the valid data block; Correspondingly, after deleting the address mapping relationship corresponding to the second target address range in the address mapping table, the method further includes: A second target data block corresponding to the second target address range is determined, and a bit value of a bit corresponding to the second target data block in the invalidation operation table is updated to the second preset value.

7. The data block management method according to claim 6, characterized in that: Also includes: When a read instruction for a third target data block is received, querying the invalid operation table for a bit value of a bit corresponding to the third target data block, and directly returning empty data if the bit value of the bit corresponding to the third target data block is the first preset value; When a write instruction for the fourth target data block is received, the target global variable is queried. If there is a fourth target address range in the target global variable that overlaps with the address range of the fourth target data block, the address range in the fourth target address range that overlaps with the address range of the fourth target data block is deleted, and the bit value of the bit corresponding to the fifth target data block in the invalid operation table is updated to the second preset value; wherein, the address range corresponding to the fifth target data block is the address range in the fourth target address range that overlaps with the address range of the fourth target data block.

8. A data block management device, characterized in that: include: a determining unit, configured to, upon receiving a target command, determine a first target data block corresponding to the target command; wherein the target command is configured to instruct to mark the first target data block as an invalid data block; a storage unit, configured to, when the length of the first target data block is less than a preset value, store the address range of the first target data block in a target global variable; wherein, if a first target address range that overlaps with the address range of the first target data block exists in the target global variable, merge the address range of the first target data block into the target address range; The first deleting unit is configured to delete the address mapping relationship corresponding to the second target address range in the address mapping table when the target global variable has a second target address range whose length is greater than or equal to the preset value.

9. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the data block management method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which, when executed, implements the steps of the data block management method according to any one of claims 1 to 7.

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