Dynamic cross-layer data reuse method for efficient deep convolutional computation

Abstract

The present application relates to the technical field of neural network optimization, and more particularly to a dynamic cross-layer data multiplexing method for efficient deep convolution calculation, comprising: step 1, designing a single-layer block optimization and loop sequence optimization model; step 2, performing separate block optimization and loop sequence optimization; step 3, performing multi-layer joint block optimization and loop sequence optimization; and step 4, performing dynamic composite block optimization and loop sequence optimization of single-layer and multi-layer. The present application can finally realize a multi-layer joint data block strategy with minimum DRAM access, a loop unrolling control strategy, and a data storage mapping update strategy, and realize a data access and data flow scheme with maximized data multiplexing of fine granularity, which can effectively support code automatic generation and calculation mapping optimization for optimizing calculation and memory efficiency.

Description

Technical Field

[0001] This invention relates to the field of neural network optimization technology, and in particular to a dynamic cross-layer data reuse method for efficient deep convolution computation. Background Technology

[0002] In practical deployments of various deep neural network models, a large number of input feature map coefficients and weight coefficients are stored in large-capacity DRAM memory. CNN accelerators have limited computing resources in their cores, and the on-chip SRAM cache is also limited in capacity. During actual multi-layer convolution calculations, the input feature map coefficients and weight coefficients are loaded from off-chip DRAM into the on-chip SRAM cache near the computing core. The MAC array of the computing core can typically only perform partial convolution calculations; the resulting output feature map coefficients need to be stored in DRAM, and then the computing core continues to perform convolution calculations on other input feature coefficients. The large volume and diversity of data in CNN network layers lead to extensive and complex data transfer between the computing core, on-chip cache, and off-chip DRAM. DRAM-based off-chip memory access is the most energy-intensive operation in deep neural network (DNN) accelerators; this is the intelligent computing memory wall problem.

[0003] Optimizing network model storage access on a specific CNN acceleration engine platform requires addressing several key aspects, including methods for partitioning CNN convolutional weight coefficients and feature coefficients, mapping core computation units, implementing external pipeline scheduling (i.e., loop ordering strategies), and data storage mapping and update strategies. This necessitates code generation and implementation mapping to optimize computational and memory access efficiency. The solution space for this optimization is extremely large, involving variables such as batch size and concurrency intensity (Tz), the width and height of the feature maps used in the computation cores (Tn*Tm), the on-chip cache input feature dimension (Ti), the on-chip cache output feature dimension (Tj), the number of cross-layer optimization layers, and the loop priority strategy category. This loop priority strategy category manifests as the following data reuse patterns: Input coefficient reuse (IRO), Output coefficient reuse (ORO), and Weight coefficient reuse (WRO).

[0004] Furthermore, there is a possibility of coefficient reuse between the input and output features of adjacent layers. For example, the output feature map coefficients of layer u are the input feature map coefficients of layer u+1. If adjacent layers are optimized separately, after the feature map coefficients of layer u are calculated, a DRAM write operation will be initiated to store these output coefficients. Then, when the next layer's convolution calculation is performed, a DRAM read operation will be initiated again to read these feature map coefficients. This results in redundant write and read access operations for feature map coefficients. If layer u is optimized separately in ORO mode, then while the output feature map coefficients are stored in on-chip SRAM, the convolution calculation of layer u+1 continues. Assuming that layer u+1 cyclically adopts IRO mode, the reuse of the feature map coefficients cached in the on-chip SRAM of the previous layer can be maximized. This combination of ORO+IRO between adjacent layers can maximize the reuse of input and output feature map coefficients. Theoretically, input and output feature map coefficients can achieve data reuse between more layers, but the reuse of weight coefficients and the factor of batch concurrency must be considered. Generally, the more layers involved in cross-layer optimization, the higher the efficiency of feature coefficient reuse between adjacent layers. However, the limited on-chip SRAM cache must be considered. Due to SRAM limitations, the more layers involved in cross-layer optimization, the smaller the block size will generally be. This results in a correspondingly smaller block size for weight coefficients, leading to more severe redundancy in weight coefficient data movement compared to fewer-layer optimization or single-layer partitioning. There needs to be a balance between the increased bandwidth caused by redundant weight coefficient data movement and the data access savings caused by data reuse between adjacent layers. This is a factor that needs to be considered when developing an optimization scheme.

[0005] Currently, existing work typically focuses only on single-layer bandwidth access optimization, neglecting the fact that the output feature data of the previous layer is already cached and can be reused by the input feature coefficients of subsequent layers. This cross-layer data reuse is highly effective for efficient deployment of network layers with a high proportion of feature coefficients. Some works do not consider input batch concurrency, which can effectively reuse weight coefficients, and is very effective for the weight coefficient-first WRO mode. Other works organize data according to the data access paradigm required for computational core calculations when constructing bandwidth access function models. This process can lead to some overlapping data in the input and output feature map coefficients. Repeated loading of this overlapping data reduces the accuracy of the model and the efficiency of coefficient optimization. Furthermore, some works consider the logical bandwidth consumption under ideal conditions when constructing bandwidth models, without considering the actual DRAM structure. This leads to a discrepancy between the actual DRAM access bandwidth consumption and the logical access bandwidth, a problem that most existing works have not addressed.

[0006] Simultaneously considering the optimal data flow strategy of batch concurrency strength optimization, block strategy optimization, cyclic sequence strategy optimization, and cross-layer data reuse optimization, achieving globally optimized on-chip DRAM access and on-chip data reuse under the constraints of on-chip cache and computing core computing resources is a problem that needs further research and solutions. It is of great significance for the efficient deployment and computational mapping of network models on specific convolutional accelerator hardware platforms. Summary of the Invention

[0007] To address the aforementioned technical problems in the existing technology, this invention proposes a dynamic cross-layer data reuse method for efficient depthwise convolution computation, the specific technical solution of which is as follows:

[0008] A dynamic cross-layer data reuse method for efficient depthwise convolution computation includes:

[0009] Step 1: Design single-layer block optimization and loop sequence optimization models;

[0010] Step 2: Perform individual block optimization and loop order optimization;

[0011] Step 3: Perform multi-level joint block optimization and loop order optimization;

[0012] Step 4: Perform dynamic composite block optimization and loop sequence optimization for single-layer and multi-layer applications.

[0013] Furthermore, the design of the model in step 1 specifically includes:

[0014] Based on the characteristics of the data flow in depthwise convolution computation, three data access modes are set, including input feature map coefficient reuse (IRO) mode, output feature map coefficient reuse (ORO) mode, and weight coefficient reuse (WRO) mode.

[0015] Based on the data flow characteristics of the three data access modes, the single access data volume and the number of loop accesses for the input feature map, output feature map, and weights are set in each mode.

[0016] Furthermore, the amount of data accessed per single session for the input feature map, output feature map, and weights in each mode specifically includes: input feature map coefficients: Bif1, Bif2, Bif3; output feature map coefficients: Bof1, Bof2, Bof3; and weight coefficients: Bwgt1, Bwgt2, Bwgt3. The number of cyclic accesses for the input feature map, output feature map, and weights in each mode specifically includes: number of accesses for the input feature map coefficients: Cif1, Cif2, Cif3; number of accesses for the output feature map coefficients: Cof1, Cof2, Cof3; and number of accesses for the weight coefficients: Cwgt1, Cwgt2, Cwgt3.

[0017] Furthermore, step 2 specifically includes:

[0018] Step 2.1: Divide the feature data calculated by a single convolutional layer into blocks and obtain the block parameters;

[0019] Step 2.2: Traverse all possible block combinations, calculate the memory bandwidth and storage usage under the three data access modes respectively, and compare the storage threshold and minimum memory bandwidth to determine the optimal block combination and data access mode.

[0020] Further, step 2.1 specifically includes: dividing Z, M, N, I, and J into blocks using step sizes 1, stepM, stepN, stepI, and stepJ respectively, to obtain block parameters Tz, Th, Tw, Tm, Tn, Ti, and Tj; where Z is the maximum batch size, I is the number of input feature map channels, J*M*N is the feature map coefficient dimension, Th=S*(Tm-1)+P, Tw=S*(Tn-1)+Q, S is the convolution step size, I*J*P*Q is the convolution kernel size, and Tp=P and Tq=Q are taken; Tz is the batch cyclic block size, Tm*Tn and Th*Tw are the horizontal and vertical block sizes of the data feature map coefficients, Ti is the input feature map channel block size, and Tj is the output feature map channel block size.

[0021] Furthermore, in step 2.2, the calculation of memory bandwidth and storage usage is specifically as follows:

[0022] The bandwidth of the input feature maps ifmaps: BWif = Bif * Cif * size(ifmaps);

[0023] The bandwidth of the output feature maps ofmaps is: BWof = Bof * Cof * size(ofmaps);

[0024] Bandwidth of convolution kernel weights: BWwgt = Bwgt * Cwgt * size(weight);

[0025] Storage usage: SRAMtot = Bif * size(ifmaps) + Bwgt * size(weight) + Bof * size(ofmaps);

[0026] Total bandwidth: BWtot = BWif + BWof + BWwgt;

[0027] Where Bif, Bof, and Bwgt represent the data sizes of the input feature map, output feature map, and convolution kernel, respectively; Cif, Cof, and Cwgt represent the number of iterations of the input feature map, output feature map, and convolution kernel, respectively; and size represents the size.

[0028] The comparison of storage thresholds and minimum bandwidth to determine the optimal block combination and data access mode specifically involves:

[0029] Given a storage threshold SRAM_TH and a minimum bandwidth minBW, under the conditions that SRAMtot <= SRAM_TH and BWtot2 <= minBW, i.e., if the storage usage of the current mode does not exceed the storage threshold SRAM_TH and the total bandwidth is smaller, then update the minimum bandwidth and data access mode. This will ultimately yield the optimal block combination and mode, which minimizes the total bandwidth and satisfies the storage limit.

[0030] Furthermore, step 3 specifically includes:

[0031] Step 3.1: Traverse the blocks of data from three adjacent convolutional layers, specifically including:

[0032] For the u-th, u+1-th, and u+2-th layers (i.e., three adjacent layers), the feature data calculated by the convolution of the u-th layer is first divided into blocks to obtain the block combination of the u-th layer. Then, the block parameters of the u-th layer are reused to obtain the block combination of the u+1-th layer. Where Tw(u+1)=Tn(u) and Th(u+1)=Tm(u), that is, the width and height of the feature map calculated by the convolution of the u-th layer are directly reused as the width and height of the input feature map of the convolution of the u+1-th layer. Then, the block parameters of the u+1-th layer are reused to obtain the block combination of the u+2-th layer. At the same time, the block parameters of the lower layer are adjusted based on the block results of the upper layer.

[0033] Step 3.2: Iterate through and calculate the bandwidth and storage usage of the current layer for different block combinations, set storage constraints, iterate through and check whether the total storage usage of the three adjacent layers meets the storage constraints, and select the block combination with the smallest total bandwidth.

[0034] Furthermore, step 4 specifically includes:

[0035] Step 4.1: Select a three-layer adjacent layer group GOP to generate four candidate block patterns, including:

[0036] Mode 1: Perform block optimization on each layer separately, calculate the bandwidth of each layer and sum them to obtain the total bandwidth BAND1, and the last two layers will be merged into the next GOP;

[0037] Mode 2: The first two layers are optimized by double-layer block partitioning, and the third layer is optimized by separate block partitioning. The bandwidth of each layer is calculated and summed to obtain the total bandwidth BAND2. The third layer will be merged into the next GOP.

[0038] Mode 3: The first layer is optimized by separate block partitioning, and the last two layers are optimized by double-layer block partitioning. The bandwidth of each layer is calculated and summed to obtain the total bandwidth BAND3. The last two layers will be merged into the next GOP.

[0039] Mode 4: Perform multi-layer joint block optimization of three layers, calculate the bandwidth of each layer and sum them to obtain the total bandwidth BAND4;

[0040] Step 4.2: Compare the total bandwidth of the four modes and select the mode corresponding to the minimum value as the optimal partitioning strategy for the selected adjacent layer group GOP.

[0041] Beneficial effects: This invention can ultimately realize a multi-layer joint data block strategy, a loop unrolling control strategy, and a data storage mapping update strategy with minimal DRAM access, thereby achieving a fine-grained data access and data flow scheme that maximizes data reuse. It can effectively support the automatic generation of code and optimization of computation and memory access efficiency. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the code design for the three data access modes IRO / ORO / WRO according to an embodiment of the present invention;

[0043] Figure 2 This is a schematic diagram of the block relationship in an embodiment of the present invention;

[0044] Figure 3 This is a flowchart illustrating the code implementation of single-layer independent block optimization and loop order optimization in an embodiment of the present invention.

[0045] Figure 4 This is a flowchart illustrating the code implementation of the two-layer joint block optimization and loop order optimization in an embodiment of the present invention.

[0046] Figure 5 This is a flowchart illustrating the code implementation of layer joint block optimization and loop order optimization in an embodiment of the present invention.

[0047] Figure 6 This is a flowchart illustrating the code implementation of the composite cross-layer multi-layer adaptive block scanning mode strategy according to an embodiment of the present invention.

[0048] Figure 7 This is a flowchart of the composite cross-layer multi-layer adaptive block scanning mode strategy according to an embodiment of the present invention;

[0049] Figure 8 This is a diagram showing the cross-layer block optimization results of different layers of the VGG network in this embodiment of the invention.

[0050] Figure 9 This is a comparison diagram of block optimization of different combination modes of the first three layers of the VGG network in an embodiment of the present invention. Detailed Implementation

[0051] To make the objectives, technical solutions, and technical effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0052] This embodiment provides a dynamic cross-layer data reuse method for efficient depthwise convolution computation, specifically including the following:

[0053] Step 1: Design single-layer block optimization and cyclic sequence optimization models.

[0054] Based on the characteristics of the data flow in depthwise convolution computation, three data access modes are determined: Input Feature Coefficient Reuse (IRO), Output Feature Coefficient Reuse (ORO), and Weight Coefficient Reuse (WRO). Figure 1 As shown.

[0055] Based on the characteristics of IRO, ORO, and WRO data streams, the amount of data accessed per cycle for the input feature map, output feature map, and weights under the three data access modes is determined. Specifically, this includes the input feature map coefficients: Bif1, Bif2, Bif3; the output feature map coefficients: Bof1, Bof2, Bof3; and the weight coefficients: Bwgt1, Bwgt2, Bwgt3. The number of cyclic accesses for the input feature map, output feature map, and weights under the three data access modes is also determined. Specifically, this includes the number of accesses for the input feature map coefficients: Cif1, Cif2, Cif3; the number of accesses for the output feature map coefficients: Cof1, Cof2, Cof3; and the number of accesses for the weight coefficients: Cwgt1, Cwgt2, Cwgt3. The batch cyclic block size is set to Tz, the horizontal and vertical block sizes for the data feature map coefficients are Tm*Tn and Th*Tw, the input feature map channel block size is Ti, and the output feature map channel block size is Tj, as shown in Table 1 below.

[0056]

[0057] Table 1: Data volume per access and number of loop accesses under IRO / ORO / WRO modes.

[0058] Step 2: Single-layer independent block optimization and loop order optimization.

[0059] The goal of single-layer convolutional computation block segmentation and loop order optimization is to determine the block parameters Tz, Tm, Tn, Th, Tw, Ti, and Tj. Assume the maximum batch size is Z, the number of input feature map channels is I, the input feature map coefficient dimension is J*M*N, and the convolution kernel size is I*J*P*Q. Since the mainstream convolution kernel P*Q is relatively small, typically 3*3, we can choose Tp=P and Tq=Q. The relationship between the block parameters Tz, Th, Tw, Tm, Tn, Ti, Tj and Z, M, N, I, J is as follows: Figure 2As shown. Where Th=S*(Tm-1)+P, Tw=S*(Tn-1)+Q, and S is the convolution stride.

[0060] Table 1 lists different modes where Z, M, N, I, and J are divided into blocks using step sizes of 1, stepM, stepN, stepI, and stepJ, respectively, yielding block parameters Tz, Th, Tw, Tm, Tn, Ti, and Tj. Under different values ​​of Tz, Th, Tw, Tm, Tn, Ti, and Tj, the data size Bif / Bof / Bwgt stored in the computing core and on-chip cache, as well as the DRAM loop read counts Cif / Cof / Cwgt, are obtained. Assuming the total on-chip SRAM cache size is SRAM_TH, the required SRAM size and the amount of data read from DRAM are calculated based on the characteristics of each data flow combination. Then, the bandwidth consumption is compared for all Tz, Th, Tw, Tm, Tn, Ti, and Tj values ​​that satisfy the condition that the total SRAM consumption does not exceed SRAM_TH. The minimum bandwidth condition minBW is determined as the optimal block combination, and different loop order modes are input. The specific implementation process described above can be found in [reference needed]. Figure 3 The algorithm function shown is 1.

[0061] Step 3: Multi-level joint block optimization and loop sequence optimization.

[0062] There is a possibility of coefficient reuse between the input and output features of adjacent layers. Combining adjacent ORO+IRO layers means that the weight coefficients of adjacent layers need to be cached. Different network models have different parameters, and not all ORO+IRO combinations of adjacent layers have better memory access bandwidth consumption. To minimize total memory access bandwidth while ensuring that the overall SRAM consumption does not exceed the available on-chip SRAM budget, the combination with the minimum total memory access bandwidth for different block parameters of adjacent layers should be found. This optimization process can be referenced as follows: Figure 4 The algorithm function shown is 2.

[0063] There is a possibility of coefficient reuse among the input and output features of adjacent three layers. The combination of adjacent three layers (ORO+IRO / ORI+IRO) implies the need to cache the weight coefficients of these three layers. Different network models have different parameters, and not all such combinations of adjacent three layers offer optimal memory access bandwidth consumption. To minimize total memory access bandwidth while ensuring overall SRAM consumption does not exceed the available on-chip SRAM budget, the combination with the minimum total memory access bandwidth under different block parameters for adjacent three layers should be found. This optimization process can be referenced as follows: Figure 5 As shown in algorithm function 3.

[0064] Actual observations revealed that for some network layers with large feature maps, joint optimization of three layers resulted in better bandwidth access performance than optimization of only one or two layers. However, performance beyond three layers was not as good as optimization with fewer than three layers.

[0065] Step 4: Optimization of dynamic composite block division and loop sequence for single-layer and multi-layer applications.

[0066] For an L-layer network, it is divided into no more than three grouped blocks of different lengths (GOPs). The block partitioning and cycle order optimization within each GOP are determined, including: independent optimization of three adjacent layers; optimization of the preceding layer as a single layer followed by two layers across layers; optimization of the preceding two layers across layers followed by one layer as a single layer; and optimization of all three layers as single-layer blocks. This primarily depends on the characteristics of the network structure parameters of these three layers. This optimization selection process can be referenced as follows: Figure 6 The algorithm function 4 shown, and as shown in Figure 4 Figure 7 The algorithm flow is shown below.

[0067] This embodiment uses a VGG network as an example to present the experimental simulation results of the adaptive block partitioning method. Figure 8 As shown, different layers of the VGG network conform to the cross-layer block optimization results, indicating that only the first three layers' GOP combination optimization performance is better than other partitioning performance. Figure 9 As shown, the block optimization results of different combination modes of the first three layers are presented. Compared with single-layer optimization, the three-layer cross-layer optimization can reduce the bandwidth by about 25% under the premise of satisfying the SRAM constraint. Compared with the single-layer optimization after the first two layers are jointly optimized, the bandwidth can be reduced by about 3.3%. Compared with the joint optimization after the first layer is optimized, the bandwidth can be reduced by about 13.8%.

[0068] In summary, this invention addresses the differences in neural network model structures, which consist of varying numbers of network layers. Each layer may have different convolutional kernel sizes, input channels, and output channels. Based on the different parameters of each layer, mathematical models for cache consumption and external memory access bandwidth consumption under different combination modes are determined. It is explained that bandwidth and memory consumption are crucial factors in selecting optimal block partitioning and cyclic ordering strategies. Furthermore, considering the possibility of reuse of input and output feature coefficients between adjacent layers, the question arises: should adjacent layers use a combination of ORO+IRO optimization, or should two layers be optimized using separate block partitioning and cyclic ordering to minimize overall bandwidth consumption? Different network model parameters lead to significantly different results. To ensure that overall SRAM consumption does not exceed the on-chip available SRAM budget, while also satisfying the constraint of maximizing data reuse, cross-layer combination optimization or single-layer optimization strategies are determined, thereby achieving optimal selection of block partitioning and cyclic ordering across multiple layers.

[0069] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the implementation process of the present invention has been described in detail above, those skilled in the art can still modify the technical solutions described in the foregoing examples or make equivalent substitutions for some of the technical features. All modifications and equivalent substitutions made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A dynamic cross-layer data reuse method for depthwise convolution computation, characterized in that, include: Step 1: Design single-layer block optimization and loop sequence optimization models; Step 2: Perform individual block optimization and loop order optimization; Step 3: Perform multi-level joint block optimization and loop order optimization; Step 4: Perform dynamic composite block optimization and loop sequence optimization for single-layer and multi-layer applications; The model design in step 1 specifically includes: Based on the characteristics of the data flow in depthwise convolution computation, three data access modes are set, including input feature map coefficient reuse (IRO) mode, output feature map coefficient reuse (ORO) mode, and weight coefficient reuse (WRO) mode. Based on the data flow characteristics of the three data access modes, the single access data volume and the number of loop accesses for the input feature map, output feature map, and weights are set in each mode. Step 2 specifically includes: Step 2.1: Divide the feature data calculated by a single convolutional layer into blocks and obtain the block parameters; Step 2.2: Traverse all possible block combinations, calculate the memory bandwidth and storage usage under the three data access modes respectively, and compare the storage threshold and minimum memory bandwidth to determine the optimal block combination and data access mode. Step 3 specifically includes: Step 3.1: Traverse the blocks of data from three adjacent convolutional layers, specifically including: For the u-th, u+1-th, and u+2-th layers (i.e., three adjacent layers), the feature data calculated by the convolution of the u-th layer is first divided into blocks to obtain the block combination of the u-th layer. Then, the block parameters of the u-th layer are reused to obtain the block combination of the u+1-th layer. Where Tw(u+1)=Tn(u) and Th(u+1)=Tm(u), that is, the width and height of the feature map calculated by the convolution of the u-th layer are directly reused as the width and height of the input feature map of the convolution of the u+1-th layer. Then, the block parameters of the u+1-th layer are reused to obtain the block combination of the u+2-th layer. At the same time, the block parameters of the lower layer are adjusted based on the block results of the upper layer. Step 3.2: Iterate through and calculate the bandwidth and storage usage of the current layer for different block combinations, set storage constraints, iterate through and check whether the total storage usage of the three adjacent layers meets the storage constraints, and select the block combination with the smallest total bandwidth. Step 4 specifically includes: Step 4.1: Select a three-layer adjacent layer group GOP to generate four candidate block patterns, including: Mode 1: Perform block optimization on each layer separately, calculate the bandwidth of each layer and sum them to obtain the total bandwidth BAND1, and the last two layers will be merged into the next GOP; Mode 2: The first two layers are optimized by double-layer block partitioning, and the third layer is optimized by separate block partitioning. The bandwidth of each layer is calculated and summed to obtain the total bandwidth BAND2. The third layer will be merged into the next GOP. Mode 3: The first layer is optimized by separate block partitioning, and the last two layers are optimized by double-layer block partitioning. The bandwidth of each layer is calculated and summed to obtain the total bandwidth BAND3. The last two layers will be merged into the next GOP. Mode 4: Perform multi-layer joint block optimization of three layers, calculate the bandwidth of each layer and sum them to obtain the total bandwidth BAND4; Step 4.2: Compare the total bandwidth of the four modes and select the mode corresponding to the minimum value as the optimal partitioning strategy for the selected adjacent layer group GOP.

2. The dynamic cross-layer data reuse method as described in claim 1, characterized in that, The single access data volume of the input feature map, output feature map, and weights in each mode specifically includes: input feature map coefficients: Bif1, Bif2, Bif3; output feature map coefficients: Bof1, Bof2, Bof3; and weight coefficients: Bwgt1, Bwgt2, Bwgt3. The number of cyclic accesses of the input feature map, output feature map, and weights in each mode specifically includes: number of accesses of input feature map coefficients: Cif1, Cif2, Cif3; number of accesses of output feature map coefficients: Cof1, Cof2, Cof3; and number of accesses of weight coefficients: Cwgt1, Cwgt2, Cwgt3.

3. The dynamic cross-layer data reuse method as described in claim 1, characterized in that, Step 2.1 specifically includes: dividing Z, M, N, I, and J into blocks using step sizes 1, stepM, stepN, stepI, and stepJ respectively, to obtain block parameters Tz, Th, Tw, Tm, Tn, Ti, and Tj; where Z is the maximum batch size, I is the number of input feature map channels, J*M*N is the feature map coefficient dimension, Th=S*(Tm-1)+P, Tw=S*(Tn-1)+Q, S is the convolution step size, I*J*P*Q is the convolution kernel size, and Tp=P and Tq=Q are taken; Tz is the batch cyclic block size, Tm*Tn and Th*Tw are the horizontal and vertical block sizes of the data feature map coefficients, Ti is the input feature map channel block size, and Tj is the output feature map channel block size.

4. The dynamic cross-layer data reuse method as described in claim 1, characterized in that, In step 2.2, the comparison of the storage threshold and minimum bandwidth to determine the optimal block combination and data access mode specifically involves: Given a storage threshold SRAM_TH and a minimum bandwidth minBW, if the storage usage of the current mode does not exceed the storage threshold SRAM_TH and the total bandwidth is smaller, then update the minimum bandwidth and data access mode. This will ultimately yield the optimal block combination and mode, minimizing the total bandwidth while satisfying the storage limit.

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