Satellite-borne cpu on-orbit reconstruction device

Abstract

The invention relates to an on-orbit reconstruction device, and provides a satellite-borne cpu on-orbit reconstruction device which comprises a satellite-borne cpu used for completing tasks distributed by a system; the monitoring FPGA receives the uploading information of the measurement and control link and / or the inter-satellite link, analyzes the uploading information and then sends the uploading information to the bridging FPGA; the bridging FPGA receives the uploading information sent by the monitoring FPGA and the service information sent by the plurality of spaceborne devices, performs classified storage, generates corresponding interrupt signals, provides the interrupt signals to the spaceborne cpu for scheduling processing, processes the service information generated by the spaceborne cpu, and sends the processed service information to the corresponding spaceborne devices; the cpu program memory stores a cpu program running program, a bootstrap program and an application program; the FPGA program memory is used for bridging storage of an FPGA pre-stored program and an uploading program, in-orbit reloading of a guiding program and an application program of a satellite-borne cpu is achieved through multiple ways, and the FPGA program memory has the advantages of being high in reliability and flexible to use; and secondly, the bridging FPGA has rich logic resources, so that service information processing is realized, memory decoding is completed, and hardware requirements are reduced.

Description

Technical Field

[0001] The present invention relates to an on-orbit reconstruction device, and in particular to an on-orbit reconstruction device for a satellite-borne CPU. Background Art

[0002] With the need for space exploration, spacecraft are increasingly being used. The CPU is an essential processor within spacecraft. However, due to limitations in CPU selection, processing power, and development cycles, a CPU may not be able to meet all mission functions. Furthermore, due to the specific nature of space applications and the unique nature of spacecraft missions, CPU software development time is short and testing is inadequate, leading to potential software defects that can impact mission completion. Therefore, onboard CPUs require in-orbit reconfiguration to modify software functionality or improve their design.

[0003] There is currently no widely adopted solution for on-orbit reconfiguration of onboard CPUs. Existing technologies fail to provide an effective on-orbit software update mechanism and lack support for hardware adaptability. Summary of the Invention

[0004] To address the above issues, the present invention provides an on-orbit CPU reconstruction device. The device divides on-orbit CPU software into three categories: boot software, pre-stored application software, and upstream application software. Based on the software's reliability requirements, the device implements on-orbit software reconstruction through different approaches. The above objectives of the present invention are achieved through the following technical solutions: The present invention provides a satellite-borne CPU on-orbit reconstruction device, comprising a satellite-borne CPU, a monitoring FPGA, a bridge FPGA, a CPU program memory and an FPGA program memory, wherein: Onboard CPU, used to complete tasks assigned by the system; Monitoring FPGA, connected to the FPGA program memory, and receives the upper injection information of the measurement and control link and / or the intersatellite link and parses it and sends it to the bridge FPGA; Bridge FPGA, chip select decoding and interface bridge between the onboard CPU and the CPU program memory of the onboard CPU peripherals, receive and monitor the injection information sent by the FPGA and the service information sent by multiple onboard devices, classify and store them, and generate corresponding interrupt signals to provide them to the onboard CPU for scheduling and processing. At the same time, the service information generated by the onboard CPU is processed and sent to the corresponding onboard devices; CPU program memory, used to store CPU program operation, boot program and application program; FPGA program memory is used to bridge the storage of FPGA pre-stored programs and uploaded programs.

[0005] Furthermore, the onboard CPU has the ability to adapt to the high radiation and single particle environment of space for business processing; The monitoring FPGA is a highly reliable anti-fuse FPGA used for system control. It monitors the onboard CPU's dog feed signal in real time and automatically resets the onboard CPU when an anomaly is detected. It also reloads and refreshes the bridge FPGA through the Select MAP interface. The bridge FPGA is a RAM-based FPGA used for interface bridging and service information preprocessing. CPU program memory, including CPU program running memory, CPU boot program memory and CPU application memory; wherein, the CPU program running memory is a DRAM or SRAM device, the CPU boot program memory is a read-only memory ROM device, and the CPU application memory is an MRAM or NOR FLASH device; The FPGA program memory includes a bridge FPGA pre-stored program memory and an FPGA on-injection program memory, wherein the bridge FPGA pre-stored program memory is a read-only memory PROM device, and the FPGA on-injection program memory is a NOR FLASH device.

[0006] Furthermore, the onboard CPU is directly connected to the CPU program running memory, and is connected to the CPU boot program memory and the CPU application program memory through the bridge FPGA.

[0007] Furthermore, the CPU application memory is divided into program storage area 1 and program storage area 2, wherein the application 1 stored in program storage area 1 adopts triple modular redundancy and EDAC; the application stored in program storage area 2 adopts EDAC.

[0008] Furthermore, the CPU boot program memory includes an external mode and a built-in mode, and the external mode is set by default; wherein, The external mode is implemented using an external programmable read-only memory (PROM); the built-in mode is implemented by the bridge FPGA using internal BRAM to build a ROM, and adopts triple-module redundancy, and the switching is implemented by the bridge FPGA.

[0009] Furthermore, the write signal of the CPU application memory is generated by the onboard CPU or the bridge FPGA and sent to the monitoring FPGA; the monitoring FPGA has a quasi-prohibition design for the write signal of the CPU application memory, which is used to provide the CPU application memory with a write protection function, and allows the contents in the CPU application memory to be modified when the write signal is allowed.

[0010] Furthermore, the bridge FPGA has a bridge mode and a direct control mode. In the bridge mode, the onboard CPU directly accesses the CPU application memory; in the direct control mode, the write signal of the CPU application memory is controlled by the bridge FPGA, and the update of the CPU application memory, including application 1, is realized through the bridge FPGA.

[0011] Furthermore, when the bridge FPGA is in bridge mode, the onboard CPU has a boot reconstruction mode and an application reconstruction mode. In the boot reconstruction mode, the onboard CPU loads a boot program for on-orbit reconstruction of the CPU pre-stored application area; in the application reconstruction mode, the onboard CPU loads application 1 to realize on-orbit reconstruction of application 2. At the same time, the bridge FPGA sets the address of program storage area 1 to read-only to protect application 1.

[0012] Furthermore, when the CPU boot program memory adopts the built-in mode, the boot program is solidified in the ROM inside the bridge FPGA, and then the injection program of the bridge FPGA is injected into the FPGA injection program memory through the monitoring FPGA for storage.

[0013] Furthermore, after the program storage area 2 is reconstructed by the application program 1 and the boot program is used to reconstruct the program storage area 1, the bridge FPGA is used to reconstruct the program storage area 1, and the bridge FPGA is used to reconstruct the program and the boot program.

[0014] Compared with the prior art, the present invention has at least one of the following beneficial effects: The present invention provides an on-orbit CPU reconfiguration device that achieves on-orbit reloading of the on-board CPU's boot program and application programs through multiple approaches, offering the advantages of high reliability and flexible use. Furthermore, the use of a bridged FPGA effectively reduces the on-board CPU load, providing a higher operating frequency and thus improving the CPU's processing power. Furthermore, the bridged FPGA possesses abundant logic resources, enabling not only business information processing but also memory decoding, significantly reducing hardware requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a principle block diagram of the on-orbit CPU reconstruction device of the present invention; Figure 2 It is a memory address allocation diagram of the on-board CPU on-orbit reconstruction device of the present invention; Figure 3 This is a typical information frame format of the on-board CPU on-orbit reconstruction device of the present invention. DETAILED DESCRIPTION

[0016] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making any creative work are within the scope of protection of this application. However, the present invention can realize the automated processing of multiple states of the sub-array using different operating systems, processing methods, etc., and should not be interpreted as being limited to the implementation methods proposed herein. On the contrary, these embodiments are proposed to achieve full and complete disclosure and to enable more people in the relevant technical field to fully understand the scope of the present invention. In these drawings, for clarity, relative sizes may be scaled or only the actual devices of the system may be schematically represented.

[0017] Those skilled in the art will appreciate that, unless otherwise stated, the singular forms "a," "an," "said," and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present invention refers to the presence of the stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0018] First embodiment The present invention provides a satellite-borne CPU on-orbit reconstruction device, such as Figure 1 As shown, it includes onboard CPU, monitoring FPGA, bridge FPGA, CPU program memory and FPGA program memory, among which, Onboard CPU, used to complete tasks assigned by the system; Monitor FPGA, connected to FPGA program memory, and receive command, live information and / or intersatellite link uplink information from measurement and control link, analyze the correctness and compliance, and send it to bridge FPGA through internal interface; Bridge FPGA, chip select decoding and interface bridge between the onboard CPU and the CPU program memory of the onboard CPU peripherals, receive and monitor the injection information sent by the FPGA and the service information sent by multiple onboard devices, classify and store them, and generate corresponding interrupt signals to provide them to the onboard CPU for scheduling and processing. At the same time, the service information generated by the onboard CPU is processed and sent to the corresponding onboard devices; CPU program memory, used to store CPU program operation, boot program and application program; FPGA program memory is used to bridge the storage of FPGA pre-stored programs and uploaded programs.

[0019] Furthermore, the onboard CPU has the ability to adapt to the high radiation and single particle environment of space for business processing; The monitoring FPGA is a highly reliable anti-fuse FPGA used for system control. It monitors the onboard CPU's dog feed signal in real time and automatically resets the onboard CPU when an anomaly is detected. It also reloads and refreshes the bridge FPGA through the Select MAP interface. The onboard CPU is the BM3823 chip with excellent space radiation resistance, with a total dose resistance of ≥ 1×103Gy (Si), a single event lock-up (SEL) threshold of ≥ 75MeV·cm2 / mg, and a single event functional on-orbit error rate (GEO orbit): ≤ 5×10-5 times / day·device; the monitoring FPGA is a highly reliable anti-fuse FPGA (AX500), the program is burned in once and cannot be changed, and it is insensitive to single particles in space; the bridge FPGA is an FPGA based on RAM-type process (JFM4VSX55RT), which has rich logic and storage resources and has reconstruction characteristics; the CPU program running memory is selected as a 256M*40bits DRAM chip (3DSD2G40VS5493), with a maximum operating speed of 133MHz and a data access capability of about 5Gbps; the CPU boot program memory is selected as two 32K*8bits PROM chips (JMR28F256), and the memory adopts deep expansion (PROM0, PROM1); the CPU application memory is selected as four 2M*16bits NOR The FLASH chip (JFM29GL256RH) uses deep memory expansion (NOR0, NOR1, NOR2, NOR3). The bridge FPGA uses two 16Mbits PROM chips (XQR17V16). The FPGA program memory uses four 2M*16bit NORFLASH chips (JFM29GL256RH).

[0020] The bridge FPGA is a RAM-based FPGA used for interface bridging and service information preprocessing. CPU program memory, including CPU program running memory, CPU boot program memory and CPU application memory; among them, the CPU program running memory has the characteristics of fast access speed and large capacity, and is generally a DRAM or SRAM device; the CPU boot program memory has the characteristics of fast access speed and large capacity, and is a read-only memory ROM device; the CPU application memory has the characteristics of data not being lost in the event of power failure and can be reprogrammed, and is an MRAM or NOR FLASH device; FPGA program memory includes bridged FPGA pre-stored program memory and FPGA on-injection program memory. Among them, the bridged FPGA pre-stored program memory has the characteristics of not losing data during power failure and cannot be reprogrammed. It is a read-only memory PROM device. The FPGA on-injection program memory has the characteristics of not losing data during power failure and can be reprogrammed and has a large capacity. It is a NOR FLASH device.

[0021] Furthermore, the onboard CPU is directly connected to the CPU program running memory, and is connected to the CPU boot program memory and the CPU application program memory through the bridge FPGA.

[0022] Furthermore, the CPU application memory is divided into program storage area 1 and program storage area 2. Among them, the application 1 stored in program storage area 1 adopts triple modular redundancy and EDAC, which has higher reliability and single-event resistance; the application stored in program storage area 2 adopts EDAC.

[0023] Furthermore, the CPU boot program memory includes an external mode and a built-in mode, and the external mode is set by default; wherein, The external mode is implemented using an external programmable read-only memory (PROM); the built-in mode is implemented by the bridge FPGA using internal BRAM to build a ROM, and adopts triple-module redundancy, and the switching is implemented by the bridge FPGA.

[0024] In this embodiment, Figure 2 As shown, the boot program memory address is allocated to 0x00000000 ~ 0x0000FFFF. When the CPU output chip select ROMSN[0] is valid and the CPU access address 0x00000000 ~ 0x00007FFF, the bridge FPGA maps the storage space of PROM0; when the CPU output chip select ROMSN[0] is valid and the CPU access address 0x00008000 ~ 0x0000FFFF, the bridge FPGA maps the storage space of PROM1. The application memory address is allocated to 0x08000000 ~ 0x0FFFFFFF. When the CPU output chip select ROMSN[1] is valid, the bridge FPGA implements NOR0, NOR1, NOR2 and NOR3 storage space mapping according to the CPU access address. The program running memory DRAM address is allocated to 0x3000 0000 ~ 0x3FFF FFFF and is directly controlled by the onboard CPU.

[0025] Furthermore, the write signal of the CPU application memory is generated by the onboard CPU or the bridge FPGA and sent to the monitoring FPGA; the monitoring FPGA has a quasi-prohibition design for the write signal of the CPU application memory, which is used to provide the CPU application memory with a write protection function, and allows the contents in the CPU application memory to be modified when the write signal is allowed.

[0026] Furthermore, the bridge FPGA has a bridge mode and a direct control mode. In the bridge mode, the onboard CPU directly accesses the CPU application memory; in the direct control mode, the write signal of the CPU application memory is controlled by the bridge FPGA, and the update of the CPU application memory, including application 1, is realized through the bridge FPGA.

[0027] Furthermore, when the bridge FPGA is in bridge mode, the onboard CPU has a boot reconstruction mode and an application reconstruction mode. In the boot reconstruction mode, the onboard CPU loads a boot program for on-orbit reconstruction of the CPU pre-stored application area; in the application reconstruction mode, the onboard CPU loads application 1 to realize on-orbit reconstruction of application 2. At the same time, the bridge FPGA sets the address of program storage area 1 to read-only to protect application 1.

[0028] Furthermore, when the CPU boot program memory adopts the built-in mode, the boot program is solidified in the ROM inside the bridge FPGA, and then the injection program of the bridge FPGA is injected into the FPGA injection program memory through the monitoring FPGA for storage.

[0029] Furthermore, after the program storage area 2 is reconstructed by the application program 1 and the boot program is used to reconstruct the program storage area 1, the bridge FPGA is used to reconstruct the program storage area 1, and the bridge FPGA is used to reconstruct the program and the boot program.

[0030] Combine Figure 3 The typical format of the onboard information frame is shown in FIG. The operation method of the onboard CPU on-orbit reconstruction device is as follows: S1: Determine whether to update the CPU boot program. If so, enter S2; otherwise, enter S6.

[0031] S2: Modify the bridge FPGA design: Immobilize the CPU bootloader in the bridge FPGA's ROM, implement triple-module redundancy in the bridge FPGA, and update the CPU bootloader mapping address to the internal memory. Then, generate the bridge FPGA upload frame information according to the upload information frame format protocol requirements.

[0032] S3: Send the uplink frame information of the bridge FPGA to the monitoring FPGA through the measurement and control channel or data transmission channel of the satellite-to-ground link or inter-satellite link.

[0033] S4: The monitoring FPGA identifies the bridge FPGA injection program according to the sub-leader in the frame format, completes the continuity, compliance and correctness judgment, and writes it into the bridge FPGA injection program memory.

[0034] S5: After the bridge FPGA program is loaded, the monitoring FPGA receives a remote control command to switch the bridge FPGA program to the loading state and sends a bridge FPGA reload command. After the bridge FPGA is loaded, the monitoring FPGA automatically sends a reset signal to the onboard CPU. The onboard CPU loads the bridge FPGA's built-in bootloader, which then loads the corresponding application program to run.

[0035] S6: Determine whether it is in bridge mode. If so, proceed to S7; otherwise, proceed to S18.

[0036] S7: The monitoring FPGA receives the remote control command through the measurement and control link, sets the "write signal" to be allowed, and sets the update mode to the bridge mode.

[0037] S8: Determine whether it is the boot program update mode, if so, enter S9, otherwise enter S19.

[0038] S9: The monitoring FPGA receives the "Bootstrap Update Mode" remote control command via the measurement and control link and sets the onboard CPU update register to Bootstrap Update Mode (the default is Application Update Mode). The monitoring FPGA then automatically initiates an onboard CPU reset command, causing the onboard CPU to load the bootstrap program and enter the bootstrap program loading state.

[0039] S10: Send the onboard CPU's injection information to the monitoring FPGA through the satellite-to-ground link or the inter-satellite link's measurement and control channel or data transmission channel.

[0040] S11: The monitoring FPGA identifies the secondary header in the frame format as the onboard CPU's injection program, completes continuity, compliance, and correctness judgments, and forwards the injection information to the bridge FPGA.

[0041] S12: Determine whether it is in bridge mode. If so, proceed to S13; otherwise, proceed to S20.

[0042] S13: The bridge FPGA receives the onboard CPU injection information, stores it in the internal cache of the bridge FPGA, and sets the CPU injection information reception interrupt to be valid.

[0043] S14: Determine whether it is the boot program update mode, if so, enter S15, otherwise enter S21.

[0044] S15: The onboard CPU boot program receives an interrupt from the upper note information, reads data from the bridge FPGA cache through IO interaction, completes the conformity and correctness judgment of the upper note information, cancels the frame format of the upper note information, and extracts valid data; after the upper note information is received, the integrity check of the valid data is performed.

[0045] S16: After the onboard CPU boot program checks that the information is complete and correct, it directly writes it into the CPU application storage area 1 through the bridge FPGA.

[0046] S17: After the injection is completed, the monitoring FPGA receives the instruction to set the "write signal" to disabled, and receives the instruction "cpu application 1 start" to set the application 1 mode for the onboard cpu program selection register, and then automatically sends the onboard cpu reset instruction, and the onboard cpu starts the application 1 to run.

[0047] S18: The monitoring FPGA receives the remote control command through the measurement and control link, sets the "write signal" to be allowed, and sets the update mode to the direct control mode.

[0048] S19: The monitoring FPGA receives the "application update mode" remote control command via the measurement and control link and sets the onboard CPU update register to application update mode. The monitoring FPGA then automatically initiates a reset command for the onboard CPU, causing the onboard CPU to load the bootloader, which then loads the corresponding application.

[0049] S20: The bridge FPGA receives the onboard CPU notification information, completes the conformity and correctness judgment of the notification information, cancels the frame format of the notification information, and directly writes the valid data into the CPU application storage area 1.

[0050] S21: The onboard CPU application receives an interrupt from the upper note information, reads data from the bridge FPGA cache through IO interaction, completes the conformity and correctness judgment of the upper note information, and cancels the frame format of the upper note information; after the upper note information is received, an integrity check is performed.

[0051] S22: After the onboard CPU application checks that the above information is complete and correct, it is directly written into the CPU application storage area 2 through the bridge FPGA.

[0052] S23: After the injection is completed, the monitoring FPGA receives the instruction to set the "write signal" to disabled, and receives the instruction "cpu application 2 start" to set the application 2 mode for the onboard cpu program selection register, and then automatically sends the onboard cpu reset instruction, and the onboard cpu starts application 2.

[0053] Furthermore, in this embodiment, the onboard CPU application 1 is preferentially used to reconstruct the application storage area 2, and the onboard CPU boot program is used to reconstruct the CPU application storage area 1; secondly, the bridge FPGA is used to reconstruct the CPU application storage area 1; finally, the bridge FPGA reconstruction program is used to reconstruct the CPU boot program.

[0054] The above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be noted that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be considered as the scope of protection of the present invention.

Claims

1. A satellite-borne CPU on-orbit reconfiguration device, characterized in that: It includes onboard CPU, monitoring FPGA, bridge FPGA, CPU program memory and FPGA program memory, among which, The onboard CPU is used to complete tasks assigned by the system; The monitoring FPGA is connected to the FPGA program memory and receives the upstream information of the measurement and control link and / or the intersatellite link and parses it before sending it to the bridging FPGA; The bridge FPGA is connected to the chip select decoding and interface bridge of the onboard CPU and the CPU program memory of the onboard CPU peripheral device, receives the upper injection information sent by the monitoring FPGA and the service information sent by multiple onboard devices, classifies and stores them, and generates corresponding interrupt signals to provide them to the onboard CPU for scheduling processing, and at the same time processes the service information generated by the onboard CPU and sends it to the corresponding onboard devices; The CPU program memory is used to store the CPU program operation, boot program and application program; The FPGA program memory is used to bridge the storage of FPGA pre-stored programs and uploaded programs.

2. The on-orbit CPU reconfiguration device according to claim 1, characterized in that: The onboard CPU has the ability to adapt to high radiation and single particle environments in space and is used for business processing; The monitoring FPGA is a highly reliable anti-fuse FPGA used for controlling the system. The monitoring FPGA monitors the dog feeding signal of the onboard CPU in real time and automatically resets the onboard CPU when an abnormality is detected. The bridge FPGA is reloaded and refreshed through the SelectMAP interface. The bridge FPGA is an FPGA based on a RAM-type process and is used for interface bridging and preprocessing of the service information; The CPU program memory includes a CPU program running memory, a CPU boot program memory and a CPU application memory; wherein the CPU program running memory is a DRAM or SRAM device, the CPU boot program memory is a read-only memory ROM device, and the CPU application memory is an MRAM or NOR FLASH device; The FPGA program memory includes a bridge FPGA pre-stored program memory and an FPGA on-injection program memory, wherein the bridge FPGA pre-stored program memory is a read-only memory PROM device, and the FPGA on-injection program memory is the NORFLASH device.

3. The on-orbit CPU reconfiguration device according to claim 2, characterized in that: The onboard CPU is directly connected to the CPU program running memory, and is connected to the CPU boot program memory and the CPU application program memory through the bridge FPGA.

4. The on-orbit CPU reconfiguration device according to claim 2, characterized in that: The CPU application memory is divided into program storage area 1 and program storage area 2, wherein the application 1 stored in the program storage area 1 adopts triple modular redundancy and EDAC; the application stored in the program storage area 2 adopts the EDAC.

5. The on-orbit CPU reconfiguration device according to claim 2, characterized in that: The CPU boot program memory includes an external mode and a built-in mode, and the external mode is set by default; wherein, The external mode is implemented by the external programmable read-only memory PROM; the built-in mode is implemented by the bridge FPGA using internal BRAM to construct ROM, and adopting the triple module redundancy, and switching is implemented by the bridge FPGA.

6. The on-orbit CPU reconfiguration device according to claim 4, characterized in that: The write signal of the CPU application memory is generated by the onboard CPU or the bridge FPGA and sent to the monitoring FPGA; the monitoring FPGA has a quasi-prohibition design for the write signal of the CPU application memory, so that the CPU application memory has a write protection function, and the contents in the CPU application memory are allowed to be modified when the write signal allows.

7. The on-orbit CPU reconfiguration device according to claim 6, characterized in that: The bridge FPGA has a bridge mode and a direct control mode. In the bridge mode, the onboard CPU directly accesses the CPU application memory; in the direct control mode, the write signal of the CPU application memory is controlled by the bridge FPGA, and the update of the CPU application memory, including the application 1, is realized through the bridge FPGA.

8. The on-orbit CPU reconfiguration device according to claim 7, characterized in that: When the bridge FPGA is in the bridge mode, the onboard CPU has a boot reconstruction mode and an application reconstruction mode. In the boot reconstruction mode, the onboard CPU loads a boot program for on-orbit reconstruction of the CPU pre-stored application area; in the application reconstruction mode, the onboard CPU loads the application 1 to realize on-orbit reconstruction of the application 2. At the same time, the bridge FPGA sets the address of the program storage area 1 to read-only to protect the application 1.

9. The on-orbit CPU reconfiguration device according to claim 8, characterized in that: When the CPU boot program memory adopts the built-in mode, the boot program is solidified in the ROM inside the bridge FPGA, and then the injection program of the bridge FPGA is injected into the FPGA injection program memory through the monitoring FPGA for storage.

10. The on-orbit CPU reconfiguration device according to claim 9, characterized in that: The program storage area 2 is reconstructed by the application program 1. After the boot program reconstructs the program storage area 1, the bridge FPGA is used to reconstruct the program storage area 1. The bridge FPGA reconstruction program is used to reconstruct the boot program.

Images