Double-thread complementary algebraic derivative estimation compensation algorithm based on FPGA

Abstract

The invention provides a dual-thread complementary algebraic derivative estimation compensation algorithm based on an FPGA (Field Programmable Gate Array). The method is characterized in that a reference signal and a measurement signal enter an FPGA after passing through ADC1 and ADC2 modules and then respectively pass through a biorthogonal phase-locked amplification module 3 and a phase difference module 4 in the FPGA, a pair of orthogonal signals only containing Doppler frequency shift is obtained after passing through a phase difference module 5, and then the signals enter a double-thread complementary data aging error compensation (DAEC) module 6 for compensation; the calculated signal does not contain the aging error, and finally, a Cordic calculation module 7 is utilized to obtain a final phase, and the final phase is calculated. The FPGA implementation method can be used for compensating the data aging error in a heterodyne interference measurement system, and can be widely applied to the fields of displacement measurement, position control, position sensor calibration, platform calibration and the like.

Description

(1) Technical field

[0001] This invention relates to a dual-threaded complementary algebraic derivative estimation and compensation algorithm based on heterodyne interferometry, specifically an FPGA-implemented algorithm for high-precision displacement measurement under dynamic conditions. This algorithm can be used to compensate for data aging errors and has applications in dynamic displacement monitoring, laser ranging, and other fields, belonging to the field of signal processing technology. (2) Technical background

[0002] Positioning calibration under dynamic conditions is gaining increasing attention in high-precision fields such as semiconductor lithography and additive manufacturing. Heterodyne interferometry is widely used for stage position calibration due to its high dynamic range and direct traceability to the instrument. When processing the measurement and reference signals in heterodyne interferometry, signal processing algorithms and optical receivers introduce time delays and phase shifts into the measurement data, resulting in an inaccurate representation of the stage's current position. This error, known as data aging error, depends on the stage's velocity and can become significant when the velocity is unstable during dynamic calibration.

[0003] Traditional measurement methods typically assume that data aging errors are linearly correlated with velocity (i.e., Doppler frequency). However, these methods are less effective in compensating for non-constant velocity conditions. Therefore, this paper proposes an FPGA-based dual-threaded complementary algebraic derivative estimation compensation algorithm that accurately compensates for data aging errors in non-constant velocity conditions, improving the accuracy and real-time performance of dynamic measurements.

[0004] In the prior art, there are few applications of heterodyne interferometry using FPGA, and most of them are single-threaded processing, which cannot effectively solve the measurement errors caused by time delay and signal mutation. Therefore, the present invention proposes a new compensation scheme through a dual-thread complementary mechanism and an algebraic derivative estimation method. The present invention solves the data aging error in the field programmable gate array (FPGA) in real time by tracking the phase derivative, and proposes a comprehensive data aging error model and compensation method. FPGA hardware-in-the-loop simulation shows that under dynamic conditions, the data aging error under fixed and variable delays is greatly reduced, and sub-nanometer resolution can still be maintained during quasi-static calibration. This improves the dynamic accuracy of displacement measurement, especially for non-constant speed motion. (3) Summary of the invention

[0005] The purpose of the present invention is to provide a dual-threaded complementary algebraic derivative estimation compensation algorithm based on an FPGA platform with a simple structure and strong real-time performance, which can effectively compensate for data aging errors in dynamic measurements, especially under non-constant speed motion, and provide high-precision displacement measurement.

[0006] The purpose of the present invention is achieved as follows: the present invention implements an algebraic derivative estimation algorithm on an FPGA platform to calculate the derivative of the signal after phase differentiation in real time, and combines it with a dual-thread complementary mechanism to compensate for data aging errors. The core idea of the algorithm is to estimate the high-order derivatives of the displacement signal (such as velocity and acceleration) through multiple integrations and Taylor expansions, and to eliminate errors in the initialization phase through dual-thread alternating calculation and output, thereby ensuring the continuity and high precision of the measurement results. It is characterized by: it consists of five parts: 1. signal input module 2. ADC conversion module 3. dual-orthogonal phase-locked module 4. phase solution module 5. dual-thread complementary data aging error compensation (DAEC) module.

[0007] (Claim 1) The ADC conversion module in the method, as an analog-to-digital converter, is mainly responsible for converting the laser light emitted by the dual-frequency laser from an optical signal into a measurable sine wave.

[0008] The dual-orthogonal phase-locked module in the proposed method is primarily responsible for avoiding the influence of unequal amplitudes of the reference and measurement signals and the frequency uncertainty of the dual-frequency laser. A dual-orthogonal phase-locked amplification algorithm module is designed. After preprocessing, the noise contained in the reference and measurement signals is suppressed and the DC component is removed. The preprocessed reference and measurement signals are shown in Equations (2) and (3). I r =Rcos[2π(f1-f2+f′)t] (1) I m =Mcos[2π(f1-f2+Δf+f′)t] (2)

[0009] The expressions of the two fixed frequency signals generated by the DDS in the dual orthogonal phase-locked module are shown in equations (4) and (5). The frequencies of the two signals are equal to the frequency difference of the dual-frequency lasers. D sin =2 sin[2π(f1-f2)t] (3) D cos =2 cos[2π(f1-f2)t] (4) The DDS-generated signal is multiplied by the reference and measurement signals, resulting in four mixed signals. Each of these four signals contains a high-frequency component equal to the sum of the frequencies of the two multiplied signals, and a low-frequency component equal to the difference between the frequencies of the two multiplied signals. After passing through a low-pass filter (LPF), the high-frequency component is removed, while the low-frequency component is retained. The resulting four signals are expressed as follows. f r×sin = -Rcos(2πf′t) (5) f r×cos =Rsin(2πf′t) (6) f m×sin= -Mcos[2π(f′+Δf)t] (7) f m×cos =Msin[2π(f′+Δf)t] (8)

[0010] The phase difference module in the method is mainly responsible for eliminating the variable f′ and calculating (f r×sin )×(f m×sin )-(f r×cos )(f m×cos ) (9) and (f r×cos )(f m×sin )-(f r×sin )(f m×cos ) (10) Two signals with equal amplitudes and containing only frequency Δf can be obtained as shown in equations (12) and (13).

[0011] The phase calculation module in this method uses the Cordic algorithm. It is primarily responsible for performing an inverse tangent operation on equations (12) and (13) to obtain the phase difference φ. The expression for φ is shown in equation (14).

[0012] The dual-threaded, complementary Data Aging Error Compensation (DAEC) module in this method is primarily responsible for determining the system's equivalent time delay, τ, before measurement. During the measurement process, it calculates first-, second-, and even higher-order derivatives of the original phase in real time. It uses the equivalent time delay and phase derivatives to calculate the data aging error in real time. Finally, this error is subtracted from the original phase measurement.

[0013] The relevant algorithms are described in detail below.

[0014] Due to design and configuration reasons, signals may not travel the same length of path, such as different cables, paths on printed circuit boards, or even the length of fiber optic cables, which causes signals to experience different paths. This delay. When these signals are combined to generate values, unequal delays introduce errors. First, a delay model is established: Assuming the delay between the input signal and the corresponding output signal is τ, the actual phase φ is different from the measured phase φ with delay. d The relationship between φ d (t)=φ(t-τ) (14)

[0015] In order to compensate for the constant time delay, the time delay τ is obtained in advance by calibration or theoretical derivation. The module tracks the Doppler frequency f by calculating the first-order derivative of the original phase measurement in real time. D (equivalent to speed), then the actual phase can be calculated by φ(T) = φ d (t)-Δφ=φ d (t)+2πf D τ. In order to compensate for the non-constant time delay, the time delay at each Doppler frequency is measured in advance. Since the time delay varies with frequency, the error cannot be compensated as in the above formula. Usually, it will be a finite time delay τ(f D ) or phase error φ(f D ) value is stored in the lookup table LUT and is converted to the instantaneous Doppler frequency f D The actual phase can then be obtained by φ(t)=φ d (t)-φ(f D )calculate.

[0016] If we use the measured phase and its Taylor expansion to represent the actual phase, the actual phase can be obtained by equation (67).

[0017] In signal processing and system control applications, several methods have been developed for estimating the derivatives of noisy signals. The basic idea is to smooth the signal first and then calculate its derivative. Common methods include polynomial regression, Tikhonov regularization, smoothing splines, convolution smoothing, and total variation regularization. These methods either require a large number of complex computations or rely on future samples (non-causal systems). Therefore, implementing online and real-time derivative estimation in FPGAs is impractical. We have chosen an algebraic derivative estimation method that uses a finitely weighted integral combination of the noisy signal to estimate its derivative in time, which is arbitrarily small. This method is highly robust to significant noise.

[0018] When extracting the original phase φ d We used the algebraic derivative estimation method to calculate each derivative of . The basic principle is further explained below: The algebraic derivative estimation method uses a Taylor polynomial model to fit the signal y(t) and calculate its derivative. Its core is to use the differential properties in the complex frequency domain to obtain the first-order derivative information of the encoder signal and express the result in the real domain through the inverse Laplace transform. The signal y(t) is an arbitrary smooth curve that changes with time, t∈[0,∞). y(t) is expressed near t=0 using a truncated Taylor series expansion as shown in Equation (15). In Equation (16), N is the expansion order of the angular displacement signal, which determines the signal fitting accuracy. The N+1 order derivative of Equation (15) is shown in Equation (16). Perform frequency domain transformation on Equation (16) and multiply both sides by s -k , and we get formula (16). Different values of k correspond to equation (17) containing information about the 1st to kth order derivatives of y(t). Taking k = N, we can obtain the first-order derivative of y(t). According to the Leibniz formula, Equation (17) is expanded into Equation (18). The expression of Equation (18) in the time domain after inverse transformation is shown in Equation (19). When formula (19) is expanded, the term j=N+1 is the first-order derivative component of the angular displacement Use variable z1 to replace the integral term, the encoder angular velocity The expression is shown in formula (20). Since t = 0 is the singular point of Eq. (20), the small time region [0, t ε ) The speed measurement results are unavailable, and this area is called the speed measurement singularity domain. ε is the singularity domain boundary. The differentials of z1 are expressed in the form of time-varying linear filters as shown in Equation (21).

[0019] Based on this, we can obtain The biggest difference between the complementary algebraic derivative estimation and the finite difference method is that it does not directly reflect the sudden change of the signal, but makes the sudden change of the signal derivative tend to be gentle. Because the complementary algebraic derivative estimation multiplies both sides of Equation (17) by s in the frequency domain -k This measure is equivalent to adding a k-order integration link, which makes it have the characteristics of the cascade integrator that passes low frequencies and blocks high frequencies. This characteristic makes the complementary algebraic derivative estimation speed measurement have strong anti-interference ability.

[0020] If fifth-order integration is used, the first and second derivatives of the original phase can be estimated as: z′1=z2-450t 4 φ(t) (24) z′2=z3+2400t 3 φ(t) (25) z′3=z4-5400t 2 φ(t) (26) z′4=z5+4320tφ(t) (27) z′5 = -720φ(t) (28) In equations (22) and (23), ε is the transient time. Since t = 0 is a singular point in equations (22) and (23), the velocity measurement results in the small time region [0, ε) near this point are unavailable. This region is called the singularity region, and ε is the singularity region boundary.

[0021] The algorithm is improved by adopting a dual-thread complementary approach: two complementary algebraic derivative estimation threads are simultaneously executed, with the initialization times of the two threads separated by half a period T / 2. That is, the first thread is initialized at a full period T, and the second thread is initialized at an odd multiple of the half period T / 2. When the first thread is initialized, the second thread switches to output the speed result, and vice versa. The dual-thread speed measurement expression is shown in Equation (29). In formula (29): n = 0, 1... (IV) Description of the accompanying drawings

[0022] Figure 1 The present invention is a flowchart of phase solution and compensation of a dual-thread complementary algebraic derivative estimation and compensation algorithm based on FPGA.

[0023] Figure 2 The invention relates to an embodiment of a dual-thread complementary algebraic derivative estimation and compensation algorithm based on FPGA.

[0024] Figure 3 The structure diagram of a dual-thread complementary algebraic derivative estimation and compensation algorithm based on FPGA is shown.

[0025] Figure 4 The present invention is a schematic diagram of an algebraic derivative estimation method of an FPGA-based dual-thread complementary algebraic derivative estimation compensation algorithm.

[0026] Figure 5 The present invention is a timing diagram of a dual-thread complementary method of an FPGA-based dual-thread complementary algebraic derivative estimation compensation algorithm. (V) Specific implementation methods

[0027] The present invention will be further described below with reference to specific embodiments.

[0028] Figure 1This is a flowchart of the phase solution and compensation of a dual-threaded complementary algebraic derivative estimation and compensation algorithm based on an FPGA platform, implemented on a Kintex-7MK7325FA FPGA board. The algorithm comprises an ADC module, a dual-orthogonal phase-locked amplifier module, a phase differential module, and a DAEC module. The reference and measurement signals pass through the ADC module and then enter the FPGA platform. They then pass through the dual-orthogonal phase-locked amplifier module and the phase differential module within the FPGA. After passing through the phase differential module, a pair of orthogonal signals containing only Doppler frequency shift are obtained. The signals then enter the DAEC module for compensation. The calculated signal contains no aging error. Finally, the Cordic solution module is used to obtain the final phase, which then enters the data aging error compensation module (DAEC) to calculate the final phase.

[0029] Figure 2 This is an embodiment of the dual-thread complementary algebraic derivative estimation compensation algorithm based on FPGA of the present invention. It is composed of the system optical path, the reference optical signal f r1 and measure the optical signal f m1 , photoelectric conversion module APD, reference signal f r and the measured signal f m It consists of nine parts: ADC module, dual orthogonal phase-locked module, phase differential module, Cordic solution module and DAEC module.

[0030] Two lasers are emitted from the system optical path, namely the reference light signal f r1 and measure the optical signal f m1 After passing through the photoelectric conversion module, the optical signals are converted into electrical signals. After passing through the ADC module, the expressions of the two signals are as follows: I r =Rcos[2π(f1-f2+f′)t] (30) I m =Mcos[2π(f1-f2+Δf+f′)t] (31)

[0031] The expressions of the two fixed frequency signals generated by the DDS in the dual orthogonal phase-locked module are shown in Equations (32) and (33). The frequencies of the two signals are equal to the frequency difference of the dual-frequency lasers. D sin =2 sin[2π(f1-f2)t] (32) D cos =2 cos[2π(f1-f2)t] (33) The DDS-generated signal is multiplied by the reference and measurement signals, resulting in four mixed signals. Each of these four signals contains a high-frequency component equal to the sum of the frequencies of the two multiplied signals, and a low-frequency component equal to the difference between the frequencies of the two multiplied signals. After passing through a low-pass filter (LPF), the high-frequency component is removed, while the low-frequency component is retained. The resulting four signals are expressed as follows. f r×sin = -Rcos(2πf′t) (34) f r×cos =Rsin(2πf′t) (35) f m×sin = -Mcos[2π(f′+Δf)t] (36) f m×cos =Msin[2π(f′+Δf)t] (37)

[0032] The phase difference module in the method is mainly responsible for eliminating the variable f′ and calculating (f r×sin )×( f m ×sin )-(f r×cos )(f m×cos ) (38) (f r×cos )(f m×sin )-(f r×sin )(f m×cos ) (39) Two signals with equal amplitudes and containing only frequency Δf can be obtained as shown in equations (40) and (41).

[0033] The phase calculation module in this method uses the Cordic algorithm. It is primarily responsible for performing an inverse tangent operation on the above equation to obtain the phase difference φ. The expression for φ is shown in Equation (42). Trigonometric functions cannot be directly calculated in FPGAs. Storing trigonometric results in the FPGA in advance and using lookup tables to calculate trigonometric functions consumes significant resources and results in low accuracy. Currently, the CORDIC algorithm is commonly used for trigonometric calculations. The following describes the CORDIC algorithm in detail.

[0034] The CORDIC algorithm uses the concept of "pseudo-rotation" to convert complex algorithms into multiple "pseudo-rotations" to gradually approximate the output value. For example, given that x1 and y1 are on the unit circle, rotate the line (0, 0) and (x1, y1) by θ. Let the angle between (0, 0) and (x1, y1) and the positive x-axis be α, as shown in Equations (43) and (44). x2=cos(α+θ) (43) y2=sin(α+θ) (44) After expansion, the expressions are as shown in Equations (45) and (46). Since on the unit circle, x1 = sinα, y1 = cosα. x2=x1×cosθ-y1×sinθ (45) y2=x1×sinθ+y1×cosθ (46) Convert it into matrix form and extract the common factors, as shown in Equation (47). Calculating decimals in an FPGA is very complex and requires a large bit width. Furthermore, it is impossible to store the tangent values of all angles in the FPGA. Therefore, a single rotation is transformed into multiple superimposed rotations, with the tangent value of each rotation angle being a power of 2. A single decimal multiplication operation is transformed into multiple shift and addition operations, where K = cosθ0 × cosθ1… × cosθ n , d n =±1 represents the direction of rotation.

[0035] From formula (42), we can see that when calculating x2 for the first time, we need to calculate x1-d0×2 0 ×y1. There are three steps to do. First, 0 ×y1 is a simple shift operation in the FPGA. The second step determines the sign of d0 based on the relative position of the rotated angle and θ, which is a simple comparison operation in the FPGA. The final step is subtracting from x1, which is an addition operation in the FPGA. Similarly, the three-step operation of any rotation consists of simple shifts, comparisons, additions, and subtractions, making it extremely easy to implement in the FPGA. Finally, the coefficient K needs to be calculated. Given the same number of rotations, cosθ is the same for each rotation regardless of direction. Therefore, given a fixed number of rotations, the value of K is also fixed and can be extracted and stored in the FPGA.

[0036] Figure 3 The structure diagram of the dual-thread complementary algebraic derivative estimation and compensation algorithm based on FPGA of the present invention is shown in FIG. Enter the dual-threaded, complementary Data Aging Error Compensation (DAEC) module. This module is primarily responsible for determining the system's equivalent time delay, τ, before measurement. During the measurement, first-, second-, and even higher-order derivatives of the original phase are calculated in real time. Using the equivalent time delay and phase derivatives, the data aging error is calculated in real time. Finally, this error is subtracted from the original phase measurement.

[0037] Due to design and configuration reasons, signals may not travel the same length of path, such as different cables, paths on printed circuit boards, or even the length of fiber optic cables, which causes signals to experience different paths. This delay. When these signals are combined to generate values, unequal delays introduce errors. First, a delay model is established: Assuming the delay between the input signal and the corresponding output signal is τ, the actual phase φ is different from the measured phase φ with delay. d The relationship between is as follows (49). φ d (t)=φ(t-τ) (49) In order to compensate for the constant time delay, the time delay τ is obtained in advance by calibration or theoretical derivation. The module tracks the Doppler frequency f by calculating the first-order derivative of the original phase measurement in real time. D (equivalent to speed), and then the actual phase can be calculated as follows (50). φ(t)=φ d (t)-Δφ=φ d (t)+2πf D τ (50) In order to compensate for the non-constant time delay, the time delay at each Doppler frequency is measured in advance. Since the time delay varies with frequency, the error cannot be compensated as above. Usually, it will be a finite time delay τ(f D ) or phase error φ(f D ) value is stored in the lookup table LUT and is converted to the instantaneous Doppler frequency f D As the address to access the corresponding delay or phase error. Then, the actual phase can be calculated by equation (51). φ(t)=φ d (t)-φ(f D ) (51)

[0038] Figure 4 The principle diagram of the algebraic derivative estimation method of the dual-thread complementary algebraic derivative estimation compensation algorithm based on FPGA of the present invention. d The present invention uses the algebraic derivative estimation method when estimating the derivative of each order. The first-order derivative estimation diagram is as follows Figure 4As shown below. The basic principle is further explained below: The algebraic derivative estimation method uses a Taylor polynomial model to fit the signal y(t) and calculate the derivative. Its core is to use the differential properties in the complex frequency domain to obtain the first-order derivative information of the encoder signal and express the result in the real domain through the inverse Laplace transform. The signal y(t) is an arbitrary smooth curve that changes with time, t∈[0,∞). y(t) is expressed near t=0 using a truncated Taylor series expansion as shown in Equation (52). In formula (53), N is the expansion order of the angular displacement signal, which determines the signal fitting accuracy. The N+1 order derivative of formula (59) is shown in formula (53). Perform frequency domain transformation on Equation (53) and multiply both sides by s -k , and we get formula (54). The corresponding formula for different values of k contains information about the 1st to kth order derivatives of y(t). Taking k = N can obtain the first order derivative of y(t) According to the Leibniz formula, Equation () is expanded into Equation (55). The expression of Equation (55) in the time domain after inverse transformation is shown in Equation (56). When formula (56) is expanded, the term j=N+1 is the first-order derivative component Substitute the integral term with variable z1, The expression is shown in formula (57). Since t=0 is the singular point of the equation, the small time region [0, t ε ) The speed measurement results are unavailable, and this area is called the speed measurement singularity domain. ε is the singularity domain boundary. The differentials of z1 are expressed in the form of time-varying linear filters as shown in Equation (58).

[0039] Based on this, we can obtain The biggest difference between the complementary algebraic derivative estimation and the finite difference method is that it does not directly reflect the sudden change of the signal, but makes the sudden change of the signal derivative tend to be gentle. Because the complementary algebraic derivative estimation multiplies both sides of the equation by s in the frequency domain -kThis measure is equivalent to adding a k-order integration link, which makes it have the characteristics of a cascade integrator that passes low frequencies and blocks high frequencies. This characteristic makes the complementary algebraic derivative estimation speed measurement highly resistant to interference. If a fifth-order integration is used, the first and second derivatives of the original phase can be estimated as: z′1=z2-450t 4 φ(t) (61) z′2=z3+2400t 3 φ(t) (62) z′3=z4-5400t 2 φ(t) (63) z′4=z5+4320tφ(t) (64) z′5=-720φ(t) (65) In equations (59) and (60), ε is the transient time. The next step in compensating for the data aging error is to solve the error term φ d (t)τ and φ d (t)τ 2 The equivalent time delay τ and phase derivative are known. The error term can be directly solved using the following equation (66). Where n! represents the factorial of n, is the measured phase φ d The first derivative is velocity; the second derivative is acceleration.

[0040] Figure 5 The present invention is a timing diagram of a dual-thread complementary method of a dual-thread complementary algebraic derivative estimation compensation algorithm based on FPGA. Since t=0 is a singular point in the equation, the speed measurement results in the small time region [0, ε) near this point are unavailable. This region is called the singularity domain, and ε is the boundary of the singularity domain. The dual-thread complementary method is adopted to improve the algorithm: two complementary algebraic derivative estimation threads are performed simultaneously, and the initialization time of the two threads is half a cycle T / 2 apart, that is, the first thread is initialized at the full cycle T, and the second thread is initialized at an odd multiple of the half cycle T / 2. When the first thread is initialized, it switches to the second thread to output the result, and vice versa. The expression of the dual-thread complementary method is shown in the following equation (68). In formula (67): n = 0, 1….

Claims

1. A dual-threaded complementary algebraic derivative estimation and compensation algorithm based on FPGA. Phase calculation module 1, instantaneous phase derivative module 2, dual-threaded complementary algebraic derivative estimation module 3, Δφ storage module 4, complementary algorithm module 5, and final phase φ(t) output module 6. Each module is connected via a 32-bit phase data bus in the following order: the data input of the instantaneous phase derivative module 2 is connected to the output of the phase calculation module 1, the output of the instantaneous phase derivative module 2 is connected to the data input of the dual-threaded complementary algebraic derivative estimation module 3, the complementary algorithm module 5 is connected to the output of the Δφ storage module 4, and the data input of the final phase φ(t) output module 6 is connected to the data output of the complementary algorithm module 5.

2. The FPGA-based dual-threaded complementary algebraic derivative estimation and compensation algorithm according to claim 1 is characterized in that The instantaneous phase derivative module 2 includes a five-stage cascade integrator, a coefficient multiplier, and an adder. The five-stage cascade integrator chain has an output connected to a variable coefficient multiplier (numbered 2-6) and an input connected to the original phase φ. d The data bus output is connected to the A input port of adder 1 through integrator 1. The coefficient ports of variable-coefficient multipliers (2-6) are connected to preset register banks, and their outputs are connected in sequence to the B input ports of adders (1-5). The second-order derivative calculation channel reuses the hardware resources of integrators (1-5), and its data path is switched via a multiplexer. The variable t in the delay unit is generated by an internal counter.

3. The FPGA-based dual-threaded complementary algebraic derivative estimation and compensation algorithm according to claim 1 is characterized in that The dual-threaded complementary algebraic derivative estimation module 3, which simultaneously performs two complementary algebraic derivative estimation threads, includes a register bank, a clock counter, and a 2:1 data selector. Register banks (1-2) are initialized by the full cycle T and half cycle T / 2 of the clock counter, respectively. The 2:1 data selector has a selection logic that outputs register 1 data when the counter value mod T = 0 and register 2 data when the counter value mod T = T / 2. Initialization occurs at intervals of T / 2 ± 1 clock cycle.

4. The FPGA-based dual-threaded complementary algebraic derivative estimation and compensation algorithm according to claim 1 is characterized in that the complementary algorithm module 5 compensates for non-constant time delays, LUT1 and LUT2 store first-order and second-order error data, and the address bus is generated by the derivative information [11:0] bit mapping. The constant delay compensation LUT3: stores the delay τ parameter table, and the address bus is generated by the Doppler frequency f D The 8-bit quantized value (equivalent to speed) is generated; the phase calculation unit performs φ(t)=φ d (t)-φ(f D ) operation, the data path is configured with an 18-bit fixed-point arithmetic unit; Doppler tracking channel, the input end is connected to the first-order derivative data bus, and the output end updates the LUT3 address.

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