Electrical circuit fault feature extraction method and device, equipment and storage medium

Abstract

The invention relates to an electrical circuit fault feature extraction method and device, equipment and a storage medium. The method comprises the steps of obtaining a fault current signal of a load electrical circuit in a to-be-detected power grid range, and performing rapid feature extraction according to the fault current signal of the load electrical circuit to obtain physical features of the load electrical circuit; and performing depth feature extraction according to the fault current signal of the load electrical circuit to obtain depth features of the load electrical circuit, performing fusion processing on the physical features of the load electrical circuit and the corresponding depth features by using a feature fusion model, and determining a fault feature set of the load electrical circuit. By adopting the method, the physical characteristics of the load electrical circuit and the depth characteristics of the load electrical circuit in the to-be-detected power grid range can be respectively acquired, and the physical characteristics of the load electrical circuit and the corresponding depth characteristics are fused, so that the finally acquired fault characteristics of the load electrical circuit are more comprehensive.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a method, device, equipment and storage medium for extracting fault characteristics of an electrical circuit. Background Art

[0002] With the development of power grid technology, the scale of electrical lines is increasing. To ensure the safe operation of electrical lines, it is necessary to promptly identify faults that occur in electrical lines. The primary step in electrical line fault identification is electrical line feature extraction. Therefore, electrical line fault feature extraction becomes particularly important in the electrical line fault identification process.

[0003] In related technologies, time domain, frequency domain or time-frequency domain feature extraction methods are mainly used to extract fault features of electrical lines.

[0004] However, in the related art, during the process of extracting fault features of electrical circuits, there is a problem that the extracted fault features are incomplete. Summary of the Invention

[0005] Based on this, it is necessary to provide an electrical circuit fault feature extraction method, device, equipment and storage medium that can extract more comprehensive electrical circuit fault features to address the above technical problems.

[0006] In a first aspect, the present application provides a method for extracting electrical line fault features, comprising:

[0007] Obtaining fault current signals of load electrical lines within the range of the power grid to be tested;

[0008] Performing rapid feature extraction based on the fault current signal of the load electrical circuit to obtain physical features of the load electrical circuit; and performing deep feature extraction based on the fault current signal of the load electrical circuit to obtain deep features of the load electrical circuit;

[0009] The feature fusion model is used to fuse the physical features and corresponding deep features of the load electrical circuit to determine the fault feature set of the load electrical circuit; the feature fusion model is a network model built based on the attention mechanism.

[0010] In one embodiment, obtaining a fault current signal of a load electrical line within a power grid to be tested includes:

[0011] Obtaining current signals of load electrical circuits within the range of the power grid to be tested;

[0012] A fault current signal of the load electrical circuit is screened out from the current signal of the load electrical circuit.

[0013] In one embodiment, a rapid feature extraction is performed based on a fault current signal of a load electrical circuit to obtain physical features of the load electrical circuit, including:

[0014] De-noising the fault current signal of the load electrical circuit to obtain a de-noised current signal;

[0015] Extracting time domain features based on the denoised current signal to obtain time domain features of the load electrical circuit; and extracting frequency domain features based on the denoised current signal to obtain frequency domain features of the load electrical circuit; and extracting time and frequency domain features based on the denoised current signal to obtain time and frequency domain features of the load electrical circuit; wherein the time domain features include at least one of a current peak-to-peak value, a current average value, a kurtosis factor peak factor, and a current effective value; the frequency domain features include at least one of a kth harmonic amplitude and a kth harmonic factor, a total harmonic distortion rate, a spectrum mean, and a spectrum standard deviation; and the time and frequency domain features include at least one of a detail coefficient mean value and a detail coefficient variance of a multi-layer wavelet transform;

[0016] The physical characteristics of the load electrical circuit are determined according to the time domain characteristics, the corresponding frequency domain characteristics and the corresponding time-frequency domain characteristics of the load electrical circuit.

[0017] In one embodiment, performing deep feature extraction based on a fault current signal of a load electrical circuit to obtain deep features of the load electrical circuit includes:

[0018] Performing time-frequency conversion on the fault current signal of the load electrical circuit to obtain corresponding time-frequency image information;

[0019] Preprocessing the time-frequency image information to obtain preprocessed image information;

[0020] The feature extraction network model is used to perform deep feature extraction on the preprocessed image information to obtain the deep features of the load electrical circuit.

[0021] In one embodiment, preprocessing the time-frequency image information to obtain preprocessed image information includes:

[0022] Performing cropping processing on the time-frequency image information to obtain cropped image information;

[0023] Normalizing the cropped image information to obtain normalized image information;

[0024] The normalized image information is subjected to information enhancement processing to obtain preprocessed image information.

[0025] In one embodiment, the feature extraction network model includes an initial convolution layer and an inverted residual module, the inverted residual module includes a channel-by-channel convolution layer, an extended point-by-point convolution layer, and an output convolution layer using a linear activation function; using the feature extraction network model, deep feature extraction is performed on the preprocessed image information to obtain deep features of the load electrical circuit, including:

[0026] The preprocessed image information is input into the initial convolution layer, and features are extracted from the preprocessed image information to obtain preliminary features of the load electrical circuit;

[0027] The preliminary features are input into the channel-by-channel convolution layer, and the preliminary features are convolved to obtain the local features of the load electrical circuit;

[0028] The local features are input into the extended point-by-point convolution layer, and the inter-channel feature fusion processing is performed on the local features to obtain the fusion features of the load electrical circuit;

[0029] The fused features are input into the output convolution layer, and the fused features are optimized to obtain the deep features of the load electrical circuit.

[0030] In one embodiment, the feature fusion model includes an attention mechanism module, a global average pooling layer, and a fully connected layer. The feature fusion model is used to fuse the physical features of the load electrical circuit and the corresponding deep features to determine a fault feature set of the load electrical circuit, including:

[0031] Using the attention mechanism module, the physical features of the load electrical circuit and the corresponding deep features are weightedly fused to obtain the weighted fusion features of the load electrical circuit;

[0032] The weighted fusion features are input into the global average pooling layer for global feature extraction to obtain the global features of the load electrical circuit;

[0033] Input the global features into the fully connected layer to determine the channel attention weight corresponding to the feature fusion model;

[0034] According to the channel attention weights, the weighted fusion features are recalibrated to obtain the fault feature set of the load electrical circuit.

[0035] In a second aspect, the present application further provides an electrical line fault feature extraction device, comprising:

[0036] An acquisition module is used to acquire a fault current signal of a load electrical circuit within the range of the power grid to be tested;

[0037] A feature extraction module is used to perform rapid feature extraction based on the fault current signal of the load electrical circuit to obtain physical features of the load electrical circuit; and perform deep feature extraction based on the fault current signal of the load electrical circuit to obtain deep features of the load electrical circuit;

[0038] The feature fusion module is used to use the feature fusion model to fuse the physical features of the load electrical circuit and the corresponding deep features to determine the fault feature set of the load electrical circuit; the feature fusion model is a network model built based on the attention mechanism.

[0039] In a third aspect, the present application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method of any embodiment of the first aspect when executing the computer program.

[0040] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method of any one of the embodiments of the first aspect above.

[0041] In a fifth aspect, the present application further provides a computer program product, comprising a computer program, which, when executed by a processor, implements the steps of the method of any one of the embodiments of the first aspect above.

[0042] The above-mentioned electrical line fault feature extraction method, apparatus, device, and storage medium include: obtaining a fault current signal of a load electrical line within the scope of a power grid to be tested, performing rapid feature extraction based on the fault current signal of the load electrical line to obtain physical features of the load electrical line, and performing deep feature extraction based on the fault current signal of the load electrical line to obtain deep features of the load electrical line, and using a feature fusion model to fuse the physical features and corresponding deep features of the load electrical line to determine a fault feature set of the load electrical line, wherein the feature fusion model is a network model constructed based on an attention mechanism. Using the above-mentioned method, the physical features and deep features of the load electrical line within the scope of the power grid to be tested can be obtained respectively, and the physical features and corresponding deep features of the load electrical line can be fused to make the ultimately obtained fault features of the load electrical line more comprehensive. At the same time, the above-mentioned method fuses the physical features and corresponding deep features of the load electrical line based on the feature fusion model constructed based on the attention mechanism, which can improve the accuracy of the feature fusion results. In addition, the above-mentioned method is not limited to the complexity of the applicable scenarios, thereby improving the practicality and wide applicability of the electrical line fault feature extraction method. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments of the present application or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 Schematic diagram of an application environment of a method for extracting electrical circuit fault features in one embodiment;

[0045] Figure 2 1 is a flow chart of a method for extracting electrical circuit fault features in one embodiment;

[0046] Figure 3 is a flow chart of a method for extracting electrical circuit fault features in another embodiment;

[0047] Figure 4 is a flow chart of a method for extracting electrical circuit fault features in another embodiment;

[0048] Figure 5 is a flow chart of a method for extracting electrical circuit fault features in another embodiment;

[0049] Figure 6 is a flow chart of a method for extracting electrical circuit fault features in another embodiment;

[0050] Figure 7 is a flow chart of a method for extracting electrical circuit fault features in another embodiment;

[0051] Figure 8 is a flow chart of a method for extracting electrical circuit fault features in another embodiment;

[0052] Figure 9 is a flow chart of a method for extracting electrical circuit fault features in another embodiment;

[0053] Figure 10 is a structural block diagram of an electrical circuit fault feature extraction device in one embodiment;

[0054] Figure 11 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0056] The electrical circuit fault feature extraction method provided in the embodiment of the present application can be applied to Figure 1 In the application environment shown, the application environment includes a power grid system, a waveform signal acquisition device and a computer device. The computer device communicates with the waveform signal acquisition device through a network, and the communication method can be Wi-Fi, mobile network or Bluetooth connection, etc. Optionally, the power grid system may include a plurality of different loads and electrical circuits connected to each load; the above-mentioned electrical circuits may be AC or DC electrical circuits. In the embodiment of the present application, the above-mentioned electrical circuits may be low-voltage electrical circuits. The computer device may be, but is not limited to, various personal computers, laptops, smart phones, tablet computers and Internet of Things devices. The Internet of Things devices may be smart speakers, smart TVs, smart air conditioners, smart car devices, projection equipment, etc.

[0057] In an exemplary embodiment, Figure 2 As shown in the figure, a method for extracting fault characteristics of electrical circuits is provided. Figure 1 The computer device in the example is used for illustration. The method includes the following steps:

[0058] S100: Acquire a fault current signal of a load electrical circuit within the range of the power grid to be tested.

[0059] It should be noted that load electrical lines within the test grid range may cause line faults due to factors such as broken wires and loose terminals, thereby generating line fault problems. Correspondingly, the waveform signal acquisition device in the electrical line fault feature extraction system can collect fault current signals of load electrical lines within the test grid range of the power grid system. In the embodiments of the present application, the line fault problem is described as a series arc fault.

[0060] In practical applications, the waveform signal acquisition device can acquire fault current signals of load electrical circuits within the range of the power grid to be tested in the power grid system. The load electrical circuits may include electrical circuits of various loads within the range of the power grid to be tested.

[0061] The computer device may obtain pre-stored fault current signals of load electrical lines within the power grid to be tested from local locations, disks, hard disks, the cloud, and other locations.

[0062] In an embodiment of the present application, the computer device can receive in real time the fault current signal of the load electrical line within the power grid to be tested, which is sent by the waveform signal acquisition device.

[0063] S200, performing rapid feature extraction based on the fault current signal of the load electrical circuit to obtain physical features of the load electrical circuit; and performing deep feature extraction based on the fault current signal of the load electrical circuit to obtain deep features of the load electrical circuit.

[0064] It should be noted that when the load electrical circuit includes multiple electrical circuits with different loads, rapid feature extraction can be performed based on the fault current signals of the electrical circuits of each load, and deep feature extraction can be performed based on the fault current signals of the electrical circuits of each load. In the embodiment of the present application, an example is used in which the load electrical circuit includes an electrical circuit with one load.

[0065] Specifically, the computer device can use a fast feature extraction algorithm to quickly extract features from the fault current signal of the load electrical circuit to obtain the physical characteristics of the load electrical circuit; alternatively, the computer device can pre-train a fast feature extraction model and then input the fault current signal of the load electrical circuit into the fast feature extraction model, which then outputs the physical characteristics of the load electrical circuit. Optionally, the fast feature extraction algorithm can include, but is not limited to, principal component analysis, fast Fourier transform, or wavelet transform. Furthermore, the fast feature extraction model can be implemented using at least one of a convolutional neural network model, a fully connected neural network model, a long short-term memory neural network model, a residual neural network model, and the like.

[0066] At the same time, the computer device can use a deep feature extraction algorithm to perform deep feature extraction on the fault current signal of the load electrical circuit to obtain deep features of the load electrical circuit. Optionally, the deep feature extraction algorithm can be an extraction algorithm based on a deep learning model, an autoencoder, etc., which is not limited to this embodiment of the present application.

[0067] S300: Using a feature fusion model, the physical features of the load electrical circuit and the corresponding deep features are fused to determine a fault feature set of the load electrical circuit. The feature fusion model is a network model built based on an attention mechanism.

[0068] In practical applications, the feature fusion model can be implemented by at least one of a convolutional neural network model, a long short-term memory neural network model, a residual neural network model, a recurrent neural network model, a fully connected neural network model, etc. In an embodiment of the present application, the feature fusion model is a network model constructed based on the attention mechanism.

[0069] Specifically, the computer device can input the physical features and corresponding depth features of the load electrical circuit into the feature fusion model to fuse the physical features and corresponding depth features of the load electrical circuit, and then the feature fusion model outputs a fault feature set of the load electrical circuit.

[0070] The technical solution in the embodiment of the present application obtains the fault current signal of the load electrical circuit within the range of the power grid to be tested, performs rapid feature extraction based on the fault current signal of the load electrical circuit to obtain the physical characteristics of the load electrical circuit, and performs deep feature extraction based on the fault current signal of the load electrical circuit to obtain the deep characteristics of the load electrical circuit, and uses a feature fusion model to fuse the physical characteristics and corresponding deep characteristics of the load electrical circuit to determine the fault feature set of the load electrical circuit, wherein the feature fusion model is a network model constructed based on the attention mechanism; the above method can respectively obtain the physical characteristics and deep characteristics of the load electrical circuit within the range of the power grid to be tested, and fuse the physical characteristics and corresponding deep characteristics of the load electrical circuit, so that the fault characteristics of the load electrical circuit finally obtained are more comprehensive; at the same time, the above method fuses the physical characteristics and corresponding deep characteristics of the load electrical circuit based on the feature fusion model constructed based on the attention mechanism, which can improve the accuracy of the feature fusion result; in addition, the above method has no limitation on the complexity of the applicable scenario, thereby improving the practicality and wide applicability of the electrical circuit fault feature extraction method.

[0071] The following describes the process of obtaining the fault current signal of the load electrical circuit within the range of the power grid to be tested. Figure 3 As shown, the steps in S100 above can be implemented in the following ways:

[0072] S110: Acquire current signals of load electrical circuits within the range of the power grid to be measured.

[0073] In practical applications, waveform signal acquisition equipment can continuously and in real time acquire current signals of load electrical lines within the power grid to be tested.

[0074] S120: Filter out a fault current signal of the load electrical circuit from the current signal of the load electrical circuit.

[0075] The current signal of the load electrical circuit may include a normal current signal collected when the load electrical circuit is normal and a fault current signal collected when the load electrical circuit is faulty.

[0076] In the embodiment of the present application, taking the fault line problem of the load electrical circuit as an example, Figure 4 The figure shows the current signals of the load electrical circuit within the test power grid, collected by the waveform signal acquisition device over a period of time. The dotted line in the waveform signal indicates the time when the series fault arc begins. The waveform signal before the arc starts is the normal current signal within the load electrical circuit current signal. The waveform signal after the arc starts is the fault current signal within the load electrical circuit current signal.

[0077] Specifically, the computer device may perform abnormality detection on the current signal of the load electrical circuit to filter out the fault current signal of the load electrical circuit from the current signal of the load electrical circuit.

[0078] In addition, the computer device can also pre-train a fault signal screening algorithm, and then input the current signal of the load electrical circuit into the fault signal selection algorithm, which filters out the fault current signal of the load electrical circuit from the current signal of the load electrical circuit.

[0079] The technical solution in the embodiment of the present application obtains the current signal of the load electrical circuit within the range of the power grid to be tested, and filters out the fault current signal of the load electrical circuit from the current signal of the load electrical circuit; the above method can filter out the fault current signal of the load electrical circuit from the current signal of the load electrical circuit, so as to reduce the amount of data processed in the subsequent fault feature extraction process, reduce the complexity of the fault feature extraction, and improve the accuracy of the fault feature extraction.

[0080] The following describes the process of obtaining the physical characteristics of the load electrical circuit by performing rapid feature extraction based on the fault current signal of the load electrical circuit. Figure 5 As shown, the step of performing rapid feature extraction based on the fault current signal of the load electrical circuit to obtain the physical characteristics of the load electrical circuit in the above S200 can be implemented in the following manner:

[0081] S210 , performing denoising processing on the fault current signal of the load electrical circuit to obtain a denoised current signal.

[0082] The computer device may employ a denoising algorithm to denoise the fault current signal of the load electrical circuit to obtain a denoised current signal. Optionally, the denoising algorithm may be an empirical mode decomposition method, a denoising algorithm based on a convolutional neural network, or the like.

[0083] In an embodiment of the present application, the computer device may employ a filtering algorithm to filter the fault current signal of the load electrical circuit to perform denoising on the fault current signal of the load electrical circuit to obtain a denoised current signal. Optionally, the filtering algorithm may be a wavelet transform filtering method, a moving average filtering method, a clipping filtering method, an arithmetic average filtering method, a recursive average filtering method, or the like.

[0084] S220. Extract time domain features based on the denoised current signal to obtain time domain features of the load electrical circuit; and extract frequency domain features based on the denoised current signal to obtain frequency domain features of the load electrical circuit; and extract time and frequency domain features based on the denoised current signal to obtain time and frequency domain features of the load electrical circuit. The time domain features include at least one of current peak-to-peak value, current average value, kurtosis factor peak factor, and current effective value; the frequency domain features include at least one of kth harmonic amplitude and kth harmonic factor, total harmonic distortion, spectrum mean, and spectrum standard deviation; and the time and frequency domain features include at least one of detail coefficient mean and detail coefficient variance of multi-layer wavelet transform.

[0085] Among them, the computer device can pre-train a time domain feature extraction algorithm, input the denoised current signal into the time domain feature extraction algorithm, and the time domain feature extraction algorithm extracts the time domain features of the denoised current signal and outputs the time domain features of the load electrical circuit.

[0086] In the embodiment of the present application, the time domain features include at least one of the current peak-to-peak value, the current average value, the kurtosis factor peak factor, and the current effective value; the acquisition process of each feature in the time domain features can be described as follows:

[0087] (1) Peak-to-peak current of the load electrical circuit

[0088] The computer device can obtain the maximum positive peak value and the minimum negative peak value in the current signal after noise removal, and then calculate the maximum positive peak value in the current signal after noise removal. With minimum negative peak The peak-to-peak value of the current in the load electrical circuit is obtained by subtracting the peak-to-peak value of the current in the load electrical circuit. It can be expressed by formula (1):

[0089] (1)

[0090] The peak-to-peak value of the current reflects the current fluctuation amplitude of the load electrical circuit. The larger the peak-to-peak value of the current, the more intense the arc discharge generated by the load electrical circuit and the higher the current fluctuation amplitude.

[0091] (2) Average current of the load electrical circuit

[0092] The computer equipment can calculate the average amplitude of the current signal after noise removal to obtain the average current value of the load electrical circuit; the peak-to-peak current value of the load electrical circuit It can be expressed by formula (2):

[0093] (2)

[0094] Where N represents the number of sampling points corresponding to the fault current signal of the load electrical circuit, Indicates the amplitude corresponding to each sampling point in the fault current signal in the denoised current signal. In the embodiment of the present application, the average current value of the load electrical circuit can be understood as the overall current level of the load electrical circuit during the arc discharge process.

[0095] (3) Kurtosis factor of the loaded electrical circuit

[0096] The computer device can obtain the kurtosis value and the root mean square value of the de-noised current signal, and calculate the kurtosis of the de-noised current signal and the fourth power of the root mean square value of the de-noised current signal to obtain the kurtosis factor of the load electrical circuit; the kurtosis factor of the load electrical circuit It can be expressed by formula (3):

[0097] (3)

[0098] in, represents the kurtosis of the denoised current signal (i.e., the normalized fourth-order central moment of the denoised current signal), It represents the RMS value of the current signal after noise removal (i.e. the effective value of the current in the load electrical circuit).

[0099] In the embodiment of the present application, the kurtosis factor of the load electrical circuit can be understood as the flatness of the fault current signal of the load electrical circuit; the larger the kurtosis factor of the load electrical circuit, the more transient mutations or glitches there are in the fault current signal of the load electrical circuit; the smaller the kurtosis factor of the load electrical circuit, the flatter the distribution of the fault current signal of the load electrical circuit, similar to the Gaussian distribution, indicating that the fault current signal is more stable.

[0100] (4) Peak factor of the loaded electrical circuit

[0101] The computer device can obtain the peak value and the corresponding RMS value of the de-noised current signal, and then divide the peak value of the de-noised current signal by the RMS value of the de-noised current signal to obtain the peak factor of the load electrical circuit; the peak factor of the load electrical circuit It can be expressed by formula (4):

[0102] (4)

[0103] in, Represents the peak value (i.e., the maximum positive peak value) of the current signal after denoising. In the embodiments of the present application, the crest factor of the load electrical circuit is used as an indicator to measure the degree of distortion of the fault current signal. It can reflect the nonlinearity of the arc current in the fault current signal and the presence of spike components in the fault current signal.

[0104] At the same time, the computer device can pre-train a frequency domain feature extraction algorithm, input the denoised current signal into the frequency domain feature extraction algorithm, and the frequency domain feature extraction algorithm performs time domain feature extraction on the denoised current signal and outputs the frequency domain features of the load electrical circuit. In an embodiment of the present application, the frequency domain features include at least one of the kth harmonic amplitude and the kth harmonic factor, the total harmonic distortion rate, the spectrum mean, and the spectrum standard deviation; the kth harmonic amplitude can include the fifth harmonic amplitude, the seventh harmonic amplitude, and the ninth harmonic amplitude, and correspondingly, the kth harmonic factor can include the fifth harmonic factor, the seventh harmonic factor, and the ninth harmonic factor. Among them, the acquisition process of each feature in the frequency domain feature can be described as:

[0105] (1) kth harmonic amplitude of the load electrical circuit

[0106] Computer equipment can use the fast Fourier transform method to first perform time-frequency conversion on the de-noised current signal of the load electrical circuit to obtain the corresponding frequency domain signal (Right now ); frequency domain signal It can be expressed by the following formula (5):

[0107] (5)

[0108] in, Indicates the sequence number corresponding to each sampling point i in the frequency domain;

[0109] Furthermore, the computer device can take the absolute value of the frequency domain signal to obtain the amplitude of the kth harmonic component , that is, the kth harmonic amplitude of the load electrical circuit, can be expressed by formula (6):

[0110] (6)

[0111] Where k represents the harmonic order.

[0112] (2) kth harmonic factor of the load electrical circuit

[0113] The computer equipment can derive the kth harmonic amplitude of the load electrical circuit from the fundamental amplitude of the load electrical circuit to obtain the kth harmonic factor of the load electrical circuit; the kth harmonic factor of the load electrical circuit It can be expressed by the following formula (7):

[0114] (7)

[0115] in, Indicates the fundamental amplitude of the loaded electrical circuit.

[0116] (3) Total harmonic distortion rate of the load electrical circuit

[0117] The computer device can determine the total harmonic distortion rate of the load electrical circuit based on the fundamental amplitude of the load electrical circuit and the kth harmonic amplitude of the load electrical circuit obtained above; the total harmonic distortion rate of the load electrical circuit It can be expressed by the following formula (8):

[0118] (8)

[0119] Among them, the total harmonic distortion rate of the load electrical circuit is an indicator used to measure the total distortion degree of the harmonic components in the fault circuit signal relative to the fundamental component, which can reflect the relative strength of the non-fundamental components in the fault circuit signal.

[0120] (4) Spectral mean of the loaded electrical circuit

[0121] The computer device can perform spectrum analysis on the de-noised current signal of the load electrical circuit to obtain N spectrum components, and obtain the amplitude of each spectrum component, and then average the amplitude of each spectrum component to obtain the spectrum mean of the load electrical circuit; the spectrum mean of the load electrical circuit It can be expressed by the following formula (9):

[0122] (9)

[0123] in, It represents the number of spectrum data points obtained by fast Fourier transform of the denoised current signal. Indicates the The amplitude of a spectral component.

[0124] (5) Spectral standard deviation of the loaded electrical circuit

[0125] The computer equipment can calculate the square of the difference between the amplitude of each spectrum component and the spectrum mean and then open it to obtain the spectrum standard deviation of the load electrical circuit; the spectrum standard deviation of the load electrical circuit It can be expressed by the following formula (10):

[0126] (10)

[0127] In addition, the computer device can pre-train a time-frequency domain feature extraction algorithm, input the denoised current signal into the time-frequency domain feature extraction algorithm, and the time-frequency domain feature extraction algorithm extracts the time-frequency domain features of the denoised current signal and outputs the time-frequency domain features of the load electrical circuit.

[0128] In the embodiment of the present application, the time-frequency domain features include at least one of the detail coefficient mean and detail coefficient variance of the multi-layer wavelet transform. Optionally, the multi-layer wavelet transform can be a two-layer wavelet transform, a six-layer wavelet transform, etc. In the embodiment of the present application, the multi-layer wavelet transform is a four-layer wavelet transform as an example for explanation. The process of obtaining each feature in the time-frequency domain features can be described as follows:

[0129] Specifically, the computer device can use the adaptive wavelet transform strategy to perform discrete wavelet transform processing on the denoised current signal of the load electrical circuit to obtain a corresponding discrete wavelet transform signal. In the embodiment of the present application, the computer device can use the wavelet basis to perform discrete wavelet transform processing on the denoised current signal of the load electrical circuit to obtain a corresponding discrete wavelet transform signal; the discrete wavelet transform signal It can be expressed by the following formula (11):

[0130] (11)

[0131] in, represents the wavelet basis, Respectively expressed in wavelet basis Lower fault current signal In scale and location The transformation coefficient ( Used to control the scaling of wavelet transform, Used to control the position of wavelet transform on the time axis), represents the conjugate complex number of the wavelet basis; optionally, the wavelet basis can be a db wavelet, such as db4, db2, db6, db8, etc., and can also be a Haar wavelet, Morlet wavelet, etc., which is not limited in this embodiment of the present application.

[0132] It should be noted here that after performing discrete wavelet transform on the denoised current signal of the load electrical circuit, the approximation coefficient A1 and the detail coefficient D1 of the first layer can be obtained. Furthermore, the approximation coefficient A1 of the first layer can be discrete wavelet transformed to obtain the approximation coefficient A2 of the second layer and the detail coefficient D2 of the second layer. And so on, the approximation coefficient of the previous layer can be continuously discrete wavelet transformed to obtain the approximation coefficient of the next layer and the detail coefficient of the next layer.

[0133] In practical applications, based on the previous steps, the detail coefficient D4 of the four-layer wavelet transform can be obtained, and then the detail coefficient D4 can be averaged to obtain the average value of the detail coefficient of the four-layer wavelet transform, and the variance of the detail coefficient D4 can be calculated to obtain the variance of the detail coefficient of the four-layer wavelet transform.

[0134] S230 : Determine the physical characteristics of the load electrical circuit according to the time domain characteristics, the corresponding frequency domain characteristics, and the corresponding time-frequency domain characteristics of the load electrical circuit.

[0135] In the embodiment of the present application, the time domain characteristics, the corresponding frequency domain characteristics, and the corresponding time-frequency domain characteristics of the load electrical circuit may be determined as the physical characteristics of the load electrical circuit.

[0136] The technical solution in the embodiment of the present application can obtain the time domain characteristics, corresponding frequency domain characteristics and corresponding time-frequency domain characteristics of the load electrical circuit, and determine the physical characteristics of the load electrical circuit based on the time domain characteristics, corresponding frequency domain characteristics and corresponding time-frequency domain characteristics of the load electrical circuit, so that the physical characteristics of the load electrical circuit finally obtained are more comprehensive. At the same time, the method does not need to apply a network model to realize physical feature extraction, thereby reducing the amount of calculation in the physical feature extraction process and speeding up the efficiency of physical feature extraction.

[0137] The following describes the process of extracting the depth feature of the load electrical circuit based on the fault current signal of the load electrical circuit to obtain the depth feature of the load electrical circuit. Figure 6 As shown, the step of performing deep feature extraction based on the fault current signal of the load electrical circuit to obtain the deep features of the load electrical circuit in the above S200 may include:

[0138] S240 : Perform time-frequency conversion on the fault current signal of the load electrical circuit to obtain corresponding time-frequency image information.

[0139] Among them, the computer device can pre-train a time-frequency conversion algorithm, input the fault current signal of the load electrical line into the time-frequency conversion algorithm, and the time-frequency conversion algorithm performs time-frequency conversion on the fault current signal of the load electrical line and outputs corresponding time-frequency image information.

[0140] In an embodiment of the present application, the computer device may perform wavelet transform on the fault current signal of the load electrical line to complete the time-frequency conversion of the fault current signal to obtain corresponding time-frequency image information.

[0141] S250: Preprocess the time-frequency image information to obtain preprocessed image information.

[0142] Specifically, the computer device may perform denoising, grayscale processing, standardization, etc. on the time-frequency image information to complete preprocessing of the time-frequency image information to obtain preprocessed image information.

[0143] In one embodiment, if Figure 7 As shown, the steps in the above S250 may include:

[0144] S251 : Perform cropping processing on the time-frequency image information to obtain cropped image information.

[0145] In practical applications, the computer device can crop the time-frequency image information into cropped image information of a size equal to the image information that can be processed by the feature extraction network model to meet the input requirements of the feature extraction network model.

[0146] S252: Perform normalization processing on the cropped image information to obtain normalized image information.

[0147] It should be noted here that the cropped image information may include the pixel value of each pixel in the cropped image.

[0148] In an embodiment of the present application, the computer device may normalize the pixel value of each pixel in the cropped image information to obtain the normalized pixel value of each pixel. The normalization method for the pixel value of any pixel can be expressed by the following formula (12):

[0149] (12)

[0150] in, Represents the pixel value of any pixel point, Indicates the pixel value corresponding to the pixel point.

[0151] S253: Perform information enhancement processing on the normalized image information to obtain pre-processed image information.

[0152] Specifically, the computer device may perform information enhancement on the normalized image information to obtain pre-processed image information. Optionally, the information enhancement may include at least one of geometric transformation, color transformation, cropping, noise addition, random rotation, scaling, and the like.

[0153] S260: Using a feature extraction network model, perform deep feature extraction on the preprocessed image information to obtain deep features of the load electrical circuit.

[0154] Furthermore, the computer device can input the preprocessed image information into a feature extraction network model, and the feature extraction network model performs deep feature extraction on the preprocessed image information and outputs the deep features of the load electrical circuit.

[0155] The technical solution in the embodiment of the present application performs time-frequency conversion on the fault current signal of the load electrical circuit to obtain corresponding time-frequency image information, preprocesses the time-frequency image information to obtain preprocessed image information, and uses a feature extraction network model to perform deep feature extraction on the preprocessed image information to obtain deep features of the load electrical circuit; the above method performs preprocessing before performing deep feature extraction, thereby improving the accuracy of the deep features of the load electrical circuit finally obtained, and the deep feature extraction is implemented using the feature extraction network model, which can also speed up the speed and efficiency of deep feature extraction.

[0156] In one embodiment, the feature extraction network model includes an initial convolution layer and an inverted residual module, and the inverted residual module includes a channel-by-channel convolution layer, an expanded point-by-point convolution layer, and an output convolution layer using a linear activation function; Figure 8 As shown, the step of performing deep feature extraction on the pre-processed image information using the feature extraction network model to obtain deep features of the load electrical circuit in S260 may include:

[0157] S261. Input the preprocessed image information into the initial convolution layer, perform feature extraction on the preprocessed image information, and obtain preliminary features of the load electrical circuit.

[0158] In an embodiment of the present application, the feature extraction network model can be represented as a lightweight convolutional neural network model. The lightweight convolutional neural network model can be a MobileNetV architecture, such as MobileNetV1, MobileNetV3, MobileNetV5, etc. In an embodiment of the present application, the MobileNetV architecture is MobileNetV2 as an example. The initial convolutional layer can include multiple convolutional layers.

[0159] Specifically, the computer device can input the preprocessed image information into the initial convolutional layer, which extracts low-level and high-level features from the enhanced image information to obtain preliminary features of the load electrical circuit, namely the feature map. It should be noted that low-level features can represent the local spatial structure and can identify edges, amplitude mutations, and local pattern changes in the fault current signal; high-level features can represent the category information of highly generalized features, demonstrating stronger discrimination and generalization performance.

[0160] In the embodiment of the present application, the process of extracting preliminary features by the initial convolutional layer can be expressed by the following formula (13):

[0161] (13)

[0162] in, Represents the preliminary features of the load electrical circuit. The above initial convolution layer uses a 3x3 convolution kernel. represents the feature extraction convolution kernel, represents the feature extraction bias, Represents the image information after preprocessing, Represents convolution processing.

[0163] S262. Input the preliminary features into a channel-by-channel convolution layer, perform convolution processing on the preliminary features, and obtain local features of the load electrical circuit.

[0164] In practical applications, the initial convolution layer is followed by a channel-by-channel convolution layer. Specifically, the computer device may input preliminary features into the channel-by-channel convolution layer to perform convolution processing (i.e., channel-by-channel convolution processing or refinement processing) on the preliminary features to obtain local features of the load electrical circuit, i.e., a feature map. In the embodiment of the present application, the process of performing convolution processing by the channel-by-channel convolution layer can be expressed by the following formula (14):

[0165] (14)

[0166] in, Represents the local characteristics of the load electrical circuit, represents channel-wise convolution, represents the channel-by-channel convolution kernel, Represents the channel-by-channel convolution bias.

[0167] S263. Input the local features into the extended point-by-point convolution layer, perform inter-channel feature fusion processing on the local features, and obtain the fusion features of the load electrical circuit.

[0168] At the same time, the extended point-by-point convolution layer is connected after the channel-by-channel convolution layer. The computer device can input local features into the extended point-by-point convolution layer, perform inter-channel feature fusion processing on the local features, and obtain fusion features of the load electrical circuit, i.e., a feature map. The feature extraction network model performing point-by-point convolution processing can greatly reduce the computational complexity and number of parameters of the feature extraction network model. In this embodiment of the present application, the process of performing inter-channel feature fusion processing on the extended point-by-point convolution layer can be expressed by the following formula (15):

[0169] (15)

[0170] in, Indicates the integration characteristics of the load electrical circuit, represents the extended point-wise convolution, represents the extended point-wise convolution kernel, Represents the dilated point-wise convolution bias.

[0171] S264: Input the fused features into the output convolution layer, optimize the fused features, and obtain the deep features of the load electrical circuit.

[0172] In the embodiment of the present application, the output convolution layer can be understood as a linear bottleneck layer. The computer device can input the fused features into the output convolution layer, optimize the fused features to avoid nonlinear loss, and obtain the deep features of the load electrical circuit, i.e., the feature map. In the embodiment of the present application, the process of performing the optimization processing on the output convolution layer can be expressed by the following formula (16):

[0173] (16)

[0174] in, Indicates the depth characteristics of the load electrical circuit, represents the trainable weights of the output convolutional layer, It should be noted that the deep features of the load electrical circuit may include detailed features such as the distribution pattern of arcs generated by the load electrical circuit, morphological changes, and abnormal fluctuations of arc current.

[0175] The technical solution in the embodiment of the present application inputs the preprocessed image information into the initial convolution layer, performs feature extraction on the preprocessed image information to obtain preliminary features of the load electrical circuit, inputs the preliminary features into the channel-by-channel convolution layer, performs convolution processing on the preliminary features to obtain local features of the load electrical circuit, inputs the local features into the extended point-by-point convolution layer, performs inter-channel feature fusion processing on the local features to obtain fused features of the load electrical circuit, inputs the fused features into the output convolution layer, optimizes the fused features to obtain deep features of the load electrical circuit; the above method can perform deep feature extraction through a feature extraction network model constructed by the initial convolution layer and the inverted residual module, which not only improves computational efficiency, but also can flexibly extract low-level and high-level features in the fault current signal to improve the accuracy and efficiency of deep feature extraction.

[0176] The following describes the process of using the feature fusion model to fuse the physical features of the load electrical circuit and the corresponding deep features to determine the fault feature set of the load electrical circuit. In one embodiment, the feature fusion model includes an attention mechanism module, a global average pooling layer, and a fully connected layer; Figure 9 As shown, the steps in the above S300 may include:

[0177] S310: Using the attention mechanism module, perform weighted fusion on the physical features of the load electrical circuit and the corresponding deep features to obtain weighted fusion features of the load electrical circuit.

[0178] In the embodiment of the present application, the process of weighted fusion of the physical features of the load electrical circuit and the corresponding deep features using the attention mechanism module can be expressed by the following formula (17):

[0179] (17)

[0180] in, represents the weight of a single channel, Represents the physical characteristics of the load electrical circuit (multidimensional characteristics), Deep features (multi-dimensional features) representing the load electrical circuits, represents the weighted fusion feature of the load electrical circuit. Optionally, The dimensions can be H × W × C (i.e., height × width × number of channels), where H represents time and W represents frequency. At the same time, the attention mechanism is applied to the channels of the attention mechanism module. In the embodiment of the present application, the attention mechanism module can adaptively adjust the weights between different channels.

[0181] It should be noted here that the attention mechanism module performs weighted fusion of the features of each channel (including physical features and depth features), which enables the feature fusion model to automatically focus on channels with higher information content or critical signals when subsequently processing weighted fusion features, while suppressing channels with more redundancy or noise, thereby improving the expressiveness of the overall feature representation and the robustness of the feature fusion model.

[0182] S320: Input the weighted fusion features into the global average pooling layer to extract global features, and obtain the global features of the load electrical circuit.

[0183] In the embodiment of the present application, the weighted fusion feature is input into the global average pooling layer for global feature extraction. The process of obtaining the global feature of the load electrical circuit can be expressed by the following formula (18):

[0184] (18)

[0185] in, Represents the process of global feature extraction by the global average pooling layer, Represents the global characteristics of the load electrical circuit.

[0186] S330: Input the global features into the fully connected layer to determine the channel attention weight corresponding to the feature fusion model.

[0187] It should be noted that the fully connected layer can include two layers of fully connected networks. Specifically, the computer device can input the global features into the fully connected layer to map different dimensions in the global features to the same dimension, thereby obtaining the channel attention weights corresponding to the feature fusion model. The processing of the fully connected layer can be expressed by the following formula (19):

[0188] (19)

[0189] in, represents the Sigmoid activation function, represents the ReLU activation function, 、 and 、 They represent the trainable parameters respectively.

[0190] S340. Recalibrate the weighted fusion features according to the channel attention weights to obtain a fault feature set of the load electrical circuit.

[0191] Furthermore, the computer device can recalibrate the weighted fusion features according to the channel attention weights based on the feature fusion model (i.e., channel-level recalibration) to obtain the fault feature set of the load electrical circuit. The recalibration process can be expressed by the following formula (20):

[0192] (20)

[0193] in, A fault feature set representing the load electrical circuit. Optionally, the fault feature set may include spatial features (such as the arc's geometry, edge information, and spatial distribution, which can reflect the arc's position, size, and extension in the fault current signal), dynamic features (which can reflect fluctuations and periodic changes during the series fault arcing process), intensity features (which can reflect the intensity and changes of the series fault arcing), and pattern features (which can reflect the persistent fluctuations and sudden changes of different series fault arcing patterns).

[0194] The technical solution in the embodiment of the present application utilizes an attention mechanism module to perform weighted fusion of the physical features and corresponding deep features of the load electrical circuit to obtain the weighted fusion features of the load electrical circuit, input the weighted fusion features into the global average pooling layer for global feature extraction to obtain the global features of the load electrical circuit, input the global features into the fully connected layer, determine the channel attention weights corresponding to the feature fusion model, and recalibrate the weighted fusion features according to the channel attention weights to obtain the fault feature set of the load electrical circuit; the above method can fuse the physical features and deep features of the load electrical circuit, so as to obtain more comprehensive fault features of the load electrical circuit, and provide reliable reference information for subsequent accurate detection of faults of the load electrical circuit; at the same time, the feature fusion process in the above method introduces an attention mechanism, which can dynamically adjust the weights of the physical features and deep features, highlight key features, suppress redundant information, and improve the accuracy of the fault features finally obtained.

[0195] In one embodiment, the present application also provides a method for extracting electrical circuit fault features, which is applied to computer equipment. The method includes the following steps:

[0196] (1) Obtain the current signal of the load electrical circuit within the range of the power grid to be tested;

[0197] (2) Screening out the fault current signal of the load electrical circuit from the current signal of the load electrical circuit;

[0198] (3) De-noising the fault current signal of the load electrical circuit to obtain a de-noised current signal;

[0199] (4) extracting time domain features based on the denoised current signal to obtain time domain features of the load electrical circuit; and extracting frequency domain features based on the denoised current signal to obtain frequency domain features of the load electrical circuit; and extracting time and frequency domain features based on the denoised current signal to obtain time and frequency domain features of the load electrical circuit; wherein the time domain features include at least one of current peak-to-peak value, current average value, kurtosis factor peak factor and current effective value; the frequency domain features include at least one of kth harmonic amplitude and kth harmonic factor, total harmonic distortion rate, spectrum mean and spectrum standard deviation; the time and frequency domain features include at least one of detail coefficient mean and detail coefficient variance of multi-layer wavelet transform;

[0200] (5) determining the physical characteristics of the load electrical circuit based on the time domain characteristics, the corresponding frequency domain characteristics, and the corresponding time-frequency domain characteristics of the load electrical circuit; and,

[0201] (6) Perform time-frequency conversion on the fault current signal of the load electrical circuit to obtain the corresponding time-frequency image information;

[0202] (7) Normalizing the time-frequency image information to obtain normalized image information;

[0203] (8) Performing information enhancement processing on the normalized image information to obtain preprocessed image information;

[0204] (9) Inputting the preprocessed image information into the initial convolution layer of the feature extraction network model, extracting features from the preprocessed image information, and obtaining preliminary features of the load electrical circuit;

[0205] (10) Inputting the preliminary features into the channel-by-channel convolution layer in the feature extraction network model, performing convolution processing on the preliminary features to obtain the local features of the load electrical circuit;

[0206] (11) Inputting the local features into the extended point-by-point convolution layer in the feature extraction network model, performing inter-channel feature fusion processing on the local features, and obtaining the fusion features of the load electrical circuit;

[0207] (12) Inputting the fused features into the output convolution layer of the feature extraction network model, optimizing the fused features, and obtaining the deep features of the load electrical circuit;

[0208] (13) Using the attention mechanism module in the feature fusion model, the physical features of the load electrical circuit and the corresponding deep features are weightedly fused to obtain the weighted fusion features of the load electrical circuit;

[0209] (14) Inputting the weighted fusion features into the global average pooling layer in the feature fusion model to extract global features and obtain the global features of the load electrical circuit;

[0210] (15) Input the global features into the fully connected layer of the feature fusion model and determine the channel attention weight corresponding to the feature fusion model;

[0211] (16) Using the feature fusion model, the weighted fusion features are recalibrated according to the channel attention weights to obtain the fault feature set of the load electrical circuit.

[0212] The execution process of the above (1) to (16) can be specifically referred to the description of the above embodiment. The implementation principles and technical effects are similar and will not be repeated here.

[0213] It should be understood that, although the steps in the flowcharts of the above embodiments are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowcharts of the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily to be performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0214] Based on the same inventive concept, embodiments of the present application also provide an electrical circuit fault feature extraction device for implementing the aforementioned electrical circuit fault feature extraction method. The solution provided by this device is similar to the solution described in the aforementioned method. Therefore, the specific limitations of one or more embodiments of the electrical circuit fault feature extraction device provided below can be found in the limitations of the electrical circuit fault feature extraction method described above and will not be further elaborated here.

[0215] In an exemplary embodiment, Figure 10 As shown, an electrical line fault feature extraction device is provided, comprising: an acquisition module 11, a feature extraction module 12 and a feature fusion module 13, wherein:

[0216] An acquisition module 11 is used to acquire a fault current signal of a load electrical circuit within the range of the power grid to be tested;

[0217] A feature extraction module 12 is configured to perform rapid feature extraction based on the fault current signal of the load electrical circuit to obtain physical features of the load electrical circuit; and perform deep feature extraction based on the fault current signal of the load electrical circuit to obtain deep features of the load electrical circuit;

[0218] The feature fusion module 13 is used to use a feature fusion model to fuse the physical features of the load electrical circuit and the corresponding deep features to determine the fault feature set of the load electrical circuit; the feature fusion model is a network model built based on the attention mechanism.

[0219] The electrical circuit fault feature extraction device provided in the embodiment of the present application can be used to execute the technical solution in the above-mentioned electrical circuit fault feature extraction method embodiment of the present application. Its implementation principle and technical effects are similar and will not be repeated here.

[0220] In one embodiment, the acquisition module 11 is specifically configured to:

[0221] Obtaining current signals of load electrical circuits within the range of the power grid to be tested;

[0222] A fault current signal of the load electrical circuit is screened out from the current signal of the load electrical circuit.

[0223] The electrical circuit fault feature extraction device provided in the embodiment of the present application can be used to execute the technical solution in the above-mentioned electrical circuit fault feature extraction method embodiment of the present application. Its implementation principle and technical effects are similar and will not be repeated here.

[0224] In one embodiment, the feature extraction module 12 includes: a denoising processing unit, a first feature extraction unit, and a determination unit, wherein:

[0225] A denoising processing unit, configured to perform denoising on a fault current signal of a load electrical circuit to obtain a denoised current signal;

[0226] a first feature extraction unit, configured to extract time domain features based on the denoised current signal to obtain time domain features of the load electrical circuit; and extract frequency domain features based on the denoised current signal to obtain frequency domain features of the load electrical circuit; and extract time-frequency domain features based on the denoised current signal to obtain time-frequency domain features of the load electrical circuit; wherein the time domain features include at least one of a current peak-to-peak value, a current average value, a kurtosis factor peak factor, and a current effective value; the frequency domain features include at least one of a kth harmonic amplitude and a kth harmonic factor, a total harmonic distortion rate, a spectrum mean, and a spectrum standard deviation; and the time-frequency domain features include at least one of a detail coefficient mean value and a detail coefficient variance of a multi-layer wavelet transform;

[0227] The determining unit is used to determine the physical characteristics of the load electrical circuit according to the time domain characteristics, the corresponding frequency domain characteristics and the corresponding time-frequency domain characteristics of the load electrical circuit.

[0228] The electrical circuit fault feature extraction device provided in the embodiment of the present application can be used to execute the technical solution in the above-mentioned electrical circuit fault feature extraction method embodiment of the present application. Its implementation principle and technical effects are similar and will not be repeated here.

[0229] In one embodiment, the feature extraction module 12 includes: a time-frequency conversion unit, a preprocessing unit, and a second feature extraction unit, wherein:

[0230] A time-frequency conversion unit, configured to perform time-frequency conversion on the fault current signal of the load electrical circuit to obtain corresponding time-frequency image information;

[0231] A preprocessing unit, configured to preprocess the time-frequency image information to obtain preprocessed image information;

[0232] The second feature extraction unit is used to use the feature extraction network model to perform deep feature extraction on the preprocessed image information to obtain the deep features of the load electrical circuit.

[0233] The electrical circuit fault feature extraction device provided in the embodiment of the present application can be used to execute the technical solution in the above-mentioned electrical circuit fault feature extraction method embodiment of the present application. Its implementation principle and technical effects are similar and will not be repeated here.

[0234] In one embodiment, the pre-processing unit is specifically configured to:

[0235] Normalizing the time-frequency image information to obtain normalized image information;

[0236] The normalized image information is subjected to information enhancement processing to obtain preprocessed image information.

[0237] The electrical circuit fault feature extraction device provided in the embodiment of the present application can be used to execute the technical solution in the above-mentioned electrical circuit fault feature extraction method embodiment of the present application. Its implementation principle and technical effects are similar and will not be repeated here.

[0238] In one embodiment, the feature extraction network model includes an initial convolution layer and an inverted residual module, the inverted residual module includes a channel-by-channel convolution layer, an extended point-by-point convolution layer, and an output convolution layer using a linear activation function; the second feature extraction unit is specifically used to:

[0239] The preprocessed image information is input into the initial convolution layer, and features are extracted from the preprocessed image information to obtain preliminary features of the load electrical circuit;

[0240] The preliminary features are input into the channel-by-channel convolution layer, and the preliminary features are convolved to obtain the local features of the load electrical circuit;

[0241] The local features are input into the extended point-by-point convolution layer, and the inter-channel feature fusion processing is performed on the local features to obtain the fusion features of the load electrical circuit;

[0242] The fused features are input into the output convolution layer, and the fused features are optimized to obtain the deep features of the load electrical circuit.

[0243] The electrical circuit fault feature extraction device provided in the embodiment of the present application can be used to execute the technical solution in the above-mentioned electrical circuit fault feature extraction method embodiment of the present application. Its implementation principle and technical effects are similar and will not be repeated here.

[0244] In one embodiment, the feature fusion model includes an attention mechanism module, a global average pooling layer, and a fully connected layer; the feature fusion module 13 is specifically used to:

[0245] Using the attention mechanism module, the physical features of the load electrical circuit and the corresponding deep features are weightedly fused to obtain the weighted fusion features of the load electrical circuit;

[0246] The weighted fusion features are input into the global average pooling layer for global feature extraction to obtain the global features of the load electrical circuit;

[0247] Input the global features into the fully connected layer to determine the channel attention weight corresponding to the feature fusion model;

[0248] According to the channel attention weights, the weighted fusion features are recalibrated to obtain the fault feature set of the load electrical circuit.

[0249] The electrical circuit fault feature extraction device provided in the embodiment of the present application can be used to execute the technical solution in the above-mentioned electrical circuit fault feature extraction method embodiment of the present application. Its implementation principle and technical effects are similar and will not be repeated here.

[0250] The specific limitations of the electrical circuit fault feature extraction device can be found in the limitations of the electrical circuit fault feature extraction method described above and will not be further elaborated here. Each module in the aforementioned electrical circuit fault feature extraction device can be implemented in whole or in part via software, hardware, or a combination thereof. Each of these modules can be embedded in or independent of a processor in a computer device in hardware form, or stored in a computer device memory in software form, allowing the processor to call and execute the corresponding operations of each module.

[0251] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 11 As shown. The computer device includes a processor, a memory, and a network interface connected via a system bus. The processor of the computer device is used to provide processing power. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store physical characteristics, depth characteristics, and fault characteristic sets of load electrical circuits. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, it implements a method for extracting fault characteristics of an electrical circuit.

[0252] Those skilled in the art will understand that Figure 11The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0253] In one embodiment, a computer device is also provided, including a memory and a processor, wherein a computer program is stored in the memory. When the processor executes the computer program, the technical solution in the above-mentioned electrical circuit fault feature extraction method embodiment of the present application is implemented. The implementation principle and technical effect are similar and will not be repeated here.

[0254] In one embodiment, a computer-readable storage medium is also provided, on which a computer program is stored. When the computer program is executed by a processor, the technical solution of the above-mentioned electrical circuit fault feature extraction method of the present application is implemented. Its implementation principle and technical effect are similar and will not be repeated here.

[0255] In one embodiment, a computer program product is also provided, including a computer program. When the computer program is executed by a processor, the technical solution of the above-mentioned electrical line fault feature extraction method of the present application is implemented. The implementation principle and technical effect are similar and will not be repeated here.

[0256] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the above-described method embodiments. Any reference to memory, storage, database, or other media used in the embodiments provided herein may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0257] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0258] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for extracting electrical line fault features, characterized in that: The method comprises: Obtaining fault current signals of load electrical lines within the range of the power grid to be tested; Performing rapid feature extraction based on the fault current signal of the load electrical circuit to obtain physical features of the load electrical circuit; and performing deep feature extraction based on the fault current signal of the load electrical circuit to obtain deep features of the load electrical circuit; A feature fusion model is used to fuse the physical features and corresponding deep features of the load electrical circuit to determine the fault feature set of the load electrical circuit; the feature fusion model is a network model constructed based on the attention mechanism.

2. The method according to claim 1, characterized in that The obtaining of the fault current signal of the load electrical circuit within the range of the power grid to be tested includes: Acquiring a current signal of the load electrical circuit within the range of the power grid to be measured; A fault current signal of the load electrical circuit is screened out from the current signal of the load electrical circuit.

3. The method according to claim 1 or 2, characterized in that The fast feature extraction based on the fault current signal of the load electrical circuit to obtain the physical characteristics of the load electrical circuit includes: performing denoising processing on the fault current signal of the load electrical circuit to obtain a denoised current signal; Performing time domain feature extraction on the denoised current signal to obtain time domain features of the load electrical circuit; and performing frequency domain feature extraction on the denoised current signal to obtain frequency domain features of the load electrical circuit; and performing time-frequency domain feature extraction on the denoised current signal to obtain time-frequency domain features of the load electrical circuit; wherein the time domain features include at least one of current peak-to-peak value, current average value, kurtosis factor peak factor and current effective value; the frequency domain features include at least one of kth harmonic amplitude and kth harmonic factor, total harmonic distortion, spectrum mean and spectrum standard deviation; the time-frequency domain features include at least one of detail coefficient mean and detail coefficient variance of multi-layer wavelet transform; The physical characteristics of the load electrical circuit are determined according to the time domain characteristics, the corresponding frequency domain characteristics and the corresponding time-frequency domain characteristics of the load electrical circuit.

4. The method according to claim 1 or 2, characterized in that The extracting deep features according to the fault current signal of the load electrical circuit to obtain the deep features of the load electrical circuit includes: Performing time-frequency conversion on the fault current signal of the load electrical circuit to obtain corresponding time-frequency image information; Preprocessing the time-frequency image information to obtain preprocessed image information; A feature extraction network model is used to perform deep feature extraction on the preprocessed image information to obtain deep features of the load electrical circuit.

5. The method according to claim 4, characterized in that The preprocessing of the time-frequency image information to obtain preprocessed image information includes: Performing cropping processing on the time-frequency image information to obtain cropped image information; performing normalization processing on the cropped image information to obtain normalized image information; Information enhancement processing is performed on the normalized image information to obtain the preprocessed image information.

6. The method according to claim 4, characterized in that The feature extraction network model includes an initial convolution layer and an inverted residual module, wherein the inverted residual module includes a channel-by-channel convolution layer, an extended point-by-point convolution layer, and an output convolution layer using a linear activation function; the feature extraction network model is used to perform deep feature extraction on the preprocessed image information to obtain the deep features of the load electrical circuit, including: Inputting the preprocessed image information into the initial convolution layer, performing feature extraction on the preprocessed image information, and obtaining preliminary features of the load electrical circuit; Inputting the preliminary features into the channel-by-channel convolution layer, performing convolution processing on the preliminary features to obtain local features of the load electrical circuit; Inputting the local features into the extended point-by-point convolution layer, performing inter-channel feature fusion processing on the local features, and obtaining fusion features of the load electrical circuit; The fused features are input into the output convolution layer, and the fused features are optimized to obtain the deep features of the load electrical circuit.

7. The method according to claim 1 or 2, characterized in that The feature fusion model includes an attention mechanism module, a global average pooling layer, and a fully connected layer. The feature fusion model is used to fuse the physical features and corresponding deep features of the load electrical circuit to determine the fault feature set of the load electrical circuit, including: Using the attention mechanism module, weighted fusion is performed on the physical features and corresponding deep features of the load electrical circuit to obtain a weighted fusion feature of the load electrical circuit; Inputting the weighted fusion features into the global average pooling layer to perform global feature extraction to obtain the global features of the load electrical circuit; Inputting the global features into the fully connected layer, and determining the channel attention weight corresponding to the feature fusion model; The weighted fusion features are recalibrated according to the channel attention weights to obtain a fault feature set of the load electrical circuit.

8. An electrical circuit fault feature extraction device, characterized in that: The device comprises: An acquisition module is used to acquire a fault current signal of a load electrical circuit within the range of the power grid to be tested; a feature extraction module, configured to perform rapid feature extraction based on the fault current signal of the load electrical circuit to obtain physical features of the load electrical circuit; and perform deep feature extraction based on the fault current signal of the load electrical circuit to obtain deep features of the load electrical circuit; A feature fusion module is used to use a feature fusion model to fuse the physical features and corresponding deep features of the load electrical circuit to determine the fault feature set of the load electrical circuit; the feature fusion model is a network model constructed based on the attention mechanism.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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