Analog circuit implementation method for convolutional neural network
Through optical conversion and convolution pooling operations, the problem of signal transmission delay and long calculation time in convolutional neural network hardware is solved, and efficient signal processing and low-energy consumption convolutional neural network architecture are realized.
Patent Information
- Application Number
- CN202510660793.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-03-11
- Filing Date
- 2025-05-22
- Publication Date
- 2025-08-15
AI Technical Summary
In the existing convolutional neural network hardware implementation, there are problems such as long signal transmission delay, long calculation time, high energy consumption, large memory usage and noise-sensitive, especially in analog circuits, signal transmission is affected by circuit layout and signal propagation speed.
The optical conversion module is used to convert the image into vectors, the convolution operation is performed through the convolution module, and the pooling module is used to perform pooling operations. The parallelism of optical signals and the efficient computing power of the convolution neural network architecture are used to convert it into optical mapping and propagation, reducing signal processing time.
It improves the efficiency of signal processing, reduces energy consumption, reduces storage space requirements, and reduces noise sensitivity, improving the stability and accuracy of calculations.
Smart Images
Figure CN120494012A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of neural network technology, and in particular to a method for implementing an analog circuit for a convolutional neural network. Background Art
[0002] Convolutional Neural Network (CNN) is a special type of artificial neural network that uses a mathematical operation called convolution instead of general matrix multiplication in at least one of its layers. CNN is specifically designed to process pixel data and is used for image recognition and processing. Currently, there are two main implementation methods for CNN hardware acceleration: (1) Digital circuit solution: Based on FPGA / ASIC parallel computing architecture, fixed-point / floating-point arithmetic units are used to implement convolution kernel calculations. Typical examples include Google TPU and Xilinx DPU, which rely on high-precision ADC / DAC for analog-to-digital conversion. (2) Mixed signal solution: Some use analog multiplication and accumulation units (such as RRAM / CB memory-based calculations), but digital control circuits are still required to coordinate the operations of each layer, resulting in frequent signal conversion overhead.
[0003] However, the following problems exist in the operation of CNN hardware: (1) The operation requires a large number of multiplier arrays, which consumes a lot of energy; (2) The register storage weights lead to the memory wall problem. In the 130nm process, a single 32x32 convolution kernel storage takes up 0.36mm. 2 (3) The conversion delay in the analog-to-digital hybrid solution accounts for more than 30%, which restricts the throughput improvement and limits the real-time performance; (4) The accuracy of the existing analog computing unit is significantly reduced under process deviation. The PVT fluctuation at the 65nm node causes the signal-to-noise ratio to deteriorate by more than 6dB, and it is sensitive to noise.
[0004] In addition, during the application of convolutional neural networks, signal transmission in analog circuits is affected by factors such as circuit layout and signal propagation speed. The propagation of analog signals may be affected by problems such as impedance matching and parasitic capacitance, resulting in increased signal transmission delays and thus extended calculation time. Summary of the Invention
[0005] The main purpose of this application is to provide an analog circuit implementation method for convolutional neural networks, which mainly solves the technical problems of long signal transmission delay and long calculation time in analog circuits.
[0006] To achieve the above objectives, the present application provides a method for implementing an analog circuit for a convolutional neural network, comprising:
[0007] receiving a first image;
[0008] performing optical transformation on the first image to obtain a plurality of first vectors;
[0009] Performing a convolution operation on the multiple first vectors to obtain a second vector;
[0010] Perform a pooling operation on the second vector to obtain a second image.
[0011] In addition, to achieve the above-mentioned purpose, the present application provides a circuit for simulating a convolutional neural network, wherein the circuit for simulating a convolutional neural network includes a conversion module, a convolution module, and a pooling module;
[0012] The output end of the conversion module is connected to the input end of the convolution module, and the output end of the convolution module is connected to the input end of the pooling module;
[0013] The conversion module is configured to perform optical conversion on the received first image to obtain a plurality of first vectors;
[0014] The convolution module is configured to perform a convolution operation on the plurality of first vectors to obtain a second vector;
[0015] The pooling module is used to perform a pooling operation on the second vector to obtain a second image.
[0016] Optionally, the conversion module includes a photosensitive device and an optical waveguide;
[0017] The output end of the photosensitive device is connected to the input end of the optical waveguide;
[0018] Wherein, the photosensitive device is used to convert the received first image into an image data matrix;
[0019] The optical waveguide is used to convert the image data matrix into a plurality of first vectors.
[0020] Optionally, the convolution module includes a plurality of analog multipliers and integrators;
[0021] The input ends of the multiple analog multipliers are connected to the output end of the conversion module, the output ends of the multiple analog multipliers are connected to the input end of the integrator, and the output end of the integrator is connected to the input end of the pooling module.
[0022] Optionally, the analog multiplier is an operational amplifier, the input end of the operational amplifier is connected to the output end of the conversion module, and the output end of the operational amplifier is connected to the input end of the integrator.
[0023] Optionally, the convolution module further includes a diode;
[0024] The anode of the diode is connected to the output end of the conversion module, and the cathode of the diode is connected to the input end of the operational amplifier.
[0025] Optionally, the pooling module includes a plurality of pooling units;
[0026] The input ends of the multiple pooling units are connected to the output end of the convolution module;
[0027] The multiple pooling units are used to perform a maximum pooling operation on the second vector to obtain a second image.
[0028] Optionally, the pooling module further includes an activation unit;
[0029] The input end of the activation unit is connected to the output end of the convolution module, and the output end of the activation unit is connected to the input ends of the multiple pooling units;
[0030] The activation unit is used to perform activation processing on the second vector.
[0031] Optionally, the pooling unit includes a plurality of pooling circuits connected in parallel, and the pooling circuit includes a resistor and an operational amplifier;
[0032] The input end of the operational amplifier is connected to the output end of the convolution module, the ground end of the operational amplifier is grounded, the first end of the resistor is connected to the input end of the operational amplifier, and the second end of the resistor is connected to the output end of the operational amplifier.
[0033] In addition, to achieve the above-mentioned objectives, the present application also provides a convolutional neural network architecture, which includes a circuit for simulating a convolutional neural network.
[0034] Compared with the prior art, the embodiments of the present application have the following beneficial effects:
[0035] An embodiment of the present application provides an analog circuit implementation method for a convolutional neural network, comprising: receiving a first image; performing an optical conversion on the first image to obtain a plurality of first vectors; performing a convolution operation on the plurality of first vectors to obtain a second vector; and performing a pooling operation on the second vector to obtain a second image. In an embodiment of the present application, a first image is received, and the first image may be an image signal received by a convolutional neural network architecture. The first image is optically converted by a conversion module to obtain a plurality of first vectors; a convolution operation is performed on the plurality of first vectors by a convolution module to obtain a second vector; and a pooling operation is performed on the second vector by a pooling module to obtain a second image. In an embodiment of the present application, by optically converting the image, the position transformation and data processing process in the convolution operation are converted into optical level mapping and propagation, and the convolution and pooling operations of the CNN network are converted into matrix multiplication through optical devices and a convolutional neural network architecture, thereby utilizing the parallelism of optical signals and the efficient computing power of the neural network architecture to reduce the time of signal processing and improve the efficiency of signal processing.
[0036] In addition, the convolutional neural network provided by the embodiment of the present application uses optical devices, which has low energy consumption and can solve the technical problem of high energy consumption of the multiplier array. The convolutional neural network provided by the embodiment of the present application has less storage space and can solve the technical problem of the convolution kernel storage occupying a large amount of space in the prior art. In this application, the parallelism of optical signals and the efficient computing power of the convolutional neural network architecture are used to solve the technical problem of noise sensitivity. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] In order to more clearly illustrate the solutions in this application, a brief introduction will be given below to the drawings required for use in the description of the embodiments of this application. Obviously, the drawings described below are some embodiments of this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0038] Figure 1 This is a flow chart of a method for implementing an analog circuit for a convolutional neural network provided in an embodiment of the present application;
[0039] Figure 2 Schematic diagram of the structure of a circuit for simulating a convolutional neural network provided in an embodiment of the present application;
[0040] Figure 3a Schematic diagram of imaging of optical signals provided in an embodiment of the present application;
[0041] Figure 3b Schematic diagram of mapping imaging of the optical waveguide matrix provided in an embodiment of the present application;
[0042] Figure 4aThis is one of the optical waveguide matrix mapping effect diagrams provided in the embodiment of the present application;
[0043] Figure 4b This is the second optical waveguide matrix mapping effect diagram provided by the embodiment of the present application;
[0044] Figure 5 Schematic diagram of the structure of the pooling module provided in the embodiment of the present application;
[0045] Figure 6 This is a schematic diagram of the convolutional neural network architecture provided by an embodiment of the present application;
[0046] Figure 7 This is a workflow diagram of the convolutional neural network architecture provided in the embodiment of the present application.
[0047] Description of reference numerals:
[0048] 10. Conversion module; 20. Convolution module; 30. Pooling module; 31. Pooling unit; R, resistor; TIA, operational amplifier. DETAILED DESCRIPTION
[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of the application are for the purpose of describing specific embodiments only and are not intended to limit this application. The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of this application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.
[0050] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.
[0051] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.
[0052] See also Figure 1 , Figure 1 This is a flow chart of the analog circuit implementation method for convolutional neural network provided by the embodiment of the present application. Figure 1As shown, the analog circuit implementation method for a convolutional neural network provided in the embodiment of the present application includes:
[0053] S110: Receive a first image.
[0054] S120: Perform optical transformation on the first image to obtain a plurality of first vectors.
[0055] S130: Perform a convolution operation on the multiple first vectors to obtain a second vector.
[0056] S140: Perform a pooling operation on the second vector to obtain a second image.
[0057] The analog circuit implementation method for a convolutional neural network provided in this embodiment can be applied to a convolutional neural network architecture, which includes a conversion module, a convolution module, and a pooling module.
[0058] In this embodiment, a first image is received, which may be an image signal received by a convolutional neural network architecture. A conversion module performs an optical conversion on the first image to obtain a plurality of first vectors. A convolution module performs a convolution operation on the plurality of first vectors to obtain a second vector. A pooling module performs a pooling operation on the second vectors to obtain a second image.
[0059] In an embodiment of the present application, by performing optical transformation on the image, the position transformation and data processing process in the convolution operation is converted into optical level mapping and propagation, thereby reducing the signal processing time and improving the efficiency of signal processing.
[0060] See also Figure 2 , Figure 2 Schematic diagram of the structure of the circuit for simulating convolutional neural network provided by the embodiment of the present application. Figure 2 As shown, the circuit for simulating a convolutional neural network includes a conversion module 10, a convolution module 20 and a pooling module 30; the output end of the conversion module 10 is connected to the input end of the convolution module 20, and the output end of the convolution module 20 is connected to the input end of the pooling module 30.
[0061] The circuit for simulating a convolutional neural network provided in an embodiment of the present application includes a conversion module 10, a convolution module 20 and a pooling module 30, wherein the conversion module 10 is used to optically convert an image element to obtain multiple first vectors; the convolution module 20 is used to perform a convolution operation on the multiple first vectors to obtain a second vector; and the pooling module 30 is used to perform a pooling operation on the second vector to obtain a second image.
[0062] The working principle of the above-mentioned circuit for simulating a convolutional neural network is to receive a first image, perform optical conversion on the received first image through the conversion module 10 to obtain multiple first vectors, and transmit the above-mentioned multiple first vectors to the convolution module 20; the convolution module 20 performs a convolution operation on the multiple first vectors to obtain a second vector, and transmits the above-mentioned second vector to the pooling module 30; the pooling module 30 performs a pooling operation on the second vector to obtain a second image.
[0063] The circuit for simulating a convolutional neural network in the embodiment of the present application performs optical transformation on the image, converting the position transformation and data processing process in the convolution operation into optical mapping and propagation, thereby reducing the signal processing time and improving the efficiency of signal processing.
[0064] Optionally, the conversion module includes a photosensitive device and an optical waveguide;
[0065] The output end of the photosensitive device is connected to the input end of the optical waveguide.
[0066] The conversion module in this embodiment includes a photosensitive device and an optical waveguide, wherein the photosensitive device is used to convert an image into an image data matrix, and the optical waveguide is used to convert the image data matrix into multiple vectors, which are referred to as first vectors.
[0067] Optionally, see Figure 3a shows a schematic diagram of imaging of optical signals, Figure 3b The schematic diagram of the mapping imaging of the optical waveguide matrix is shown. Figure 3a and Figure 3b , we can use the photosensitive device to represent the input matrix A, and change the incident map to the corresponding position through the optical waveguide to form
[0068] The working principle of the conversion module in this embodiment is that the photosensitive device receives an image, converts the image into an image data matrix, and transmits the above image data matrix to the optical waveguide; the optical waveguide converts the received image data matrix into multiple first vectors.
[0069] The following examples illustrate the conversion of images by photosensitive devices and optical waveguides:
[0070] For example, the input of the transformation module is matrix A and the convolution kernel is W:
[0071]
[0072] See also Figure 4a , Figure 4a This is one of the optical waveguide matrix mapping effect diagrams provided in the embodiment of the present application. Figure 4a The mapping effect of matrix A is shown.
[0073] For the above 4×4 input matrix and 2×2 convolution kernel, the 4×4 input matrix is divided into 9 2×2 local regions by sliding window, and each region is flattened into a 4-dimensional row vector. Then A can be expanded into At the same time, the 2×2 convolution kernel is also flattened into a 1×4 row vector, that is, W is expanded to W. and They are as follows:
[0074]
[0075] Matrix multiplication result (9×1 column vector):
[0076]
[0077] Arrange the above column vectors into a 3×3 matrix in row-major order:
[0078]
[0079] Then the shape is like The convolution with a stride of 1 and padding of 0 can be expressed as
[0080] Through matrix multiplication The resulting 3×3 matrix is exactly the same as the output of the traditional convolution operation. The position and calculation formula of each element are strictly corresponding.
[0081] In this way, the original convolution operation can be converted into a multiplication operation of the two matrices, and the result can be properly rearranged to obtain an output feature map that is completely consistent with the traditional convolution operation.
[0082] See also Figure 4b , Figure 4b This is the second optical waveguide matrix mapping effect diagram provided by the embodiment of the present application. Figure 4b shows the matrix mapping effect.
[0083] In this way, the original input matrix A is represented by the photosensitive device, and the incident map is changed to the corresponding position through the optical waveguide to form In this way, the original convolution operation can be converted into a multiplication operation of the two matrices, and the result can be properly rearranged to obtain an output feature map that is completely consistent with the traditional convolution operation.
[0084] In this embodiment, the input image is processed using a photosensitive device and an optical waveguide, and the position transformation and data processing process in the convolution operation is converted into optical mapping and propagation, which significantly reduces the signal processing time and avoids signal delay.
[0085] Compared with traditional electronic components, optical devices generally consume less power, which can reduce energy consumption and thus improve energy efficiency, making them suitable for applications with high power consumption requirements.
[0086] Optical signals are not affected by electromagnetic interference during processing, significantly reducing noise and signal distortion. Compared to traditional electronic circuits, optical circuits are less sensitive to noise, which improves computing stability and accuracy, and can better maintain signal quality in complex environments.
[0087] Optionally, the convolution module includes a plurality of analog multipliers and integrators;
[0088] The input ends of the multiple analog multipliers are connected to the output end of the conversion module, the output ends of the multiple analog multipliers are connected to the input end of the integrator, and the output end of the integrator is connected to the input end of the pooling module.
[0089] Optionally, the analog multiplier is an operational amplifier, the input end of the operational amplifier is connected to the output end of the conversion module, and the output end of the operational amplifier is connected to the input end of the integrator.
[0090] Optionally, the convolution module further includes a diode;
[0091] The anode of the diode is connected to the output end of the conversion module, and the cathode of the diode is connected to the input end of the operational amplifier.
[0092] The convolution module in this embodiment includes a diode, an analog multiplier and an integrator. Optionally, the analog multiplier is an operational amplifier.
[0093] The anode of the diode is connected to the output end of the conversion module, the cathode of the diode is connected to the input end of the operational amplifier, the input end of the operational amplifier is connected to the output end of the conversion module, and the output end of the operational amplifier is connected to the input end of the integrator.
[0094] In this embodiment, the multiplication operation of the vector is realized by combining the operational amplifier and the diode; the addition operation of the vector is realized by the integrator; and the convolution operation of the vector is realized in this way.
[0095] See also Figure 5 , Optionally, the pooling module includes a plurality of pooling units 31;
[0096] The input ends of the multiple pooling units 31 are connected to the output end of the convolution module;
[0097] The multiple pooling units 31 are used to perform a maximum pooling operation on the second vector to obtain a second image.
[0098] Optionally, the pooling unit 31 includes a plurality of pooling circuits connected in parallel, each of the pooling circuits including a resistor R and an operational amplifier TIA;
[0099] The input end of the operational amplifier TIA is connected to the output end of the convolution module, the ground end of the operational amplifier TIA is grounded, the first end of the resistor R is connected to the input end of the operational amplifier TIA, and the second end of the resistor R is connected to the output end of the operational amplifier TIA.
[0100] In this embodiment, the pooling module includes multiple pooling units 31, which include multiple parallel pooling circuits, each including a resistor R and an operational amplifier TIA. The pooling module in this embodiment receives multiple second vectors and selects the maximum value as output.
[0101] Optionally, the pooling module further includes an activation unit;
[0102] The input end of the activation unit is connected to the output end of the convolution module, and the output end of the activation unit is connected to the input ends of the multiple pooling units;
[0103] The activation unit is used to perform activation processing on the second vector.
[0104] The pooling module provided in this embodiment further includes an activation unit.
[0105] The activation unit receives the second vector output by the convolution module and activates the second vector through an activation function.
[0106] In addition, an embodiment of the present application also provides a convolutional neural network architecture, which includes multiple circuits for simulating convolutional neural networks as described above.
[0107] See also Figure 6 , Figure 6 This is a schematic diagram of the convolutional neural network architecture provided in an embodiment of the present application.
[0108] Convolutional neural network architecture is adapted to the hardware implementation of matrix multiplication. Figure 6 As shown in Figure 1, the core structure of a convolutional neural network architecture consists of vertically intersecting wordlines and bitlines, with weight values stored at each intersection via a memristor. When an input vector is applied to the wordline in the form of a voltage signal, according to Kirchhoff's current law, the current generated on the bitline is the product of the input voltage and the memristor admittance (weight), which corresponds exactly to the dot product operation in matrix multiplication.
[0109] In practice, a dual-memristor encoding scheme is used to support positive and negative weights. Each weight is represented by the difference in admittance between the two memristors. For example, for a weight of 0.5, G+ = 0.5 and G- = 0; for a weight of -0.3, G+ = 0 and G- = 0.3.
[0110] A transimpedance amplifier (TIA) converts the current signal on the bit line into a voltage signal, and a simple comparator circuit then implements the ReLU activation function. A bias term is added to the convolutional neural network architecture by adding a fixed admittance column and applying a constant 1V input voltage.
[0111] By using the photosensitive device and optical waveguide to process the input matrix A, the position transformation and data processing process in the convolution operation is converted into optical mapping and propagation. It can be directly input into the convolutional neural network architecture like the input vector in the multi-layer perceptron, and calculated with the matrix representing the convolution kernel weight in the convolutional neural network architecture to realize the convolution operation.
[0112] Please also refer to Figure 5 In a convolutional neural network architecture, operational amplifiers that meet the pooling range can be connected in parallel to obtain the maximum voltage among the four inputs, thereby implementing a maximum pooling operation. By cascading multiple layers of this structure, a complete convolutional neural network calculation process can be constructed, leveraging the advantages of optical properties and convolutional neural network architecture to achieve efficient convolution calculations. For a cascade of multi-layer perceptrons, the output voltage of the hidden layer can be directly used as the input of the next layer of the convolutional neural network architecture, repeating the matrix multiplication calculation.
[0113] Through the above method, this embodiment can use the convolutional neural network architecture to implement the sense-storage-computation circuit of the convolutional neural network.
[0114] To understand the overall technical solution, please refer to Figure 7 ,like Figure 7 As shown, the image data matrix of the input image is obtained, A1, A2...An, and the above matrix is processed by the optical waveguide matrix through the photosensitive device, converting the position transformation and data processing process in the convolution operation into optical level mapping and propagation. Just like the input vector in a multi-layer perceptron, it can be calculated in the neural network price with the matrix representing the convolution kernel weight, and the convolution operation and bias addition are realized through the convolution kernel. Then, the results after adding each bias are summed up as the output of the convolution layer, activated by the activation function, and the maximum pooling operation is performed through the operational amplifier and pooling unit to output the image.
[0115] The circuit for simulating a convolutional neural network in the embodiment of the present application performs an optical transformation on the image, converting the position transformation and data processing process in the convolution operation into optical mapping and propagation, thereby reducing signal processing time and improving signal processing efficiency. Because the convolutional neural network architecture provided by the embodiment of the present application includes a circuit for simulating a convolutional neural network, the convolutional neural network architecture provided by the embodiment of the present application also has the above-mentioned technical effects.
[0116] Obviously, the embodiments described above are only some of the embodiments of the present application, rather than all of the embodiments. The preferred embodiments of the present application are given in the accompanying drawings, but they do not limit the patent scope of the present application. The present application can be implemented in many different forms. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive. Although the present application has been described in detail with reference to the aforementioned embodiments, for those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned specific embodiments, or to make equivalent replacements for some of the technical features therein. Any equivalent structure made using the contents of the present application specification and the accompanying drawings, directly or indirectly used in other related technical fields, is also within the scope of patent protection of the present application.
Claims
1. A method for implementing an analog circuit for a convolutional neural network, characterized in that: The method comprises: receiving a first image; performing optical transformation on the first image to obtain a plurality of first vectors; Performing a convolution operation on the multiple first vectors to obtain a second vector; Perform a pooling operation on the second vector to obtain a second image.
2. A circuit for simulating a convolutional neural network, characterized in that The circuit for simulating a convolutional neural network includes a conversion module, a convolution module, and a pooling module; The output end of the conversion module is connected to the input end of the convolution module, and the output end of the convolution module is connected to the input end of the pooling module; The conversion module is configured to perform optical conversion on the received first image to obtain a plurality of first vectors; The convolution module is configured to perform a convolution operation on the plurality of first vectors to obtain a second vector; The pooling module is used to perform a pooling operation on the second vector to obtain a second image.
3. The circuit for simulating a convolutional neural network according to claim 2, wherein: The conversion module includes a photosensitive device and an optical waveguide; The output end of the photosensitive device is connected to the input end of the optical waveguide; Wherein, the photosensitive device is used to convert the received first image into an image data matrix; The optical waveguide is used to convert the image data matrix into a plurality of first vectors.
4. The circuit for simulating a convolutional neural network according to claim 2, wherein: The convolution module includes a plurality of analog multipliers and integrators; The input ends of the multiple analog multipliers are connected to the output end of the conversion module, the output ends of the multiple analog multipliers are connected to the input end of the integrator, and the output end of the integrator is connected to the input end of the pooling module.
5. The circuit for simulating a convolutional neural network according to claim 4, wherein: The analog multiplier is an operational amplifier, the input end of the operational amplifier is connected to the output end of the conversion module, and the output end of the operational amplifier is connected to the input end of the integrator.
6. The circuit for simulating a convolutional neural network according to claim 5, wherein: The convolution module also includes a diode; The anode of the diode is connected to the output end of the conversion module, and the cathode of the diode is connected to the input end of the operational amplifier.
7. The circuit for simulating a convolutional neural network according to claim 2, wherein: The pooling module includes a plurality of pooling units; The input ends of the multiple pooling units are connected to the output end of the convolution module; The multiple pooling units are used to perform a maximum pooling operation on the second vector to obtain a second image.
8. The circuit for simulating a convolutional neural network according to claim 7, wherein: The pooling module further includes an activation unit; The input end of the activation unit is connected to the output end of the convolution module, and the output end of the activation unit is connected to the input ends of the multiple pooling units; The activation unit is used to perform activation processing on the second vector.
9. The circuit for simulating a convolutional neural network according to claim 7, wherein: The pooling unit includes a plurality of pooling circuits connected in parallel, each of the pooling circuits including a resistor and an operational amplifier; The input end of the operational amplifier is connected to the output end of the convolution module, the ground end of the operational amplifier is grounded, the first end of the resistor is connected to the input end of the operational amplifier, and the second end of the resistor is connected to the output end of the operational amplifier.
10. A convolutional neural network architecture, characterized in that The convolutional neural network architecture includes a circuit for simulating a convolutional neural network as described in any one of claims 1-8.