Quantum hybrid code execution method, system, equipment, medium and product

Abstract

The invention relates to a quantum hybrid code execution method, system and device, a medium and a product. The method comprises the steps of obtaining a to-be-executed mixed code comprising a classic code and a quantum code, compiling the mixed code through a classic compiler to obtain a target main program comprising a target classic binary code and a target quantum binary code, and executing the target main program, when a target quantum binary code in the target main program is executed, obtaining a target quantum logic gate sequence corresponding to the quantum binary code based on the target quantum binary code and a preset quantum compiling system library, inputting a target quantum circuit instruction into the quantum acceleration equipment, obtaining a target quantum execution result output by the quantum acceleration equipment, and executing the target quantum execution result according to the target quantum logic gate sequence. Wherein the quantum compiling system library comprises a corresponding relationship between the quantum binary code and the quantum logic gate sequence. By adopting the method, the execution efficiency of the quantum hybrid code can be improved.

Description

Technical Field

[0001] The present application relates to the field of quantum computing technology, and in particular to a quantum hybrid code execution method, system, device, medium and product. Background Art

[0002] Emerging technologies, such as quantum computing, are a key driver of further advancements in computing performance. In the field of high-performance computing, the full potential of quantum-accelerated computing lies in combining classical and quantum computing models, as well as integrating quantum-accelerated hardware with quantum acceleration algorithms.

[0003] The execution process of hybrid code in related technologies includes: classical code directly outputs binary code that can be executed by the processor through a classical compiler, and quantum code calls quantum hardware for execution by interpreting scripts. However, the execution of the classical code and quantum code requires calling different compilers, resulting in low execution efficiency of the hybrid code. Summary of the Invention

[0004] Based on this, it is necessary to provide a quantum hybrid code execution method, system, device, medium and product that can improve execution efficiency to address the above technical problems.

[0005] In a first aspect, the present application provides a quantum hybrid code execution method, comprising:

[0006] Obtaining a hybrid code to be executed, where the hybrid code includes a classical code and a quantum code;

[0007] Compile the mixed code using a classical compiler to obtain a target main program, which includes a target classical binary code and a target quantum binary code;

[0008] executing a target main program, wherein, when executing a target quantum binary code in the target main program, obtaining a target quantum logic gate sequence corresponding to the quantum binary code based on the target quantum binary code and a preset quantum compilation system library, performing circuit synthesis processing based on the target quantum logic gate sequence to obtain a target quantum circuit instruction; inputting the target quantum circuit instruction into a quantum acceleration device to obtain a target quantum execution result output by the quantum acceleration device;

[0009] Among them, the quantum compilation system library includes the correspondence between quantum binary codes and quantum logic gate sequences.

[0010] In one embodiment, circuit synthesis processing is performed based on a quantum logic gate sequence to obtain target quantum circuit instructions, including:

[0011] Input the quantum logic gate sequence into the quantum bit virtual layer to obtain the logical quantum bit information output by the quantum bit virtual layer;

[0012] Performing an arrangement process based on the mapping relationship between the logical quantum bit information and the virtual bits corresponding to the quantum bit virtual layer to obtain the arranged quantum bit information;

[0013] Circuit synthesis processing is performed based on the arranged quantum bit information to obtain the target quantum circuit instructions.

[0014] In one embodiment, the method further comprises:

[0015] Obtain the quality state data of each physical quantum bit in the quantum acceleration device;

[0016] The virtual bit mapping relationship is determined based on the quality status data of each physical quantum bit.

[0017] In one embodiment, determining a virtual bit mapping relationship based on the quality status data of each physical quantum bit includes:

[0018] Determining a virtual qubit that performs a computation process from among the physical qubits based on the quality status data of the physical qubits;

[0019] Based on the positional relationship of the virtual quantum bits relative to the physical quantum bits, a virtual bit mapping relationship is obtained.

[0020] In one embodiment, the quality state data of the physical qubit includes the fidelity of the physical qubit and / or the decoherence time of the physical qubit.

[0021] In a second aspect, the present application also provides a quantum hybrid code execution system, including: a classical compilation system and a runtime system, wherein:

[0022] A classical compilation system is used to obtain a mixed code to be executed, the mixed code including a classical code and a quantum code, compile the mixed code using a classical compiler to obtain a target main program, the target main program including a target classical binary code and a target quantum binary code; execute the target main program, wherein, when executing the target quantum binary code in the target main program, based on the target quantum binary code and a preset quantum compilation system library, a target quantum logic gate sequence corresponding to the quantum binary code is obtained, and a runtime system is called to process the target quantum logic gate sequence, the quantum compilation system library including a correspondence between quantum binary codes and quantum logic gate sequences;

[0023] The runtime system is used to perform circuit synthesis processing based on the target quantum logic gate sequence, obtain target quantum circuit instructions, input the target quantum circuit instructions into the quantum acceleration device, and obtain the target quantum execution results output by the quantum acceleration device.

[0024] In one embodiment, the runtime system includes:

[0025] The qubit virtual layer is used to output logical qubit information according to the sequence of quantum logic gates;

[0026] A bit mapping module is used to perform arrangement processing based on the mapping relationship between the logical quantum bit information and the virtual bit corresponding to the quantum bit virtual layer to obtain the arranged quantum bit information;

[0027] The circuit synthesis module is used to perform circuit synthesis processing based on the arranged quantum bit information to obtain the target quantum circuit instructions.

[0028] In a third aspect, the present application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0029] Obtaining a hybrid code to be executed, where the hybrid code includes a classical code and a quantum code;

[0030] Compile the mixed code using a classical compiler to obtain a target main program, which includes a target classical binary code and a target quantum binary code;

[0031] executing a target main program, wherein, when executing a target quantum binary code in the target main program, obtaining a target quantum logic gate sequence corresponding to the quantum binary code based on the target quantum binary code and a preset quantum compilation system library, performing circuit synthesis processing based on the target quantum logic gate sequence to obtain a target quantum circuit instruction; inputting the target quantum circuit instruction into a quantum acceleration device to obtain a target quantum execution result output by the quantum acceleration device;

[0032] Among them, the quantum compilation system library includes the correspondence between quantum binary codes and quantum logic gate sequences.

[0033] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the following steps are implemented:

[0034] Obtaining a hybrid code to be executed, where the hybrid code includes a classical code and a quantum code;

[0035] Compile the mixed code using a classical compiler to obtain a target main program, which includes a target classical binary code and a target quantum binary code;

[0036] executing a target main program, wherein, when executing a target quantum binary code in the target main program, obtaining a target quantum logic gate sequence corresponding to the quantum binary code based on the target quantum binary code and a preset quantum compilation system library, performing circuit synthesis processing based on the target quantum logic gate sequence to obtain a target quantum circuit instruction; inputting the target quantum circuit instruction into a quantum acceleration device to obtain a target quantum execution result output by the quantum acceleration device;

[0037] Among them, the quantum compilation system library includes the correspondence between quantum binary codes and quantum logic gate sequences.

[0038] In a fifth aspect, the present application further provides a computer program product, comprising a computer program, which, when executed by a processor, implements the following steps:

[0039] Obtaining a hybrid code to be executed, where the hybrid code includes a classical code and a quantum code;

[0040] Compile the mixed code using a classical compiler to obtain a target main program, which includes a target classical binary code and a target quantum binary code;

[0041] executing a target main program, wherein, when executing a target quantum binary code in the target main program, obtaining a target quantum logic gate sequence corresponding to the quantum binary code based on the target quantum binary code and a preset quantum compilation system library, performing circuit synthesis processing based on the target quantum logic gate sequence to obtain a target quantum circuit instruction; inputting the target quantum circuit instruction into a quantum acceleration device to obtain a target quantum execution result output by the quantum acceleration device;

[0042] Among them, the quantum compilation system library includes the correspondence between quantum binary codes and quantum logic gate sequences.

[0043] The above-mentioned quantum hybrid code execution method, system, device, medium and product obtain a hybrid code including classical code and quantum code to be executed, compile the hybrid code through a classical compiler, obtain a target main program including target classical binary code and target quantum binary code, and execute the target main program. When the target quantum binary code in the target main program is executed, the target quantum logic gate sequence corresponding to the quantum binary code is obtained based on the target quantum binary code and a preset quantum compilation system library. The target quantum circuit instruction is input into the quantum acceleration device to obtain the target quantum execution result output by the quantum acceleration device. The quantum compilation system library includes the correspondence between the quantum binary code and the quantum logic gate sequence. In this way, by directly calling Use a classical compiler to directly compile the mixed code and output the main program in binary code form. During the execution of the main program, the preset quantum compilation system library is linked to convert the quantum part in the main program into a logical quantum gate sequence for circuit synthesis, and the target quantum circuit instructions that can be prepared by the quantum acceleration device hardware are output to control the quantum hardware acceleration device to obtain the target quantum execution result. In this way, only the classical compiler is called during the compilation stage, and the quantum code part dynamically calls the quantum compilation system library and circuit synthesis according to the compiled binary code during the execution process to generate the target quantum circuit instructions. From the perspective of programming model and compiler, the compilation environment of classical computing and quantum computing is unified, the compilation efficiency is improved, and the execution efficiency of quantum hybrid code is thereby improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0045] Figure 1 A diagram illustrating an application environment of a quantum hybrid code execution method according to an embodiment;

[0046] Figure 2 1 is a flow chart of a method for executing a quantum hybrid code according to an embodiment;

[0047] Figure 3 1 is a flow chart of steps for obtaining target quantum circuit instructions in one embodiment;

[0048] Figure 4 A block diagram of a quantum hybrid code execution system according to an embodiment;

[0049] Figure 5 A structural block diagram of a quantum hybrid code execution system in another embodiment;

[0050] Figure 6 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0052] The quantum hybrid code execution method provided in the embodiment of the present application can be applied to Figure 1 In the application environment shown, a classical computer device 102 is communicatively connected to a quantum accelerator device 104. The classical computer device 102 compiles and executes a hybrid code including a quantum code, outputs a quantum circuit based on the quantum code portion of the hybrid code, and executes the quantum circuit through the quantum accelerator device 104 to obtain a quantum execution result corresponding to the quantum code portion.

[0053] The classical computer device 102 may include, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices may include smart speakers, smart TVs, smart air conditioners, and smart car devices. Portable wearable devices may include smart watches, smart bracelets, and head-mounted devices. The quantum accelerator 104 may be a quantum measurement and control instrument.

[0054] In an exemplary embodiment, Figure 2 As shown, a quantum hybrid code execution method is provided, which is applied to Figure 1 Taking the classic computer device 102 in FIG. 1 as an example, the method includes the following steps 202 to 206. Among them:

[0055] Step 202: Obtain a hybrid code to be executed, where the hybrid code includes a classical code and a quantum code.

[0056] Among them, classical code refers to the part of the hybrid code that performs calculations and data processing according to classical physical logic, and quantum code refers to the part of the hybrid code that performs calculations and data processing according to quantum physical logic. From a programming perspective, quantum programs in related technologies are generally a hybrid code form of classical and quantum codes. When executing quantum programs, classical programs are generally required as computing support.

[0057] In one possible implementation, the classical code and the quantum code can be implemented using the same programming language, and the quantum code portion can be implemented using the same programming language. Exemplarily, both the classical code and the quantum code are written in Python, and hardware calls are distinguished through the language framework's API (Application Programming Interface).

[0058] In one possible implementation, the classical code and the quantum code can be implemented using different programming languages. For example, the classical code portion of the hybrid code can be written in Python or a traditional programming language such as C or C++. The quantum code in the hybrid code can be written in a quantum-specific programming language such as Q# or OpenQASM, and the quantum code and the classical code interact through an interface.

[0059] Step 204 : compile the mixed code using a classical compiler to obtain a target main program, where the target main program includes a target classical binary code and a target quantum binary code.

[0060] Exemplarily, the classic compiler may be a GCC (GNU Compiler Collection) compiler, a Python compiler, an LLVM (Low Level Virtual Machine) compiler, or other classic compilers.

[0061] Among them, the classical code part is directly compiled into executable binary code through a classical compiler; the target classical binary code can be directly executed by calling the computing process; the quantum code part is compiled into an intermediate representation in binary code form through a classical compiler, which serves as a common interface between the quantum code and the quantum hardware platform.

[0062] Exemplarily, the format of the target main program is elf format.

[0063] For example, Quantum Intermediate Representation (QIR) is an intermediate representation that serves as a universal interface between quantum programming languages / frameworks and target quantum computing platforms.

[0064] Step 206: Execute the target main program. When the target quantum binary code in the target main program is executed, a target quantum logic gate sequence corresponding to the quantum binary code is obtained based on the target quantum binary code and a preset quantum compilation system library. Circuit synthesis processing is performed based on the target quantum logic gate sequence to obtain a target quantum circuit instruction. The target quantum circuit instruction is input into the quantum acceleration device to obtain a target quantum execution result output by the quantum acceleration device.

[0065] The quantum compilation system library includes the correspondence between quantum binary codes and quantum logic gate sequences. In other embodiments of the present application, the quantum compilation system library can also be called a quantum compilation dynamic library.

[0066] A quantum logic gate sequence refers to a circuit of quantum gates. The quantum accelerator performs quantum calculations after receiving operation instructions based on quantum gates.

[0067] In one possible implementation, the quantum compilation system library can be determined based on different quantum acceleration device hardware platforms. In one possible implementation, the quantum compilation system library can be determined based on different quantum instruction sets.

[0068] In one possible implementation, circuit synthesis processing is performed based on a target quantum logic gate sequence to obtain target quantum circuit instructions, including: determining a physical qubit topology corresponding to a quantum accelerator device, and generating target quantum circuit instructions that can operate the quantum accelerator device based on the physical qubit topology and the target quantum logic gate sequence. Exemplarily, the circuit synthesis processing includes inserting a SWAP operation based on the quantum native gate.

[0069] Among them, physical quantum bit topology refers to the topological relationship between quantum bits in the quantum acceleration device.

[0070] In one possible implementation, please refer to Figure 3 The process of performing circuit synthesis processing based on the target quantum logic gate sequence to obtain the target quantum circuit instruction includes steps 302 to 306, wherein:

[0071] Step 302: Input the quantum logic gate sequence into the quantum bit virtual layer to obtain the logical quantum bit information output by the quantum bit virtual layer.

[0072] Among them, the quantum bit virtual layer is set in the operating system of the classical computer device 102, and the physical quantum bits in the quantum acceleration device are virtually abstractly described through the operating system of the classical computer device 102, so as to provide the physical quantum bits with relatively stable quality state in the quantum acceleration device to the compilation environment to carry out the compilation of quantum codes.

[0073] The qubit virtual layer includes virtual qubit topology, which outputs logical qubit information based on the quantum logic gate sequence and the virtual qubit topology. The virtual qubit topology refers to the topological relationship between virtual qubits.

[0074] Step 304: perform arrangement processing based on the logical quantum bit information and the virtual bit mapping relationship corresponding to the quantum bit virtual layer to obtain the arranged quantum bit information.

[0075] In one possible implementation of the present application, a virtual qubit corresponds to a physical qubit with a better quality state among the physical qubits. In this possible implementation, the provided quantum hybrid code execution method further includes obtaining quality state data for each physical qubit in the quantum acceleration device, and determining a virtual bit mapping relationship based on the quality state data for each physical qubit.

[0076] Exemplarily, the quality status data includes the fidelity of the physical qubit and / or the decoherence time of the physical qubit. Exemplarily, the physical qubits whose fidelity is greater than a preset fidelity threshold are marked as virtual qubits; or, the physical qubits whose decoherence time is less than a preset decoherence time are marked as virtual qubits; or, the physical qubits obtained are sorted according to their fidelity, and a preset number of physical qubits with better fidelity values are marked as virtual qubits. In the embodiments of the present application, other exemplary methods can optionally be used to determine virtual qubits based on the quality data.

[0077] Exemplarily, the quality status data includes quantum volume or gate error rate.

[0078] In one implementation of this possible embodiment, virtual bit mapping information is determined based on the state data of each physical qubit, including: determining the virtual qubit that executes the calculation process from each physical qubit based on the quality state data of each physical qubit; and obtaining the virtual bit mapping relationship based on the positional relationship of the virtual qubit relative to each physical qubit.

[0079] Exemplarily, the quantum acceleration device includes 10 physical quantum bits, and the indices between the physical quantum bits are 0, 1, 2, ..., 9 respectively; when the quality states of the physical quantum bits with indices 1 and 2 are detected, the quantum bit virtual layer provides 8 bits with indices 0 and 3 to 9 to the compilation environment for use, and the indices presented by each virtual quantum bit in the quantum bit virtual layer are 0, 1, 2, ..., 7 respectively, wherein the virtual bit mapping relationship includes: the virtual quantum bit with index 0 corresponds to the physical quantum bit with index 0 in the quantum acceleration device, the virtual quantum bit with index 1 corresponds to the physical quantum bit with index 3 in the quantum acceleration device, the virtual quantum bit with index 2 corresponds to the physical quantum bit with index 4 in the quantum acceleration device, and so on.

[0080] The quality status data of each physical qubit is obtained by the classical computer device 102 from the quantum acceleration device 104. For example, a process interrupt mechanism can be used to trigger the acquisition of the quality status data of each physical qubit from the quantum acceleration device 104 at each process interruption to update the virtual bit mapping relationship. Another example is to set a timer to periodically obtain the quality status data of each physical qubit from the quantum acceleration device 104 at a preset duration.

[0081] Step 306: Perform circuit synthesis processing based on the arranged quantum bit information to obtain target quantum circuit instructions.

[0082] Among them, the arranged quantum bit information is the control information corresponding to the physical quantum bit; circuit synthesis processing is performed based on the arranged quantum bit information and the physical quantum bit topology to obtain the target quantum circuit instructions.

[0083] In one possible implementation, the target classical binary code and the target quantum binary code in the target main program are intertwined. For example, steps 1-2 are the classical part, step 3 is the quantum part, and step 4 is the classical part. Step 4 can only be executed based on the processing result of the quantum acceleration device in step 3. Step 5 is the quantum part, and step 5 can only be executed based on the execution result of step 4. Step 6 is the classical part, and so on. During the execution of the target main program, the program is executed serially. When the target classical binary code is executed, the processor in the classical computer device is directly used to execute the target classical binary code. When the target quantum binary code is executed, the quantum acceleration device is called for execution in the manner of obtaining the target quantum execution result corresponding to the target quantum binary code in step 206. Then, subsequent code is executed based on the target quantum execution result.

[0084] Exemplarily, the process of inputting a target quantum circuit instruction into a quantum acceleration device and obtaining a target quantum execution result output by the quantum acceleration device includes: transmitting the target quantum circuit instruction into a quantum acceleration device such as a quantum measurement and control instrument, starting to manipulate quantum bits, and then reading the execution result output by the quantum acceleration device.

[0085] The quantum hybrid code execution method provided in the above embodiment obtains a hybrid code including a classical code and a quantum code to be executed, compiles the hybrid code through a classical compiler, obtains a target main program including a target classical binary code and a target quantum binary code, and executes the target main program. When the target quantum binary code in the target main program is executed, the target quantum logic gate sequence corresponding to the quantum binary code is obtained based on the target quantum binary code and a preset quantum compilation system library. The target quantum circuit instruction is input into the quantum acceleration device to obtain the target quantum execution result output by the quantum acceleration device. The quantum compilation system library includes the correspondence between the quantum binary code and the quantum logic gate sequence. In this way, by directly calling the classical The compiler directly compiles the mixed code and outputs the main program in binary code form. During the execution of the main program, it links to the preset quantum compilation system library to convert the quantum part in the main program into a logical quantum gate sequence for circuit synthesis, and outputs the target quantum circuit instructions that can be prepared by the quantum acceleration device hardware to control the quantum hardware acceleration device to obtain the target quantum execution result. In this way, only the classical compiler is called during the compilation stage. The quantum code part dynamically calls the quantum compilation system library and circuit synthesis according to the compiled binary code during the execution process to generate the target quantum circuit instructions. From the perspective of programming model and compiler, the compilation environment of classical computing and quantum computing is unified, the compilation efficiency is improved, and the execution efficiency of quantum mixed code is thereby improved.

[0086] In the process of performing circuit synthesis processing based on the target logic gate sequence to obtain the target quantum circuit instructions, the physical quantum bits are abstracted by the operating system of the classical computer device at the quantum bit virtual layer and mapped to the virtual quantum bits for calculation. This avoids the situation where the quality of some physical quantum bits in the quantum acceleration device may be unstable. Therefore, the quantum hybrid code execution method provided by the above embodiment can improve the robustness of the quantum execution results.

[0087] In an exemplary embodiment, a quantum hybrid code execution method is provided, wherein the method is applied to Figure 1 The following steps are described using the classic computer device 102 as an example, including the following steps S1 to S3.

[0088] Step S1, obtaining a hybrid code to be executed, where the hybrid code includes a classical code and a quantum code;

[0089] Step S2, compiling the hybrid code using a classical compiler to obtain a target main program, where the target main program includes a target classical binary code and a target quantum binary code;

[0090] Step S3, executing the target main program, wherein when executing the target quantum binary code in the target main program, steps S31 to S32 are executed, wherein:

[0091] Step S31: Based on the target quantum binary code and a preset quantum compilation system library, a target quantum logic gate sequence corresponding to the quantum binary code is obtained.

[0092] Step S32: input the quantum logic gate sequence into the quantum bit virtual layer to obtain the logical quantum bit information output by the quantum bit virtual layer.

[0093] Step S33: performing arrangement processing based on the logical quantum bit information and the virtual bit mapping relationship corresponding to the quantum bit virtual layer to obtain the arranged quantum bit information.

[0094] Optionally, the virtual bit mapping relationship is determined by: obtaining quality state data of each physical qubit in the quantum accelerator; determining a virtual qubit that performs a computation from each physical qubit based on the quality state data of each physical qubit; and obtaining the virtual bit mapping relationship based on the positional relationship of the virtual qubit relative to each physical qubit. The quality state data includes the fidelity of the physical qubit and / or the decoherence time of the physical qubit.

[0095] Step S34: Perform circuit synthesis processing based on the arranged quantum bit information to obtain target quantum circuit instructions.

[0096] Step S35: input the target quantum circuit instruction into the quantum acceleration device to obtain the target quantum execution result output by the quantum acceleration device.

[0097] In the related art, in actual quantum computing, physical quantum bits have many imperfections and noise interference, which will affect the effect and results of quantum computing. The quantum hybrid code execution method provided in the above embodiment uses a virtual quantum bit management architecture to map physical quantum bits to virtual quantum bits through the abstraction of the operating system, and provides a relatively stable virtual quantum bit topology to the compilation environment through the quantum bit virtual layer.

[0098] It should be understood that, although the steps in the flowcharts of the above embodiments are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowcharts of the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily to be performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0099] It should be understood that the term "based on" as used herein is used to describe one or more factors that influence a determination, and does not exclude other factors that may influence the determination. For example, the phrase "determine A based on B" means that the determination of A may be based entirely or at least partially on factor B. In other words, B is a factor that influences the determination of A, but does not exclude the determination of A being based on C as well.

[0100] Based on the same inventive concept, embodiments of the present application also provide a quantum hybrid code execution system for implementing the aforementioned quantum hybrid code execution method. The solution provided by this system is similar to the solution described in the aforementioned method. Therefore, the specific limitations in one or more of the following quantum hybrid code execution system embodiments can be found in the above-mentioned limitations on the quantum hybrid code execution method and will not be further elaborated here.

[0101] In an exemplary embodiment, Figure 4 As shown, a quantum hybrid code execution system is provided for use in a classical computer device 102. The quantum hybrid code execution system includes: a classical compilation system 402 and a runtime system 404, wherein:

[0102] The classical compilation system 402 is configured to obtain a hybrid code to be executed, the hybrid code including a classical code and a quantum code, compile the hybrid code using a classical compiler to obtain a target main program, the target main program including a target classical binary code and a target quantum binary code, and execute the target main program. When executing the target quantum binary code in the target main program, based on the target quantum binary code and a preset quantum compilation system library, a target quantum logic gate sequence corresponding to the quantum binary code is obtained, and the runtime system is called to process the target quantum logic gate sequence, the quantum compilation system library including the correspondence between quantum binary codes and quantum logic gate sequences.

[0103] The runtime system 404 is used to perform circuit synthesis processing based on the target quantum logic gate sequence to obtain target quantum circuit instructions, input the target quantum circuit instructions into the quantum acceleration device, and obtain the target quantum execution result output by the quantum acceleration device.

[0104] By adopting the above-mentioned quantum hybrid code execution system, it is possible to perform real-time circuit synthesis of quantum hybrid code through the classical compilation system and the runtime compilation system during program execution, realize code runtime support, and unify the compilation environment of classical computing and quantum computing from the perspective of programming model and compiler, thereby improving compilation efficiency and thus improving the execution efficiency of quantum hybrid code.

[0105] In an exemplary embodiment, please refer to Figure 5 , the runtime system 404 includes: a quantum bit virtual layer 502, a bit mapping module 504 and a circuit synthesis module 506, wherein:

[0106] The quantum bit virtual layer 502 is used to output logical quantum bit information according to a quantum logic gate sequence.

[0107] For example, the quantum bit virtualization layer can be set as a software module in the operating system of the classical computer device 102.

[0108] The bit mapping module 504 is used to perform arrangement processing based on the logical quantum bit information and the virtual bit mapping relationship corresponding to the quantum bit virtual layer to obtain the arranged quantum bit information.

[0109] The circuit synthesis module 506 is used to perform circuit synthesis processing based on the arranged quantum bit information to obtain the target quantum circuit instructions.

[0110] In an exemplary embodiment, the runtime system further includes a mapping determination module configured to obtain quality status data of each physical quantum bit in the quantum acceleration device; and determine a virtual bit mapping relationship based on the quality status data of each physical quantum bit.

[0111] In an exemplary embodiment, the mapping determination module is used to determine the virtual quantum bit that performs the calculation process from each physical quantum bit based on the quality state data of each physical quantum bit; and obtain the virtual bit mapping relationship based on the positional relationship of the virtual quantum bit relative to each physical quantum bit.

[0112] In an exemplary embodiment, the quality state data of the physical qubit includes the fidelity of the physical qubit and / or the decoherence time of the physical qubit.

[0113] Each module in the aforementioned quantum hybrid code execution system can be implemented in whole or in part through software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in hardware form, or stored in a computer device memory in software form, allowing the processor to call and execute the corresponding operations of each module.

[0114] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as shown in FIG. Figure 6 As shown. The computer device includes a processor, memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals via wired or wireless means, and the wireless means can be achieved via Wi-Fi, mobile cellular networks, NFC (near-field communication), or other technologies. When the computer program is executed by the processor, a quantum hybrid code execution method is implemented. The display unit of the computer device is used to produce a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device casing, or an external keyboard, touchpad or mouse.

[0115] Those skilled in the art will understand that Figure 6 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0116] In one embodiment, a computer device is further provided, including a memory and a processor. The memory stores a computer program, and the processor implements the steps in the above method embodiments when executing the computer program.

[0117] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0118] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0119] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0120] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. In particular, any reference to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchains. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), data processing logic devices based on quantum computing, and the like.

[0121] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0122] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A quantum hybrid code execution method, characterized in that: The method comprises: Obtaining a hybrid code to be executed, wherein the hybrid code includes a classical code and a quantum code; Compiling the hybrid code using a classical compiler to obtain a target main program, wherein the target main program includes a target classical binary code and a target quantum binary code; executing the target main program, wherein, when executing a target quantum binary code in the target main program, obtaining a target quantum logic gate sequence corresponding to the quantum binary code based on the target quantum binary code and a preset quantum compilation system library, performing circuit synthesis processing based on the target quantum logic gate sequence to obtain a target quantum circuit instruction; inputting the target quantum circuit instruction into a quantum acceleration device to obtain a target quantum execution result output by the quantum acceleration device; The quantum compilation system library includes the correspondence between quantum binary codes and quantum logic gate sequences.

2. The method according to claim 1, characterized in that The circuit synthesis processing is performed based on the quantum logic gate sequence to obtain target quantum circuit instructions, including: Inputting the quantum logic gate sequence into a quantum bit virtual layer to obtain logical quantum bit information output by the quantum bit virtual layer; Performing an arrangement process based on the logical quantum bit information and the virtual bit mapping relationship corresponding to the quantum bit virtual layer to obtain arranged quantum bit information; Circuit synthesis processing is performed based on the arranged quantum bit information to obtain the target quantum circuit instruction.

3. The method according to claim 2, characterized in that The method further comprises: Obtaining quality state data of each physical quantum bit in the quantum acceleration device; The virtual bit mapping relationship is determined according to the quality status data of each of the physical quantum bits.

4. The method according to claim 3, characterized in that Determining the virtual bit mapping relationship according to the quality status data of each physical quantum bit includes: Determining a virtual qubit that performs a calculation process from each of the physical qubits based on the quality status data of each of the physical qubits; The virtual bit mapping relationship is obtained based on the positional relationship of the virtual quantum bits relative to the physical quantum bits.

5. The method according to claim 4, characterized in that The quality state data of the physical quantum bit includes the fidelity of the physical quantum bit and / or the decoherence time of the physical quantum bit.

6. A quantum hybrid code execution system, characterized in that: The system includes: a classic compilation system and a runtime system, wherein: The classical compilation system is configured to obtain a hybrid code to be executed, the hybrid code including a classical code and a quantum code, compile the hybrid code using a classical compiler to obtain a target main program, the target main program including a target classical binary code and a target quantum binary code; and execute the target main program. When executing the target quantum binary code in the target main program, based on the target quantum binary code and a preset quantum compilation system library, a target quantum logic gate sequence corresponding to the quantum binary code is obtained, and the runtime system is called to process the target quantum logic gate sequence, the quantum compilation system library including a correspondence between quantum binary codes and quantum logic gate sequences. The runtime system is configured to perform circuit synthesis processing based on the target quantum logic gate sequence to obtain target quantum circuit instructions, input the target quantum circuit instructions into a quantum acceleration device, and obtain a target quantum execution result output by the quantum acceleration device.

7. The system according to claim 6, characterized in that The runtime system includes: A quantum bit virtual layer, configured to output logical quantum bit information according to the quantum logic gate sequence; A bit mapping module is used to perform arrangement processing based on the logical quantum bit information and the virtual bit mapping relationship corresponding to the quantum bit virtual layer to obtain arranged quantum bit information; A circuit synthesis module is used to perform circuit synthesis processing based on the arranged quantum bit information to obtain the target quantum circuit instruction.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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