Gamma circuit, data driving circuit and display panel

Abstract

The embodiment of the invention discloses a gamma circuit, a data driving circuit and a display panel, and the gamma circuit comprises a voltage generation module and a voltage adjustment module, and the voltage generation module is used for generating an initial gamma voltage sequence according to a power voltage and transmitting the initial gamma voltage sequence to the voltage adjustment module. The voltage adjusting module is used for adjusting the voltage of the initial gamma voltage sequence according to a control signal, generating at least two groups of gamma voltage sequences and respectively transmitting different gamma voltage sequences to different data driving circuits, the control signal is received from the time sequence control circuit, and the time sequence control circuit is connected with the data driving circuit. The gamma voltage sequences are used for being matched with the data signals to control the data driving circuits to output the data voltages to the pixel units in the display area, and the problem that the brightness of the pixel units is insufficient due to the fact that the scanning signals are pulled down in advance can be compensated by providing the different gamma voltage sequences to the different data driving circuits.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gamma circuit, a data driving circuit and a display panel. Background Art

[0002] With the development of display technology, the size and refresh rate of display panels have gradually increased, and the scan lines have become longer and longer. The scan signal will be delayed due to the low-pass filtering effect after passing through a certain length of scan line. Due to the delay in the falling edge of the scan signal, the data signal corresponding to the second row of pixels has not yet dropped to the TFT off voltage, causing the data signal corresponding to the second row of pixels to be mistakenly charged to the first row of pixels, resulting in poor display effect. The existing solution is to control the first row of scan signals to be pulled down in advance to avoid mischarging of data signals. However, because the delay of the scan signal in the middle of the display panel is higher than the delay on the two sides of the display panel, pulling down the scan signal in advance will cause the two sides of the display panel to receive the data signal for a shorter time, resulting in insufficient charging, which in turn leads to insufficient brightness in the display areas on both sides.

[0003] Therefore, how to avoid insufficient pixel brightness on both sides of the display panel caused by mischarging is an urgent problem that needs to be solved. Summary of the Invention

[0004] In view of the above-mentioned deficiencies in the prior art, the present application provides a gamma circuit, a data driving circuit and a display panel that can effectively compensate for insufficient pixel brightness caused by premature pull-down of a scan signal.

[0005] An embodiment of the present application provides a gamma circuit, including a voltage generating module and a voltage adjusting module, wherein the voltage generating module is used to generate an initial gamma voltage sequence based on a power supply voltage and transmit the initial gamma voltage sequence to the voltage adjusting module, and the voltage adjusting module is used to adjust the voltage of the initial gamma voltage sequence based on a control signal and generate at least two groups of gamma voltage sequences, and transmit different gamma voltage sequences to different data driving circuits, respectively, wherein the control signal is received from a timing control circuit, and the gamma voltage sequences are used to cooperate with the data signal to control the data driving circuit to output data voltages to pixel units in a display area.

[0006] Optionally, the voltage adjustment module includes an amplifier, a first resistor, a second resistor, a first adjustment unit, a second adjustment unit and a third adjustment unit, the first resistor is electrically connected between the inverting end and the output end of the amplifier, the second resistor is electrically connected between the non-phase end of the amplifier and the voltage generating module, the first adjustment unit, the second adjustment unit and the third adjustment unit are connected in parallel between the ground end and the inverting end of the amplifier; the first adjustment unit is used to cooperate with the amplifier to adjust the initial gamma voltage to a first gamma voltage sequence, the second adjustment unit is used to cooperate with the amplifier to adjust the initial gamma voltage to a second gamma voltage sequence, and the third adjustment unit is used to cooperate with the amplifier to adjust the initial gamma voltage to a third gamma voltage sequence.

[0007] Optionally, the first gamma voltage sequence, the second gamma voltage sequence, and the third gamma voltage sequence each include a first gamma voltage, a second gamma voltage, a third gamma voltage, and a fourth gamma voltage, the first gamma voltage and the fourth gamma voltage are symmetrical about a center reference voltage, the second gamma voltage and the third gamma voltage are symmetrical about the center reference voltage, the first gamma voltage and the second gamma voltage are used to cooperate to generate a data signal of a positive polarity, the third gamma voltage and the fourth gamma voltage are used to cooperate to generate a data signal of a negative polarity, and the difference between the first gamma voltage and the center reference voltage is greater than the difference between the second gamma voltage and the center reference voltage; in the first gamma voltage sequence, the difference between the first gamma voltage and the center reference voltage is a first gamma voltage difference, in the second gamma voltage sequence, the difference between the first gamma voltage and the center reference voltage is a second gamma voltage difference, and in the third gamma voltage sequence, the difference between the first gamma voltage and the center reference voltage is a third gamma voltage difference, wherein the first gamma voltage difference is greater than the second gamma voltage difference, and the second gamma voltage difference is greater than the third gamma voltage difference.

[0008] Optionally, the first adjustment unit includes a first switch tube and a third resistor, the second adjustment unit includes a second switch tube and a fourth resistor, and the third adjustment unit includes a third switch tube, wherein the control end of the first switch tube is electrically connected to the timing control circuit, the first conductive end of the first switch tube is electrically connected to the ground end, the second conductive end of the first switch tube is electrically connected to the first end of the third resistor, and the second end of the third resistor is electrically connected to the inverting end of the amplifier; the control end of the second switch tube is electrically connected to the timing control circuit, the first conductive end of the second switch tube is electrically connected to the ground end, the second conductive end of the second switch tube is electrically connected to the first end of the fourth resistor, and the second end of the fourth resistor is connected to the inverting end of the amplifier; the control end of the third switch tube is electrically connected to the timing control circuit, and the first conductive end of the third switch tube is electrically connected to In the timing control circuit, the first conductive end of the third switching tube is electrically connected to the ground end, and the second conductive end of the third switching tube is electrically connected to the inverting end of the amplifier, wherein the resistance of the third resistor is greater than the resistance of the fourth resistor; the first switching tube is turned on according to a first control signal to control the third resistor to be electrically connected to the inverting end of the amplifier, and the first resistor and the third resistor cooperate with the amplifier to adjust the initial gamma voltage sequence to obtain a first gamma voltage sequence; the second switching tube is turned on according to a second control signal to control the fourth resistor to be electrically connected to the inverting end of the amplifier, and the first resistor and the fourth resistor cooperate with the amplifier to adjust the initial gamma voltage sequence to obtain the second gamma voltage sequence; the third switching tube is turned on according to a third control signal to use the initial gamma voltage sequence as the third gamma voltage sequence.

[0009] An embodiment of the present application also provides a data driving circuit, which is used to receive an initial data signal and a control signal from a timing control circuit and a gamma voltage sequence from a gamma circuit, and output a corresponding data voltage to a pixel unit in a display area, wherein the data driving circuit includes an input control module and a logic processing module, wherein the input control module is used to receive the initial data signal and the control signal, and receive the gamma voltage sequence under the control of the control signal, and transmit the initial data signal and the gamma voltage sequence to the logic processing module, wherein the logic processing module generates a grayscale data signal based on the initial data signal and the gamma voltage sequence, and the grayscale data signal is used to form the data voltage.

[0010] Optionally, the input control module includes a fourth switch tube and a first capacitor, the control end of the fourth switch tube is electrically connected to the timing control circuit, the first conductive end of the fourth switch tube is electrically connected to the gamma circuit, the second conductive end of the fourth switch tube is electrically connected to the logic processing module, and the first capacitor is electrically connected between the ground end and the second conductive end of the fourth switch tube; the fourth switch tube is used to be turned on according to the control signal output by the timing control circuit to transmit the gamma voltage sequence output by the gamma circuit to the logic control module.

[0011] An embodiment of the present application further provides a display panel, wherein a non-display area of the display panel comprises a timing control circuit, a gamma circuit as described in claims 1-4, and a plurality of data driving circuits as described in claims 5-6, wherein the timing control circuit controls the data driving circuit to output a data signal comprising a continuous first period, a second period, and a third period, and the plurality of data driving circuits comprise a first data driving circuit, a second data driving circuit, and a third data driving circuit; in the first period, the timing control circuit outputs a first control signal to the gamma circuit and the data driving circuit, and the gamma circuit outputs a first gamma voltage sequence according to the first control signal, and a first The data driving circuit receives the first gamma voltage sequence according to the first control signal; in the second time period, the timing control circuit outputs a second control signal to the gamma circuit and the data driving circuit, the gamma circuit outputs a second gamma voltage sequence according to the second control signal, and the second data driving circuit receives the second gamma voltage sequence according to the second control signal; in the third time period, the timing control circuit outputs a third control signal to the gamma circuit and the data driving circuit, the gamma circuit outputs a third gamma voltage sequence according to the third control signal, and the third data driving circuit receives the third gamma voltage sequence according to the third control signal.

[0012] Optionally, the display area of the display panel includes a first sub-display area, a second sub-display area and a third sub-display area, and the first sub-display area, the second sub-display area and the third sub-display area are arranged in sequence from the edge of the display area to the middle of the display area, the first data driving circuit is used to control the first sub-display area to display an image according to the first gamma voltage sequence, the second data driving circuit is used to control the second sub-display area to display an image according to the second gamma voltage sequence, and the third data driving circuit is used to control the third sub-display area to display an image according to the third gamma voltage sequence.

[0013] Optionally, the timing control circuit adjusts the first gamma voltage to obtain a first gamma voltage subdivision sequence and a second gamma voltage subdivision sequence, the first sub-display area includes a first partition and a second partition, the data driving circuit controls the first partition to display an image according to the first gamma voltage subdivision sequence, and controls the second partition to display an image according to the second gamma voltage subdivision sequence, the first partition is located at the edge of the display area, and the second partition is adjacent to the second sub-display area.

[0014] Optionally, the first gamma voltage subdivision sequence and the second gamma voltage subdivision sequence both include a fifth gamma voltage, the fifth gamma voltage is located between the first gamma voltage and the second gamma voltage, in the first gamma voltage subdivision sequence, the difference between the fifth gamma voltage and the first gamma voltage is a first voltage difference, and in the second gamma voltage subdivision sequence, the difference between the fifth gamma voltage and the first gamma voltage is a second voltage difference, and the first voltage difference is less than the second voltage difference.

[0015] Compared with the problems in the prior art, the embodiments of the present application adjust the initial gamma voltage sequence to generate at least two groups of gamma voltage sequences and provide them to different data driving circuits, so that the pixel units in different display areas can be controlled by the data driving circuit to display different brightness at the same grayscale, thereby effectively solving the problem of brightness reduction of the pixel units due to insufficient charging. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A schematic structural diagram of a display device provided in the first embodiment of the present application; Figure 2 for Figure 1 A schematic diagram of the side structure of the display panel; Figure 3 for Figure 2 A schematic diagram of the planar layout structure of the array substrate; Figure 4 for Figure 3 Schematic diagram of the logic for generating medium gamma voltage; Figure 5 for Figure 3 Schematic diagram of voltage adjustment of the gamma circuit and data drive circuit; Figure 6 An embodiment of the present application provides a Figure 4 Schematic diagram of the circuit architecture of the mid-gamma circuit; Figure 7 is a voltage schematic diagram of each gamma voltage sequence; Figure 8 for Figure 6 Schematic diagram of the equivalent circuit of the medium voltage adjustment module; Figure 9 It is a timing diagram of the control signal output of the timing control circuit; Figure 10 for Figure 4 Figure 2 is a circuit block diagram of a data driving circuit; Figure 11 for Figure 10 Equivalent circuit diagram of the input control module; Figure 12 This is a schematic diagram of the gamma voltage subdivision sequence; Figure 13 This is a logic diagram of the working process of the gamma voltage subdivision sequence.

[0018] Explanation of the accompanying symbols: display device-100, display panel-10, power supply module-20, supporting frame 30, display area-10a, timing control circuit-11, data driving circuit-12, scan driving circuit-13, gamma circuit-14, pixel unit-P, backlight module-17, array substrate-10c, liquid crystal layer-10e, color filter substrate-10d, first direction-F1, second direction-F2, data line-S, scan line-G, data driving circuit-12, first data driving circuit 12a, second data driving circuit 12b, third data driving circuit 12c, fourth data driving circuit 12d, fifth data driving circuit 12e, sixth data driving circuit 12f, input control module 121, logic processing module 122, shift register module 123, data latch module 124, analog-to-digital conversion module 125, output buffer module 126, first sub-display area a, second sub-display area b, third sub-display area c, fourth sub-display area d , fifth sub-display area-e, sixth sub-display area-f, center line-L, power supply voltage-AVDD, first gamma voltage-GM1, second gamma voltage-GM7, third gamma voltage-GM8, fourth gamma voltage-GM14, fifth gamma voltage-GM5, voltage generating module-141, voltage adjusting module-142, output control module-143, first adjusting unit-142a, second adjusting unit-142b, third adjusting unit-142c, amplifier-OP, first resistor-R 1. Second resistor R2, third resistor R3, fourth resistor R4, first switch Q1, second switch Q2, third switch Q3, ground GND, fourth switch Q4, first capacitor C1, first gamma voltage difference VM1, second gamma voltage difference VM2, third gamma voltage difference VM3, first control signal K1, second control signal K2, third control signal K3, data signal Data, first voltage difference V1, second voltage difference V2. DETAILED DESCRIPTION

[0019] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0020] The following descriptions of the embodiments are made with reference to the accompanying drawings to illustrate specific embodiments that may be implemented in accordance with the present application. The serial numbers assigned to the components herein, such as "first," "second," etc., are merely used to distinguish the objects being described and do not have any sequential or technical meaning. References to "connection" and "coupling" in this application include both direct and indirect connections (couplings) unless otherwise specified. Directional terms mentioned in this application, such as "upper," "lower," "front," "back," "left," "right," "inner," "outer," and "side," are merely referenced to the directions in the accompanying drawings. Therefore, the directional terms used are intended to better and more clearly illustrate and understand this application, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be construed as limiting this application.

[0021] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be internal communication between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances. It should be noted that the terms "first", "second", etc. in the description, claims, and drawings of this application are used to distinguish different objects, rather than to describe a specific order.

[0022] In addition, the terms "include", "may include", "include", or "may include" used in this application indicate the existence of the corresponding functions, operations, elements, etc. disclosed, and do not limit one or more other functions, operations, elements, etc. In addition, the terms "include" or "include" indicate the existence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, and do not exclude the existence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusions. In addition, when describing the embodiments of the present application, "may" is used to indicate "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0024] See also Figure 1 , Figure 1This is a schematic diagram of the structure of a display device provided in the first embodiment of the present application. The display device 100 includes a display panel 10, a power module 20, and a support frame 30. The display panel 10 and the power module 20 are fixed to the support frame 30. The power module 20 is located on the back side of the display panel 10, i.e., the non-display side of the display panel 10. The power module 20 is used to provide the power supply voltage for the display panel 10 to display images. The support frame 30 provides a secure and protective function for the display panel 10 and the power module 20.

[0025] In other embodiments of the present application, the display device 100 may not need to be provided with a support frame 30 , for example, it is a portable electronic device such as a mobile phone, a tablet computer, etc.

[0026] See also Figure 2 , Figure 2 for Figure 1 Schematic diagram of the side structure of the display panel.

[0027] The display panel 10 includes an array substrate 10c, a color filter substrate 10d, and a liquid crystal layer 10e sandwiched between the array and color filter substrates 10c and 10d. Drivers mounted on the array and color filter substrates 10c and 10d generate electric fields based on data signals, thereby rotating the liquid crystal molecules in the liquid crystal layer 10e to emit light of a corresponding brightness, thereby displaying images.

[0028] In this embodiment, the display panel 10 may be a liquid crystal display panel or other types of display panels, which is not limited in this application.

[0029] Taking a liquid crystal display panel as an example, the display panel 10 also includes a backlight module (BM) 17. The BM 17 is used to provide light for display to the display area 10a of the display panel 10. The display panel 10 emits light corresponding to the image signal to be displayed to perform image display. The display panel 10 also includes other components or elements, such as a signal processing module and a signal sensing module.

[0030] See also Figure 3 , Figure 3 for Figure 2 Schematic diagram of the planar layout structure of the array substrate.

[0031] like Figure 3As shown, corresponding to the display area 10a of the display panel 10, the array substrate 10c is provided with a plurality of data lines S and a plurality of scan lines G arranged in a grid pattern. The plurality of scan lines G extend along a first direction F1 and are sequentially arranged along a second direction F2. The plurality of data lines extend along the second direction F2 and are sequentially arranged along the first direction. The first direction F1 and the second direction F2 are perpendicular to each other. Pixel units P are correspondingly provided at the intersections of the plurality of scan lines G and the plurality of data lines S.

[0032] The non-display area of the display panel 10 is also provided with a timing control circuit 11, a data driver circuit 12, a scan driver circuit 13, and a gamma circuit 14. The timing control circuit 11 receives an image signal representing image information, a synchronization clock signal CLK, a horizontal synchronization signal, and a vertical synchronization signal from an external signal source, and outputs a gate output control signal for the scan driver circuit 13, a source output control signal for the data driver circuit 12, and a data signal representing image information. The scan driver circuit 13 is configured to output a scan signal to the pixel unit P to control the pixel unit P to receive a data signal from the data driver circuit 12 for image display. The gamma circuit 14 is configured to provide a reference voltage to the data driver circuit 12, which then outputs data signals of varying grayscale based on the reference voltage.

[0033] In this embodiment, the display area 10a includes multiple display areas and multiple data driving circuits 12, wherein each data driving circuit 12 corresponds to one display area. The data driving circuit 12 is used to output data signals to the pixel units P in the corresponding display area to control the display area to display images.

[0034] For example, the display area 10a includes six display areas, which may be the first sub-display area a, the second sub-display area b, the third sub-display area c, the fourth sub-display area d, the fifth sub-display area e and the sixth sub-display area f, respectively. The first sub-display area a and the fourth sub-display area d are symmetrical about the center line L, the first sub-display area a and the fourth sub-display area d are respectively arranged adjacent to the scan driving circuit 13 on both sides, the second sub-display area b and the fifth sub-display area e correspond to the center line L, the second sub-display area b is arranged adjacent to the first sub-display area a along the first direction F1, the fifth sub-display area e is arranged adjacent to the fourth sub-display area d along the first direction F1, the third sub-display area c and the sixth sub-display area f are symmetrical about the center line L, and the third sub-display area c and the sixth sub-display area f are adjacent to each other, that is, the fifth sub-display area and the sixth sub-display area f are the middle area of the display area 10a.

[0035] At the same time, the display panel 10 includes six data driving circuits, namely a first data driving circuit 12a, a second data driving circuit 12b, a third data driving circuit 12c, a fourth data driving circuit 12d, a fifth data driving circuit 12e and a sixth data driving circuit 12f. Among them, the first data driving circuit 12a to the sixth data driving circuit 12f correspond to the first sub-display area a to the sixth sub-display area f, respectively, and are used to control the first sub-display area a to the sixth sub-display area f to display images.

[0036] Due to the low-pass filtering effect, the scanning signal is delayed. The scanning signal delay in the middle position of the display area 10a, that is, the third sub-display area c and the sixth sub-display area f, is greater. The closer to the scanning drive circuit 13, that is, the first sub-display area a and the fourth sub-display area d, the smaller the delay. Therefore, in order to avoid the delay of the scanning signal causing the data signal corresponding to the pixel unit in the next row to be mischarged into the pixel unit in the previous row, it is usually pulled down in advance. Pulling down the scanning signal can effectively avoid the mischarging of the data signal in the third sub-display area c and the sixth sub-display area f, but the delay is small when the scanning signal is transmitted to the first sub-display area a and the fourth sub-display area f. Pulling down the scanning signal in advance will cause the edge areas, that is, the first sub-display area a and the fourth sub-display area d, to have insufficient charging time, resulting in poor display effects. Based on this, an embodiment of the present application provides a gamma circuit that can effectively avoid the problem of poor display effects caused by insufficient charging. Please also refer to Figure 4 and Figure 5 , Figure 4 for Figure 3 Schematic diagram of the logic of gamma voltage generation. Figure 5 for Figure 3 Schematic diagram of voltage adjustment for the gamma circuit and data driver circuit.

[0037] like Figure 4 and Figure 5 As shown, the gamma circuit 14 outputs a first gamma voltage GM1, a second gamma voltage GM7, a third gamma voltage GM8, and a fourth gamma voltage GM14 based on the power supply voltage AVDD. The first gamma voltage GM1 and the fourth gamma voltage GM14 are respectively the positive and negative voltages when the display panel 10 displays full white, corresponding to grayscale 255. The second gamma voltage GM7 and the third gamma voltage GM8 are respectively the positive and negative voltages when the display panel displays full black, corresponding to grayscale 0. The other grayscales, i.e., grayscales 1 to 254, are generated by the data driving circuit 12 based on the first gamma voltage GM1 to the fourth gamma voltage GM14. The first gamma voltage GM1 and the fourth gamma voltage GM14 are symmetrical about a central reference voltage GM0, and the second gamma voltage GM7 and the third gamma voltage GM8 are symmetrical about the central reference voltage GM0. The central reference voltage GM0 is a common voltage.

[0038] Specifically, the gamma circuit 14 includes a plurality of resistors R connected in series, and is used to divide the received power supply voltage AVDD into the required gamma voltages, i.e., the first gamma voltage GM1 to the fourth gamma voltage GM14, through the plurality of resistors R. The data driving circuit 12 includes a plurality of resistors R connected in series, and is used to divide the received gamma voltages into the plurality of resistors R to generate a plurality of different grayscale voltages, wherein a positive polarity grayscale voltage of 0 to a grayscale voltage of 255 is generated according to the first gamma voltage GM1 and the second gamma voltage GM7, and a negative polarity grayscale voltage of 0 to a grayscale voltage of 255 is generated according to the third gamma voltage GM8 and the fourth gamma voltage GM14, that is, n data signals Data1 to Datan are generated.

[0039] See also Figure 6 , Figure 6 An embodiment of the present application provides a Figure 4 Schematic diagram of the circuit architecture of the mid-gamma circuit.

[0040] like Figure 6 As shown, the gamma circuit 14 includes a voltage generating module 141 and a voltage adjusting module 142, wherein the voltage generating module 141 is used to generate an initial gamma voltage sequence, i.e., a first gamma voltage GM1 to a fourth gamma voltage GM14, according to a power supply voltage, and transmit the initial gamma voltage to the voltage adjusting module 142. The voltage adjusting module 142 is used to adjust the initial gamma voltage sequence according to a control signal output by the timing control circuit 11, and generate at least two groups of gamma voltage sequences, and provide different gamma voltage sequences to different data driving circuits 12. The gamma voltage sequences are used to cooperate with the data signals to control the data driving circuit 12 to output data voltages to the pixel units P in the display area. Furthermore, according to the division of the display area 10a, the voltage adjustment module 142 generates different gamma voltage sequences respectively. That is, the number of gamma voltage sequences can be adjusted according to the number of display areas in the display area 10a. For example, three gamma voltage sequences can be generated corresponding to the first sub-display area a, the second sub-display area b, and the third sub-display area c, which can be the first gamma voltage sequence GS1 ( Figure 7 ), the second gamma voltage sequence GS2 ( Figure 7 ) and the third gamma voltage sequence GS3 ( Figure 7), wherein the first gamma voltage sequence GS1 is output to the first data driving circuit 12a to control the first sub-display area a to display an image, the second gamma voltage sequence GS2 is output to the second data driving circuit 12b to control the second sub-display area b to display an image, and the third gamma voltage sequence GS3 is output to the third data driving circuit 12c to control the third sub-display area c to display an image. Similarly, since the fourth sub-display area d, the fifth sub-display area e, and the sixth sub-display area f are symmetrically arranged with the first sub-display area a, the second sub-display area b, and the third sub-display area c, respectively, the first gamma voltage sequence GS1, the second gamma voltage sequence GS2, and the third gamma voltage sequence GS3 can also be provided to the fourth data driving circuit 12d, the fifth data driving circuit 12e, and the sixth data driving circuit 12f, respectively, to control the fourth sub-display area d, the fifth sub-display area e, and the sixth sub-display area f to display an image, respectively.

[0041] like Figure 7 As shown, Figure 7 Schematic diagram of the voltage of each gamma voltage sequence.

[0042] The differences between the first gamma voltage GM1, the second gamma voltage GM2, the third gamma voltage GM3 and the fourth gamma voltage GM4 in the first gamma voltage sequence GS1 and the central reference voltage GM0 are all greater than the differences between the first gamma voltage GM1, the second gamma voltage GM2, the third gamma voltage GM3 and the fourth gamma voltage GM4 in the second gamma voltage sequence GS2 and the central reference voltage GM0, and the differences between the first gamma voltage GM1, the second gamma voltage GM2, the third gamma voltage GM3 and the fourth gamma voltage GM4 in the second gamma voltage sequence GS2 and the central reference voltage GM0 are all greater than the differences between the first gamma voltage GM1, the second gamma voltage GM2, the third gamma voltage GM3 and the fourth gamma voltage GM4 in the third gamma voltage sequence GS3 and the central reference voltage GM0.

[0043] For example, in the first gamma voltage sequence GS1, the voltage difference between the first gamma voltage GM1 and the center reference voltage GM0 is a first gamma voltage difference VM1, in the second gamma voltage sequence GS2, the voltage difference between the first gamma voltage GM1 and the center reference voltage GM0 is a second gamma voltage difference VM2, and in the third gamma voltage sequence GS3, the voltage difference between the first gamma voltage GM1 and the center reference voltage GM0 is a third gamma voltage difference VM3, wherein the first gamma voltage difference VM1 is greater than the second gamma voltage difference VM2, and the second gamma voltage difference VM2 is greater than the third gamma voltage difference VM3.

[0044] The first gamma voltage sequence GS1 to the third gamma voltage sequence GS3 are obtained by adjusting the initial gamma voltage, and the first sub-display area a to the third sub-display area c are respectively controlled to display images according to the first gamma voltage sequence GS1 to the third gamma voltage sequence GS3. Since the first gamma voltage difference VM1, the second gamma voltage difference VM2 and the third gamma voltage difference decrease in sequence, at the same gray scale, the brightness of the first sub-display area a is greater than the brightness of the second sub-display area b, and the brightness of the second sub-display area b is greater than the brightness of the third sub-display area c, that is, the brightness of the first sub-display area a to the third sub-display area c decreases in sequence, which effectively compensates for the sequential increase in the brightness of the first sub-display area a to the third sub-display area c due to the early pull-down of the scan signal, thereby making the brightness of the first sub-display area a to the third sub-display area c consistent.

[0045] In this embodiment, the first to third sub-display areas a to c are symmetrical with the fourth to sixth sub-display areas d to f, respectively. Therefore, the first to third gamma voltage sequences GS1 to GS3 can also control the fourth to sixth sub-display areas d to f to display the same image. Of course, the gamma voltage sequence can also be adjusted according to the specific conditions of the display panel. For example, when the first to sixth sub-display areas a to d are controlled by the same scan drive circuit, the brightness of the first sub-display area a is the lowest and the brightness of the sixth sub-display area f is the highest due to the early pull-down of the scan signal. At this time, the gamma voltage sequence output to the first to sixth data drive circuits 12a to 12f can be adjusted by the same method to make the brightness of the first to sixth sub-display areas a to d consistent.

[0046] Please also refer to Figure 8 and Figure 9 , Figure 8 for Figure 6 Equivalent circuit diagram of the medium voltage adjustment module, Figure 9 This is the control signal output timing diagram of the timing control circuit.

[0047] like Figure 8 As shown, the voltage adjustment module 142 includes an amplifier OP, a first resistor R1, a second resistor R2, a first adjustment unit 142a, a second adjustment unit 142b, and a third adjustment unit 142c. The first resistor R1 is electrically connected between the inverting terminal and the output terminal of the amplifier OP, and the second resistor is electrically connected to the non-inverting terminal of the amplifier OP. The initial gamma voltage output by the voltage generation module 141 is transmitted to the amplifier OP via the second resistor R2. The first adjustment unit 142a, the second adjustment unit 142b, and the third adjustment unit 142c are connected in parallel between the ground terminal and the inverting terminal of the amplifier OP to adjust the adjustment range of the initial gamma voltage by the amplifier OP.

[0048] The first adjustment unit 142a is used to cooperate with the amplifier OP to adjust the initial gamma voltage sequence to the first gamma voltage sequence, the second adjustment unit 142b is used to cooperate with the amplifier OP to adjust the initial gamma voltage sequence to the second gamma voltage sequence, and the third adjustment unit 142c is used to cooperate with the amplifier OP to adjust the initial gamma voltage sequence to the third gamma voltage sequence.

[0049] Specifically, the first adjustment unit 142a includes a first switch tube Q1 and a third resistor R3, the second adjustment unit 142b includes a second switch tube Q2 and a fourth resistor R4, and the third adjustment unit 142c includes a fourth switch tube Q4, wherein the control end of the first switch tube Q1 is electrically connected to the timing control circuit 11, the first conductive end of the first switch tube Q1 is electrically connected to the ground end GND, the second control end of the first switch tube Q1 is electrically connected to the first end of the third resistor R3, and the second end of the third resistor R3 is electrically connected to the inverting end of the amplifier OP.

[0050] A control terminal of the second switch tube Q2 is electrically connected to the timing control circuit 11, a first conductive terminal of the second switch tube Q2 is electrically connected to the ground terminal GND, a second control terminal of the second switch tube Q2 is electrically connected to a first terminal of a fourth resistor R4, and a second terminal of the fourth resistor R4 is electrically connected to an inverting terminal of the amplifier OP.

[0051] The control terminal of the fourth switch Q4 is electrically connected to the timing control circuit 11, the first conductive terminal of the fourth switch Q4 is electrically connected to the ground terminal GND, and the second control terminal of the fourth switch Q4 is electrically connected to the inverting terminal of the amplifier OP. The third resistor R3 is larger than the fourth resistor R4.

[0052] like Figure 9As shown, the gamma voltage output period includes a first period t1, a second period t2, and a third period t3. During the first period t1, the timing control circuit 11 outputs a first control signal K1 to the first adjustment unit 142a to turn on the first switch Q1. The amplifier OP amplifies the voltage of the initial gamma voltage sequence by a factor of (1+R1 / R3) to generate a first gamma voltage sequence, which is then transmitted to the first data driver circuit 12a and the second data driver circuit 12b. During the second period t2, the timing control circuit 11 outputs a second control signal K2 to the second adjustment unit 142b to turn on the second switch Q2. The amplifier OP amplifies the voltage of the initial gamma voltage sequence by a factor of (1+R1 / R4) to generate a second gamma voltage sequence, which is then transmitted to the third data driver circuit 12c and the fourth data driver circuit 12d. The base level of the first gamma voltage sequence is greater than the base level of the second gamma voltage sequence. In the third period t3, the timing control circuit 11 outputs the third control signal K3 to the third adjustment unit 142c to control the fourth switch Q4 to be turned on, and the amplifier OP transmits the initial gamma voltage sequence as the third gamma voltage sequence to the fifth data driving circuit 12e and the sixth data driving circuit 12f.

[0053] By increasing the base level of the initial gamma voltage sequence through amplifier OP, the base levels of the gamma voltages corresponding to the first through third sub-display areas a through c are sequentially decreased. This allows the first through third sub-display areas a through c to perform brightness compensation using different gamma voltages, thereby reducing the brightness differences between the first through third sub-display areas a and c, and improving the compensation effect.

[0054] Please also refer to Figure 10 and Figure 11 , Figure 10 for Figure 4 The circuit block diagram of the data driving circuit, Figure 11 for Figure 10 Schematic diagram of the equivalent circuit of the input control module.

[0055] like Figure 10As shown, the data driving circuit 12 includes an input control module 121, a logic processing module 122, a shift register module 123, a data latch module 124, a digital-to-analog conversion module 125 and an output buffer module 126, wherein the input control module 121 is electrically connected to the timing control circuit 11, the gamma circuit 14 and the logic processing module 122. The input control module 121 is used to receive the initial data signal and the control signal from the timing control circuit 11, and receive the gamma voltage sequence from the gamma circuit 14 under the control of the control signal, and then transmit the initial data signal and the gamma voltage sequence to the output buffer module 126. The data signals are input to the logic processing module 122. The logic processing module 122 generates a grayscale data signal according to the initial data signal and the gamma voltage sequence and transmits it to the shift register module 123 and the data latch module 124 for storage. The digital-to-analog conversion module 125 is used to perform analog-to-digital conversion on the data signal in the data latch module 124 to obtain a digital data signal and transmit the converted data signal to the output buffer module 126 for storage. At a preset time, the output buffer module 126 outputs the data voltage to the pixel unit P in the corresponding display area to control the pixel unit P to display an image.

[0056] like Figure 11 As shown, the input control module 121 includes a fourth switch transistor Q4 and a first capacitor C1. The control terminal of the fourth switch transistor Q4 is electrically connected to the timing control circuit 11, the first conductive terminal of the fourth switch transistor Q4 is electrically connected to the voltage adjustment module 142 in the gamma circuit 14, the second conductive terminal of the fourth switch transistor Q4 is electrically connected to the data driving circuit 12, and the first capacitor C1 is electrically connected between the ground terminal GND and the second terminal of the fourth switch transistor Q4. The fourth switch transistor Q4 is configured to be turned on under the control of the timing control circuit 11 to transmit the corresponding gamma voltage sequence to the first capacitor C1 for storage, and continuously transmit it to the data driving circuit 12, so that the gamma voltage sequence received by the data driving circuit 12 controls the pixel unit to display an image.

[0057] The multiple data driving circuits 12 receive different gamma voltage sequences under the control of the timing control circuit 11 and control the corresponding display areas to display images based on the received gamma voltage sequences. Taking the first data driving circuit 12a, the second data driving circuit 12b, and the third data driving circuit 12c as an example, during a first time period t1, the timing control circuit 11 outputs a first control signal K1 to the first adjustment unit 142a to control the voltage adjustment module 142 to output the first gamma voltage sequence. Simultaneously, the timing control circuit 11 outputs the first control signal K1 to the input control module 121 in the first data driving circuit 12a to control the first data driving circuit 12 to receive and store the first gamma voltage sequence.

[0058] During the second period t2, the timing control circuit 11 outputs the second control signal K2 to the second adjustment unit 142b to control the voltage adjustment module 142 to output the second gamma voltage sequence. At the same time, the timing control circuit 11 outputs the second control signal to the input control module 121 in the second data driving circuit 12b to control the second data driving circuit 12b to receive the second gamma voltage sequence for storage.

[0059] During the third period t3, the timing control circuit 11 outputs a third control signal K3 to the third adjustment unit 142c, controlling the voltage adjustment module 142 to output the third gamma voltage sequence. Simultaneously, the timing control circuit 11 outputs a third control signal K3 to the input control module 121 in the third data driver circuit 12c, controlling the third data driver circuit 12c to receive and store the third gamma voltage sequence. After the gamma scan period ends, the first through third data driver circuits 12a through 12c control the corresponding display areas to display images based on the received gamma voltage sequence. Similarly, the fourth, fifth, and sixth data driver circuits 12d, 12e, and 12f receive their corresponding gamma voltage sequences under the control of the timing control circuit 11. The specific adjustment methods are the same as described above and are not further described in this embodiment.

[0060] Please also refer to Figure 12 and Figure 13 , Figure 12 This is a schematic diagram of the gamma voltage subdivision sequence. Figure 13 This is a logic diagram of the working process of the gamma voltage subdivision sequence.

[0061] like Figure 12 and Figure 13 As shown, when the gamma circuit 14 generates a basic gamma voltage sequence, the timing control circuit 11 can further adjust the basic gamma voltage sequence (GM1, GM7, GM8 and GM14) to generate a gamma voltage subdivision sequence (GM1, GM2, GM3, ..., GM14), wherein the first gamma voltage sequence, the second gamma voltage sequence and the third gamma voltage sequence are all basic gamma voltage sequences.

[0062] The specific steps are as follows: S101 , a gamma circuit generates an initial gamma voltage.

[0063] S102, controlling the first data driving circuit and the fourth data driving circuit to receive a first gamma voltage sequence; S103, controlling the second data driving circuit and the fifth data driving circuit to receive a second gamma voltage sequence; S104 , controlling the third data driving circuit and the sixth data driving circuit to receive a third gamma voltage sequence.

[0064] Specifically, the timing control circuit 11 can generate a first gamma voltage subdivision sequence and a second gamma voltage subdivision sequence based on the first gamma voltage sequence, and simultaneously provide the first gamma voltage subdivision sequence and the second gamma voltage subdivision sequence to the first sub-display area a, wherein the first sub-display area a may include a first partition and a second partition, the first gamma voltage subdivision sequence can be provided to the first partition, and the second gamma voltage subdivision sequence can be provided to the second partition. For example, the first gamma voltage subdivision sequence and the second gamma voltage subdivision sequence include a fifth gamma voltage GM5, which is located between the first gamma voltage GM1 and the second gamma voltage GM7, wherein, in the first gamma voltage subdivision sequence, the difference between the first gamma voltage GM1 and the fifth gamma voltage GM5 is a first voltage difference v1, and in the second gamma voltage subdivision sequence, the difference between the first gamma voltage GM1 and the fifth gamma voltage is a second voltage difference v2, wherein the first voltage difference v1 is smaller than the second voltage difference v2, so that in the first gamma voltage subdivision sequence, the voltage of the fifth gamma voltage GM5 is closer to the first gamma voltage GM1, that is, the voltage of the fifth gamma voltage GM5 is farther away from the center reference voltage GM0, so that the brightness of the first sub-area under the same gray scale can be adjusted to be higher than the brightness of the second sub-area, so that the brightness compensation in the first sub-display area a is more uniform.

[0065] Similarly, the second sub-display area b can be divided into a third and a fourth sub-area. The timing control circuit 11 can generate a third and a fourth gamma voltage sub-sequence based on the second gamma voltage sequence. The third gamma voltage sub-sequence can be provided to the third sub-area, and the fourth gamma voltage sub-sequence can be provided to the fourth sub-area. The third sub-display area c can be divided into a fifth and a sixth sub-area. The timing control circuit 11 can generate a fifth and a sixth gamma voltage sub-sequence based on the third gamma voltage sequence. The fifth gamma voltage sub-sequence can be provided to the fifth sub-area, and the sixth gamma voltage sub-sequence can be provided to the sixth sub-area. Similarly, the fourth sub-display area d, the fifth sub-display area e, and the sixth sub-display area f are symmetrical with the first sub-display area a, the second sub-display area b, and the third sub-display area c, respectively. Therefore, the fourth sub-display area d, the fifth sub-display area e, and the sixth sub-display area f can be configured with the same partitions and controlled by the same gamma voltages for display.

[0066] For example, the display area 10a includes 2160 columns of pixels, the first sub-display area a includes columns 1 to 360 of pixels, the first sub-area includes columns 1 to 180 of pixels, and the second sub-area includes columns 181 to 360 of pixels. A first gamma voltage subdivision sequence is applied to the first sub-area, i.e., the pixels in columns 1 to 180, and a second gamma voltage subdivision sequence is applied to the second sub-area, i.e., the pixels in columns 181 to 360. The fourth sub-display area d includes columns 1801 to 2160, the first gamma voltage subdivision sequence can be applied to the pixels in columns 1981 to 2160, and the second gamma voltage subdivision sequence can be applied to the pixels in columns 1801 to 1980. The second sub-display area b includes pixels in columns 361 to 720, the third sub-display area may include pixels in columns 361 to 540, and the fourth sub-display area may include pixels in columns 541 to 720. The third sub-display area e may be provided to pixels in columns 361 to 540, and the fourth sub-display area e may be provided to pixels in columns 541 to 720. Similarly, the fifth sub-display area e is symmetrical with the second sub-display area b. Therefore, the third and fourth sub-display areas may also be provided to the third sub-display area d. The third sub-display area c may include pixels in columns 721 to 1080, wherein the fifth sub-display area may include pixels in columns 721 to 900, and the sixth sub-display area may include pixels in columns 901 to 1080. The fifth sub-display area e may be provided to pixels in columns 721 to 900, and the sixth sub-display area may be provided to pixels in columns 901 to 1080. Likewise, the sixth sub-display area f is symmetrical to the third sub-display area c, so the fifth gamma voltage subdivision sequence and the sixth gamma voltage subdivision sequence can also be provided to the sixth sub-display area f.

[0067] It should be understood that the application of the present invention is not limited to the above examples. For those skilled in the art, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A gamma circuit, characterized in that: The present invention comprises a voltage generating module and a voltage adjusting module, wherein the voltage generating module is used to generate an initial gamma voltage sequence according to a power supply voltage and transmit the sequence to the voltage adjusting module, and the voltage adjusting module is used to adjust the voltage of the initial gamma voltage sequence according to a control signal and generate at least two groups of gamma voltage sequences, and transmit different gamma voltage sequences to different data driving circuits respectively, wherein the control signal is received from a timing control circuit, and the gamma voltage sequence is used to cooperate with the data signal to control the data driving circuit to output data voltages to pixel units in the display area.

2. The gamma circuit according to claim 1, wherein The voltage adjustment module includes an amplifier, a first resistor, a second resistor, a first adjustment unit, a second adjustment unit, and a third adjustment unit, wherein the first resistor is electrically connected between the inverting terminal and the output terminal of the amplifier, the second resistor is electrically connected between the non-inverting terminal of the amplifier and the voltage generation module, and the first adjustment unit, the second adjustment unit, and the third adjustment unit are connected in parallel between a ground terminal and the inverting terminal of the amplifier; The first adjustment unit is used to cooperate with the amplifier to adjust the initial gamma voltage to a first gamma voltage sequence, the second adjustment unit is used to cooperate with the amplifier to adjust the initial gamma voltage to a second gamma voltage sequence, and the third adjustment unit is used to cooperate with the amplifier to adjust the initial gamma voltage to a third gamma voltage sequence.

3. The gamma circuit according to claim 2, wherein: The first gamma voltage sequence, the second gamma voltage sequence, and the third gamma voltage sequence each include a first gamma voltage, a second gamma voltage, a third gamma voltage, and a fourth gamma voltage, wherein the first gamma voltage and the fourth gamma voltage are symmetrical about a central reference voltage, and the second gamma voltage and the third gamma voltage are symmetrical about the central reference voltage, the first gamma voltage and the second gamma voltage are used to cooperate to generate a data signal of a positive polarity, and the third gamma voltage and the fourth gamma voltage are used to cooperate to generate a data signal of a negative polarity, and the difference between the first gamma voltage and the central reference voltage is greater than the difference between the second gamma voltage and the central reference voltage; In the first gamma voltage sequence, the difference between the first gamma voltage and the central reference voltage is a first gamma voltage difference, in the second gamma voltage sequence, the difference between the first gamma voltage and the central reference voltage is a second gamma voltage difference, and in the third gamma voltage sequence, the difference between the first gamma voltage and the central reference voltage is a third gamma voltage difference, wherein the first gamma voltage difference is greater than the second gamma voltage difference, and the second gamma voltage difference is greater than the third gamma voltage difference.

4. The gamma circuit according to claim 2, wherein: The first adjustment unit includes a first switch tube and a third resistor, the second adjustment unit includes a second switch tube and a fourth resistor, and the third adjustment unit includes a third switch tube, wherein the control end of the first switch tube is electrically connected to the timing control circuit, the first conductive end of the first switch tube is electrically connected to the ground end, the second conductive end of the first switch tube is electrically connected to the first end of the third resistor, and the second end of the third resistor is electrically connected to the inverting end of the amplifier; The control terminal of the second switch tube is electrically connected to the timing control circuit, the first conductive terminal of the second switch tube is electrically connected to the ground terminal, the second conductive terminal of the second switch tube is electrically connected to the first terminal of the fourth resistor, and the second terminal of the fourth resistor is connected to the inverting terminal of the amplifier; The control terminal of the third switch tube is electrically connected to the timing control circuit, the first conductive terminal of the third switch tube is electrically connected to the timing control circuit, the first conductive terminal of the third switch tube is electrically connected to the ground terminal, and the second conductive terminal of the third switch tube is electrically connected to the inverting terminal of the amplifier, wherein the resistance of the third resistor is greater than the resistance of the fourth resistor; The first switching tube is turned on according to a first control signal to control the third resistor to be electrically connected to the inverting terminal of the amplifier, and the first resistor and the third resistor cooperate with the amplifier to adjust the initial gamma voltage sequence to obtain a first gamma voltage sequence. The second switching tube is turned on according to a second control signal to control the fourth resistor to be electrically connected to the inverting terminal of the amplifier, and the first resistor and the fourth resistor cooperate with the amplifier to adjust the initial gamma voltage sequence to obtain the second gamma voltage sequence. The third switching tube is turned on according to a third control signal to use the initial gamma voltage sequence as the third gamma voltage sequence.

5. A data driving circuit, characterized in that: The data driving circuit is used to receive an initial data signal and a control signal from a timing control circuit and a gamma voltage sequence from a gamma circuit, and output a corresponding data voltage to a pixel unit in a display area. The data driving circuit includes an input control module and a logic processing module. The input control module is used to receive the initial data signal and the control signal, and receive the gamma voltage sequence under the control of the control signal, and transmit the initial data signal and the gamma voltage sequence to the logic processing module. The logic processing module generates a grayscale data signal based on the initial data signal and the gamma voltage sequence, and the grayscale data signal is used to form the data voltage.

6. The data driving circuit according to claim 5, wherein: The input control module includes a fourth switch tube and a first capacitor, wherein the control end of the fourth switch tube is electrically connected to the timing control circuit, the first conductive end of the fourth switch tube is electrically connected to the gamma circuit, the second conductive end of the fourth switch tube is electrically connected to the logic processing module, and the first capacitor is electrically connected between a ground end and the second conductive end of the fourth switch tube; The fourth switch tube is configured to be turned on according to a control signal output by a timing control circuit, so as to transmit the Gamma voltage sequence output by the Gamma circuit to the logic control module.

7. A display panel, characterized in that: The non-display area of the display panel comprises a timing control circuit, a gamma circuit according to any one of claims 1 to 4, and a plurality of data driving circuits according to any one of claims 5 to 6, wherein the timing control circuit controls the data driving circuit to output a data signal including a first period, a second period, and a third period, and the plurality of data driving circuits include a first data driving circuit, a second data driving circuit, and a third data driving circuit; During the first period, the timing control circuit outputs a first control signal to the gamma circuit and the data driving circuit, the gamma circuit outputs a first gamma voltage sequence according to the first control signal, and the first data driving circuit receives the first gamma voltage sequence according to the first control signal; During the second period, the timing control circuit outputs a second control signal to the gamma circuit and the data driving circuit, the gamma circuit outputs a second gamma voltage sequence according to the second control signal, and the second data driving circuit receives the second gamma voltage sequence according to the second control signal; In the third period, the timing control circuit outputs a third control signal to the gamma circuit and the data driving circuit, the gamma circuit outputs a third gamma voltage sequence according to the third control signal, and the third data driving circuit receives the third gamma voltage sequence according to the third control signal.

8. The display panel according to claim 7, wherein: The display area of the display panel includes a first sub-display area, a second sub-display area and a third sub-display area. The first sub-display area, the second sub-display area and the third sub-display area are arranged in sequence from the edge of the display area to the middle of the display area. The first data driving circuit is used to control the first sub-display area to display an image according to the first gamma voltage sequence, the second data driving circuit is used to control the second sub-display area to display an image according to the second gamma voltage sequence, and the third data driving circuit is used to control the third sub-display area to display an image according to the third gamma voltage sequence.

9. The display panel according to claim 8, wherein: The timing control circuit adjusts the first gamma voltage to obtain a first gamma voltage subdivision sequence and a second gamma voltage subdivision sequence. The first sub-display area includes a first partition and a second partition. The data driving circuit controls the first partition to display an image according to the first gamma voltage subdivision sequence, and controls the second partition to display an image according to the second gamma voltage subdivision sequence. The first partition is located at an edge of the display area, and the second partition is adjacent to the second sub-display area.

10. The display panel according to claim 9, wherein: The first gamma voltage subdivision sequence and the second gamma voltage subdivision sequence both include a fifth gamma voltage, the fifth gamma voltage being between the first gamma voltage and the second gamma voltage. In the first gamma voltage subdivision sequence, a difference between the fifth gamma voltage and the first gamma voltage is a first voltage difference. In the second gamma voltage subdivision sequence, a difference between the fifth gamma voltage and the first gamma voltage is a second voltage difference, and the first voltage difference is less than the second voltage difference.

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