Memory including sense amplifier and method of operating memory

Abstract

The invention relates to a memory including a sense amplifier and a method of operating the memory. The operating method of the memory may include: receiving a first activation command and a first row address; initiating a first mismatch compensation operation in a sense amplifier array for a normal cell array corresponding to the first row address and in a redundant sense amplifier array for a redundant cell array corresponding to the normal cell array; determining whether to access the normal cell array based on the first row address and the repair information; in response to a determination to access the normal cell array, deactivating the redundant sense amplifier array for the redundant cell array; activating a word line of the normal cell array corresponding to the first row address; and sensing and amplifying data of a memory cell corresponding to the activated word line by a sense amplifier array for the normal cell array.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0020745, filed on February 14, 2024, which is hereby incorporated by reference herein in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to memory, and more particularly, to data sensing in memory. Background Art

[0004] Memory devices use sense amplifiers to sense and amplify data in memory cells. Sense amplifiers sense and amplify small voltage differences between bit lines. Ideally, even small potential differences between bit lines would require the sense amplifier to accurately sense and amplify these differences. However, in reality, this is not possible.

[0005] The minimum value of the potential difference between the bit lines for the sense amplifier to accurately sense data is called the offset voltage. When the potential difference between the two ends of the bit line is less than the offset voltage, the sense amplifier may not be able to perform accurate amplification and sensing operations. Factors that cause the offset voltage may include mismatches between the PMOS transistors and NMOS transistors that make up the sense amplifier. The PMOS transistors and NMOS transistors that make up the sense amplifier need to be manufactured identically, but since PMOS transistors and NMOS transistors cannot be manufactured exactly the same in practice, mismatches always exist. Summary of the Invention

[0006] In an embodiment of the present disclosure, a method for operating a memory may include: receiving a first activation command and a first row address; starting a first mismatch compensation operation in a sense amplifier array for a normal cell array corresponding to the first row address and in a redundant sense amplifier array for a redundant cell array corresponding to the normal cell array; determining whether to access the normal cell array based on the first row address and repair information; in response to a determination that the normal cell array is to be accessed, deactivating the redundant sense amplifier array for the redundant cell array; activating a word line of the normal cell array corresponding to the first row address; and sensing and amplifying data of a memory cell corresponding to the activated word line through the sense amplifier array for the normal cell array.

[0007] In an embodiment of the present disclosure, a memory may include: a normal cell array; a normal sense amplifier array that senses and amplifies data of the normal cell array; a redundant cell array; a redundant sense amplifier array that senses and amplifies data of the redundant cell array; and a repair determination circuit that determines whether to access the redundant cell array based on a row address and repair information, wherein mismatch compensation operations of the normal sense amplifier array and the redundant sense amplifier array may be initiated in response to application of an activation command, and after determination by the repair determination circuit, one of the normal sense amplifier array and the redundant sense amplifier array may be deactivated. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a diagram illustrating a configuration of a memory according to an embodiment of the present disclosure.

[0009] Figure 2 The present invention is shown in the embodiment of the present invention. Figure 1 A diagram showing the detailed configuration of the memory bank in FIG.

[0010] Figure 3 The present invention is shown in the embodiment of the present invention. Figure 2 FIG. 1 is a diagram of a detailed configuration of sense amplifiers included in a normal sense amplifier array.

[0011] Figure 4 It is used to describe the embodiment of the present disclosure Figure 3 The timing diagram of the operation of the sense amplifier.

[0012] Figure 5 is a flowchart for describing an activation operation of a memory according to an embodiment of the present disclosure.

[0013] Figure 6 is a flowchart for describing an activation operation of a memory according to an embodiment of the present disclosure.

[0014] Figure 7 According to the embodiment of the present disclosure Figure 6 Timing diagram of the operation of the sense amplifier. DETAILED DESCRIPTION

[0015] Various embodiments of the present disclosure are directed to memories having reduced access time while reducing mismatch in sense amplifiers.

[0016] According to embodiments of the present disclosure, access time can be reduced while reducing mismatch in sense amplifiers.

[0017] Hereinafter, embodiments according to the technical spirit of the present disclosure will be described with reference to the accompanying drawings.

[0018] Figure 1is a diagram showing a configuration of the memory 100 according to an embodiment of the present disclosure.

[0019] Reference Figure 1 , the memory 100 may include a command decoder 110 , an address control circuit 120 , a control logic 130 , a data transmission / reception circuit 140 , and a memory bank 150 .

[0020] The command decoder 110 can determine the type of operation instructed by the memory controller to the memory 100 by decoding the command / address CA received from the memory controller (not shown). For example, the command decoder 110 can determine whether an active operation, a precharge operation, a refresh operation, a write operation, or a read operation is instructed.

[0021] The control logic 130 may control internal components of the memory 100 according to the decoding result of the command decoder 110. The control signal CTRL may represent a signal by which the control logic 130 controls the internal components of the memory 100.

[0022] The address control circuit 120 may classify the address received from the command decoder 110 into a row address R_ADD and a column address C_ADD, and transmit the row address R_ADD and the column address C_ADD to the memory bank 150. When a row operation (e.g., an active operation) is indicated according to the decoding result of the command decoder 110, the address control circuit 120 may recognize the address as the row address R_ADD, and recognize the address as the column address C_ADD when a column operation (i.e., a read operation and a write operation) is indicated.

[0023] The data transmission / reception circuit 140 may receive data DATA or transmit data DATA. The data transmission / reception circuit 140 may receive data DATA to be written to the memory bank 150 during a write operation and may transmit data DATA read from the memory bank 150 during a read operation.

[0024] The memory bank 150, on which an activation operation, a precharge operation, a read operation, and a write operation are performed, may include components for storing data and accessing data. Figure 1 Only one memory bank 150 is shown, but naturally the memory 100 may include a plurality of memory banks 150 .

[0025] Figure 2 The present invention is shown in FIG. Figure 1 FIG. 1 is a diagram showing a detailed configuration of the memory bank 150 in FIG.

[0026] refer to Figure 2, the memory body 150 may include a normal cell array 210_0 to 210_N (where N is an integer of 1 or greater), a redundant cell array 215, a normal row circuit 220_0 to 220_N, a redundant row circuit 225, a normal sense amplifier array 230_0 to 230_N, a redundant sense amplifier array 235, a normal sense amplifier array control circuit 240_0 to 240_N, a redundant sense amplifier array control circuit 245, a normal column circuit 250_0 to 250_N, a redundant column circuit 255, and a repair determination circuit 260.

[0027] Each of the normal cell arrays 210_0 to 210_N may include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells formed at intersections of the word lines and the bit lines. Each memory cell may include a capacitor for storing data and a transistor serving as a switch.

[0028] Normal row circuits 220_0 to 220_N may activate a word line selected by a row address R_ADD from among a plurality of word lines included in normal cell arrays 210_0 to 210_N. Depending on the value of row address R_ADD, one of normal row circuits 220_0 to 220_N may activate the word line selected by row address R_ADD. For example, when the value of row address R_ADD is 0 to 511, normal row circuit 220_0 may activate the word line corresponding to the value of row address R_ADD, while when the value of row address R_ADD is 512 to 1023, normal row circuit 220_1 may activate the word line corresponding to the value of row address R_ADD.

[0029] The normal sense amplifier arrays 230_0 to 230_N can sense and amplify data stored in memory cells of the normal cell arrays 210_0 to 210_N during an activation operation. Depending on the value of the row address R_ADD, one of the normal sense amplifier arrays 230_0 to 230_N can be activated and operated. For example, when the value of the row address R_ADD is 0 to 511, the normal sense amplifier array 230_0 can operate, while when the value of the row address R_ADD is 512 to 1023, the normal sense amplifier array 230_1 can operate.

[0030] The normal sense amplifier array control circuits 240_0 to 240_N can control the operation of the normal sense amplifier arrays 230_0 to 230_N. The normal sense amplifier arrays 230_0 to 230_N can perform a mismatch compensation operation and a sense amplification operation. The mismatch compensation operation can be an operation performed before the sense amplification operation to reduce the mismatch of the sense amplifiers of the sense amplifier arrays 230_0 to 230_N, while the sense amplification operation can be an operation to sense and amplify data in a memory cell.

[0031] Normal column circuits 250_0 to 250_N can access data from the sense amplifiers selected by column address C_ADD in the normal sense amplifier arrays 230_0 to 230_N during read and write operations. Depending on the value of column address C_ADD, one of normal column circuits 250_0 to 250_N can be activated and operated. For example, when the value of column address C_ADD is 0 to 511, normal column circuit 250_0 can access data from the sense amplifiers selected by column address C_ADD in the normal sense amplifier array 230_0, while when the value of column address C_ADD is 512 to 1023, normal column circuit 250_1 can access data from the sense amplifiers selected by column address C_ADD in the normal sense amplifier array 230_1.

[0032] The repair determination circuit 260 can determine whether to access the redundant cell array 215 by using the row address R_ADD and the repair information. The repair information may be information about defective rows stored in the repair determination circuit 260. For example, the repair information may include information indicating that rows 100 and 760 are defective. When the row address R_ADD matches the repair information, the repair determination circuit 360 may provide a determination result to the normal row circuits 220_0 to 220_N and the sense amplifier array control circuits 240_0 to 240_N and 245, allowing the redundant cell array 215 to be accessed instead of the normal cell arrays 210_0 to 210_N.

[0033] The repair information of the repair determination circuit 260 includes information indicating that row 100 is defective, and when the value of the row address R_ADD is 100, one of the redundant word lines of the redundant cell array 215 may be accessed instead of the word line 100 of the normal cell array 210_0.

[0034] Redundant cell array 215 may include redundant memory cells for replacing memory cells in defective rows of normal cell arrays 210_0 to 210_N. Redundant row circuit 225 may drive redundant word lines of redundant cell array 215, and redundant sense amplifier array 235 may sense and amplify data of memory cells in redundant cell array 215. Redundant sense amplifier array control circuit 245 may control redundant sense amplifier array 235.

[0035] Figure 3 The present invention is shown in FIG. Figure 2 FIG. 2 is a diagram of a detailed configuration of the sense amplifier 300 included in the normal sense amplifier array 230_0 in FIG.

[0036] refer to Figure 3The sense amplifier 300 may include a first inverter 310, a second inverter 320, a first offset cancellation switch 341, a second offset cancellation switch 342, a first isolation switch 351, and a second isolation switch 352. Since the sense amplifier 300 amplifies the voltage difference between the bit lines BLT and BLB, the sense amplifier 300 is also called a bit line sense amplifier.

[0037] The input terminal of the first inverter 310 can be connected to the first bit line BLT through the first sense node GT, and the output terminal of the first inverter 310 can be connected to the second internal bit line IB. The input terminal of the second inverter 320 can be connected to the second bit line BLB (i.e., the complementary bit line of the first bit line) through the second sense node GB, and the output terminal of the second inverter 320 can be connected to the first internal bit line IT. The first inverter 310 can be formed by connecting a PMOS transistor 311 and an NMOS transistor 312 in series between a pull-up voltage terminal RTO and a pull-down voltage terminal SB, while the second inverter 320 can be formed by connecting a PMOS transistor 321 and an NMOS transistor 322 in series between the pull-up voltage terminal RTO and the pull-down voltage terminal SB.

[0038] The first offset cancellation switch 341 can electrically connect the first internal bit line IT and the second sense node GB (i.e., the second bit line BLB) in response to the offset cancellation signal OC. The second offset cancellation switch 342 can electrically connect the second internal bit line IB and the first sense node GT (i.e., the first bit line BLT) in response to the offset cancellation signal OC. Each of the first offset cancellation switch 341 and the second offset cancellation switch 342 can be implemented as an NMOS transistor.

[0039] The first isolation switch 351 can electrically connect the first bit line BLT and the first internal bit line IT in response to a first isolation signal ISOT. The second isolation switch 352 can electrically connect the second bit line BLB and the second internal bit line IB in response to a second isolation signal ISOB. Each of the first isolation switch 351 and the second isolation switch 352 can be implemented using an NMOS transistor. The first isolation signal ISOT and the second isolation signal ISOB can be signals that are sequentially turned on during a sensing operation.

[0040] The first capacitor 331 may be connected to the first bit line BLT, and the second capacitor 332 may be connected to the second bit line BLB. The first capacitor 331 and the second capacitor 332 are parasitic capacitors, and during the mismatch compensation operation, the offsets of the first inverter 310 and the second inverter 320 may be stored in the parasitic capacitors 331 and 332, respectively. The offsets of the first inverter 310 and the second inverter 320 may be stored in the first capacitor 331 and the second capacitor 332, respectively.

[0041] Voltage levels of the offset cancellation signal OC, the first isolation signal ISOT, the second isolation signal ISOB, the pull-up voltage level RTO, and the pull-down voltage level SB may be controlled by the normal sense amplifier array control circuit 240_0 .

[0042] The normal sense amplifier array 230_0 may include a plurality of sense amplifiers 300, and the normal sense amplifier arrays 230_0 to 230_N and the redundant sense amplifier array 235 may also include a plurality of sense amplifiers 300. Figure 3 Multiple sense amplifiers in the configuration shown.

[0043] Figure 4 It is used to describe the embodiment of the present disclosure Figure 3 FIG. 1 is a timing diagram of the operation of the sense amplifier 300 in FIG.

[0044] refer to Figure 3 and Figure 4 , the operations of the sense amplifier 300 may include a precharge operation PCG, a mismatch compensation operation MC, and a sense amplification operation SA.

[0045] During the precharge operation PCG, the first isolation signal ISOT, the second isolation signal ISOB, and the offset cancellation signal OC may be activated to a logic high level. A precharge voltage VBLP may be applied to the pull-up voltage stage RTO and the pull-down voltage stage SB. Since the same voltage level is applied to the pull-up voltage terminal RTO and the pull-down voltage terminal SB, the sense amplifier 300 may be in a deactivated state in which the inverters 310 and 320 are deactivated. During the precharge operation PCG, the first bit line BLT and the second bit line BLB may be at the level of the precharge voltage VBLP.

[0046] During the mismatch compensation operation MC, while the offset cancellation signal OC is activated at a logic high level, the first isolation signal ISOT and the second isolation signal ISOB may be deactivated at a logic low level. The first offset cancellation switches 341 and 342 are turned on, and the first isolation switches 351 and 352 are turned off, so that the input and output terminals of the first inverter 310 can both be connected to the first bit line BLT, and the input and output terminals of the second inverter 320 can both be connected to the second bit line BLB. A core voltage VCORE (a power supply voltage used in the sense amplifier) is supplied to the pull-up voltage stage RTO, and a ground voltage VSS is supplied to the pull-down voltage stage SB, so that the first inverter 310 and the second inverter 320 can be activated. As a result, a balanced state reflecting the offsets of the transistors 311 and 312 of the first inverter 310 can be stored in the first capacitor 331, while a balanced state reflecting the offsets of the transistors 321 and 322 of the second inverter 320 can be stored in the second capacitor 332. Since subsequent operations are performed in a state where offsets of the transistors 311 , 312 , 321 , and 322 of the first and second inverters 310 and 320 are reflected in the capacitors 331 and 332 through the mismatch compensation operation MC, the influence of mismatch may be minimized in the subsequent operations.

[0047] The sense amplification operation SA may include a charge sharing section CS and an amplification section AMP. In the charge sharing section CS, the first isolation signal ISOT, the second isolation signal ISOB, and the offset cancellation signal OC may be deactivated to a logic low level, and a bit line precharge voltage VBLP may be applied to the pull-up voltage terminal RTO and the pull-down voltage terminal SB. Subsequently, the word line WL is activated, allowing the data in the memory cell connected to the word line WL to be charge-shared with one of the bit lines BLT and BLB. In other words, the voltage level of one of the bit lines BLT and BLB may increase or decrease depending on the data value of the memory cell.

[0048] In the amplifying part AMP, the first isolation signal ISOT and the second isolation signal ISOB are activated to a logic high level, the core voltage VCORE is provided to the pull-up voltage stage RTO, and the ground voltage VSS is provided to the pull-down voltage stage SB, so that an amplifying operation of amplifying the voltage difference between the bit lines BLT and BLB can be performed by the inverters 310 and 320.

[0049] When the sense amplification operation SA ends, the precharge operation PCG may begin again, and during the precharge operation, the first isolation signal ISOT, the second isolation signal ISOB, and the offset cancellation signal OC may be activated to a logic high level. The precharge voltage VBLP may be applied to the pull-up voltage stage RTO and the pull-down voltage stage SB.

[0050] Figure 5 is a flowchart for describing an activation operation of the memory 100 according to an embodiment of the present disclosure.

[0051] Reference Figure 5 , an activation operation of the memory 100 may begin by receiving an activation command and a row address (501). The command decoder 110 may decode the command and address CA to determine that the memory controller has instructed the memory 100 to perform the activation operation, and the address control circuit 120 may classify the address received from the command decoder 110 as a row address R_ADD. For ease of description, the value of the row address R_ADD is 32, however, other values may also be used.

[0052] The repair determination circuit 260 may determine whether to access the redundant cell array 215 (503) by using the row address R_ADD and the repair information. The repair information stores the value of the row address corresponding to the defect, and the repair determination circuit 260 may determine whether the value of the received row address R_ADD matches one of the values of the row address included in the repair information.

[0053] When the row address R_ADD does not match the value of the defect address included in the repair information, access to the normal cell array may be determined (i.e., "No" in 503). Because the value of the row address R_ADD is 32, the normal cell array 210_0 may be accessed. The normal sense amplifier array control circuit 240_0 may control the sense amplifiers of the normal sense amplifier array 230_0 to sequentially perform the mismatch compensation operation 505 and the sense amplification operation 507. During the sense amplification operation, the normal row circuit 220_0 may activate the word line 32 selected by the row address R_ADD.

[0054] When the row address R_ADD matches one of the values of the defect address included in the repair information, access to the redundant cell array 215 may be determined (i.e., "Yes" in 503). The redundant sense amplifier array control circuit 245 may control the sense amplifiers of the redundant sense amplifier array 235 to sequentially perform the mismatch compensation operation 509 and the sense amplification operation 511. During the sense amplification operation, the redundant row circuit 225 may activate a redundant word line designated as the replacement word line 32 among the redundant word lines.

[0055] The activation operation may be terminated by receiving a precharge command (513). The command decoder 110 may decode the command / address CA to determine that the memory controller has instructed the memory 100 to perform a precharge operation, and may perform the precharge operation to terminate the activation operation. Although not shown in the figure, read operations and write operations may be performed in the memory 100 during the activation operation.

[0056] In the memory 100, the time required from the point of application of the activation command to the time when the data of the storage cell of the selected row is sensed and amplified, that is, the time from the point of application of the activation command until the read operation and the write operation can be performed is called the row address to column address delay (tRCD), and this is one of the very important performance indicators in the memory 100.

[0057] Figure 6 is a flowchart for describing the activation operation of the memory 100 according to an embodiment of the present disclosure. Figure 5 In contrast, the activation operation is changed in order to reduce tRCD.

[0058] refer to Figure 6 , the activation operation of the memory 100 may be started by receiving an activation command and a row address (601). The command decoder 110 may decode the command and address CA to determine that the memory controller has instructed the memory 100 to perform the activation operation, and the address control circuit 120 may classify the address received from the command decoder 110 as a row address R_ADD. For ease of description, the value of the row address R_ADD is 32 as an example.

[0059] The mismatch compensation operation of the normal sense amplifier array may begin (603), and the mismatch compensation operation of the redundant sense amplifier array may begin in parallel (605). Figure 5 In the embodiment, after the determination of the repair determination circuit 260, the mismatch compensation operation is performed in one of the normal sense amplifier array and the redundant sense amplifier array, but in Figure 6 In order to avoid delay, the mismatch compensation operation can be started in both the normal sense amplifier array and the redundant sense amplifier array before the determination of the repair determination circuit 260. Since the value of the row address R_ADD is 32, the mismatch compensation operation of the normal sense amplifier array 230_0 and the redundant sense amplifier array 235 can be started.

[0060] The repair determination circuit 260 may determine whether to access the redundant cell array 215 by using the row address R_ADD and the repair information (607).

[0061] When the access to the redundant cell array is not determined (i.e., "No" in 607), the mismatch compensation operation of the redundant sense amplifier array may be stopped (609). The mismatch compensation operation of the normal sense amplifier array may be continuously performed and completed (611). Subsequently, the sense amplification operation of the normal sense amplifier array may be performed (613).

[0062] When access to the redundant cell array is determined (i.e., "Yes" in 607), the mismatch compensation operation of the normal sense amplifier array may be stopped (615). The mismatch compensation operation of the redundant sense amplifier array may be continuously performed and completed (617). Subsequently, the sense amplification operation of the redundant sense amplifier array may be performed (619).

[0063] The activation operation may be terminated by receiving a precharge command (621). The command decoder 110 may decode the command / address CA to determine that the memory controller has instructed the memory 100 to perform a precharge operation, and may perform the precharge operation to terminate the activation operation. Although not shown in the figure, read operations and write operations may also be performed in the memory 100 during the activation operation.

[0064] exist Figure 6 In the embodiment of the present invention, the mismatch compensation operation can be started in parallel in the normal sense amplifier array and the redundant sense amplifier array before the determination operation of the repair determination circuit 260. The determination operation of the repair determination circuit 260 may take a considerable amount of time, but by doing so, the time delay can be minimized, and as a result, tRCD can be reduced. After the determination operation of the repair determination circuit 260, the mismatch compensation operation of the sense amplifier array that does not need to be activated between the normal sense amplifier array and the redundant sense amplifier array is stopped, so the current consumption can be minimized.

[0065] Figure 7 According to the embodiment of the present disclosure Figure 6 Timing diagram of the sense amplifier of operation (605, 609) or (603, 615).

[0066] refer to Figure 7 , the sense amplifier may start the mismatch compensation operation MC in response to the activation command during the precharge operation PCG. When the determination operation of the repair determination circuit 260 is completed during the mismatch compensation operation MC and the mismatch compensation operation MC is determined to be stopped, the sense amplifier may confirm that the state has returned to the precharge operation PCG again.

[0067] implement Figure 6 The sense amplifier in operation (603, 611, 613) or (605, 617, 619) can be operated with Figure 4 The timing diagram is the same as that of Figure 7 In this case, the mismatch compensation operation may be performed until time point 701, the operation of the charge sharing part CS may be performed from time point 701 to time point 703, and the operation of the amplifying part AMP may be performed from time point 703 to time point 705. At time point 705, the precharge operation may be performed again.

[0068] Although the embodiments of the technical concept of the present disclosure have been described above with reference to the accompanying drawings, this is only for describing the embodiments of the concept of the present disclosure, and the present disclosure is not limited to the above-mentioned embodiments. Without departing from the technical concept of the present disclosure defined in the appended claims, those skilled in the art to which the present disclosure belongs may make various types of replacements, modifications, and changes to the embodiments, and it should be understood that these replacements, modifications, and changes fall within the scope of the present disclosure. In addition, these embodiments can be combined to form additional embodiments.

Claims

1. A method for operating a memory, the method comprising: receiving a first activation command and a first row address; initiating a first mismatch compensation operation in a sense amplifier array for a normal cell array corresponding to the first row address and in a redundant sense amplifier array for a redundant cell array corresponding to the normal cell array; determining whether to access the normal cell array based on the first row address and repair information; in response to a determination that the normal cell array is to be accessed, deactivating the redundant sense amplifier array for the redundant cell array; activating a word line of the normal cell array corresponding to the first row address; as well as Data of memory cells corresponding to the activated word line are sensed and amplified by the sense amplifier array for the normal cell array.

2. The memory operating method according to claim 1 , further comprising: Receive precharge command; deactivating the activated word line in response to the precharge command; as well as The sense amplifier array for the normal cell array is deactivated in response to the precharge command.

3. The memory operating method according to claim 2, further comprising: receiving a second activation command and a second row address; initiating a second mismatch compensation operation in a sense amplifier array for a normal cell array corresponding to the second row address and in the redundant sense amplifier array for the redundant cell array; determining to access the redundant cell array based on the second row address and the repair information; in response to a determination that the redundant cell array is to be accessed, deactivating the sense amplifier array for the normal cell array; activating a redundant word line of the redundant cell array; as well as Data of memory cells corresponding to the activated redundant word line are sensed and amplified by the sense amplifier array for the redundant cell array.

4. The memory operating method according to claim 1 , wherein the first mismatch compensation operation is performed in parallel in the sense amplifier array for the normal cell array corresponding to the first row address and in the redundant sense amplifier array corresponding to the normal cell array. 5 . The memory operating method according to claim 3 , wherein the second mismatch compensation operation is performed in parallel in the sense amplifier array for the normal cell array corresponding to the second row address and in the redundant sense amplifier array.

6. A memory comprising: Normal cell array; a normal sense amplifier array, which: senses and amplifies data of the normal cell array; Redundant Cell Array; a redundant sense amplifier array, which: senses and amplifies data of the redundant cell array; and a repair determination circuit that: determines whether to access the redundant cell array based on a row address and repair information, wherein mismatch compensation operations of the normal sense amplifier array and the redundant sense amplifier array are started in response to an activation command, and Wherein, after the determination by the repair determination circuit, one of the normal sense amplifier array and the redundant sense amplifier array is deactivated.

7. The memory according to claim 6, wherein When the repair determination circuit determines to access the normal cell array: The redundant sense amplifier array is deactivated; A word line of the normal cell array corresponding to the row address is activated; as well as The normal sense amplifier array senses and amplifies data of memory cells corresponding to the word line.

8. The memory according to claim 6, wherein When the repair determination circuit determines to access the redundant cell array: The normal sense amplifier array is deactivated; The redundant word line of the redundant cell array is activated; as well as The redundant sense amplifier array senses and amplifies data of memory cells corresponding to the redundant word line.

9. The memory according to claim 6, further comprising: a normal row circuit, which: drives a word line of the normal cell array; a normal sense amplifier array control circuit, which: controls the normal sense amplifier array; a redundant row circuit that: drives a redundant word line of the redundant cell array; and A redundant sense amplifier array control circuit controls the redundant sense amplifier array.

10. The memory according to claim 9, wherein In response to the activation command, the normal sense amplifier array control circuit controls the normal sense amplifier array to start the mismatch compensation operation, and the redundant sense amplifier array control circuit controls the redundant sense amplifier array to start the mismatch compensation operation, and In response to the determination of the repair determination circuit, one of the normal sense amplifier array control circuit and the redundant sense amplifier array control circuit deactivates the sense amplifier array corresponding thereto.

11. The memory according to claim 10, wherein In response to the determination of the repair determination circuit, one of the normal row circuit and the redundancy row circuit activates one of the word lines corresponding thereto.

12. The memory according to claim 11, wherein When access to the normal cell array is determined as a result of determination by the repair determination circuit, the normal row circuit activates a word line selected by the row address among the word lines.

13. The memory according to claim 11, wherein When access to the redundant cell array is determined as a result of determination by the repair determination circuit, the redundant row circuit activates a redundant word line designated to replace a word line selected by the row address among the redundant word lines.

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