Reading method and device of memory device and memory

Abstract

The invention provides a reading method and device for a memory device and a memory, and the method comprises the steps: determining a refreshing time interval according to writing and reading time intervals supported by a plurality of reading voltages of the memory device, so as to carry out the full-disk refreshing of the memory device in the refreshing time interval; in response to the read operation instruction, reading the memory device by using a first read voltage, and determining whether a read result of the first read voltage is error-correctable; and reading the memory device using a second read voltage, which is higher than the first read voltage, in a case where the read result of the first read voltage cannot be corrected. According to the invention, after the whole disk is refreshed at regular time in the refresh time interval, the reading voltage from low to high is selected to try to read in sequence, so that the situation that proper reading voltage needs to be selected for reading through complex write-read time statistics due to threshold voltage drift is avoided; the problem of inaccurate data reading caused by threshold voltage drift is effectively solved by using fewer resources.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a method and apparatus for reading a storage device, and a memory. Background Art

[0002] The memory divides the write and read intervals into several intervals by setting different read voltages based on the threshold voltage distribution in different write and read time intervals, ensuring that each read voltage can correctly distinguish the level state (set, reset) of the memory cell within a time interval.

[0003] However, due to the threshold voltage drift (VT drfit) problem of memory, the voltage level of each memory cell drifts over time, shortening the time it takes for the read voltage to accurately read data. Related technologies require statistical or predicting the write and read times of different data blocks to select the appropriate read voltage to accurately read data. However, this approach often requires significant resources and results in significant resource consumption. Summary of the Invention

[0004] In response to the above technical problems, embodiments of the present application provide a method, apparatus, and memory for reading a memory device, aiming to solve the problem of inaccurate data reading caused by threshold voltage drift with fewer resources.

[0005] In a first aspect, an embodiment of the present application provides a method for reading a memory device, the method comprising:

[0006] Determining a refresh time interval according to write and read time intervals supported by multiple read voltages of the memory device, so as to fully refresh the memory device within the refresh time interval;

[0007] In response to a read operation instruction of the memory device, reading the memory device using a first read voltage, and determining whether a read result of the first read voltage is error correctable;

[0008] If the read result of the first read voltage is uncorrectable, the memory device is read using a second read voltage, wherein the second read voltage is higher than the first read voltage.

[0009] In a feasible embodiment, the method further includes: if a read result of the second read voltage is uncorrectable, reading the memory device using a third read voltage, wherein the third read voltage is higher than the second read voltage;

[0010] If the read result is correctable, the corrected read result is output.

[0011] In a feasible embodiment, the method further includes: writing and reading time intervals supported by multiple read voltages of the memory device at least partially overlap;

[0012] The step of determining a refresh time interval according to the write and read time intervals supported by the plurality of read voltages of the memory device includes:

[0013] A maximum write / read time interval supported by multiple read voltages of the memory device is determined as a refresh time interval of the memory device.

[0014] In a feasible embodiment, the first read voltage is a minimum voltage value among the plurality of read voltages.

[0015] In a feasible embodiment, in response to a read operation instruction of the memory device, reading the memory device using a first read voltage includes:

[0016] In response to a read operation instruction of the memory device, determining a feasible read voltage supporting the trigger time interval from the plurality of read voltages according to a trigger time interval corresponding to the read operation instruction;

[0017] A minimum read voltage among the feasible read voltages is used as a first read voltage to read the memory device.

[0018] In a feasible embodiment, determining whether the reading result of the first reading voltage is error correctable includes:

[0019] Whether a reading result of the first reading voltage is error correctable is determined by an error correction code.

[0020] In a feasible embodiment, determining whether the reading result of the first reading voltage is error correctable by using an error correction code includes:

[0021] determining the number of error bits of a reading result of the first reading voltage by using an error correction code;

[0022] When the number of error bits exceeds a preset bit threshold, determining that the reading result of the first reading voltage is uncorrectable;

[0023] When the number of error bits does not exceed a preset bit threshold, it is determined that the reading result of the first reading voltage is correctable.

[0024] In a feasible embodiment, when a reading result of the first reading voltage is not error correctable, reading the memory device using a second reading voltage includes:

[0025] When the difference between the number of error bits and the preset number of bits threshold exceeds a preset difference threshold, reading the memory device using a second read voltage;

[0026] When the difference between the number of error bits and the preset number of bit thresholds does not exceed the preset difference threshold, the memory device is continuously read using the first read voltage.

[0027] In a feasible embodiment, the method further includes:

[0028] If a read result of reading the memory device using a maximum read voltage among the read voltages is uncorrectable, the memory device is continuously read using the maximum read voltage at least once.

[0029] In a feasible embodiment, the memory device is a memory including a gate switch.

[0030] In a second aspect, an embodiment of the present application provides a reading device for a storage device, the device comprising:

[0031] a refresh module, configured to determine a refresh time interval according to write and read time intervals supported by multiple read voltages of the memory device, so as to perform a full disk refresh on the memory device within the refresh time interval;

[0032] a reading module, configured to read the memory device using a first reading voltage in response to a read operation instruction of the memory device, and determine whether a reading result of the first reading voltage is error correctable;

[0033] The retry module is configured to read the memory device using a second read voltage when a read result of the first read voltage is uncorrectable, wherein the second read voltage is higher than the first read voltage.

[0034] In a third aspect, an embodiment of the present application provides a memory, comprising a memory cell array, wherein the memory cell array comprises a plurality of memory cells;

[0035] and

[0036] an operating circuit coupled to the memory cell array;

[0037] The operation circuit is configured to execute any one of the above-mentioned methods for reading a memory device.

[0038] In a fourth aspect, an embodiment of the present application provides a memory device, comprising a controller and the memory device described above, wherein the controller is configured to control an operating circuit in the memory device to execute a reading method of the memory device.

[0039] The method provided in an embodiment of the present application performs a full disk refresh on a storage device by determining a refresh time interval based on the write and read time intervals supported by multiple read voltages. When a read operation instruction is triggered for the storage device, a first read voltage is used to read the storage device. By determining whether the read result of the first read voltage is error-correctable, it is determined whether a second read voltage higher than the first read voltage should be selected to continue reading the storage device. The solution provided in the present application, after a full disk refresh is scheduled within the refresh time interval, sequentially attempts to read data by selecting read voltages from low to high. This avoids the need to select an appropriate read voltage for reading based on complex write and read time statistics due to threshold voltage drift, effectively solving the problem of inaccurate data reading caused by threshold voltage drift by using fewer resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1a A schematic diagram of a threshold voltage drift phenomenon in a memory device;

[0042] Figure 1b A schematic diagram illustrating a bias drift phenomenon in a memory device is shown;

[0043] Figure 1c A schematic diagram showing the effects of write and read intervals supported by different read voltages;

[0044] Figure 2 A schematic flow chart of the steps of a method for reading a memory device provided in an embodiment of the present application;

[0045] Figure 3 A schematic diagram of another step flow for selecting a first reading voltage provided in an embodiment of the present application;

[0046] Figure 4 A schematic flow chart of steps for reading a memory device using different read voltages provided in an embodiment of the present application;

[0047] Figure 5 A flowchart of the steps of a reading process provided in an embodiment of the present application;

[0048] Figure 6 A schematic structural diagram of a reading device of a storage device provided in an embodiment of the present application;

[0049] Figure 7A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0050] Figure 8 A schematic diagram of the structure of a storage system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application. At the same time, in the description of the embodiments of the present application, the terms "first", "second", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0052] In order to better understand the memory device reading method, device, and memory provided by this application, the following first describes the application scenario of this application in detail. The memory device reading method provided by this application is mainly aimed at a type of data reading method of a memory, wherein the reading method can be coupled to the memory device, that is, the memory cell array in the memory, in the form of an operating circuit to realize the reading of data stored in the memory cell array.

[0053] Specifically, in a memory, due to the existence of the threshold voltage drift phenomenon, the level state of the memory cell often drifts over time, thereby shortening the time during which the read voltage can be correctly read. For example, see Figure 1a , Figure 1a Schematic diagram of the threshold voltage drift phenomenon in a memory device. Figure 1a The distribution information (curves) of the two level states (set and reset) of the memory cell at different times (T0, T1, T2 and T3) are shown. It can be seen that the distribution curves of the two level states of the memory cell have a certain offset as time changes. Among them, T0 usually represents the time when no threshold voltage drift occurs, for example, it can usually be the time when the threshold voltage drift returns to zero after data refresh. Therefore, in order to ensure that the level state of the memory cell can be accurately distinguished, it is necessary to consider the read window margin (RWM) between the threshold voltage of the set state after the threshold voltage drift and the threshold voltage of the reset state at time T0. For example, Figure 1aIn the example, there is a certain read window margin between the threshold voltage of the set state at time T0 and the threshold voltage of the reset state at time T0. As time changes, the read window margin between the threshold voltage of the set state at time T1 and the threshold voltage of the reset state at time T0 will further decrease. In particular, it can be seen that the threshold voltage of the set state at time T2 and the threshold voltage of the reset state at time T0 have begun to overlap. At this time, it will be impossible to accurately determine whether the level state of the memory cell is the reset state or the set state that is mistakenly read as the reset state due to threshold voltage drift. Therefore, threshold voltage drift will shorten the time that the read voltage can correctly read data.

[0054] In particular, for a type of memory with an oscillating transistor switch (OTS), due to the characteristics of the oscillating device, when a voltage smaller than the threshold voltage is applied to both ends of the basic circuit unit (cell) of the oscillating device, the basic circuit unit will not be turned on, but a small subthreshold conduction current will exist, which will cause a certain drift problem in the threshold of the oscillating switch, and will also cause the threshold voltage of the level state of the memory cell to drift over time, which is called bias drift. For example, Figure 1b A schematic diagram illustrating the bias drift phenomenon in a memory device is shown. It includes distribution information (curves) for the two levels (set and reset) of a memory cell under different bias drift levels (B0, B1, and B2). For example, B0 indicates no bias drift. As the number of operations on the word line or bit line (i.e., BL, WL) in the memory increases, the bias drift phenomenon becomes more severe, and the corresponding distribution curves for the two levels are shown in curves B1 and B2. Similarly, the presence of bias drift also shortens the time it takes for the read voltage to correctly read data.

[0055] For example, see Figure 1c , Figure 1cThe effect diagram of the write-read interval supported by different read voltages (vread1, vread2, vreadn) is shown. It can be seen that at time T0~T1, the read voltage vread1 can effectively distinguish the set and reset states of the storage cell. Therefore, the read voltage vread1 usually supports data retention within the time period of T0~T1, that is, the length of time the memory can keep the data from being lost without refreshing or rewriting. Similarly, the read-write voltage vread2 usually supports data retention within the time period of T1~T2, and the read-write voltage vread n usually supports data retention within the time period of Tn-1 to Tn. In other words, by dividing the write-read interval into several intervals and setting different read-write voltages vread, it is ensured that each read-write voltage vread can correctly distinguish the set and reset states of the storage cell within a corresponding time interval, thereby supporting longer data retention. For example, Figure 1c The n read and write voltages shown (vread1 to vreadn) can support data retention from T0 to Tn. Of course, considering the influence of various factors such as read disturb, write disturb, drift, and random read noise, the read and write intervals supported by different read and write voltages can retain some overlap, thereby ensuring stable and reliable data readout from T0 to Tn.

[0056] However, the above scheme usually requires statistics or prediction of the write and read time for different data blocks, so as to determine the write and read time interval of the data, and then select the appropriate read voltage corresponding thereto. However, since the storage capacity of the memory device is huge and usually supports random access, it is difficult to accurately count the write and read time of the data. This method often requires larger static random access memory (SRAM) or dynamic random access memory (DRAM) resources for statistical counting, resulting in huge resource consumption. The wrong selection of mismatched vread for reading, for example, when a read voltage higher than the threshold voltage of the basic circuit unit (cell) is mistakenly selected for reading, part of the reset will be opened, forming partial crystallization, thereby reducing the threshold voltage of the basic circuit unit in the reset state. This situation causes read interference to the basic circuit unit in the reset state. When read interference occurs multiple times, the basic circuit unit in the reset state will be misread as the set state.

[0057] To address the aforementioned issues, the present application provides a memory device reading method, apparatus, and memory, aiming to address the issue of inaccurate data reading due to threshold voltage drift with minimal resource consumption. The details are as follows.

[0058] like Figure 2 As shown, Figure 2 A flowchart of a method for reading a memory device provided in an embodiment of the present application, specifically comprising steps S210 to S230:

[0059] S210 , determining a refresh time interval according to write and read time intervals supported by multiple read voltages of the memory device, so as to perform a full disk refresh on the memory device within the refresh time interval.

[0060] In an embodiment of the present application, a refresh time interval is set based on multiple write and read time intervals supported by multiple storage and read voltages, so that the storage device is fully refreshed within the refresh time interval to ensure that the drift phenomenon of each unit in the storage device is reset to zero after the refresh.

[0061] In particular, the memory device provided herein may include a gating switch, thereby effectively resolving the problem of inaccurate data reading due to phenomena such as threshold voltage drift and bias drift. In particular, the memory device may be a three-dimensional phase-change memory (3D-PCM).

[0062] Specifically, the setting of the refresh time interval can usually be based on the retention performance of the medium used by the storage device, such as factors such as threshold voltage drift, offset drift, and interference, and combined with the number of set read and write voltages to set a reasonable refresh time interval. For example, the write and read time interval that all read voltages can normally support can be set as the refresh time interval, so that all data can be fully refreshed within this refresh time interval. In other words, the maximum write and read time interval that can be supported by the multiple read voltages of the storage device through retry operations can be determined as the refresh time interval. That is, in a feasible implementation scheme, the step of determining the refresh time interval based on the write and read time intervals supported by the multiple read voltages of the storage device includes:

[0063] A maximum write / read time interval supported by multiple read voltages of the memory device is determined as a refresh time interval of the memory device.

[0064] S220 , in response to a read operation instruction of the memory device, reading the memory device using a first read voltage, and determining whether a read result of the first read voltage is error correctable.

[0065] After the storage device is fully refreshed through the specified refresh time interval to restore the drift phenomenon of each storage unit to zero, if a read operation instruction for the storage device is triggered at this time, for example, when reading data from a storage unit in the storage device, compared to the related art of determining the read and write time of the data by predicting the write and read time of the storage unit to select a suitable read voltage, in the solution provided in the embodiment of the present application, the first read voltage will be directly used to read the storage device, and it will be determined whether the reading result of the first read voltage can be corrected.

[0066] Specifically, in a feasible implementation scheme, the first read voltage here can select the minimum voltage value among multiple read voltages, that is, by preferentially selecting the minimum voltage value among the read voltages to read the memory device, and selecting the read and write voltages from low to high to read in sequence, and performing retry operations of reading in sequence in combination with the error correction results, the retry can be stopped once the correct error correction data is obtained. On the one hand, it avoids the use of an excessively large read voltage causing the reset to open and the formation of partial crystallization. On the other hand, since the memory device is fully refreshed within a determined refresh time interval, in the actual use of memory application scenarios, in most cases, the lowest read and write voltage vread1 is used to read most of the data, and the ratio of read retries is relatively low. For example, in a set of experimental data, more than 10 10 The data can be read using vread1, while the data read using vread2 does not exceed 10 6 , that is, less than 1% of the data needs to exceed the read voltage of vread1 to be read, so this read retry mechanism actually has a relatively small impact on bandwidth and average read latency.

[0067] However, as another feasible implementation of the present application, it is also possible to combine the statistics or prediction of the write and read time to determine the possible read voltage as the feasible read voltage, thereby selecting the minimum read voltage among the feasible read voltages as the first read voltage, rather than selecting the minimum read voltage among all the read and write voltages supported by the memory device as the first read voltage, so as to further improve the read efficiency. For details, please refer to Figure 3 , Figure 3 Another flowchart of selecting a first read voltage according to an embodiment of the present application includes steps S310 to S320:

[0068] S310 , according to a trigger time interval corresponding to the read operation instruction, determining a feasible read voltage supporting the trigger time interval from the plurality of read voltages.

[0069] In an embodiment of the present application, when the write and read time intervals of the read operation can be accurately predicted in a specific scenario or through a specific media management method, the feasible read voltage that supports the trigger time interval can also be determined from the read voltage based on the trigger time interval corresponding to the read operation instruction. The feasible read voltage generally includes a part of the read voltages or all of the multiple read voltages supported by the storage device. For example, the feasible read voltage may be vread2, vread3, and so on.

[0070] S320 , using a minimum read voltage among the feasible read voltages as a first read voltage to read the memory device.

[0071] In an embodiment of the present application, after determining the feasible read voltage that supports the trigger time interval through the aforementioned scheme, it is possible to continue to consider using the minimum read voltage among the feasible read voltages as the first read voltage, and then sequentially complete the read operation of the storage device through the aforementioned low-to-high retry mechanism provided.

[0072] That is to say, through the reading method provided in this application, the write and read time intervals of the read operation can be predicted in combination with characteristic scenarios or media management methods, so as to adaptively select a certain read voltage in the middle to try to read until the final result is obtained.

[0073] After reading the memory device using the first read voltage, determining whether the read result of the first read voltage is error-correctable may be achieved through an error correction code solution. In other words, determining whether the read result of the first read voltage is error-correctable includes:

[0074] Whether a reading result of the first reading voltage is error correctable is determined by an error correction code.

[0075] The error correction code (ECC) here can be configured as a variety of types. For example, the error correction code here can be selected from Hamming code, BCH code (Bose–Chaudhuri–Hocquenghem Code), low-density parity-check code (LDPC, Low-Density Parity-Check Code), etc. This application does not limit the specific type of error correction code. It can be set based on the memory device used, and the embodiments of this application are not detailed here.

[0076] Furthermore, determining whether the read result of the first read voltage is error-correctable by using the error correction code may generally refer to matching the read result with the error correction code to determine the number of error bits in the read result. Specifically, under normal circumstances, when the number of error bits in the read result is low, the read result can often be considered error-correctable, that is, the error correction code can be used to correct the read result, thereby correcting to obtain an accurate read result. However, when the number of error bits in the read result is large, it is often difficult to correct the read result by using the error correction code, and it can be determined that the current read result is error-uncorrectable. In other words, determining whether the read result of the first read voltage is error-correctable by using the error correction code includes:

[0077] determining the number of error bits of a reading result of the first reading voltage by using an error correction code;

[0078] When the number of error bits exceeds a preset bit threshold, determining that the reading result of the first reading voltage is uncorrectable;

[0079] When the number of error bits does not exceed a preset bit threshold, it is determined that the reading result of the first reading voltage is correctable.

[0080] Among them, the preset bit number threshold here can be set based on the type of error correction code. For example, for Hamming code, it often supports correction of single-bit errors, while for some other error correction codes, such as BCH code and Reed-Solomon code, it can often also support correction of more bits, depending on the design and redundancy of the error correction code.

[0081] Furthermore, it should be noted that the number of error bits between the error correction code and the read result can also reflect the degree of error in the read result. For example, the higher the difference between the number of error bits and the preset bit threshold, the more serious the error in the data read result, which may often be caused by the use of an incorrect read voltage. Therefore, in another feasible implementation, if the read result is determined to be uncorrectable, the difference between the number of error bits and the preset bit threshold can also be used to determine whether to try again using the same read voltage. This will be explained in detail in subsequent embodiments.

[0082] S230 : When the read result of the first read voltage is uncorrectable, read the memory device using a second read voltage.

[0083] After completing the reading of the memory device using the first read voltage provided above and obtaining a corresponding read result, and verifying whether the read result of the first read voltage is correctable using an error correction code or other means, a determination is made as to whether a higher read voltage should be selected for retrying the read based on the correctability of the read result. In other words, if the read result of the first read voltage is not correctable, a second read voltage is used to read the memory device, wherein the second read voltage is higher than the first read voltage.

[0084] Of course, correspondingly, in the reading method of the memory device provided in the present application, when the reading result of the first reading voltage is correctable, an error correction code will be used to correct the reading result, so that the corrected reading result will be output as the true reading result.

[0085] Of course, it should be noted that the memory device reading method provided in the present application is a scheme that uses different read voltages from low to high to perform read retry in sequence. That is, after the memory device is read using the second read voltage, it is also determined whether the read result of the second read voltage can be corrected. If the read result of the second read voltage cannot be corrected, the memory is read using a third read voltage, wherein the third read voltage is higher than the second read voltage. That is, the reading method further includes:

[0086] When the read result of the second read voltage is uncorrectable, reading the memory device using a third read voltage, wherein the third read voltage is higher than the second read voltage;

[0087] If the read result is correctable, the corrected read result is output.

[0088] In an embodiment of the present application, when the reading result of the second reading voltage is still uncorrectable, the reading voltage will continue to be increased, and a higher third reading voltage will be used for reading. Of course, after reading using the third reading voltage, it is also necessary to further determine whether the reading structure of the third reading voltage can be corrected. If it is still not correctable, the reading voltage will be further increased until a certain reading result is correctable. The error correction code can be used to correct the correctable reading result until the corrected reading result is output.

[0089] Of course, combined with the above description, it can be seen that since the number of error bits between the error correction code and the read result can also reflect the degree of error in the read result, for some read results that cannot be corrected, the degree of error is relatively low, which may be caused by interference factors in the read process. In this case, the original read voltage can still be used to try to read again. That is to say, in one embodiment, refer to Figure 4 , Figure 4 A flowchart of a method for reading a memory device using different read voltages is provided in an embodiment of the present application, specifically including steps S410 to S420:

[0090] S410 , when the difference between the number of error bits and the preset number of bits threshold exceeds the preset difference threshold, use a second read voltage to read the memory device.

[0091] In an embodiment of the present application, when the number of error bits exceeds a preset bit threshold, that is, when it is determined that the reading result cannot be corrected, the difference between the number of error bits and the preset bit threshold is further determined, and it is determined whether the difference exceeds the preset difference threshold.

[0092] Specifically, when the difference exceeds the preset difference threshold, it indicates that there is a large deviation between the read result and the actual result, which is often caused by the use of an incorrect read voltage. Therefore, in an embodiment of the present application, a higher second read voltage will be selected to read the storage device.

[0093] S420 : When the difference between the number of error bits and the preset number of bits threshold does not exceed the preset difference threshold, continue to use the first read voltage to read the memory device.

[0094] What is different from the steps provided above is that when the difference between the number of error bits and the preset number of bit thresholds does not exceed the preset difference threshold, it indicates that although the read result is uncorrectable, there is not a large deviation from the actual result. It may often be an error caused by read interference or some other interference factors. After performing a read operation, these interference factors may be eliminated. Therefore, in the embodiment of the present application, the first read voltage will continue to be selected to continue to perform a read operation on the memory device. Of course, if the read result of the second use of the first read voltage is still uncorrectable, a higher read voltage, that is, the second read voltage, will continue to be selected for reading.

[0095] Of course, it should be noted that the solution provided above can still be applied to readings at other read voltages. That is, when the reading result of the second read voltage or a higher read voltage cannot be corrected, the difference between the number of error bits corresponding to the read result and the preset bit threshold can also be used to determine whether it is appropriate to perform another read operation at the original read voltage, or to directly use a higher read voltage for the read operation.

[0096] Furthermore, considering that the read operation itself has a refreshing effect on threshold voltage drift, if the read data after the last read voltage attempt is still uncorrectable, an additional read operation can be performed. Thus, while maintaining the same number of read and write voltage resources, longer write and read times can be supported, extending the interval between periodic refreshes and reducing the resulting additional power consumption and bandwidth impact. Specifically, in a feasible implementation, the method further includes:

[0097] If a read result of reading the memory device using a maximum read voltage among the read voltages is uncorrectable, the memory device is continuously read using the maximum read voltage at least once.

[0098] The method provided in an embodiment of the present application performs a full disk refresh on a storage device by determining a refresh time interval based on the write and read time intervals supported by multiple read voltages. When a read operation instruction is triggered for the storage device, a first read voltage is used to read the storage device. By determining whether the read result of the first read voltage is error-correctable, it is determined whether a second read voltage higher than the first read voltage should be selected to continue reading the storage device. The solution provided in the present application, after a full disk refresh is scheduled within the refresh time interval, sequentially attempts to read data by selecting read voltages from low to high. This avoids the need to select an appropriate read voltage for reading based on complex write and read time statistics due to threshold voltage drift, effectively solving the problem of inaccurate data reading caused by threshold voltage drift by using fewer resources.

[0099] In order to clearly understand the reading method of the memory device provided in the embodiment of the present application, the following will be combined with the above Figures 2 to 4 The relevant content provided provides a complete process of a storage device reading method, specifically, including the following steps:

[0100] (1) Based on the medium retention performance, such as threshold voltage drift, bias drift, interference, and other factors, combined with the number of available read and write voltage resources, set the write and read time interval that can be supported when all read and write voltages are used as the refresh time interval, and refresh all data in this refresh time interval;

[0101] (2) According to the reasonable read / write voltage setting corresponding to the medium write / read time interval, multiple read / write voltages are selected, and the information of whether the error correction code is correctable is fed back. The data is read through the read retry mechanism. When the read data is correctable, the corrected data is output. When the data is uncorrectable, the next read voltage is selected for reading until the correctable data is read, and the reading is stopped.

[0102] (3) Select the read voltage from low to high, and retry in combination with the error detection result of the error correction code. First use the lowest vread1 to read. If the error correction code determines that the read data is correctable, the read operation stops and the corrected read data is output. If the error correction code determines that it is not correctable, the next gear is changed to vread2 for reading. If the error correction code determines that it is correctable, the read operation stops and the corrected read data is output. If the error correction code determines that it is not correctable, the next higher gear is changed to vread3 for reading, and so on, until the highest gear vreadn is used for reading. If the read result is not correctable, an unreadable prompt message is output and included in the bad block management. If it is correctable, the corrected read data is output. For the specific process diagram, please refer to Figure 5 .

[0103] (4) Considering that the read operation itself has a refreshing effect on the threshold voltage drift, when the read data of the last read / write voltage, that is, vreadn, is still uncorrectable, another vreadn attempt can be made. In this way, while maintaining the same number of read voltage resources, a longer write / read time can be supported, the time interval of periodic refresh can be extended, and the additional power consumption and bandwidth impact caused by this can be reduced.

[0104] Due to die-to-die variation (a phenomenon in which performance and characteristics differ between different chips on the same wafer due to differences in process, materials, and environment during the semiconductor manufacturing process) and bias drift, the write and read time intervals covered by the set read voltage often have a large margin. Therefore, in most cases, most data can be read using the first few read and write voltages. Therefore, this method has little impact on the overall module bandwidth delay.

[0105] In one embodiment, in order to implement the aforementioned storage device reading method, the present application also provides a storage device reading device, see Figure 6 , Figure 6 A schematic structural diagram of a reading device of a storage device provided in an embodiment of the present application, specifically comprising:

[0106] a refresh module 610 configured to determine a refresh time interval according to a plurality of read voltages of the memory device and a maximum write / read time interval supported by the memory device through a retry operation, so as to perform a full disk refresh on the memory device within the refresh time interval;

[0107] a read module 620 configured to read the memory device using a first read voltage in response to a read operation instruction of the memory device, and determine whether a read result of the first read voltage is error correctable;

[0108] The retry module 630 is configured to read the memory device using a second read voltage if the read result of the first read voltage is uncorrectable, wherein the second read voltage is higher than the first read voltage.

[0109] In a feasible implementation, the retry module 630 is further configured to, if a read result of the second read voltage is uncorrectable, read the memory device using a third read voltage, wherein the third read voltage is higher than the second read voltage;

[0110] If the read result is correctable, the corrected read result is output.

[0111] In a feasible implementation, the refresh module 610 is configured to determine a refresh time interval based on a plurality of read voltages of the memory device and a maximum write / read time interval supported by the memory device through a retry operation, so as to perform a full disk refresh on the memory device within the refresh time interval.

[0112] In a feasible implementation, the refresh module 610 is further configured to determine a maximum write / read time interval supported by multiple read voltages of the memory device as a refresh time interval of the memory device.

[0113] In a feasible implementation, the reading module 620 is further configured to determine, according to the trigger time interval corresponding to the read operation instruction, a feasible reading voltage that supports the trigger time interval from the multiple reading voltages;

[0114] A minimum read voltage among the feasible read voltages is used as a first read voltage to read the memory device.

[0115] In a feasible implementation, the reading module 620 is further configured to determine whether a reading result of the first reading voltage is error correctable by using an error correction code.

[0116] In a feasible implementation, the reading module 620 is further configured to determine the number of error bits of the reading result of the first reading voltage by using an error correction code;

[0117] When the number of error bits exceeds a preset bit threshold, determining that the reading result of the first reading voltage is uncorrectable;

[0118] When the number of error bits does not exceed a preset bit threshold, it is determined that the reading result of the first reading voltage is correctable.

[0119] In a feasible implementation, the retry module 630 is further configured to read the memory device using a second read voltage when the difference between the number of error bits and the preset number of bits threshold exceeds a preset difference threshold;

[0120] When the difference between the number of error bits and the preset number of bit thresholds does not exceed the preset difference threshold, the memory device is continuously read using the first read voltage.

[0121] In a feasible implementation, the retry module 630 is further configured to continue performing at least one read operation on the memory device using the maximum read voltage among the read voltages when a read result of the memory device read using the maximum read voltage is uncorrectable.

[0122] The reading device provided in an embodiment of the present application performs a full disk refresh on a storage device by determining a refresh time interval based on the write and read time intervals supported by multiple read voltages. When a read operation instruction is triggered for the storage device, the first read voltage is used to read the storage device. By determining whether the read result of the first read voltage is error-correctable, it is determined whether a second read voltage higher than the first read voltage should be selected to continue reading the storage device. The solution provided in the present application, after a full disk refresh is scheduled within the refresh time interval, selects read voltages from low to high to attempt reading in sequence. This avoids the need to select an appropriate read voltage for reading based on complex write and read time statistics due to threshold voltage drift, effectively solving the problem of inaccurate data reading caused by threshold voltage drift by using fewer resources.

[0123] In one embodiment, the reading device of the memory device provided above is configured to be provided in the form of a circuit in an operating circuit coupled to the memory device, and the memory device is in the form of a memory cell array including a plurality of memory cells, wherein the operating circuit and the memory cell array together constitute a memory, see Figure 7 , Figure 7This is a schematic diagram of the structure of a memory provided in an embodiment of the present application. Specifically, the memory 700 includes a memory cell array 710 and an operating circuit 720, wherein the memory cell array 710 includes a plurality of memory cells 711. The operating circuit 720 is coupled to the memory cell array 710. The operating circuit 720 is configured to execute the memory device reading method described in any of the above embodiments, for example, executing the following steps:

[0124] Determining a refresh time interval according to write and read time intervals supported by multiple read voltages of the memory device, so as to fully refresh the memory device within the refresh time interval;

[0125] In response to a read operation instruction of the memory device, reading the memory device using a first read voltage, and determining whether a read result of the first read voltage is error correctable;

[0126] If the read result of the first read voltage is uncorrectable, the memory device is read using a second read voltage, wherein the second read voltage is higher than the first read voltage.

[0127] In one embodiment, the reading device of the memory device provided above is independently configured in a controller between the memory devices, that is, the controller executes the reading method of the memory device provided in this application. Figure 8 The present application also provides a storage system, including a memory 700 and a controller 800 as provided in the aforementioned embodiment, wherein the controller 800 can be configured to execute the reading method of the storage device provided in the embodiment of the present application to control the operating circuit in the memory 700, so that the operating circuit can realize the reading of the storage array in the memory 700.

[0128] Any reference to the memory, database or other media used in the various embodiments provided herein may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory may include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0129] The processors involved in the various embodiments provided in this application may be general-purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, data processing logic devices based on quantum computing, etc., but are not limited thereto.

[0130] In the above embodiments, the description of each embodiment has its own focus. For parts not described in detail in one embodiment, please refer to the relevant description of other embodiments. Those skilled in the art will clearly understand that for the convenience and brevity of description, the reading method and device of the memory device described above, as well as the specific working process and beneficial effects of the memory device, can refer to the description in the above embodiments, and the details will not be repeated here.

[0131] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0132] The above is a detailed introduction to a reading method, device and memory of a storage device provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, based on the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for reading a memory device, characterized in that: The method comprises: Determining a refresh time interval according to write and read time intervals supported by multiple read voltages of the memory device, so as to fully refresh the memory device within the refresh time interval; In response to a read operation instruction of the memory device, reading the memory device using a first read voltage, and determining whether a read result of the first read voltage is error correctable; If the read result of the first read voltage is uncorrectable, the memory device is read using a second read voltage, wherein the second read voltage is higher than the first read voltage.

2. The method according to claim 1, characterized in that The method further comprises: When the read result of the second read voltage is uncorrectable, reading the memory device using a third read voltage, wherein the third read voltage is higher than the second read voltage; If the read result is correctable, the corrected read result is output.

3. The method according to claim 1, characterized in that The write and read time intervals supported by the multiple read voltages of the memory device at least partially overlap; The step of determining a refresh time interval according to the write and read time intervals supported by the plurality of read voltages of the memory device includes: A maximum write / read time interval supported by multiple read voltages of the memory device is determined as a refresh time interval of the memory device.

4. The method according to claim 1, wherein The first read voltage is a minimum voltage value among the plurality of read voltages.

5. The method according to claim 1, characterized in that The step of reading the memory device using a first read voltage includes: determining, according to a trigger time interval corresponding to the read operation instruction, a feasible read voltage supporting the trigger time interval from the plurality of read voltages; A minimum read voltage among the feasible read voltages is used as a first read voltage to read the memory device.

6. The method according to claim 1, characterized in that The determining whether a reading result of the first reading voltage is error correctable includes: Whether a reading result of the first reading voltage is error correctable is determined by an error correction code.

7. The method according to claim 6, characterized in that The determining whether the reading result of the first reading voltage is error correctable by using an error correction code includes: determining the number of error bits of a reading result of the first reading voltage by using an error correction code; When the number of error bits exceeds a preset bit threshold, determining that the reading result of the first reading voltage is uncorrectable; When the number of error bits does not exceed a preset bit threshold, it is determined that the reading result of the first reading voltage is correctable.

8. The method according to claim 7, characterized in that When a reading result of the first reading voltage is uncorrectable, reading the memory device using a second reading voltage includes: When the difference between the number of error bits and the preset number of bits threshold exceeds a preset difference threshold, reading the memory device using a second read voltage; When the difference between the number of error bits and the preset number of bits threshold does not exceed the preset difference threshold, the memory device is read using a first read voltage.

9. The method according to claim 1, characterized in that The method further comprises: If a read result of reading the memory device using a maximum read voltage among the read voltages is uncorrectable, the memory device is continuously read using the maximum read voltage at least once.

10. The method according to any one of claims 1 to 9, characterized in that The memory device is a memory including a gate switch.

11. A reading device for a storage device, characterized in that: The device comprises: a refresh module, configured to determine a refresh time interval according to write and read time intervals supported by multiple read voltages of the memory device, so as to perform a full disk refresh on the memory device within the refresh time interval; a reading module, configured to read the memory device using a first reading voltage in response to a read operation instruction of the memory device, and determine whether a reading result of the first reading voltage is error correctable; The retry module is configured to read the memory device using a second read voltage when a read result of the first read voltage is uncorrectable, wherein the second read voltage is higher than the first read voltage.

12. A memory, characterized in that: comprising a memory cell array, wherein the memory cell array comprises a plurality of memory cells; and an operating circuit coupled to the memory cell array; The operation circuit is configured to execute the reading method of the memory device according to any one of claims 1 to 10.

13. A storage system, characterized in that: The system includes a controller and the memory according to claim 12 , wherein the controller is configured to control an operation circuit in the memory to execute a reading method of a memory device.

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