EFuse storage unit, eFuse array and operation method of eFuse storage unit

Abstract

The invention discloses an eFuse memory cell, an eFuse array and an operation method thereof, and belongs to the technical field of memory devices, the eFuse memory cell, the eFuse array and the operation method thereof comprise a differential memory group and a reference memory group which are controlled by different bit lines, each memory group comprises two subunits which are connected in parallel through the bit lines, the subunits are further connected with corresponding word lines to be controlled, and the word lines are connected with the reference memory group. The eFuse storage unit is further provided with a power supply port, a first voltage division circuit control tube and a second voltage division circuit control tube so as to carry out read operation in a voltage division comparison mode. The fuse wires are divided into the differential storage group and the reference storage group, data storage is realized by utilizing a voltage differential comparison relation caused by a difference value between resistance values of the two groups of fuse wires, and the resistance value of a specific fuse wire is changed to modify the voltage differential comparison relation between the specific fuse wire and the reference storage group, so that failed storage data are corrected; or carrying out secondary programming on all the storage units.

Description

Technical Field

[0001] The present invention relates to the technical field of memory devices, and in particular to an eFuse memory unit, an array and an operating method thereof. Background Art

[0002] An EFuse (Electrically Programmable Fuse) is a common one-time programmable memory that stores data by changing the resistance value through electromigration or melting of the fuse. Existing eFuse technology typically controls the current in the circuit to control whether the fuse blows to complete the programming operation from logic "0" to logic "1". The common eFuse memory cell architecture is as follows:

[0003] like Figure 1 The figure shows the voltage comparison and amplification process of a conventional eFuse memory cell during a read operation. After the word line (WL) is enabled, the change in the resistance of the first fuse R1 causes a change in the voltage VBL1 on the first bit line (BL1). This voltage is then compared and amplified with the voltage Vref of the reference resistor in the sense amplifier (SA), which then outputs the corresponding logic value.

[0004] Figure 7 The figure shows the differential voltage comparison and amplification process of a conventional eFuse memory cell during a read operation. After WL is selected, the first fuse programming control transistor N1 and the second voltage divider circuit control transistor N2 are turned on, forming two paths to ground from the first bit line BL1, the first fuse R1, and the first fuse programming control transistor N1, and from the second bit line BL2, the second fuse R2, and the second fuse programming control transistor N2. Changes in the resistance values of the first fuse R1 and the second fuse R2 cause the voltages V on the first bit line BL1 and the second bit line BL2 to increase, respectively. BL1 With V BL2 changes, the two are compared and amplified in SA, when V BL1 Greater than V BL2 output logic 1, otherwise output logic 0.

[0005] EFuse programming is the process of changing the resistance value of the fuse, usually the larger resistance of the fuse represents logic "1" and the smaller resistance represents logic "0". Figure 3a The electron microscope image of the fuse before programming is shown. At this time, the resistance value of the fuse is about 10Ω to 20Ω. After normal programming, Figure 3b As shown in the figure, the resistance of the fuse is usually greater than 100kΩ. However, there are many reasons that may cause eFuse programming failure during the actual programming process, such as Figure 3cThe electron microscope image shown below shows a fuse after programming failure. Since the programming operation is a one-time operation, the fuse resistance will not change after it changes, and the incorrect data cannot be corrected by repeated programming.

[0006] A common solution is double bit redundancy, which uses two eFuse units or selects one unit from each of the two eFuse units to store the same data. The two units are redundant backups of each other. When the eFuse is programmed in double bit redundancy mode, each programming address bit is mapped to two addresses (eFuse units) at the same time and programmed separately, so that the same data is stored in the two units. When performing a read operation, the data stored in the redundant addresses (units) are read out at the same time, and then the final output is formed after performing an OR logic operation. Figure 4 As shown, DA[n] and DB[n] are the outputs of two redundant backup address bits, and D[n] is the final output of eFuse.

[0007] D[n]=DA[n]+DB[n] (1)

[0008] Figure 4 The dual-bit redundancy method shown in the figure only provides redundant backup for programmed data (logical value "1"). For example, if the eFuse cell is programmed with a logical "1" and that data bit fails and becomes a logical "0," the dual-bit redundancy method still outputs the correct value "1." However, if the eFuse storage data fails, changing from a logical value "0" to a logical value "1," the dual-bit redundancy method outputs an incorrect value "1," indicating that this method cannot provide redundant backup for the data value "0."

[0009] This ensures that if one of the cells fails, the other cell can still output the correct data. However, dual-bit redundancy can only be used for the failure mode where the stored logic value "1" becomes "0". If the reverse is true, it will not work as a backup. Other redundancy correction methods or algorithms can also be used to improve the reliability of eFuse, but they also have different shortcomings. They can only correct a specific number of failed bits, or can only correct one failure in each row of the eFuse storage array, etc.

[0010] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0011] The object of the present invention is to provide an eFuse memory cell, an array and an operation method thereof, so as to solve the problems of programming operation failure and accidental programming.

[0012] In order to solve the above technical problems, the present invention provides an eFuse storage unit, including a differential storage group and a reference storage group controlled by different bit lines, each storage group includes two sub-units connected in parallel through the bit line, the sub-units are also connected to the corresponding word line for control, and the sub-units contain at least one programmable fuse, the eFuse storage unit is also configured with a power supply port, a first voltage divider circuit control tube and a second voltage divider circuit control tube to perform a read operation through a voltage divider comparison mode, the input ends of the first voltage divider circuit control tube and the second voltage divider circuit control tube are both connected to the power supply port, the first divider circuit control tube is connected to the power supply port, and the first divider circuit control tube is connected to the power supply port. The control ends of the first voltage divider circuit control tube and the second voltage divider circuit control tube are both connected to the voltage divider control row line, and the input ends of the two sub-units controlled by the same word line are respectively connected to the output ends of the first voltage divider circuit control tube and the second voltage divider circuit control tube. The resistance value of the fuse in the differential storage group is set so that the eFuse storage unit outputs the required logic value, and the ratio of the resistance values of the fuses in the reference storage group is configured to a predetermined value. When the programming of the differential storage group fails, the resistance value of the fuse in the reference storage group is programmed to correct the output of the eFuse storage unit.

[0013] Preferably, the differential storage group includes a first fuse and a third fuse, the first ends of the first fuse and the third fuse are connected to the first bit line in common, the second end of the first fuse is connected to the output end of the first voltage divider circuit control tube, the second end of the first fuse is also connected to the input end of the first fuse programming control tube, the output end of the first fuse programming control tube is grounded, and the control end of the first fuse programming control tube is connected to the first word line.

[0014] Preferably, the second end of the third fuse is connected to the input end of the third fuse programming control tube, the output end of the third fuse programming control tube is grounded, and the control end of the third fuse programming control tube is connected to the second word line.

[0015] Preferably, the reference storage group includes a second fuse and a fourth fuse, the first ends of the second fuse and the fourth fuse are commonly connected to the second bit line, the second end of the second fuse is connected to the output end of the second voltage divider circuit control tube, the second end of the second fuse is also connected to the input end of the second fuse programming control tube, the output end of the second fuse programming control tube is grounded, and the control end of the second fuse programming control tube is connected to the first word line.

[0016] Preferably, the second end of the fourth fuse is connected to the input end of the fourth fuse programming control tube, the output end of the fourth fuse programming control tube is grounded, and the control end of the fourth fuse programming control tube is connected to the second word line.

[0017] Preferably, before programming, the resistance ratio of the second fuse to the fourth fuse is configured to be 1, so as to modify the output of the eFuse storage unit by programming to modify the resistance ratio of the second fuse to the fourth fuse.

[0018] Preferably, the outputs of the differential storage group and the reference storage group are connected to a comparison amplifier through bit lines for comparison output.

[0019] Preferably, the first voltage divider circuit control transistor and the second voltage divider circuit control transistor are both NMOS transistors.

[0020] The present invention also provides an eFuse storage array, comprising a plurality of eFuse storage units as described above, wherein the plurality of eFuse storage units are arranged in an array.

[0021] The present invention also provides an operating method for an eFuse storage unit, which uses the eFuse storage unit as described above and further includes the following steps:

[0022] Selecting the corresponding word line and bit line, and programming the resistance value of the fuse in the differential storage group so that the eFuse storage unit outputs the required logic value;

[0023] When the fuse programming in the differential storage group fails, programming the resistance value of the fuse in the reference storage group to correct the output of the eFuse storage unit;

[0024] The corresponding voltage divider circuit control tube is turned on by voltage divider control row line, the even-numbered word lines are turned off, and the odd-numbered word lines are turned on to generate two voltage divider paths, and the voltage values of the voltage divider paths are compared to output a logic value.

[0025] In the eFuse storage unit provided by the present invention, fuses are divided into a differential storage group and a reference storage group. Data storage is achieved by utilizing the voltage differential comparison relationship caused by the difference between the resistance values of the two groups of fuses. At the same time, by changing the resistance value of a specific fuse, the voltage differential comparison relationship between them is modified, thereby correcting failed storage data or performing secondary programming on all storage cells. This can correct a logical value of 0 to 1 or from a logical value of 1 to 0. It also provides the eFuse with the option of secondary programming, and all cells can be modified, thereby improving usage flexibility and correction efficiency.

[0026] The eFuse storage array provided by the present invention and the eFuse storage unit provided by the present invention belong to the same inventive concept. Therefore, the eFuse storage array provided by the present invention has at least all the advantages of the eFuse storage unit provided by the present invention, which will not be repeated here.

[0027] The operating method of the eFuse storage unit provided by the present invention and the eFuse storage unit provided by the present invention belong to the same inventive concept. Therefore, the operating method of the eFuse storage unit provided by the present invention has at least all the advantages of the eFuse storage unit provided by the present invention, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0029] Figure 1 This is a comparative enlarged structural diagram of a conventional eFuse storage cell;

[0030] Figure 2 This is a diagram of the differential comparison amplification structure of a conventional eFuse storage unit;

[0031] Figure 3a This is an electron microscope image of a conventional eFuse memory cell before fuse programming;

[0032] Figure 3b This is an electron microscope image of a conventional eFuse memory cell after fuse programming;

[0033] Figure 3c This is an electron microscope image of a conventional eFuse memory cell after fuse programming failure;

[0034] Figure 4 This is a schematic diagram of the dual redundant backup structure of the eFuse storage unit;

[0035] Figure 5 1 is a schematic diagram of the structure of an eFuse storage unit according to an embodiment of the present invention;

[0036] Figure 6 This is a schematic diagram of the output conversion of an eFuse storage unit according to an embodiment of the present invention;

[0037] Figure 7 1. It is a schematic diagram of the logic input of the voltage divider circuit of the eFuse memory cell read operation according to one embodiment of the present invention;

[0038] Figure 8 1 is a schematic diagram of voltage division comparison in a read operation of an eFuse memory cell according to an embodiment of the present invention;

[0039] Figure 9 1 is a schematic diagram of the programming correction principle of an eFuse memory cell according to an embodiment of the present invention;

[0040] Figure 10 FIG2 is a schematic diagram of a 2x2 array of eFuse memory cells according to another embodiment of the present invention;

[0041] Figure 11 This is a flow chart of an operating method of an eFuse storage unit according to another embodiment of the present invention.

[0042] In the attached figure:

[0043] 100, differential storage group; 101, first subunit; 102, third subunit; 200, reference storage group; 201, second subunit; 202, fourth subunit. DETAILED DESCRIPTION

[0044] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0045] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in a sense including "and / or", the term "several" is generally used in a sense including "at least one", and the term "at least two" is generally used in a sense including "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features. Therefore, features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of such features. The term "proximal end" generally refers to the end closest to the operator, and the term "distal end" generally refers to the end closest to the patient. "One end" and "the other end" as well as "proximal end" and "distal end" generally refer to two corresponding parts, which include not only endpoints. The terms "mounted", "connected", and "connected" should be understood in a broad sense. For example, they can be fixedly connected, detachably connected, or integrated; they can be mechanically connected or electrically connected; they can be directly connected or indirectly connected through an intermediate medium; they can be internal communication between two elements or an interactive relationship between two elements. In addition, as used in the present invention, "one element is arranged on another element" generally only means that there is a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element, and it should not be understood to indicate or imply a spatial positional relationship between the two elements, that is, one element can be in any position such as inside, outside, above, below, or to the side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0046] The inventors' research found that as a memory, reliability is one of the important indicators of eFuse. However, the one-time operation characteristics of eFuse cause the data to become invalid and unable to be corrected after an error occurs, which reduces the reliability of the chip. The conventional dual-bit redundant backup method can only correct programming errors, but when the unit is accidentally programmed, that is, the resistance value increases, the backup fails, and the erroneous value "1" will be output instead of the correct value "0".

[0047] Based on this, the core idea of the present invention is to provide an eFuse storage unit that can correct stored data, divide the fuses into a differential storage group and a reference storage group, and use the voltage differential comparison relationship caused by the difference between the resistance values of the two groups of fuses to realize data storage. At the same time, by changing the resistance value of a specific fuse in the reference storage group, and then modifying the voltage differential comparison relationship between them, it is possible to correct the failed storage data or perform secondary programming on all storage cells, which can correct the logical value 0 to 1 or from the logical value 1 to 0, providing the eFuse storage unit with the option of secondary programming, and all cells can be modified, thereby improving the flexibility of use and the efficiency of correction.

[0048] For details, please refer to Figure 5-Figure 11 , which is a schematic diagram of an embodiment of the present invention. Figure 5 and Figure 6 As shown, an eFuse memory cell includes a differential memory group 100 and a reference memory group 200 controlled by different bit lines. Each memory group includes two sub-units connected in parallel via bit lines. The sub-units are also connected to corresponding word lines for control, and the sub-units contain at least one programmable fuse. The eFuse memory cell is also configured with a power supply port VDD, a first voltage divider circuit control transistor NL, and a second voltage divider circuit control transistor NR for performing a read operation through a voltage divider comparison mode. The input ends of the first voltage divider circuit control transistor NL and the second voltage divider circuit control transistor NR are both connected to the power supply port VDD. The first voltage divider circuit control transistor NL is connected to the power supply port VDD. The control ends of NL and the second voltage divider circuit control transistor NR are both connected to the voltage divider control row line RWL, and the input ends of the two sub-units controlled by the same word line are respectively connected to the output ends of the first voltage divider circuit control transistor and the second voltage divider circuit control transistor. Specifically, by setting the resistance value of the fuse in the differential storage group 100 so that the output of the eFuse storage unit has the required logic value, the ratio of the resistance value of the fuse in the reference storage group 200 is configured to a predetermined value, so that when the programming of the differential storage group 100 fails, the resistance value of the fuse in the reference storage group 200 is programmed to correct the output of the eFuse storage unit.

[0049] In each storage group, at least two fuses controlled by different word lines are connected in parallel through the bit line, or the second ends of the two fuses controlled by the same word line are respectively connected to the output ends of the first voltage divider circuit control tube NR and the second voltage divider circuit control tube NL. Here, only the differential storage group 100 is controlled by the first bit line BL1, and the reference storage group 200 is controlled by the second bit line BL2. The first fuse R1 and the third fuse R3 are connected in parallel through the first bit line BL1 in the differential storage group 100, and the second fuse R2 and the fourth fuse R4 are connected in parallel through the second bit line BL2 in the reference storage group 200. Each fuse can be programmed through the MOS tube connected thereto, which can be an NMOS tube or a PMOS tube. Here, only the NMOS tube is used as an example for description. The same principle applies to other forms of eFuse storage cells.

[0050] Specific as Figure 7 The voltage divider circuit shown includes a word line logic input. When performing a read operation, the voltage divider controls the row line RWL to a high level, and simultaneously turns on two voltage divider control transistors, the first voltage divider circuit control transistor NL and the second voltage divider circuit control transistor NR. The first word line WL1 is set to a low level, closing the path to ground, and the second word line WL2 is set to a high level, opening the path to ground, forming two left and right current paths from the power supply port VDD to ground, and generating two voltage values V BL1 and V BL2 The voltages of the two voltage divider paths have the following relationship:

[0051] V BL1 =V BL2

[0052] It can be seen that:

[0053]

[0054] Set R2 = R4, the difference between the first fuse R1 and the third fuse R3, then the voltage difference (ie V BL1 -V BL2 The difference is greater than or less than 0), and the difference is input to the SA amplifier, which generates different logic outputs, such as Figure 8 shown.

[0055] By programming the first fuse R1 and the second fuse R2 to output different values, after programming the first fuse R1, the resistance value increases, then R1 / R3>1(=R2 / R4), V BL1 <V BL2 , Q output is 0; after the third fuse R3 is programmed, the resistance value increases, then R1 / R3<1(=R2 / R4), V BL1 >V BL2, the Q output is 1. Denote R1 / R3 as A and R2 / R4 as B. As above, A greater than B represents logic 1. If A becomes smaller due to an accident, then the output logic 1 does not hold. It can be corrected by increasing A or decreasing B to output the required logic value.

[0056] From the above description of the working principle of the read operation of the eFuse storage unit of the present invention, it can be seen that V BL1 and V BL2 The voltage difference between them determines the logic value to be stored, and this voltage difference is caused by the ratio relationship between R1 / R3 and R2 / R4, which means that by changing the resistance values of the first fuse R1, the second fuse R2, the third fuse R3, and the fourth fuse R4, the comparison relationship between V BL1 and V BL2 can be changed, and the incorrect voltage ratio can be corrected, so as to modify any failure value of the eFuse unit.

[0057] Take Figure 8 The unit circuit in as an example. Assume that the resistance values of the second fuse R2 and the fourth fuse R4 are equal, and their ratio R2 / R4 is 1. If the ratio (R1 / R3) of the resistance values of the first fuse R1 and the third fuse R3 is less than 1, then, V BL1 is greater than V BL2 , and the output logic value of the eFuse storage unit is 1. When the first fuse R1 accidentally changes, causing the resistance value to increase, resulting in the ratio R1 / R3 being greater than 1, that is, R1 / R3 > R2 / R4, making V BL1 will be less than V BL2 , and the output of the eFuse storage unit changes, outputting the incorrect logic value 0.

[0058] To correct this error, the ratio of R2 / R4 can be corrected to ensure that the comparison relationship between R1 / R3 and R2 / R4 is correct again. The specific method is, for example, to make the resistance value of the second fuse R2 larger, so that R1 / R3 < R2 / R4, then V BL1 is greater than V BL2 again, and the output of the eFuse storage unit returns to the correct logic value 1. The actual operation of making the resistance value of the second fuse R2 larger is to program this fuse separately, and finally correct the incorrect output value.

[0059] Such as Figure 6As shown, a first subunit 101 and a third subunit 102 are provided in the differential storage group 100. The two subunits are connected in parallel via a first bit line BL1. Each subunit is provided with at least one fuse and at least one program control transistor. As described above, since the final output depends on the ratio between the fuse resistance in the first subunit 101 and the fuse resistance in the third subunit 102, a program control transistor can be provided to control multiple fuses, or multiple program control transistors and multiple fuses can be provided, so that the subunit can divide the voltage and output the required voltage V BL1 It can be understood that the fuse and programming control tube in the third sub-unit 102 are similar.

[0060] Exemplarily, a differential memory group 100 includes a first subunit 101 and a third subunit 102. The two subunits have the same structure, each employing a programming control transistor controlling a fuse. The differential memory group 100 can be referred to as a differential resistor pair. The differential memory group 100 includes a first fuse R1 and a third fuse R3. The first ends of the first and third fuses R1 and R3 are commonly connected to a first bit line BL1. The second ends of the first fuse R1 are connected to the output end of the first voltage divider circuit control transistor NL. The second end of the first fuse R1 is also connected to the input end of a first fuse programming control transistor N1. The output end of the first fuse programming control transistor N1 is grounded, and the control end of the first fuse programming control transistor N1 is connected to a first word line WL1. The second end of the third fuse R3 is connected to the input end of a third fuse programming control transistor N3. The output end of the third fuse programming control transistor N3 is grounded, and the control end of the third fuse programming control transistor N3 is connected to a second word line WL2.

[0061] Similarly, referring to the memory group 200, a second sub-unit 201 and a fourth sub-unit 202 are provided. The two sub-units are connected in parallel via the second bit line BL2. Each sub-unit is provided with at least one fuse and at least one program control transistor. As described above, since the final output depends on the ratio between the fuse resistance in the second sub-unit 201 and the fuse resistance in the fourth sub-unit 202, one program control transistor can be provided to control multiple fuses, or multiple program control transistors and multiple fuses can be provided, so that the sub-unit can output the required voltage V by voltage division. BL2 It can be understood that the fuse and programming control tube in the fourth sub-unit 202 are similar.

[0062] Specifically, a second subunit 201 and a fourth subunit 202 are provided in the reference memory group 200. The two subunits have the same structure, each employing a programming control transistor controlling a fuse. The reference memory group 200 can be referred to as a reference resistor pair. The reference memory group 200 includes a second fuse R2 and a fourth fuse R4. The first ends of the second fuse R2 and the fourth fuse R4 are commonly connected to the second bit line BL2. The second end of the second fuse R2 is connected to the output end of the second voltage divider circuit control transistor NR. The second end of the second fuse R2 is also connected to the input end of the second fuse programming control transistor N2. The output end of the second fuse programming control transistor N2 is grounded, and the control end of the second fuse programming control transistor N2 is connected to the first word line WL1. The second end of the fourth fuse R4 is connected to the input end of the fourth fuse programming control transistor N4. The output end of the fourth fuse programming control transistor N4 is grounded, and the control end of the fourth fuse programming control transistor N4 is connected to the second word line WL2.

[0063] In one embodiment, before programming, the ratio of the resistance values of the second fuse R2 and the fourth fuse R4 is configured to be 1, which is used to modify the ratio of the resistance values of the second fuse R2 and the fourth fuse R4 through programming to correct the output of the eFuse storage cell. The outputs of the differential storage group 100 and the reference storage group 200 are connected to the comparator amplifier via bit lines for comparison. The comparator amplifier is a sense amplifier (SA), which is one of the key components for detecting and amplifying the data in the storage cell. Because the signals on the data bit lines are usually very weak, the SA is required to sense and amplify these signals to achieve correct data reading.

[0064] In one embodiment, both the first voltage divider circuit control transistor NL and the second voltage divider circuit control transistor NR are NMOS transistors.

[0065] The eFuse storage unit provided by the present invention is a 7-port device (a first bit line BL1, a second bit line BL2, a first word line WL1, a second word line WL2, a voltage division control row line RWL, a ground port VSS and a power supply port VDD). Figure 5 As shown, the eFuse storage unit includes four fuses, a first fuse R1, a second fuse R2, a third fuse R3 and a fourth fuse R4. Each fuse can be equipped with a corresponding fuse programming control tube to achieve programming, such as Figure 5The first, second, third, and fourth fuse programming control transistors N1, N2, N3, and N4, as well as two voltage divider control transistors, the first and second voltage divider control transistors NL and NR, are connected. One end of the first and third fuses R1 and R3 is connected to form a first bit line BL1, while one end of the second and fourth fuses R2 and R4 is connected to form a second bit line BL2. The gates of the first and second fuse programming control transistors N1 and N2 are connected to form a first word line WL1, while the gates of the third and fourth fuse programming control transistors N3 and N4 are connected to form a second word line WL2. The other ends of the first, second, third, and fourth fuses R1, R2, R3, and R4 are connected to the drains of the corresponding first, second, third, and fourth fuse programming control transistors N1, N2, N3, and N4, respectively. Their sources are all connected to the ground port VSS (not labeled). The gate ends of the first voltage divider circuit control tube NL and the second voltage divider circuit control tube NR are connected to the port voltage divider control line RWL, their drain gates are connected to the power supply port VDD, and their source ends are respectively connected to the drain ends of the first fuse programming control tube N1 and the second fuse programming control tube N2.

[0066] The read operation of the EFuse storage unit is to divide the voltage ratio (V BL1 and V BL2 ) and then read the corresponding logic value data after difference amplification. BL1 Greater than V BL2 When Q outputs logic 1, when V BL1 Less than V BL2 When Q outputs logic 0. BL1 and V BL2 They are related to the ratios of R1 / R3 and R2 / R4 respectively. Therefore, the eFuse unit of the present invention can correct the erroneous voltage ratio relationship by changing the first fuse R1, the second fuse R2, the third fuse R3, and the fourth fuse R4, thereby achieving the goal of modifying any logic value of the eFuse unit.

[0067] [Example 1]

[0068] Please refer to Figure 10 , an eFuse storage array, including several eFuse storage units as described above, and several of the eFuse storage units are arranged in an array. Figure 10 The figure shows a 2x2 memory array composed of the eFuse memory cells of the present invention, in which BLCn controls the power supply to the PMOS transistor that supplies power to the bit line BLn. The memory array is composed of word lines WL and bit lines BL, eFuse memory cells, voltage divider control transistors, and voltage divider control row lines RWL.

[0069] The EFuse memory cell is a 7-port device (BL1 / BL2 / WL1 / WL2 / RWL / VSS / VDD) consisting of four fuses (R1 / R2 / R3 / R4), four fuse programming transistors (N1 / N2 / N3 / N4), and two voltage divider control transistors (NL and NR). Fuses R1 and R3 connect to form port BL1, while fuses R2 and R4 connect to form port BL2. The gates of programming transistors N1 and N2 connect to form port WL1, while the gates of programming transistors N3 and N4 connect to form port WL2. The other ends of fuses R1, R2, R3, and R4 connect to the drains of corresponding programming transistors N1, N2, N3, and N4, respectively, with their sources connected to VSS. The gates of voltage divider control transistors NL and NR connect to port RWL, their drains to VDD, and their sources to the drains of programming transistors N1 and N2, respectively.

[0070] exist Figure 10 In the memory array shown, all eFuse cells can be individually programmed by selecting the corresponding BL and WL. Since the read operation adopts the voltage division comparison mode, it is necessary to open the corresponding voltage division control tube through the voltage division control line RWL. At the same time, the WL of the even-numbered bits is closed and the WL of the odd-numbered bits is opened, respectively generating two voltage division paths to divide the voltage V BL1 and V BL2 For comparison, the polarity of the voltage difference represents the logic value. Figure 7 . Control the fuses in the differential storage group 100 and the fuses in the reference storage group 200 to conduct, forming two voltage divider circuits, which can be BL1 and V BL2 By comparing the relationship, the erroneous voltage ratio is corrected, thereby modifying any failure value of the eFuse unit.

[0071] [Example 2]

[0072] Based on the same technical concept, such as Figure 11 As shown, the present invention also provides an operating method of an eFuse storage unit, which uses the eFuse storage unit as described above and further includes the following steps:

[0073] S1, select the corresponding word line and bit line to program the resistance value of the fuse in the differential storage group 100, so that the eFuse storage unit outputs the required logic value. The output logic value Q of the eFuse storage unit depends on the ratio of the first fuse R1 / the third fuse R3 and the second fuse R2 / the fourth fuse R4. The resistance ratio determines the final output V BL1 and V BL2 The difference determines the Q value.

[0074] S2, when the fuse programming in the differential storage group 100 fails, the resistance value of the fuse in the differential storage group 100 is programmed to correct the output of the eFuse storage unit. When the first fuse R1 and / or the third fuse R3 in the differential storage group 100 unexpectedly changes, resulting in V BL1 The state changes, and the output Q will be wrong. By modifying the second fuse R2 and the fourth fuse R4 in the reference storage group 200, the V BL2 state, making V BL1 and V BL2 The difference is restored to its original state and the output Q is correct.

[0075] S3, turn on the corresponding voltage divider circuit control tube through the voltage divider control row line RWL, turn off the even-numbered word lines, and turn on the odd-numbered word lines to generate two voltage divider paths, compare the voltage values of the voltage divider paths, and output the logic value.

[0076] Here, we take the example of setting two fuses in the differential storage group 100 and setting two fuses in the reference storage group 200 as an example. The eFuse unit of the present invention compares the differential voltage caused by the resistance difference of the fuse pair, and uses the polarity of the comparison result (greater than or less than 0) to represent different logical values, and outputs the corresponding logical value 1 or 0 through amplification. Figure 7 As shown, the eFuse storage unit of the present invention is provided with a set of fuse measurement pairs (first fuse R1 / third fuse R3) and a set of fuse reference pairs (second fuse R2 / fourth fuse R4), and two control tubes, a first voltage divider circuit control tube NL and a second voltage divider circuit control tube NR, are respectively provided at one end of the first fuse R1 of the measurement pair and the second fuse R2 of the reference pair, for forming two current paths passing through the fuse measurement pair and the fuse reference pair respectively, and generating differential voltages V on the paths respectively. BL1 and V BL2 , which enters the amplifier SA and outputs the logic value Q.

[0077] The programming operation of the eFuse unit of the present invention is to program the third fuse R3 of the measurement pair, while the first fuse R1 of the measurement pair, the second fuse R2 of the reference pair, and the fourth fuse R4 remain in their original state, and their resistance values are substantially the same. BL1 and V BL2 ) for comparison, and then read out the corresponding logic value data after difference amplification. Figure 7 As shown. When V BL1 Greater than V BL2 When Q outputs logic 1, when V BL1 Less than V BL2 When Q outputs logic 0. BL1 and V BL2They are related to the ratios of R1 / R3 and R2 / R4 respectively. Therefore, the eFuse unit of the present invention can correct the erroneous voltage ratio relationship by changing the first fuse R1, the second fuse R2, the third fuse R3, and the fourth fuse R4, thereby achieving the goal of modifying any logic value of the eFuse unit.

[0078] The eFuse storage unit of the present invention generates and compares the differential voltage during the read operation. The voltage divider controls the row line RWL to a high level, the first word line WL1 to a low level, and the second word line WL2 to a high level, forming two current paths: one from the power supply port VDD through the first voltage divider circuit control transistor NL, the first fuse R1 and the third fuse R3, and the third fuse programming control transistor N3 to ground; and one from the power supply port VDD through the second voltage divider circuit control transistor NR, the second fuse R2 and the fourth fuse R4, and the fourth fuse programming control transistor N4 to ground. Since the second fuse R2 and the fourth fuse R4 remain unchanged, the voltage V on the BL line BL2 When the resistance values of the first fuse R1 and the second fuse R2 change, the voltage V BL1 changes. When V BL1 and V BL2 Compare and amplify the logic value corresponding to the output in SA.

[0079] By comparing the reference storage group and the differential storage group, specifically comparing the differential voltage caused by the difference in resistance values of the two fuse pairs, the polarity of the comparison result (greater than or less than 0) represents the logical value. Since the differential voltage is respectively related to the fuse resistance ratio, changing the fuse state (increasing the resistance value) can correct the erroneous voltage ratio relationship, thereby realizing the modification of any erroneous logical value that may appear in the eFuse unit. Therefore, the eFuse unit of the present invention has a complete correction function, which can correct unexpected "0" or "1" failures and is suitable for application scenarios with extremely high reliability requirements and harsh environments. At the same time, the storage array based on the eFuse unit of the present invention has a complete secondary programming function, which expands the scope of application.

[0080] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0081] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An eFuse storage unit, characterized in that: The invention relates to a differential storage group and a reference storage group controlled by different bit lines. Each storage group includes two sub-units connected in parallel via a bit line. The sub-units are also connected to corresponding word lines for control, and each sub-unit contains at least one programmable fuse. The eFuse storage unit is also configured with a power supply port, a first voltage divider circuit control transistor, and a second voltage divider circuit control transistor for performing a read operation in a voltage divider comparison mode. The input terminals of the first and second voltage divider circuit control transistors are both connected to the power supply port, and the control terminals of the first and second voltage divider circuit control transistors are both connected to the voltage divider control line. The input terminals of the two sub-units controlled by the same word line are respectively connected to the output terminals of the first and second voltage divider circuit control transistors. The eFuse storage unit outputs a desired logic value by setting the resistance value of the fuses in the differential storage group. The ratio of the resistance values of the fuses in the reference storage group is configured to a predetermined value. When programming of the differential storage group fails, the resistance value of the fuses in the reference storage group is programmed to correct the output of the eFuse storage unit.

2. The eFuse storage unit according to claim 1, wherein: The differential storage group includes a first fuse and a third fuse, the first ends of the first fuse and the third fuse are connected to the first bit line in common, the second end of the first fuse is connected to the output end of the first voltage divider circuit control tube, the second end of the first fuse is also connected to the input end of the first fuse programming control tube, the output end of the first fuse programming control tube is grounded, and the control end of the first fuse programming control tube is connected to the first word line.

3. The eFuse storage unit according to claim 2, wherein: The second end of the third fuse is connected to the input end of the third fuse programming control tube, the output end of the third fuse programming control tube is grounded, and the control end of the third fuse programming control tube is connected to the second word line.

4. The eFuse storage unit according to claim 1, wherein: The reference storage group includes a second fuse and a fourth fuse, the first ends of the second fuse and the fourth fuse are commonly connected to the second bit line, the second end of the second fuse is connected to the output end of the second voltage divider circuit control tube, the second end of the second fuse is also connected to the input end of the second fuse programming control tube, the output end of the second fuse programming control tube is grounded, and the control end of the second fuse programming control tube is connected to the first word line.

5. The eFuse storage unit according to claim 4, wherein: The second end of the fourth fuse is connected to the input end of the fourth fuse programming control tube, the output tube of the fourth fuse programming control tube is grounded, and the control end of the fourth fuse programming control tube is connected to the second word line.

6. The eFuse storage unit according to claim 4, wherein: The ratio of the resistance values of the second fuse and the fourth fuse is configured to be 1, and is used to modify the output of the eFuse storage unit by programming to modify the ratio of the resistance value of the second fuse and the resistance value of the fourth fuse.

7. The eFuse storage unit according to claim 1, wherein: The outputs of the differential memory group and the reference memory group are connected to a comparison amplifier through bit lines for comparison output.

8. The eFuse storage unit according to claim 1, wherein: The first voltage divider circuit control tube and the second voltage divider circuit control tube are both NMOS tubes.

9. An eFuse storage array, characterized in that: It comprises a plurality of eFuse storage units as described in any one of claims 1 to 8, wherein the plurality of eFuse storage units are arranged in an array.

10. A method for operating an eFuse storage unit, characterized in that: The eFuse storage unit according to any one of claims 1 to 8 further comprises the following steps: Selecting the corresponding word line and bit line, and programming the resistance value of the fuse in the differential storage group so that the eFuse storage unit outputs the required logic value; When the fuse programming in the differential storage group fails, programming the resistance value of the fuse in the reference storage group to correct the output of the eFuse storage unit; The corresponding voltage divider circuit control tube is turned on by voltage divider control row line, the even-numbered word lines are turned off, and the odd-numbered word lines are turned on to generate two voltage divider paths, and the voltage values of the voltage divider paths are compared to output a logic value.

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