Signal processing circuit and control method thereof, chip and electronic equipment

Abstract

The embodiment of the invention provides a signal processing circuit and a control method thereof, a chip and electronic equipment, the signal processing circuit comprises an amplification module, the amplification module has a reset stage and an amplification stage in each work cycle, and the amplification module is used for resetting in the reset stage and outputting an amplification signal according to an input signal in the amplification stage; the analog-to-digital conversion module is used for outputting a digital signal according to the amplified signal output by the amplification module; and the amplification control module is used for controlling the amplification module to enter a reset stage or an amplification stage in each work cycle. According to the application, the duration of the amplification module working in the amplification stage in the current working period can be shortened, and the phenomenon that the amplification module deviates from a normal working state due to gradual change of an input node of an operational amplifier of the amplification module caused by long-time working of the amplification module in the amplification stage is avoided.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to a signal processing circuit and a control method thereof, a chip, and an electronic device. Background Art

[0002] Currently, a programmable gain amplifier (PGA) is a circuit whose voltage gain can be controlled by programming. PGAs are often used as the pre-stage circuit of analog-to-digital converters, which helps improve the signal-to-noise ratio of signal measurement systems.

[0003] Capacitor-based programmable gain amplifiers (PGA) are widely used in related technologies due to their high common-mode voltage rejection capabilities. However, during operation, the voltages at the operational amplifier's non-inverting and inverting inputs remain suspended. If a capacitor-based PGA amplifies signals for an extended period, the voltages at the operational amplifier's non-inverting and inverting inputs may gradually change due to factors such as leakage, ultimately causing the PGA to deviate from its normal operating state. Summary of the Invention

[0004] In view of the above problems, the embodiments of the present application provide a signal processing circuit and a control method thereof, a chip, and an electronic device to solve the above technical problems.

[0005] In a first aspect, an embodiment of the present application provides a signal processing circuit, comprising:

[0006] An amplifying module, wherein the amplifying module has a reset phase and an amplifying phase in each working cycle, and the amplifying module is configured to reset in the reset phase and output an amplified signal according to the input signal in the amplifying phase;

[0007] An analog-to-digital conversion module, which is used to output a digital signal according to the amplified signal output by the amplification module;

[0008] An amplification control module, which is used to control the amplification module to enter a reset phase or an amplification phase in each working cycle;

[0009] In the amplification phase of each working cycle, when the magnitude of the digital signal meets the first preset condition, the amplification control module controls the amplification module to enter the reset phase in advance to shorten the duration of the amplification module working in the amplification phase in the current working cycle.

[0010] In a second aspect, an embodiment of the present application provides a signal processing circuit control method, including:

[0011] Controlling the amplification module to enter a reset phase or an amplification phase in each working cycle, so that the amplification module is reset in the reset phase and outputs an amplified signal according to the input signal in the amplification phase;

[0012] During the amplification phase of each working cycle, the analog-to-digital conversion module is controlled to output a digital signal according to the amplified signal output by the amplification module;

[0013] In the amplification phase of each working cycle, when the magnitude of the digital signal meets the first preset condition, the amplification module is controlled to enter the reset phase in advance to shorten the duration of the amplification module working in the amplification phase in the current working cycle.

[0014] In a third aspect, an embodiment of the present application further provides a chip comprising the above-mentioned signal processing circuit.

[0015] In a fourth aspect, an embodiment of the present application further provides an electronic device comprising the above-mentioned chip or signal processing circuit.

[0016] The present application uses an amplification control module to control the amplification module to enter a reset phase or an amplification phase during each operating cycle. During the amplification phase of the amplification module, the analog-to-digital conversion module can output a digital signal based on the amplified signal output by the amplification module, thereby achieving the conversion process of the analog signal to the digital signal. Furthermore, during the amplification phase of each operating cycle, when the magnitude of the digital signal satisfies a first preset condition, the amplification control module can control the amplification module to enter the reset phase in advance, thereby shortening the duration of the amplification phase of the current operating cycle, and avoiding the phenomenon in which the input node of the operational amplifier of the amplification module gradually changes due to the amplification module operating in the amplification phase for a long time, thereby causing the amplification module to deviate from its normal operating state.

[0017] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 A schematic diagram of a programmable gain amplifier with a capacitor architecture in the related art is shown.

[0020] Figure 2 A schematic diagram of a signal processing circuit in an embodiment of the present application is shown.

[0021] Figure 3Another schematic diagram of the signal processing circuit in an embodiment of the present application is shown.

[0022] Figure 4 A working schematic diagram of the amplification module in an embodiment of the present application is shown.

[0023] Figure 5 Another working schematic diagram of the amplification module in an embodiment of the present application is shown.

[0024] Figure 6 A working schematic diagram of the amplification control module in an embodiment of the present application is shown.

[0025] Figure 7 Another working schematic diagram of the amplification control module in an embodiment of the present application is shown.

[0026] Figure 8 Another schematic diagram of the signal processing circuit in an embodiment of the present application is shown.

[0027] Figure 9 Another schematic diagram of the signal processing circuit in an embodiment of the present application is shown.

[0028] Figure 10 A flow chart of a signal processing circuit control method in an embodiment of the present application is shown.

[0029] Figure 11 Another flow chart of the signal processing circuit control method in the embodiment of the present application is shown.

[0030] Among them, 10 is an amplification module, 20 is an analog-to-digital conversion module, 30 is an amplification control module, 40 is a first chopping switch module, and 50 is a second chopping switch module;

[0031] Digital signal Dout, operational amplifier OP, input capacitors Ci1 and Ci2, feedback capacitors Cf1 and Cf2, first reset switches Si1 and Si2, second reset switches Sf1 and Sf2, preset common-mode voltage VCM, first switch S01, second switch S02, third switch S03, fourth switch S04, fifth switch S05, sixth switch S06, seventh switch S07, and eighth switch S08. DETAILED DESCRIPTION

[0032] The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0033] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0034] In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, etc., are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0035] Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0036] In the description of the embodiments of this application, words such as "example" or "for example" are used to indicate an example, illustration, or description. Any embodiment or design described as "for example" or "for example" in the embodiments of this application is not to be construed as being preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to clearly present relative concepts.

[0037] In addition, in the embodiments of the present application, "plurality" refers to two or more. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two, or more. For example, "including at least one" means including one, two, or more, and does not limit which ones are included. For example, "including at least one of A, B, and C" means including A, B, C, A and B, A and C, B and C, or A, B, and C.

[0038] It should be noted that in the embodiments of the present application, "and / or" describes the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects are in an "or" relationship.

[0039] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0040] In the circuit structure provided in the embodiments of the present application, the first node, the second node and other nodes do not represent actual components, but represent the junction points of related couplings in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0041] A programmable gain amplifier is a circuit whose voltage gain can be controlled by programming. Figure 1 , Figure 1 A schematic diagram of a capacitor-based programmable gain amplifier in the related art is shown. The capacitor-based programmable gain amplifier includes an operational amplifier OP, an input capacitor C1, an input capacitor C2, a feedback capacitor C3, a feedback capacitor C4, a reset switch S1, a reset switch S2, a reset switch S3, and a reset switch S4. The programmable gain amplifier has a reset stage and an amplification stage.

[0042] In the reset phase of the programmable gain amplifier, reset switches S1, S2, S3, and S4 are closed, and the operational amplifier OP is connected in the form of unity gain negative feedback. At this time, the voltages at the non-inverting input and inverting output of the operational amplifier OP are equal to the common-mode output voltage of the operational amplifier, that is, VXP = VXN = VCMO. Therefore, the charge accumulated on the input capacitor C1 and the feedback capacitor C3, QXP, and the charge accumulated on the input capacitor C1 and the feedback capacitor C3, QXN, are respectively:

[0043] QXP=QC1+QC3=(VCMO-VCM)*Cp+0

[0044] QXN=QC2+QC4=(VCMO-VCM)*Cp+0

[0045] Wherein, QC1 is the charge accumulated by the input capacitor C1, QC3 is the charge accumulated by the feedback capacitor C3, QC2 is the charge accumulated by the input capacitor C2, QC4 is the charge accumulated by the feedback capacitor C4, VCMO is the output common-mode voltage of the operational amplifier, and Cp is the capacitance value of the input capacitor C1 and the input capacitor C2.

[0046] During the amplification phase of the programmable gain amplifier, reset switches S1, S2, S3, and S4 are disconnected, and the operational amplifier OP outputs differential amplified signals Vop and Von. Based on the law of charge conservation, the charge accumulated on the input capacitor C1 and the feedback capacitor C3, QXP, and the charge accumulated on the input capacitor C1 and the feedback capacitor C3, QXN, are respectively:

[0047] QXP=QC1+CQ3=(VXP-Vip)*Cp+(VXP-Von)*Cn

[0048] QXN=QC2+QC4=(VXN-Vin)*Cp+(VXN-Vop)*Cn

[0049] Wherein, VXP is the voltage at the non-inverting input terminal of the operational amplifier OP, VXN is the voltage at the inverting input terminal of the operational amplifier OP, and Cn is the capacitance value of the feedback capacitor C3 and the feedback capacitor C4.

[0050] Combining the above formulas, we can get:

[0051] 2(VCMO-VCM)*Cp=(VXP-Vip)*Cp+(VXP-Von)*Cn+(VXN-Vin)*Cp+(VXN-Vop)*Cn

[0052] 2(VCMO-VCM)*Cp=(VXP+VXN)*(Cp+Cn)-(Vip+Vin)*Cp-(Vop+Von)*Cn

[0053] According to the common-mode voltage calculation formula, VCMO = (Von + Vop) / 2, VCMI = (Vin + Vip) / 2, VCMO is the output common-mode voltage of the operational amplifier, and VCMI is the common-mode voltage of the differential input signals Vip and Vin. Therefore, the above formula can be converted to:

[0054] 2(VCMO-VCM)*Cp=(VXP+VXN)*(Cp+Cn)-2VCMI*Cp-2VCMO*Cn

[0055] (VXP+VXN)*(Cp+Cn)=2VCMO*(Cp+Cn)+2VCMI*Cp-2VCM*Cn

[0056] Due to the virtual short and virtual open characteristics of the operational amplifier OP, VXP = VXN, so the above formula can be converted to:

[0057] 2VXP*(Cp+Cn)=2VCMO*(Cp+Cn)+2VCMI*Cp-2VCM*Cn

[0058]

[0059] According to the above formula, if the common mode voltage VCM is equal to the common mode voltage VCMI of the differential input signal Vip and Vin, Item and The terms cancel each other out, so the voltages VXP and VXN at the non-inverting input and inverting input of the operational amplifier OP are equal to the output common-mode voltage VCMO of the operational amplifier.

[0060] However, since the voltages VXP and VXN at the operational amplifier OP's non-inverting and inverting inputs remain suspended for a long time during the amplification phase, if a capacitor-based programmable gain amplifier amplifies signals for a long time during the amplification phase, leakage and other factors may cause the voltages at the operational amplifier's non-inverting and inverting inputs to gradually change, ultimately causing the programmable gain amplifier to deviate from its normal operating state.

[0061] To this end, the present application provides a signal processing circuit and its control method, chip, and electronic device, which are described in detail below.

[0062] First, see Figure 2 , Figure 2 A schematic diagram of a signal processing circuit in an embodiment of the present application is shown, wherein the signal processing circuit includes an amplification module 10 , an analog-to-digital conversion module 20 and an amplification control module 30 .

[0063] Specifically, the amplifier module 10 has a reset phase and an amplification phase in each working cycle. The amplifier module 10 can be reset in the reset phase and output amplified signals Vop and Von according to the input signals Vip and Vin in the amplification phase. For example, taking the amplification factor of the amplifier module 10 as k, in the amplification phase of the amplifier module 10, the relationship between the input signals Vip and Vin and the amplified signals Vop and Von satisfies the relationship (Vip-Vin)*k=(Vop-Von), and the analog-to-digital conversion module 20 converts the differential voltage between the amplified signals Vop and Von into a digital signal Dout.

[0064] As an example, see Figure 3 , Figure 3Another schematic diagram of the signal processing circuit in an embodiment of the present application is shown, wherein the amplification module 10 includes an operational amplifier OP, input capacitors Ci1 and Ci2, feedback capacitors Cf1 and Cf2, first reset switches Si1 and Si2, and second reset switches Sf1 and Sf2. The first reset switch Si1 is connected to a preset common-mode voltage VCM and is used to control the reset of the input capacitor Ci1. The first reset switch Si2 is connected to a preset common-mode voltage VCM and is used to control the reset of the input capacitor Ci2. The second reset switch Sf1 is connected in parallel with the feedback capacitor Cf1 and is used to control the reset of the feedback capacitor Cf1. The second reset switch Sf2 is connected in parallel with the feedback capacitor Cf2 and is used to control the reset of the feedback capacitor Cf2.

[0065] Specifically, when the first reset switches Si1 and Si2 and the second reset switches Sf1 and Sf2 are closed, the amplifying module 10 is in the reset stage, the input capacitor Ci1 stops receiving the input signal Vip, the input capacitor Ci2 stops receiving the input signal Vin, the operational amplifier OP is connected in the form of unit gain negative feedback, and the voltages at the non-inverting input and the inverting input of the operational amplifier OP are reset to the output common-mode voltage of the operational amplifier OP. Therefore, after entering the reset stage, the amplifying module 10 can reset the voltages at the non-inverting input and the inverting input of the operational amplifier OP.

[0066] When the first reset switches Si1 and Si2 and the second reset switches Sf1 and Sf2 are disconnected, the amplifier module 10 is in the amplification stage. At this time, the operational amplifier OP, the input capacitors Ci1 and Ci2, and the feedback capacitors Cf1 and Cf2 form a capacitive differential amplifier circuit. According to the characteristics of the differential amplifier circuit, the input signals Vip and Vin and the amplified signals Vop and Von satisfy the following relationship:

[0067]

[0068] Wherein, CF is the capacitance value of feedback capacitors Cf1 and Cf2, and CI is the capacitance value of input capacitors Ci1 and Ci2.

[0069] It can be seen that the amplification factor of the amplifier module 10 is equal to the capacitance ratio of the input capacitor to the feedback capacitor. Therefore, the amplification factor of the amplifier module 10 can be changed by controlling the capacitance value of the input capacitor and / or the feedback capacitor.

[0070] The analog-to-digital conversion module 20 can output a digital signal Dout based on the amplified signals Vop and Von output by the amplification module 10 to implement a signal conversion process from the analog domain to the digital domain. For example, the analog-to-digital conversion module 20 can include, but is not limited to, a hybrid analog-to-digital converter consisting of one or more of a successive approximation ADC (SAR ADC), a Sigma-Delta ADC (SD ADC), a pipeline ADC, or a ramp-compare ADC.

[0071] The amplification control module 30 is used to control the amplification module 10 to enter the reset phase or the amplification phase in each working cycle, so that the amplification module 10 is reset in the reset phase and outputs the amplified signals Vop and Von in the amplification phase.

[0072] Generally, see Figure 3 The amplification control module 30 can output the clock signal CLK0, and the first reset switches Si1 and Si2, and the second reset switches Sf1 and Sf2 are controlled by the clock signal CLK0 output by the amplification control module 30. For example, taking the first reset switches Si1 and Si2, and the second reset switches Sf1 and Sf2 as NMOS transistors, when the clock signal CLK0 is at a high level, the first reset switches Si1 and Si2, and the second reset switches Sf1 and Sf2 are closed, and the amplification module 10 is in a reset stage; and when the clock signal CLK0 is at a low level, the first reset switches Si1 and Si2, and the second reset switches Sf1 and Sf2 are disconnected, and the amplification module 10 is in an amplification stage.

[0073] It can be seen that one cycle of the clock signal CLK0 can enable the amplifying module 10 to enter the reset stage and the amplifying stage in sequence. Therefore, it can be considered that one cycle of the clock signal CLK0 corresponds to one working cycle of the amplifying module 10 .

[0074] It should be noted that in the embodiment of the present application, the differential-mode voltage of the input signals Vip and Vin usually fluctuates within a certain range. Therefore, in the amplification stage of each working cycle, the differential-mode voltage of the amplified signals Vop and Von output by the amplification module 10 also fluctuates within a certain range, and the size of the digital signal Dout output by the analog-to-digital conversion module 20 also fluctuates within a certain range.

[0075] For example, assuming that the differential-mode voltage range of the input signals Vip and Vin is 0.8V to 1.2V and the amplification factor of the amplifier module 10 is 5, then the differential-mode voltage range of the amplified signals Vop and Von output by the amplifier module 10 is 4V to 6V. If the voltage corresponding to the digital signal Dout output by the analog-to-digital conversion module 20 is 8V, it means that the amplifier module 10 has deviated from the normal working state due to operating in the amplification stage for a long time and outputs the amplified signals Vop and Von with excessively high differential-mode voltages.

[0076] For another example, assuming that the differential-mode voltage range of the input signals Vip and Vin is less than 1.2V and the amplification factor of the amplifier module 10 is 5, then the differential-mode voltage of the amplified signals Vop and Von output by the amplifier module 10 should be less than 6V. If the voltage corresponding to the digital signal Dout output by the analog-to-digital conversion module 20 is 7V, it means that the amplifier module 10 has deviated from the normal working state due to operating in the amplification stage for a long time and outputs the amplified signals Vop and Von with excessively high differential-mode voltages.

[0077] For another example, assuming that the differential-mode voltage range of the input signals Vip and Vin is greater than 0.8V and the amplification factor of the amplifier module 10 is 5, then the differential-mode voltage of the amplified signals Vop and Von output by the amplifier module 10 should be greater than 4V. If the voltage corresponding to the digital signal Dout output by the analog-to-digital conversion module 20 is 2V, it means that the amplifier module 10 has deviated from the normal working state due to working in the amplification stage for a long time and outputs the amplified signals Vop and Von with too low differential-mode voltages.

[0078] In an embodiment of the present application, during the amplification phase of each working cycle, when the magnitude of the digital signal Dout satisfies a first preset condition, for example, the voltage magnitude corresponding to the digital signal Dout is less than 4V or greater than 6V, it indicates that the amplification module 10 deviates from the normal working state. At this time, the amplification control module 30 controls the amplification module 10 to enter the reset phase in advance, which can shorten the duration of the amplification module 10 operating in the amplification phase of the current working cycle, thereby avoiding the phenomenon that the amplification module 10 continues to deviate from the normal working state to amplify the signal.

[0079] For example, see Figure 4 , Figure 4FIG. 0 shows a schematic diagram of the operation of the amplification module 10 in an embodiment of the present application. When the amplification module 10 is operating normally, the duration of the reset phase of the amplification module 10 in each operating cycle is TR, and the duration of the amplification phase of the amplification module 10 in each operating cycle is TA. At time t0 in the amplification phase of the second operating cycle, the magnitude of the digital signal Dout output by the analog-to-digital conversion module 20 satisfies the first preset condition. Therefore, the amplification control module 30 changes the clock signal CLK0, thereby controlling the amplification module 10 to enter the reset phase in advance. At this time, the actual duration of the amplification phase of the amplification module 10 in the second operating cycle is TA', and TA' < TA. Therefore, the duration of the amplification phase of the amplification module 10 in the second operating cycle is shortened to avoid the phenomenon that the amplification module 10 continues to deviate from the normal operating state.

[0080] In some embodiments of the present application, the first preset condition includes that the magnitude of the digital signal Dout is less than the first threshold; or, the first preset condition includes that the magnitude of the digital signal Dout is greater than the second threshold. For example, the first threshold may correspond to a voltage of 4V, and the second threshold may correspond to a voltage of 6V. That is to say, when the magnitude of the digital signal Dout is greater than 6V or less than 4V, the amplification control module 30 controls the amplification module 10 to enter the reset phase in advance to shorten the duration of the amplification phase of the amplification module 10 in the current operating cycle.

[0081] It can be understood that the magnitudes of the first threshold and the second threshold in the above embodiments are only examples, and those skilled in the art can set them according to actual needs (such as the differential voltage range between the input signals Vip and Vin), and the present application does not make specific limitations.

[0082] In some embodiments of the present application, the amplification control module 30 may include a storage circuit (such as a register), a digital logic control circuit, and a clock signal generation circuit (such as a phase-locked loop circuit, a frequency multiplication circuit, a frequency division circuit, an RC oscillator, etc.). The storage circuit can store the first preset condition (such as the first threshold and the second threshold). The digital logic control circuit can determine whether the magnitude of the digital signal Dout satisfies the first preset condition, thereby changing the clock signal (such as the clock signal CLK0) output by the clock signal generation circuit, and finally controlling the amplification module 10 to enter the reset phase in advance.

[0083] In an embodiment of the present application, the present application controls the amplification module 10 to enter a reset phase or an amplification phase during each operating cycle through the amplification control module 30. During the amplification phase of the amplification module 10, the analog-to-digital conversion module 20 can output a digital signal Dout based on the amplified signal output by the amplification module 10, thereby realizing the conversion process of the analog signal to the digital signal. At the same time, during the amplification phase of each operating cycle, when the magnitude of the digital signal Dout meets a first preset condition, the amplification control module 30 can control the amplification module 10 to enter the reset phase in advance, thereby shortening the duration of the amplification phase of the current operating cycle of the amplification module 10, and avoiding the phenomenon that the input node of the operational amplifier OP of the amplification module 10 gradually changes due to the amplification module 10 operating in the amplification phase for a long time, thereby causing the amplification module 10 to deviate from the normal operating state.

[0084] In some embodiments of the present application, when the magnitude of the digital signal Dout satisfies a first preset condition, the amplification control module 30 further records the actual duration of the amplification module 10 operating in the amplification stage in the current working cycle; wherein, in N working cycles after the current working cycle, the amplification control module 30 controls the duration of the amplification module 10 operating in the amplification stage to be shortened from the preset duration to the actual duration; in the N+1th working cycle after the current working cycle, the amplification control module 30 controls the duration of the amplification module 10 operating in the amplification stage to be restored to the preset duration, where N is an integer greater than or equal to 1.

[0085] For example, taking N equal to 1, see Figure 5 , Figure 5 Another working schematic diagram of the amplification module 10 in an embodiment of the present application is shown. At time t0 in the amplification stage of the second working cycle, the magnitude of the digital signal Dout output by the analog-to-digital conversion module 20 meets the first preset condition. The amplification module 10 deviates from the normal working state at this time. The amplification control module 30 controls the amplification module 10 to enter the reset stage in advance, and the amplification control module 30 records the actual duration of the amplification module 10 working in the amplification stage in the second working cycle as TA'; in the third working cycle (i.e., one working cycle after the second working cycle), the amplification control module 30 controls the duration of the amplification module 10 working in the amplification stage to be shortened from the preset duration TA to the actual duration TA'; and in the fourth working cycle (i.e., the second working cycle after the second working cycle), the amplification control module 30 controls the duration of the amplification module 10 working in the amplification stage to be restored to the preset duration TA.

[0086] It can be seen that the amplification control module 30 of the present application can also record the duration of the amplification module 10 working in the amplification stage when it deviates from the normal working state, thereby changing the duration of the amplification module 10 working in the amplification stage in the subsequent N working cycles, so as to avoid the phenomenon that the amplification module 10 continues to deviate from the normal working state in the next N working cycles; at the same time, in the subsequent N+1th working cycle, the amplification control module 30 can also restore the duration of the amplification module 10 working in the amplification stage, so as to avoid the phenomenon that the amplification module 10 working in the amplification stage is too short and is frequently reset, thereby causing the conversion rate of the signal processing circuit to decrease.

[0087] In some embodiments of the present application, the amplification control module 30 has a measurement control mode and a prediction control mode; when the amplification control module 30 is in the measurement control mode, the amplification control module 30 controls the amplification module 10 to enter the reset phase or the amplification phase in each working cycle; when the amplification control module 30 is in the prediction control mode, the amplification control module 30 controls the amplification module 10 to output a pre-amplification signal Vpn of unchanged size, and records the digital signal Dout corresponding to the pre-amplification signal output by the analog-to-digital conversion module 20 as a prediction value; wherein the first threshold value and the second threshold value are determined based on the prediction value.

[0088] For example, see Figure 6 , Figure 6 A working schematic diagram of the amplification control module 30 in an embodiment of the present application is shown. After the signal processing circuit starts working, the amplification control module 30 first enters the predicted quantity control mode. The amplification control module 30 controls the amplification module 10 to output a pre-amplification signal Vpn with a constant size. The analog-to-digital conversion module 20 performs analog-to-digital conversion on the pre-amplification signal to obtain a predicted quantity value. Therefore, the amplification control module 30 can determine the first threshold and the second threshold according to the predicted quantity value.

[0089] For example, in the predicted quantity control mode, the differential mode voltage of the input signals Vip and Vin is 1V. Assuming that the amplification factor of the amplifier module 10 is 5, the pre-amplified signal Vpn output by the amplifier module 10 is 5V, and the predicted quantity value corresponding to the digital signal Dout output by the analog-to-digital conversion module 20 is 5V. When the input signals Vip and Vin are DC signals or low-frequency signals, if it is assumed that the fluctuation range of the differential mode voltage of the input signals Vip and Vin is 1±0.2V, then the fluctuation range of the differential mode voltage of the amplified signals Vop and Von output by the amplifier module 10 is 5±1V, so it can be determined that the first threshold is 4V and the second threshold is 6V.

[0090] It can be seen that the present application can first determine the first threshold and the second threshold when the amplification control module 30 is in the predictive control mode, and then make the amplification control module 30 enter the measurement control mode, so as to judge whether the amplification module 10 deviates from the normal working state according to the first threshold and the second threshold during the amplification stage of the amplification module 10.

[0091] It can be understood that the above embodiment is illustrative based on the example of pre-measuring the first threshold and the second threshold. In some possible embodiments, the first threshold and the second threshold can also be determined according to the circuit design requirements. For example, assuming that the differential mode voltage of the input signal Vip and Vin is 0.6V~0.8V according to the design requirements, and the amplification factor of the amplification module 10 is 5, the first threshold can be determined to be 3V and the second threshold can be determined to be 4V.

[0092] In some embodiments of the present application, for example, for an embodiment in which the amplification control module 30 also records the actual duration of the amplification module 10 working in the amplification stage in the current working cycle, if the actual duration is less than the first preset duration, the amplification control module 30 changes from the measurement control mode to the prediction control mode to update the first threshold and the second threshold; if the actual duration is greater than or equal to the first preset duration, the amplification control module 30 remains in the measurement control mode to continue to control the amplification module 10 to enter the reset stage or the amplification stage in each working cycle.

[0093] It should be noted that when the actual duration is less than the first preset duration, it means that the actual duration of the amplification module 10 working in the amplification stage in the current working cycle is extremely short. This situation is not caused by the amplification module 10 deviating from the normal working state, but is caused by the change in the range of the differential mode voltage of the input signals Vip and Vin.

[0094] For example, assuming that the differential-mode voltage range of the input signals Vip and Vin is 0.8V to 1.2V, the amplification factor of the amplifier module 10 is 5, the amplifier control module 30 determines the first threshold value to be 4V and the second threshold value to be 6V in the predictive control mode, and the differential-mode voltage range of the input signals Vip and Vin is changed to 1.2V to 1.6V in a certain working cycle, then the differential-mode voltage range of the amplified signals Vop and Von output by the amplifier module 10 is changed to 6V to 8V. Since the differential-mode voltage of the amplified signals Vop and Von output by the amplifier module 10 is always greater than the second threshold value, after the amplifier module 10 enters the amplification stage in this working cycle, the amplifier control module 30 will control the amplifier module 10 to enter the reset stage in a very short time, so that the actual duration of the amplifier module 10 working in the amplification stage of this working cycle is extremely short.

[0095] In the above embodiment, if the actual duration is less than the first preset duration, the amplification control module 30 will change from the measurement control mode to the prediction control mode, so that the amplification control module 30 can also update the first threshold and the second threshold to avoid the above phenomenon. Figure 7 , Figure 7 Another working schematic diagram of the amplification control module 30 in an embodiment of the present application is shown. After the signal processing circuit starts working, the amplification control module 30 first enters the prediction control mode to determine the first threshold and the second threshold, and then the amplification control module 30 enters the measurement control mode, so that the amplification module 10 enters the reset stage and the amplification stage in turn in each working cycle, and the amplification control module 30 determines whether the amplification module 10 deviates from the normal working state during the amplification stage based on the previously determined first threshold and the second threshold.

[0096] Among them, at time t1 of the amplification stage of the second working cycle, the size of the digital signal Dout output by the analog-to-digital conversion module 20 meets the first preset condition, the amplification control module 30 controls the amplification module 10 to enter the reset stage in advance, and the amplification control module 30 records the actual duration of the amplification module 10 working in the amplification stage in the second working cycle as TA'. Since TA' is less than the first preset duration T0, it means that the actual duration of the amplification module 10 working in the amplification stage in the second working cycle is extremely short. Therefore, the amplification control module 30 will immediately change from the measurement control mode to the prediction control mode, so that the amplification control module 30 re-updates the first threshold and the second threshold.

[0097] It can be seen that the amplification control module 30 of the present application can also determine whether to change back to the predicted quantity control mode based on the actual duration after the differential mode voltage range of the input signals Vip and Vin changes, thereby updating the first threshold and the second threshold for judging whether the amplification module 10 deviates from the normal working state, so as to avoid the phenomenon that the amplification module 10 has an extremely short working time in the amplification stage due to changes in the input signal.

[0098] In some embodiments of the present application, the amplification module 10 has a sampling phase and a holding phase when the amplification control module 30 is in the predictive quantity control mode; Figure 3In the sampling phase of the amplifying module 10, the first reset switches Si1 and Si2 are closed, and the second reset switches Sf1 and Sf2 are disconnected. At this time, the input capacitor Ci1 is connected to the input signal Vip, and the input capacitor Ci2 is connected to the input signal Vin; in the holding phase of the amplifying module 10, the first reset switches Si1 and Si2 are disconnected, and the second reset switches Sf1 and Sf2 are closed. At this time, the input capacitor Ci1 stops connecting to the input signal Vip, and the input capacitor Ci2 stops connecting to the input signal Vin; in the reset phase of the amplifying module 10, the first reset switches Si1 and Si2 and the second reset switches Sf1 and Sf2 are closed. At this time, the input capacitor Ci1 stops connecting to the input signal Vip, and the input capacitor Ci2 stops connecting to the input signal Vin; in the amplifying phase of the measurement control mode, the first reset switches Si1 and Si2 and the second reset switches Sf1 and Sf2 are disconnected. At this time, the input capacitor Ci1 is connected to the input signal Vip, and the input capacitor Ci2 is connected to the input signal Vin.

[0099] It should be noted that, in the sampling phase of the amplifier module 10, the first reset switches Si1 and Si2 are disconnected and the second reset switches Sf1 and Sf2 are closed. At this time, the input capacitor Ci1 is connected to the input signal Vip, the input capacitor Ci2 stops being connected to the input signal Vin, and the amount of charge accumulated in the feedback capacitors Cf1 and Cf2 is 0. Then, in the sampling phase of the amplifier module 10, the amount of charge Qsp accumulated in the input capacitor Ci1 and the feedback capacitor Cf1, and the amount of charge Qsn accumulated in the input capacitor Ci2 and the feedback capacitor Cf1 are respectively:

[0100] Qsp=(Vip-VCMO)*CI+0

[0101] Qnp=(Vin-VCMO)*CI+0

[0102] Wherein, VCMO is the output common-mode voltage of the operational amplifier OP.

[0103] During the hold phase of the amplifier module 10, the first reset switches Si1 and Si2 are closed and the second reset switches Sf1 and Sf2 are opened. At this time, the input capacitor Ci1 stops receiving the input signal Vip, and the input capacitor Ci2 stops receiving the input signal Vin. Therefore, during the hold phase of the amplifier module 10, the charge Qsp' accumulated by the input capacitor Ci1 and the feedback capacitor Cf1, and the charge Qsn' accumulated by the input capacitor Ci2 and the feedback capacitor Cf1 are respectively:

[0104] Qsp'=(VXP-VCM)*CI+(VXP-Von)*CF

[0105] Qsn'=(VXN-VCM)*CI+(VXN-Vop)*CF

[0106] Wherein, VCM is the common mode voltage of the input signal Vip and the input signal Vin, VXP is the voltage at the non-inverting input terminal of the operational amplifier OP, and VXN is the voltage at the inverting input terminal of the operational amplifier OP.

[0107] Since the operational amplifier OP is virtually shorted during the hold phase of the amplification module 10 , VXP′=VXN′. Furthermore, due to the law of charge conservation, Qsp=Qsp′ and Qsn=Qsn′. Therefore, we can know that:

[0108] Qsp-Qsn=Qsp'-Qsn'

[0109] (Vip-Vin)*CI=(VXP-VCM)*CI+(VXP-Von)*CF-(VXN-VCM)*CI-(VXN-Vop)*CF

[0110] (Vip-Vin)*CI=-(Vop-Von)*CF

[0111] Therefore, the differential mode voltage of the pre-amplified signals Vop and Von is:

[0112] Vop-Von=(Vip-Vin)*CI / CF

[0113] In the above formula, CI / CF is the amplification coefficient of the amplification module 10. It can be seen that when the amplification control module 30 is in the predicted quantity control mode, the amplification module 10 also outputs the pre-amplified signal according to the amplification coefficient. However, since the charges of the input capacitors Ci1 and Ci2 and the feedback capacitors Cf1 and Cf2 remain unchanged during the holding stage, the voltage of the pre-amplified signal will not change with the voltage of the input signal, and the analog-to-digital conversion module 20 can output the predicted quantity value based on the pre-amplified signal with unchanged voltage, and finally the amplification control module 30 determines the first threshold and the second threshold according to the predicted quantity value.

[0114] It can be understood that in some possible embodiments, the analog-to-digital conversion module 20 can also use the digital signal Dout converted from the amplified signal output by the amplification module 10 in the amplification stage as the predicted value. That is, the amplification control module 30 can also use the digital signal Dout output by the analog-to-digital conversion module 20 as the predicted value in the measurement control mode and calculate the first threshold and the second threshold.

[0115] In some embodiments of the present application, see Figure 8 , Figure 8Another schematic diagram of the signal processing circuit in an embodiment of the present application is shown, wherein the signal processing circuit further includes a first chopping switch module 40 and a second chopping switch module 50. The first chopping switch module 40 can modulate the input signal to a high frequency and input it into the amplification module 10. The second chopping switch module 50 can modulate the amplified signal output by the amplification module 10 to a low frequency and input it into the analog-to-digital conversion module 20. Then, for the offset voltage and flicker noise of the operational amplifier OP, the offset voltage and flicker noise of the operational amplifier OP will be modulated to a high frequency by the second chopping switch module 50. Therefore, the offset voltage and flicker noise of the operational amplifier OP can be eliminated by the subsequent filtering circuit, thereby improving the measurement accuracy of the signal processing circuit.

[0116] As an example, see Figure 9 , Figure 9 Another schematic diagram of the signal processing circuit in an embodiment of the present application is shown. The first chopping switch module 40 includes a first switch S01, a second switch S02, a third switch S03, and a fourth switch S04. The second chopping switch module 50 includes a fifth switch S05, a sixth switch S06, a seventh switch S07, and an eighth switch S08. The first switch S01, the fourth switch S04, the fifth switch S05, and the eighth switch S08 are controlled by the first clock signal CLK1 output by the amplification control module 30, and the second switch S02, the third switch S03, the sixth switch S06, and the seventh switch S07 are controlled by the second clock signal CLK1A output by the amplification control module 30. During the control process of the first clock signal CLK1 and the second clock signal CLK1A, the first switch S01, the second switch S02, the third switch S03, and the fourth switch S04 modulate the input signals Vip and Vin to a high frequency and input them to the amplifier module 10. The fifth switch S05, the sixth switch S06, the seventh switch S07, and the eighth switch S08 modulate the amplified signals Vop and Von to a low frequency and input them to the analog-to-digital conversion module 20, thereby achieving input chopping regulation and output chopping modulation of the amplifier module 10.

[0117] It is understandable that in some embodiments, the first switch S01, the second switch S02, the third switch S03, and the fourth switch S04 can also serve as input switches to control whether the input capacitors Ci1 and Ci2 are connected to the input signals Vip and Vin. For example, during the hold phase of the amplification module 10, the first switch S01, the second switch S02, the third switch S03, and the fourth switch S04 are all disconnected, the input capacitor Ci1 stops connecting to the input signal Vip, and the input capacitor Ci2 stops connecting to the input signal Vin, so that the input capacitors Ci1 and Ci2 stop connecting to the input signals Vip and Vin. During the sampling phase of the amplification module 10, the first switch S01 and the fourth switch S04 are closed (or the second switch S02 and the third switch S03 are closed), so that the input capacitors Ci1 and Ci2 can connect to the input signals Vip and Vin.

[0118] Furthermore, in order to better implement the signal processing circuit in the embodiment of the present application, based on the signal processing circuit, the present application also provides a signal processing circuit control method, which is applied to the signal processing circuit described in any of the above embodiments, see Figure 10 , Figure 10 A flow chart of a signal processing circuit control method in an embodiment of the present application is shown, wherein the signal processing circuit control method includes:

[0119] Step S1001, controlling the amplifying module 10 to enter a reset phase or an amplifying phase in each working cycle, so that the amplifying module 10 is reset in the reset phase and outputs an amplified signal according to the input signal in the amplifying phase;

[0120] Step S1002 , in the amplification phase of each working cycle, controlling the analog-to-digital conversion module 20 to output a digital signal Dout according to the amplified signal output by the amplification module 10 ;

[0121] In step S1003 , in the amplification phase of each working cycle, when the magnitude of the digital signal Dout satisfies a first preset condition, the amplification module 10 is controlled to enter the reset phase in advance to shorten the duration of the amplification phase of the current working cycle.

[0122] The present application controls the amplification module 10 to enter the reset phase or the amplification phase during each operating cycle. During the amplification phase of the amplification module 10, the analog-to-digital conversion module 20 can output a digital signal Dout based on the amplified signal output by the amplification module 10, thereby achieving the conversion process from the analog signal to the digital signal Dout. Furthermore, during the amplification phase of each operating cycle, when the magnitude of the digital signal Dout satisfies a first preset condition, the amplification module 10 can be controlled to enter the reset phase in advance. This can shorten the duration of the amplification phase of the amplification module 10 during the current operating cycle, thereby preventing the amplification module 10 from operating in the amplification phase for a long time, which may cause the input node of the operational amplifier OP of the amplification module 10 to gradually change, thereby causing the amplification module 10 to deviate from its normal operating state.

[0123] In some embodiments of the present application, see Figure 11 , Figure 11 Another flow chart of the signal processing circuit control method in an embodiment of the present application is shown. The signal processing circuit control method further includes:

[0124] Step S1101: When the magnitude of the digital signal Dout satisfies a first preset condition, the actual duration of the amplification module 10 operating in the amplification phase in the current working cycle is recorded;

[0125] Step S1102: in N working cycles after the current working cycle, controlling the duration of the amplification module 10 operating in the amplification phase to be shortened from the preset duration to the actual duration;

[0126] Step S1103 : In the N+1th working cycle after the current working cycle, the duration of the amplification module 10 operating in the amplification phase is controlled to be restored to a preset duration, where N is an integer greater than or equal to 1.

[0127] In the above embodiment, since the duration of the amplifying module 10 working in the amplifying stage when it deviates from the normal working state is recorded, the duration of the amplifying module 10 working in the amplifying stage in the subsequent N working cycles can be changed, thereby avoiding the phenomenon that the amplifying module 10 continues to deviate from the normal working state for N consecutive working cycles; at the same time, in the subsequent N+1th working cycle, the present application can also restore the duration of the amplifying module 10 working in the amplifying stage, thereby avoiding the phenomenon that the amplifying module 10 working in the amplifying stage is too short and is frequently reset, thereby causing the conversion rate of the signal processing circuit to decrease.

[0128] The present application also provides a chip including the aforementioned signal processing circuit. An integrated circuit (IC) is also referred to as a chip, and the chip may be, but is not limited to, a SOC (System on Chip) chip or a SIP (System in Package) chip. Because the chip of the present application includes the signal processing circuit described in the aforementioned embodiment, it possesses all the beneficial effects of the signal processing circuit in the aforementioned embodiment, and will not be further elaborated here.

[0129] The embodiment of the present application also provides an electronic device, which includes a device body and a chip as described above provided in the device body. The electronic device can be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control panel, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablet computers, and POS (point of sales terminals). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0130] The above is only a preferred embodiment of the present application and does not constitute any form of limitation to the present application. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A signal processing circuit, characterized in that: include: an amplifying module, wherein the amplifying module has a reset phase and an amplifying phase in each working cycle, the amplifying module is configured to reset in the reset phase and output an amplified signal according to the input signal in the amplifying phase; an analog-to-digital conversion module, configured to output a digital signal according to the amplified signal output by the amplification module; an amplification control module, configured to control the amplification module to enter the reset phase or the amplification phase in each working cycle; In the amplification phase of each working cycle, when the magnitude of the digital signal meets a first preset condition, the amplification control module controls the amplification module to enter the reset phase in advance, so as to shorten the duration of the amplification module working in the amplification phase in the current working cycle.

2. The signal processing circuit according to claim 1, wherein When the magnitude of the digital signal satisfies the first preset condition, the amplification control module further records the actual duration of the amplification module operating in the amplification phase in the current working cycle; Wherein, in N working cycles after the current working cycle, the amplification control module controls the amplification module to work in the amplification phase for a duration shortened from the preset duration to the actual duration; In the N+1th working cycle after the current working cycle, the amplification control module controls the amplification module to work in the amplification stage for a duration restored to the preset duration, where N is an integer greater than or equal to 1.

3. The signal processing circuit according to claim 1, wherein: The first preset condition includes that the magnitude of the digital signal is less than a first threshold; or The first preset condition includes that the magnitude of the digital signal is greater than a second threshold.

4. The signal processing circuit according to claim 3, wherein: The amplification control module has a measurement control mode and a prediction control mode; When the amplification control module is in the measurement control mode, the amplification control module controls the amplification module to enter the reset phase or the amplification phase in each working cycle; When the amplification control module is in the predicted quantity control mode, the amplification control module controls the amplification module to output a pre-amplified signal with a constant magnitude, and records the digital signal output by the analog-to-digital conversion module corresponding to the pre-amplified signal as a predicted quantity value; The first threshold and the second threshold are determined based on the predicted value.

5. The signal processing circuit according to claim 4, wherein: When the magnitude of the digital signal satisfies the first preset condition, the amplification control module further records the actual duration of the amplification module operating in the amplification phase in the current working cycle; If the actual duration is less than the first preset duration, the amplification control module changes from the measurement control mode to the prediction control mode to update the first threshold and the second threshold; If the actual duration is greater than or equal to the first preset duration, the amplification control module maintains the measurement control mode to continue controlling the amplification module to enter the reset phase or the amplification phase in each working cycle.

6. The signal processing circuit according to claim 4, wherein: The amplification module includes an operational amplifier, an input capacitor, a feedback capacitor, a first reset switch and a second reset switch; The first reset switch is used to control the reset of the input capacitor, and the second reset switch is used to control the reset of the feedback capacitor; Wherein, the amplification module has a sampling phase and a holding phase when the amplification control module is in the predictive quantity control mode; During the sampling phase of the amplifying module, the first reset switch is opened and the second reset switch is closed; during the holding phase of the amplifying module, the first reset switch is closed and the second reset switch is opened; In the reset phase of the amplification module, the first reset switch and the second reset switch are closed; in the amplification phase of the measurement control mode, the first reset switch and the second reset switch are opened.

7. The signal processing circuit according to claim 1, wherein: The signal processing circuit further includes a first chopping switch module and a second chopping switch module; The first chopping switch module is used to modulate the input signal to a high frequency and input it into the amplifying module, and the second chopping switch module is used to modulate the amplified signal output by the amplifying module to a low frequency and input it into the analog-to-digital conversion module.

8. A signal processing circuit control method, characterized in that: The signal processing circuit includes an amplification module and an analog-to-digital conversion module, and the method includes: Controlling the amplifying module to enter the reset phase or the amplifying phase in each working cycle, so that the amplifying module is reset in the reset phase and outputs an amplified signal according to the input signal in the amplifying phase; During the amplification phase of each working cycle, controlling the analog-to-digital conversion module to output a digital signal according to the amplified signal output by the amplification module; In the amplification phase of each working cycle, when the magnitude of the digital signal meets a first preset condition, the amplification module is controlled to enter the reset phase in advance to shorten the duration of the amplification module working in the amplification phase in the current working cycle.

9. The signal processing circuit control method according to claim 8, wherein: The method further comprises: When the magnitude of the digital signal satisfies the first preset condition, recording the actual duration of the amplification module operating in the amplification phase in the current working cycle; In N working cycles after the current working cycle, controlling the duration of the amplification module operating in the amplification phase to be shortened from the preset duration to the actual duration; In the N+1th working cycle after the current working cycle, the duration of the amplification module operating in the amplification phase is controlled to be restored to the preset duration, where N is an integer greater than or equal to 1.

10. A chip, characterized in that: The signal processing circuit comprises the signal processing circuit according to any one of claims 1 to 7.

11. An electronic device, characterized in that: The device comprises a device body and the chip according to claim 10 arranged in the device body.

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