A data processing method, apparatus and system

Abstract

The embodiment of the application discloses a data processing method, which can be applied to a concatenated FEC scheme in a 1.6T high-speed transmission scene. The scheme comprises the following steps: performing p:q symbol demultiplexing and alignment identification locking on p pieces of first data streams coded by Reed-Solomon (RS), to obtain a four-symbol boundary, wherein p is an integer greater than or equal to 1, q is an integer, and q = 2 * p or q = 4 * p; and performing data processing including inner code encoding and modulation on the p pieces of first data streams according to the obtained four-symbol boundary, to obtain p pieces of modulated data streams. The scheme provides a four-symbol boundary before inner code encoding, which helps to improve the error correction performance of the concatenated FEC scheme.

Description

[0001] This application is a divisional application. The original application has the application number 202410658291.7 and the original application date is May 24, 2024. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a data processing method, apparatus and system. Background Technology

[0003] Driven by technologies such as 5G, cloud computing, big data, and artificial intelligence, high-speed optical transmission networks are developing towards high capacity, packetization, and intelligence. Optical communication systems utilize the amplitude, phase, polarization, or frequency of light waves to carry information. Forward error correction (FEC) coding is used to correct transmission errors, allowing the receiver to recover the original data sent by the transmitter from the received data. A cascaded FEC transmission scheme is proposed, where the transmitting device and the transmitting processing module are connected via a connection unit interface. The transmitting device performs a first FEC encoding on the data to be transmitted and sends the first FEC-encoded data to the transmitting processing module. The transmitting processing module then performs a second FEC encoding on the first FEC-encoded data, modulates the bit sequence resulting from the second FEC encoding to generate a corresponding modulation symbol sequence, and finally generates an optical signal based on the modulation symbol sequence, which is transmitted to the receiver via optical fiber. The first FEC encoding is also called external code encoding, and the second FEC encoding is also called internal code encoding. The modulation mapping is also called symbol mapping.

[0004] Typically, the transmitting processing module performs interleaving before the second FEC encoding to shuffle the data order, thereby enhancing the error correction performance of the cascaded FEC scheme. For the data received by the transmitting processing module after the first FEC encoding, it needs to obtain the symbol boundaries of the first FEC encoding in the received data. Using the obtained symbol boundaries, the interleaving can be processed at the granularity of multiple first FEC encoded symbols, thus enabling the cascaded FEC scheme to have better error correction performance.

[0005] In existing technical solutions, for 1.6TBASE-R inner code encoding (Inner FEC) and its client sublayer being a 1.6TBASE-R 8:8 Physical Media Attachment (PMA) layer based on symbol-multiplexing (SM), the PMA layer (also known as 1.6TBASE-R 8:8SM-PMA) does not provide symbol boundaries. The lack of symbol boundaries in the PMA layer affects the error correction performance of the overall cascaded FEC scheme and is a problem that urgently needs to be solved. Summary of the Invention

[0006] This application provides a data processing method, apparatus, and system that enables the outer code symbol boundary to be obtained before the inner code is encoded, thereby achieving better cascaded FEC error correction performance and being applicable to a wide range of transmission scenarios.

[0007] In a first aspect, embodiments of this application provide a data processing method, comprising: performing p:q symbol demultiplexing and alignment identifier locking on p first data streams encoded by Reed-Solomon RS to obtain four symbol boundaries, wherein p is an integer greater than or equal to 1, q is an integer, and q = 2 × p or q = 4 × p; and performing data processing including internal code encoding and modulation on the p first data streams according to the obtained four symbol boundaries to obtain p modulated data streams.

[0008] Secondly, embodiments of this application provide a data processing method, comprising: performing p:q symbol demultiplexing and alignment identifier locking on p first data streams encoded by Reed-Solomon RS to obtain four symbol boundaries and q second data streams, wherein p is an integer greater than or equal to 1, q is an integer, and q = 2 × p or q = 4 × p; performing q:p symbol multiplexing on the q second data streams to obtain p third data streams; and performing data processing including internal code encoding and modulation on the p third data streams according to the obtained four symbol boundaries to obtain p modulated data streams.

[0009] In the above embodiments of this application, before performing internal code encoding, a four-symbol boundary is obtained, and the four-symbol boundary is used to ensure that the information bits in the internal code encoding contain an integer number of RS symbols, so that the cascaded FEC scheme has good error correction performance and can be applied to a variety of transmission scenarios.

[0010] In conjunction with the above aspects, in a first possible implementation of the above aspects, the step of performing p:q symbol demultiplexing and alignment identifier locking on the p first data streams encoded by Reed-Solomon RS specifically includes: performing p:q symbol demultiplexing on the p first data streams encoded by Reed-Solomon RS to obtain q second data streams; and performing alignment identifier locking on the q second data streams respectively to obtain four-symbol boundaries.

[0011] In conjunction with the above aspects and possible implementations thereof, in the second possible implementation of the above aspects, q = 2 × p, and the p:q symbol demultiplexing includes p 1:2 symbol demultiplexings, wherein each of the p 1:2 symbol demultiplexings corresponds one-to-one with a p first data stream; or, q = 4 × p, and the p:q symbol demultiplexing includes p 1:4 symbol demultiplexings, wherein each of the p 1:4 symbol demultiplexings corresponds one-to-one with a p first data stream. This embodiment provides two specific implementation methods for demultiplexing, which are simple to implement.

[0012] In conjunction with the second possible implementation of the above aspects, in the third possible implementation of the above aspects, the 1:2 symbol demultiplexing adopts a round-robin method of distributing 40 bits each time to demultiplex the corresponding first data stream to obtain 2 second data streams; or, the 1:4 symbol demultiplexing adopts a round-robin method of distributing 40 bits each time to demultiplex the corresponding first data stream to obtain 4 second data streams. It should be understood that using a 40-bit round-robin method can match the four-symbol boundaries, which is used to perform alignment identifier locking on each second data stream, thereby obtaining the four-symbol boundaries of the corresponding first data stream.

[0013] In conjunction with the above aspects and possible implementations thereof, in the fourth possible implementation of the above aspects, the four symbol boundaries are p, each corresponding to one of the p first data streams.

[0014] In conjunction with the fourth possible implementation of the above aspects, in the fifth possible implementation of the above aspects, all second data streams obtained in either the 1:2 symbol demultiplexing or the 1:4 symbol demultiplexing are aligned with the identifier lock, and the boundary of the distributed 40 bits is a four-symbol boundary.

[0015] In conjunction with the fourth possible implementation of the above aspects, in the sixth possible implementation of the above aspects, q = 2 × p. Within the threshold time interval, if at least one of the two second data streams fails to achieve alignment identifier locking, the boundary of the 40 bits distributed in the 1:2 symbol demultiplexing is shifted, and 1:2 symbol demultiplexing is performed again to obtain two second data streams again. Alignment identifier locking is then applied to each of the two newly obtained second data streams to obtain a four-symbol boundary. This embodiment provides a complete process for obtaining a four-symbol boundary; only when all second data streams achieve alignment identifier locking can the correct four-symbol boundary be obtained.

[0016] In conjunction with the fourth possible implementation of the above aspects, in the seventh possible implementation of the above aspects, q = 4 × p. Within the threshold time interval, if at least one of the four second data streams fails to achieve alignment identifier locking, the boundary of the 40 bits distributed in the 1:4 symbol demultiplexing is shifted, and 1:4 symbol demultiplexing is performed again to obtain four second data streams again. Alignment identifier locking is then performed on each of the four newly obtained second data streams to obtain one four-symbol boundary. This embodiment provides another complete process for obtaining four-symbol boundaries; only when all second data streams achieve alignment identifier locking can the correct four-symbol boundary be obtained.

[0017] In conjunction with the sixth or seventh possible implementation of the above aspects, in the eighth possible implementation of the above aspects, the granularity of shifting the boundary of the distributed 40 bits is 1 bit; or, the granularity of shifting the boundary of the distributed 40 bits is 40×m+1 bits, where m is an integer greater than 0. This application provides various shift granularities that can match the specific hardware implementation's processing bit width, resulting in relatively simple implementation and low complexity.

[0018] In conjunction with the above aspects and possible implementations thereof, in the ninth possible implementation of the above aspects, p = 8, q = 16; or p = 4, q = 16.

[0019] In conjunction with the above aspects and possible implementations thereof, in the tenth possible implementation of the above aspects, the codeword length of the internal code is 128 bits, wherein the information bits are 120 bits and the parity bits are 8 bits; or, the codeword length of the internal code is 126 bits, wherein the information bits are 110 bits and the parity bits are 16 bits.

[0020] In conjunction with the foregoing aspects and possible implementations thereof, in the eleventh possible implementation of the foregoing aspects, the codeword length of the RS is 544 symbols, wherein the information length is 514 symbols, and each symbol contains 10 bits. The four symbols comprise 40 bits.

[0021] In conjunction with the eleventh possible implementation of the above aspects, in the twelfth possible implementation of the above aspects, each of the first data streams is further subjected to convolutional interleaving before being encoded by the internal code. The convolutional interleaving includes delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line includes a different number of storage units, and the delay line with the smallest number of storage units includes 0 storage units. The difference in the number of storage units between any two adjacent delay lines is Q, and each storage unit is used to store 40 bits, where Q is an integer greater than or equal to 1.

[0022] In conjunction with the twelfth possible implementation of the above aspects, in the thirteenth possible implementation of the above aspects, each delay line inputs 40 bits at a time and outputs 40 bits at a time, and the continuous r×40 bits in the output data stream after convolution and interleaving include the 40 bits output by each delay line.

[0023] In conjunction with the eleventh possible implementation of the above aspects, in the fourteenth possible implementation of the above aspects, the 40 bits stored in each storage unit in the convolutional interleaving are 4 RS symbols. In this case, it can be guaranteed that the 12 consecutive RS symbols output by the convolutional interleaving unit come from 12 different RS codewords, thus enabling the cascaded FEC to have better decoding performance.

[0024] In conjunction with the foregoing aspects and possible implementations thereof, in the fifteenth possible implementation of the foregoing aspects, the modulation employs four-level pulse amplitude PAM4 modulation.

[0025] Thirdly, embodiments of this application provide a data processing apparatus, including: a first processing unit and a second processing unit; the first processing unit is configured to perform p:q symbol demultiplexing and alignment identifier locking on p first data streams encoded by Reed-Solomon RS to obtain four symbol boundaries, wherein p is an integer greater than or equal to 1, q is an integer, and q = 2 × p or q = 4 × p; the second processing unit is configured to perform data processing including internal code encoding and modulation on the p first data streams according to the obtained four symbol boundaries to obtain p modulated data streams.

[0026] Fourthly, embodiments of this application provide a data processing apparatus, including: a first processing unit and a second processing unit; the first processing unit is configured to perform p:q symbol demultiplexing and alignment identifier locking on p first data streams encoded by Reed-Solomon RS to obtain four symbol boundaries and q second data streams, wherein p is an integer greater than or equal to 1, q is an integer, and q = 2 × p or q = 4 × p; the second processing unit is configured to perform q:p symbol multiplexing on the q second data streams to obtain p third data streams; and is further configured to perform data processing including internal code encoding and modulation on the p third data streams according to the obtained four symbol boundaries to obtain p modulated data streams.

[0027] In the above embodiments of this application, the data processing device obtains the four-symbol boundary before performing internal code encoding, and uses the four-symbol boundary to ensure that the information bits in the internal code encoding contain an integer number of RS symbols, so that the cascaded FEC scheme has good error correction performance and can be applied to a variety of transmission scenarios.

[0028] In conjunction with the above aspects, in a first possible implementation of the above aspects, the first processing unit is specifically used to: perform p:q symbol demultiplexing on p first data streams encoded by Reed-Solomon RS to obtain q second data streams; and perform alignment identifier locking on the q second data streams respectively to obtain four-symbol boundaries.

[0029] In conjunction with the above aspects and possible implementations thereof, in the second possible implementation of the above aspects, q = 2 × p, and the p:q symbol demultiplexing includes p 1:2 symbol demultiplexings, wherein each of the p 1:2 symbol demultiplexings corresponds one-to-one with a p first data stream; or, q = 4 × p, and the p:q symbol demultiplexing includes p 1:4 symbol demultiplexings, wherein each of the p 1:4 symbol demultiplexings corresponds one-to-one with a p first data stream. This embodiment provides two specific implementation methods for demultiplexing, which are simple to implement.

[0030] In conjunction with the second possible implementation of the above aspects, in the third possible implementation of the above aspects, the 1:2 symbol demultiplexing adopts a round-robin method of distributing 40 bits each time to demultiplex the corresponding first data stream to obtain 2 second data streams; or, the 1:4 symbol demultiplexing adopts a round-robin method of distributing 40 bits each time to demultiplex the corresponding first data stream to obtain 4 second data streams. It should be understood that using a 40-bit round-robin method can match the four-symbol boundaries, which is used to perform alignment identifier locking on each second data stream, thereby obtaining the four-symbol boundaries of the corresponding first data stream.

[0031] In conjunction with the above aspects and possible implementations thereof, in the fourth possible implementation of the above aspects, the four symbol boundaries are p, each corresponding to one of the p first data streams.

[0032] In conjunction with the fourth possible implementation of the above aspects, in the fifth possible implementation of the above aspects, all second data streams obtained in either the 1:2 symbol demultiplexing or the 1:4 symbol demultiplexing are aligned with the identifier lock, and the boundary of the distributed 40 bits is a four-symbol boundary.

[0033] In conjunction with the fourth possible implementation of the above aspects, in the sixth possible implementation of the above aspects, q = 2 × p. Within the threshold time interval, if at least one of the two second data streams fails to achieve alignment identifier locking, the first processing unit is further configured to shift the boundary of the 40 bits distributed in the 1:2 symbol demultiplexing, and re-perform 1:2 symbol demultiplexing to obtain two second data streams again; and to perform alignment identifier locking on the two re-obtained second data streams respectively to obtain one four-symbol boundary. This embodiment provides a complete process for obtaining a four-symbol boundary; only when all second data streams achieve alignment identifier locking can the correct four-symbol boundary be obtained.

[0034] In conjunction with the fourth possible implementation of the above aspects, in the seventh possible implementation of the above aspects, q = 4 × p. Within the threshold time interval, if at least one of the four second data streams fails to achieve alignment identifier locking, the first processing unit is further configured to shift the boundary of the 40 bits distributed in the 1:4 symbol demultiplexing, and re-perform 1:4 symbol demultiplexing to obtain four second data streams again; and perform alignment identifier locking on each of the four re-obtained second data streams to obtain one four-symbol boundary. This embodiment provides another complete process for obtaining four-symbol boundaries; only when all second data streams achieve alignment identifier locking can the correct four-symbol boundary be obtained.

[0035] In conjunction with the sixth or seventh possible implementation of the above aspects, in the eighth possible implementation of the above aspects, the granularity of shifting the boundary of the distributed 40 bits is 1 bit; or, the granularity of shifting the boundary of the distributed 40 bits is 40×m+1 bits, where m is an integer greater than 0. This application provides various shift granularities that can match the specific hardware implementation's processing bit width, resulting in relatively simple implementation and low complexity.

[0036] In conjunction with the above aspects and possible implementations thereof, in the ninth possible implementation of the above aspects, p = 8, q = 16; or p = 4, q = 16.

[0037] In conjunction with the above aspects and possible implementations thereof, in the tenth possible implementation of the above aspects, the codeword length of the internal code is 128 bits, wherein the information bits are 120 bits and the parity bits are 8 bits; or, the codeword length of the internal code is 126 bits, wherein the information bits are 110 bits and the parity bits are 16 bits.

[0038] In conjunction with the foregoing aspects and possible implementations thereof, in the eleventh possible implementation of the foregoing aspects, the codeword length of the RS is 544 symbols, wherein the information length is 514 symbols, and each symbol contains 10 bits. The four symbols comprise 40 bits.

[0039] In conjunction with the eleventh possible implementation of the above aspects, in the twelfth possible implementation of the above aspects, the second processing unit is further configured to perform convolutional interleaving on the received data stream, the convolutional interleaving including delaying the input data stream according to r delay lines, where r is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between any two adjacent delay lines is Q, each storage unit is used to store 40 bits, where Q is an integer greater than or equal to 1.

[0040] In conjunction with the twelfth possible implementation of the above aspects, in the thirteenth possible implementation of the above aspects, each delay line inputs 40 bits at a time and outputs 40 bits at a time, and the continuous r×40 bits in the output data stream after convolution and interleaving include the 40 bits output by each delay line.

[0041] In conjunction with the eleventh possible implementation of the above aspects, in the fourteenth possible implementation of the above aspects, the 40 bits stored in each storage unit in the convolutional interleaving are 4 RS symbols. In this case, it can be guaranteed that the 12 consecutive RS symbols output by the convolutional interleaving unit come from 12 different RS codewords, thus enabling the cascaded FEC to have better decoding performance.

[0042] In conjunction with the foregoing aspects and possible implementations thereof, in the fifteenth possible implementation of the foregoing aspects, the modulation employs four-level pulse amplitude PAM4 modulation.

[0043] In some possible implementations, the data processing apparatus provided in this application is used in scenarios including Ethernet, optical transport networks, and space optical communication.

[0044] Fifthly, embodiments of this application provide a chip for performing the methods described in any of the first or second aspects.

[0045] Sixthly, embodiments of this application provide an optical module. The optical module includes a processor and an interface. The processor is used to execute the methods described in any of the first or second aspects and to transmit signals through the interface. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor.

[0046] In a seventh aspect, embodiments of this application provide a communication device. The communication device includes a host-side device and an optical module as described in any embodiment of the sixth aspect, the optical module being connected to the host-side device.

[0047] Eighthly, embodiments of this application provide another device. This device includes a processor and an interface. The processor is used to perform the methods described in any of the embodiments of the first or second aspect, and to transmit signals through the interface. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor. The device may be a router, switch, server, or optical transport network equipment, etc.

[0048] Ninthly, embodiments of this application provide a communication system including a first communication device and a second communication device, wherein at least one of the first communication device and the second communication device is a communication device as described in any embodiment of the seventh aspect, and the first communication device and the second communication device are connected.

[0049] In a tenth aspect, this application provides a computer-readable storage medium storing instructions that, when executed by a computer, cause the method described in any of the embodiments of the first or second aspect to be implemented.

[0050] In the eleventh aspect, this application provides a computer program product including program instructions that, when executed, implement the method described in any of the embodiments of the first or second aspect above. Attached Figure Description

[0051] Figure 1 This is a schematic diagram of a communication system used in an embodiment of this application;

[0052] Figure 2 for Figure 1 A schematic diagram of a data transmission process in the communication system shown.

[0053] Figure 3 This is a schematic diagram of another communication system used in an embodiment of this application;

[0054] Figure 4 A flowchart of a data processing method provided in an embodiment of this application;

[0055] Figure 5(a) is a flowchart of an embodiment of this application for obtaining a four-symbol boundary;

[0056] Figure 5(b) is a flowchart of a specific method for obtaining four-symbol boundaries provided in an embodiment of this application;

[0057] Figure 5(c) is a flowchart of another specific method for obtaining four-symbol boundaries provided in an embodiment of this application;

[0058] Figure 6(a) is a schematic diagram of a convolutional interleaving process provided in an embodiment of this application;

[0059] Figure 6(b) is a schematic diagram of another convolutional interleaving process provided in an embodiment of this application;

[0060] Figure 7 A schematic diagram of a data processing architecture provided in this application;

[0061] Figure 8 A schematic diagram of another data processing architecture provided in this application;

[0062] Figure 9 A schematic diagram of another data processing architecture provided in this application;

[0063] Figure 10 A schematic diagram of another data processing architecture provided in this application;

[0064] Figure 11 A schematic diagram of the structure of a data processing device provided in this application;

[0065] Figure 12 A schematic diagram of the structure of an optical module provided in this application;

[0066] Figure 13 This is a schematic diagram of the structure of a communication device provided in this application. Detailed Implementation

[0067] This application provides a data processing method, apparatus, and system that enables the outer code symbol boundary to be obtained before the inner code is encoded, thereby achieving better cascaded FEC error correction performance and being applicable to a wide range of transmission scenarios.

[0068] It should be noted that the terms "first," "second," etc., in this application specification, claims, and the accompanying drawings are used to distinguish similar objects, not to limit a specific order or sequence. It should be understood that the above terms can be used interchangeably where appropriate so that the embodiments described in this application can be implemented in a sequence other than that described in this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0069] Figure 1 This is a schematic diagram of a communication system used in an embodiment of this application. Figure 1 As shown, the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches, routers, or servers. The transmitting device 01 is also called a client device at the transmitting end, and the receiving device 05 is also called a client device at the receiving end. The channel transmission medium 03 can be optical fiber. The client device is sometimes also called a host device. The client device includes a client chip and an interface. The client chip is also called a host chip. The connection interface between the transmitting device 01 and the transmitting processing module 02 can be connected through an attachment unit interface (AUI), and the connection interface between the receiving device 05 and the receiving processing module 04 can also be connected through an AUI. The transmitting processing module 02 and the receiving processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during data transmission. For example, the processing module can be a DR optical module, FR optical module, or LR optical module, such as a 1.6T FR1 coherent optical module (referred to as a 1.6T FR coherent optical module), a 1.6T TLR1 coherent optical module (referred to as a 1.6T LR coherent optical module), a 1.6T ZR coherent optical module, etc. Furthermore, the transmitting device 01, transmitting processing module 02, channel transmission medium 03, receiving processing module 04, and receiving device 05 in this communication system can all support bidirectional transmission or unidirectional transmission; specific limitations are not specified here.

[0070] Figure 2 for Figure 1The diagram illustrates a data transmission process in the communication system shown. Figure 2 As shown, during the data transmission process from transmitting device 01 to receiving device 05, transmitting device 01 performs external code encoding on the data and then transmits the externally encoded data to transmitting processing module 02. Transmitting processing module 02 performs internal code encoding on the externally encoded data to obtain data with both external and internal code encoding, and transmits this encoded data to channel transmission medium 03. Channel transmission medium 03 transmits the externally and internally encoded data to receiving processing module 04. Receiving processing module 04 performs internal code decoding on the externally and internally encoded data and transmits the internally decoded data to receiving device 05. Receiving device 05 performs external code decoding on the internally decoded data.

[0071] It should be understood that the distinction between "internal" in "internal code" and "external" in "external code" is based solely on the distance between the entity performing the data operation and the channel transmission medium 03. The entity operating on the internal code is closer to the channel transmission medium, while the entity operating on the external code is farther away. In this embodiment, after data is sent from the transmitting device 01, it is transmitted to the channel transmission medium 03 via the transmitting processing module 02, and then from the channel transmission medium 03 via the receiving processing module 04 to the receiving device 05. The data encoded by the transmitting device 01 is farther from the channel transmission medium 03 than the data encoded by the transmitting processing module 02, and the data decoded by the receiving device 05 is farther from the channel transmission medium 03 than the data decoded by the receiving processing module 04. Therefore, the data encoded by the transmitting device 01 is called data encoded with the external code, the data encoded by the transmitting processing module 02 is called data encoded with the internal code, the data decoded by the receiving device 05 is called data decoded with the external code, and the data decoded by the receiving processing module 04 is called data decoded with the internal code. In one possible implementation, both the internal and external encoding methods described above employ FEC encoding, thus forming a cascaded FEC transmission scheme. For example, the transmitting device 01 can use Reed-Solomon (RS) code for external encoding, and the transmitting processing module 02 can use Hamming code for internal encoding. Alternatively, the transmitting device 01 can use RS code for external encoding, and the transmitting processing module 02 can use Bose-Chaudhuri-Hocquenghem (BCH) code for internal encoding. A BCH code correcting a single error is equivalent to a Hamming code. Another example is that the transmitting device 01 can use RS code for external encoding, and the transmitting processing module 02 can also use Polar code for internal encoding. In some specific application scenarios, the transmitting device 01 can use RS(544,514) code, also known as KP4 code, for external encoding.

[0072] Figure 3 This is a schematic diagram of another communication system used in an embodiment of this application. For example... Figure 3As shown, the communication system includes a transmitting device 01, a channel transmission medium 03, and a receiving device 05. The transmitting device 01 performs external code encoding and internal code encoding on the data. The encoded data is then sent to the transmission medium 03. The receiving device 05 decodes the data received from the transmission medium 03, performing internal code decoding and external code decoding. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches, routers, or servers. The transmitting device 01 is also referred to as a client-side device or host-side device located at the transmitting end, and the receiving device 05 is also referred to as a client-side chip located at the receiving end. The channel transmission medium 03 can be optical fiber. The client-side device includes a client-side chip and an interface. The client-side chip is also referred to as a host-side chip. The transmitting device 01, channel transmission medium 03, and receiving device 05 in this communication system can all support bidirectional transmission or unidirectional transmission; specific limitations are not specified here. That is to say, Figure 3 The transmitting device 01 shown also integrates Figure 2 The function of the sending processing module 02 shown is as follows: Figure 3 The receiving device 05 shown also integrates Figure 2 The receiving end processing module 04 is shown to have the following functions. At this time, the transmitting end device 01 may also employ linear pluggable optics (LPO), co-packaged optics (CPO), or near packaged optics (NPO) technology.

[0073] It should also be noted that the above content is an exemplary description of the application scenarios of the data processing method provided in the embodiments of this application, and does not constitute a limitation on the application scenarios of the data processing method. As those skilled in the art will know, as business needs change, the application scenarios can be adjusted according to the application needs, and the embodiments of this application do not list them one by one.

[0074] Figure 4 This is a schematic flowchart illustrating a data processing method provided in an embodiment of this application. It should be understood that this data processing method is applied at the sending end, for example, it can be specifically implemented through the methods described above. Figure 2 The shown origin processing module 02 can be implemented in this way, or for example, it can be implemented through the above-mentioned... Figure 3 The shown transmitting device 01 is implemented.

[0075] 101. Perform p:q symbol demultiplexing and alignment identifier locking on p first data streams after RS ​​encoding to obtain four symbol boundaries, where p is an integer greater than or equal to 1, q is an integer, and q = 2 × p or q = 4 × p.

[0076] In this embodiment, all p first data streams are data streams encoded with external codes. For ease of explanation, the following description uses RS encoding as an example of external code encoding. In practical applications, other encoding methods can also be used for external code encoding. The data stream after RS ​​encoding can include multiple RS codewords. In this embodiment, the code length of the RS code is counted in units of symbols. The symbols in the RS code can be called RS symbols, also known as external code RS symbols. For example, the RS code uses RS(544,514) code, also known as KP4 code. The code length of the RS code is 544 RS symbols, that is, the codeword of the RS code includes 544 RS symbols, and one RS symbol contains 10 bits. Each a in each first data stream RS The adjacent RS symbols come from a RS 1 RS codeword, where a RS An integer power greater than or equal to 4 and equal to 2.

[0077] In some specific applications, for 1.6T transmission scenarios, such as under 1.6TBASE-R internal encoding, p=8. The p=8 first data streams are obtained by processing 8 AUI data streams of 1.6TAUI-8 using 1.6TBASE-R 8:8SM-PMA. In this case, the nominal rate of each data stream in the p=8 first data streams is 212.5 Gbits per second (b / s). Furthermore, each a in each first data stream... RS = 4 adjacent RS symbols from a RS = 4 RS codewords. The 8 AUI data streams of the 1.6TAUI-8 are obtained by processing 16 Physical Coding Sublayerlane (PCSL) data streams through 1.6TBASE-R 16:8SM-PMA. In the 16 PCSL data streams, every 4 adjacent RS symbols come from 4 different RS codewords.

[0078] In other specific applications, for 1.6T transmission scenarios, such as under 1.6TBASE-R internal code encoding, p=4. The p=4 first data streams are obtained by processing four AUI data streams of 1.6TAUI-4 using 1.6TBASE-R 4:4SM-PMA. In this case, the nominal rate of each data stream in the p=4 first data streams is 425 Gbits per second (b / s). Furthermore, each a in each first data stream... RS= 4 adjacent RS symbols from a RS = 4 RS codewords. The 4 AUI data streams of the 1.6TAUI-4 are obtained by processing 16 PCSL data streams through 1.6TBASE-R 16:4SM-PMA. In the 16 PCSL data streams, every 4 adjacent RS symbols come from 4 different RS codewords.

[0079] It should be noted that in some specific applications, the p first data streams are also referred to as p PMA data streams.

[0080] As shown in Figure 5(a), p:q symbol demultiplexing is performed on the p first data streams to obtain q second data streams. The cases of q = 2 × p and q = 4 × p are described below.

[0081] 1) For the case where q = 2 × p:

[0082] As shown in Figure 5(b), the p:q symbol demultiplexing includes p 1:2 symbol demultiplexings, and each of the p 1:2 symbol demultiplexings corresponds one-to-one with a p first data stream. Each 1:2 symbol demultiplexing uses a round-robin method, distributing 40 bits at a time, to demultiplex the input first data stream into two output second data streams.

[0083] Alignment marker locking is performed on each of the q second data streams. Here, alignment marker locking is also simply referred to as alignment lock. The alignment marker locking operation utilizes the known alignment marker (AM) in the PCSL data stream.

[0084] It should be noted that the alignment identifier locking of the two output second data streams can only be achieved if, in the aforementioned 1:2 symbol demultiplexing, 40 bits are distributed corresponding to 4 symbols (i.e., 4 foreign code RS symbols), that is, the 40-bit boundary corresponds to 4 symbol boundaries. Here, achieving alignment identifier locking means that the alignment identifier has been correctly locked. In this case, the boundary of the 40 distributed bits is a four-symbol boundary. It should be understood that the number of four-symbol boundaries is equal to the number of first data streams, that is, p four-symbol boundaries correspond to p first data streams.

[0085] It should be noted that within a certain time interval (also called a threshold time interval) or a certain bit interval (e.g., 222, 822, 400 bits), when the alignment flag locking is not achieved in the two output second data streams, the 40-bit boundary distributed in the above 1:2 symbol demultiplexing is shifted. This shift is also called a slip. In some specific applications, the 40-bit boundary is shifted by 1 bit. In other specific applications, the 40-bit boundary is shifted by a bit greater than 1. In this case, it is necessary to ensure that all possible boundaries are evaluated. A slip of 40 × m + 1 bits can be made, where m is a positive integer, such as 41 bits or 81 bits. When the shift interval matches the specific hardware implementation's bit width, the implementation is relatively simple and has low complexity. The above shift operation continues until the alignment flag locking is achieved in all two output second data streams.

[0086] When both second data streams output by 1:2 symbol demultiplexing achieve alignment identifier locking, four-symbol locking is achieved, and the four-symbol boundary corresponding to the first data stream is also obtained.

[0087] 2) For the case where q = 4 × p:

[0088] As shown in Figure 5(c), the p:q symbol demultiplexing includes p 1:4 symbol demultiplexings, and each of the p 1:4 symbol demultiplexings corresponds one-to-one with a p first data stream. Each 1:4 symbol demultiplexing uses a round-robin method, distributing 40 bits at a time, to demultiplex the input first data stream into four output second data streams.

[0089] Alignment marker locking is performed on each of the q second data streams. Here, alignment marker locking is also simply referred to as alignment lock.

[0090] The alignment identifier locking of the four output second data streams can only be achieved if, in the aforementioned 1:4 symbol demultiplexing, 40 bits are distributed corresponding to 4 symbols (i.e., 4 foreign code RS symbols), that is, the 40-bit boundary corresponds to 4 symbol boundaries. Here, achieving alignment identifier locking means that the alignment identifier is correctly locked. In this case, the boundary of the 40 distributed bits is a four-symbol boundary. It should be understood that the number of four-symbol boundaries is equal to the number of first data streams, that is, p four-symbol boundaries correspond to p first data streams.

[0091] Within a certain time interval (also called a threshold time interval) or a certain bit interval (e.g., 222, 822, 400 bits), when the alignment flag locking is not achieved in the four output second data streams, the 40-bit boundary distributed in the above 1:4 symbol demultiplexing is shifted (also called slip). In some specific applications, the 40-bit boundary distributed in the above 1:4 symbol demultiplexing is slipped by 1 bit. In other specific applications, the 40-bit boundary distributed in the above 1:4 symbol demultiplexing is slipped by a bit greater than 1. In this case, it is necessary to ensure that all possible boundaries are evaluated. A slip of 40 × m + 1 bits can be made, where m is a positive integer, for example, a slip of 41 bits or 81 bits. When the shift interval matches the specific hardware implementation's processing bit width, the implementation is relatively simple and has low complexity. The above shift operation continues until the alignment flag locking is achieved in all four output second data streams.

[0092] When both second data streams output by 1:2 symbol demultiplexing achieve alignment identifier locking, four-symbol locking is achieved, and the four-symbol boundary corresponding to the first data stream is also obtained.

[0093] For the cases q = 2 × p and q = 4 × p, when all q second data streams achieve alignment identifier locking, symbol-quartet locking is also achieved, and the symbol-quartet boundary corresponding to each first data stream is also obtained. This symbol-quartet boundary can be simply referred to as the symbol boundary. In this case, the q second data streams are q PCSL data streams. The four adjacent RS symbols in the q second data streams come from four different RS codewords. More specifically, for a second data stream, starting from the alignment identifier, the symbols in the data stream are represented in the form A, B, C, D, A, B, C, D… etc., where A, B, C, and D represent one RS symbol from four different codewords.

[0094] It should be noted that each a in each of the first data streams RS = 4 adjacent RS symbols from a RS = 4 different RS codewords, and the four-symbol boundary corresponding to a first data stream can be obtained, which means that the four adjacent RS symbols in the first data stream can be obtained.

[0095] 102. Based on the obtained four-symbol boundary, perform data processing including internal code encoding and modulation on the p first data streams to obtain p modulated data streams.

[0096] Based on the obtained four-symbol boundaries, 40 adjacent (also called consecutive) bits in each first data stream can be obtained, corresponding to 4 RS symbols. More specifically, the 4 RS symbols come from 4 different RS codewords. The 4 RS symbols are also called RS-FEC symbol quartets.

[0097] The following uses a first data stream as an example to illustrate the internal code encoding method. Specifically, every K information bits in the first data stream are internally encoded to generate NK check bits, thereby obtaining an internal codeword consisting of N bits, where 1 < K < N. In this application, K is considered to be a multiple of 10. Combining the obtained four-symbol boundary, the K information bits in each internal codeword can correspond to K / 10 external code RS symbols.

[0098] In some specific applications, the K information bits in each inner codeword correspond to K / 10 outer code RS symbols, and the corresponding K / 10 outer code RS symbols come from K / 10 different outer code RS codewords. This allows the FEC concatenation scheme, which includes RS encoding and inner code encoding, to achieve optimal performance. For example, the inner code encoding uses BCH(126,110), where K=110 information bits in each inner codeword correspond to K / 10=11 outer code symbols, and the corresponding K / 10=11 outer code symbols come from K / 10=11 different outer code RS codewords. Another example is the inner code encoding using a linear block code of N=128 and K=120, where K=120 information bits in each inner codeword correspond to K / 10=12 outer code symbols, and the corresponding K / 10=12 outer code symbols come from K / 10=12 different outer code RS codewords. To ensure that the K information bits in each internal codeword correspond to K / 10 different external codewords (RS codes), the first data stream undergoes convolutional interleaving before internal code encoding. The convolutional interleaving process is described in detail below.

[0099] Specifically, the convolutional interleaver (CIE) performing the convolutional interleaving process includes r delay lines, each with a different number of storage units. The delay line with the fewest storage units has 0 storage units. The difference in the number of storage units between any two adjacent delay lines is Q, where r is an integer greater than 1 and Q is an integer greater than or equal to 1. Each storage unit stores d bits, where d is an integer greater than or equal to 1. The bits in the input data stream of the CIE are sequentially input to the r delay lines according to their numbers, with d bits input and output from each delay line at a time. In some applications, the CIE outputs d bits at a time. In other applications, the CIE outputs r × d bits at a time, where r × d bits come from the r delay lines and include the d bits output from each delay line. The consecutive r × d bits in the output data stream of the CIE include the d bits output from each delay line.

[0100] It should be understood that the r delay lines each comprise 0, Q, 2Q, ..., (r-1)Q storage units, with each unit storing d bits. The r delay lines correspond to r delay values, which include 0 bits, Q×d bits, 2Q×d bits, ..., (r-1)Q×d bits. The more bits a delay line includes in its delay values, the longer the delay (also called latency) of that delay line to the data stream. It should be understood that when a delay line contains no storage units, the delay is 0 bits, which is called zero-latency pass-through. It should be understood that the aforementioned storage units are also called delay elements.

[0101] Figure 6(a) is a schematic diagram of the first structure of convolutional interleaving in an embodiment of this application. As shown in Figure 6(a), the number of storage units in the r delay lines decreases sequentially according to the sequence number of the r delay lines. That is, delay line 0 has (r-1)Q storage units, each delay line decreases by Q storage units sequentially, and delay line r-1 has 0 storage units. Figure 6(b) is a schematic diagram of the second structure of convolutional interleaving in an embodiment of this application. As shown in Figure 6(b), the number of storage units in the r delay lines increases sequentially according to the sequence number of the r delay lines. That is, delay line 0 has 0 storage units, each delay line increases by Q storage units sequentially, and delay line r-1 has (r-1)Q storage units.

[0102] It should be noted that at any given moment, the input and output switches of the convolutional interleaver are located on the same delay line. After the current delay line receives and outputs d bits in a single input, the switch is switched to the next delay line. This ensures that the bits in the input data stream are sequentially input to the r delay lines according to their sequence numbers, and that the consecutive r×d bits in the output data stream include the d bits output from each delay line. The specific data read / write operations are as follows: d bits are read from the memory cell closest to the output port of the current delay line; the d bits stored in each memory cell of the current delay line are transferred to the next memory cell; then, d bits are written to the memory cell closest to the input port of the current delay line. Afterward, the switch is moved to the next delay line, and the above operations are repeated, and so on.

[0103] It should be understood that when the same parameters r, Q, and d are used, the convolutional interleaving processing in Figure 6(a) and the convolutional interleaving processing in Figure 6(b) are the inverse operations of each other. That is, when the sending-end processing module uses the convolutional interleaving structure shown in Figure 6(a), the corresponding convolutional deinterleaving in its receiving-end processing module uses the structure shown in Figure 6(b). Similarly, when the sending-end processing module uses the convolutional interleaving structure shown in Figure 6(b), the corresponding convolutional deinterleaving in its receiving-end processing module uses the structure shown in Figure 6(a).

[0104] Typically, the number of bits stored in each memory cell is d = a. RS ×10=40. Based on the obtained four-symbol boundaries, the 40 bits stored in each storage unit come from 40 consecutive bits in a first data stream, corresponding to 4 RS symbols. The 4 RS symbols come from 4 different RS codewords.

[0105] After the p first data streams are encoded using internal codes, they are also modulated to obtain p modulated data streams. In some specific applications, the modulation uses four-level pulse amplitude modulation (PAM4).

[0106] In the embodiments of this application, the data processing flow can be divided into two parts. The first data processing may include p:q symbol demultiplexing and alignment identifier locking. The second data processing, in addition to internal code encoding and modulation, may also include at least one of 1:8 K-bit distribution, cyclic shift, 8:1 bit-pair interleaver, pad insertion, and precoder.

[0107] It should be noted that in some specific applications, the convolutional interleaving operation can be skipped to achieve a lower latency for the overall cascaded FEC scheme, which can be applied in application scenarios requiring low latency.

[0108] The following examples, using a linear block code with N=128 and K=120 as the internal code, provide several implementations to illustrate the possible values ​​of p.

[0109] Example 1: Consider 1.6TBASE-R code encoding, p = 8 and q = 2 × p = 16.

[0110] like Figure 7 As shown, the eight AUI data streams of 1.6TAUI-8 are processed by 1.6TBASE-R 8:8SM-PMA to obtain p=8 first data streams. The p=8 first data streams are then demultiplexed using 8:16 symbols and aligned identifiers are locked to obtain the four symbol boundaries (also called four symbol boundaries) of the p=8 first data streams. The 8:16 symbol demultiplexing includes p=8 1:2 symbol demultiplexing operations, as shown in Figure 5(b). Each 1:2 symbol demultiplexing operation uses a round-robin method, distributing 40 bits at a time, to demultiplex the input one first data stream into two output second data streams.

[0111] Based on the obtained four-symbol boundaries, a second data processing step involving internal code encoding and PAM4 modulation is performed on p=8 first data streams to obtain p=8 PAM4 modulated data streams. This second data processing step may include convolutional interleaving, 1:8 120-bit distribution, cyclic shifting, internal code (128, 120) encoding, 8:1 bit-pair interleaving, padding insertion, and PAM4 modulation.

[0112] The convolutional interleaver contains r = 3 delay lines, with a difference of Q = 24 between the number of storage units in each pair of adjacent delay lines. Each storage unit stores d = 40 bits. Based on the obtained four-symbol boundaries, the d = 40 bits stored in each storage unit during convolutional interleaving correspond to 4 RS symbols. Furthermore, based on the obtained four-symbol boundaries, the cyclic shift is performed on 12 symbols out of 120 information bits at a symbol-level granularity.

[0113] It should be noted that, in this embodiment, as Figure 7 As shown, in the second data processing, p=8 first data streams are processed to obtain p=8 PAM4 data streams. For each first data stream, the 1024-bit padding insertion is performed after the internal code encoding operation, or it can be performed before the internal code encoding. In this case, each of the 8 data streams before internal code encoding periodically inserts 120 bits of padding. Each group of 120 bits, after internal code encoding, yields 128 bits of encoded padding. After 8:1 bit pair interleaving, a total of 128 × 8 = 1024 bits of padding are obtained.

[0114] In this embodiment, before internal code encoding, a four-symbol boundary is obtained, and the four-symbol boundary is used to make the 120 information bits of the internal code (128,120) come from 12 different RS codewords, so that the cascaded FEC scheme has good error correction performance and can be applied to a variety of transmission scenarios.

[0115] Example 2: Consider 1.6TBASE-R code encoding, p = 4 and q = 4 × p = 16.

[0116] like Figure 8 As shown, the four AUI data streams of 1.6TAUI-4 are processed by 1.6TBASE-R 4:4SM-PMA to obtain p = 4 first data streams. The p = 4 first data streams are then demultiplexed using 4:16 symbols and aligned identifiers are locked to obtain the four symbol boundaries (also called the four symbol boundaries) of the p = 4 first data streams. The 4:16 symbol demultiplexing includes p = 4 1:4 symbol demultiplexing operations, as shown in Figure 5(c). Each 1:4 symbol demultiplexing operation uses a round-robin method, distributing 40 bits at a time, to demultiplex the input one first data stream to obtain four output second data streams.

[0117] Based on the obtained four-symbol boundaries, a second data processing step involving internal code encoding and PAM4 modulation is performed on p=4 first data streams to obtain p=4 PAM4 modulated data streams. The second data processing step includes convolutional interleaving, 1:8 120-bit distribution, cyclic shift, internal code (128,120) encoding, 8:1 bit pair interleaving, padding insertion, and PAM4 modulation.

[0118] The convolutional interleaver contains r = 3 delay lines, with a difference of Q = 24 between the number of storage units in each pair of adjacent delay lines. Each storage unit stores d = 40 bits. Based on the obtained four-symbol boundaries, the d = 40 bits stored in each storage unit during convolutional interleaving correspond to 4 RS symbols. Furthermore, based on the obtained four-symbol boundaries, the cyclic shift is performed on 12 symbols out of 120 information bits at a symbol-level granularity.

[0119] It should be noted that, in this embodiment, as Figure 8 As shown, in the second data processing, p=4 first data streams are processed to obtain p=4 PAM4 data streams. For each first data stream, the 1024-bit padding insertion is performed after the internal code encoding operation, or it can be performed before the internal code encoding. In this case, each of the eight data streams before internal code encoding periodically inserts 120 bits of padding. Each group of 120 bits, after internal code encoding, yields 128 bits of encoded padding. After 8:1 bit pair interleaving, a total of 128 × 8 = 1024 bits of padding are obtained.

[0120] In this embodiment, before internal code encoding, a four-symbol boundary is obtained, and the four-symbol boundary is used to make the 120 information bits of the internal code (128,120) come from 12 different RS codewords, so that the cascaded FEC scheme has good error correction performance and can be applied to a variety of transmission scenarios.

[0121] It should be noted that in the above embodiment, the input to the second data processing, which includes internal code encoding, is the p first data streams. In some specific applications, the input to the second data processing can be p data streams obtained by q:p symbol multiplexing of the data streams implementing alignment identifier locking. In this case, another flow of the data processing method is as follows:

[0122] 201. Perform p:q symbol demultiplexing and alignment identifier locking on p first data streams encoded by RS to obtain four-symbol boundaries and obtain q second data streams that implement alignment identifier locking, where p is an integer greater than or equal to 1, q is an integer, and q = 2 × p or q = 4 × p;

[0123] 202. Multiplex q:p symbols in the second data stream to obtain p third data streams. Perform second data processing, including internal code encoding and modulation, on the p third data streams according to the obtained four-symbol boundaries to obtain p modulated data streams.

[0124] When q = 2 × p, the q:p symbol multiplexing includes p 2:1 symbol multiplexings, each corresponding one-to-one with the p first data streams mentioned above. More specifically, each 2:1 symbol multiplexing multiplexes the two second data streams obtained from the 1:2 symbol demultiplexing of one first data stream into a 2:1 symbol multiplexing. This 2:1 symbol multiplexing, combined with the acquired four-symbol boundary, uses a round-robin method with four symbols (containing a total of 40 bits) to multiplex the two input second data streams into one output third data stream. The p 2:1 symbol multiplexings multiplex the input q = 2 × p second data streams to output p third data streams.

[0125] When q = 4 × p, the q:p symbol multiplexing includes p 4:1 symbol multiplexings, and each of the p 4:1 symbol multiplexings corresponds one-to-one with the aforementioned p first data streams. More specifically, each 4:1 symbol multiplexing multiplexes the four second data streams obtained from the 1:4 symbol demultiplexing of one first data stream into 4:1 symbols. This single 4:1 symbol multiplexing, combined with the acquired four-symbol boundary, uses a round-robin method with four symbols (containing a total of 40 bits) to multiplex the four input second data streams into one output third data stream. The p 4:1 symbol multiplexings multiplex the input q = 4 × p second data streams to output p third data streams.

[0126] It should be noted that in some specific applications, before performing q:p symbol multiplexing on the q second data streams, the q second data streams are deskewed to ensure that there is no offset between the deskewed q second data streams, thus supporting accurate calculation of possible path data delay. In this case, the deskew is also called full deskew. In other specific applications, the deskew is based on 40-bit deskew, which means that there are d bits between the q second data streams. skew An offset of bits, where d skew When the offset is a multiple of 40, it is also called a 40-bit deskew.

[0127] The following examples, using a linear block code with N=128 and K=120 for internal encoding, provide several implementation methods to illustrate another process of the above data processing method.

[0128] Example 3: Consider 1.6TBASE-R internal code encoding, p = 8 and q = 2 × p = 16.

[0129] like Figure 9 As shown, the eight AUI data streams of 1.6TAUI-8 are processed by 1.6TBASE-R 8:8SM-PMA to obtain p = eight first data streams. The p = eight first data streams are then demultiplexed using 8:16 symbols and aligned identifiers are locked to obtain the four symbol boundaries (also called 4 symbol boundaries) of the p = eight first data streams and to obtain q = 16 second data streams. The 8:16 symbol demultiplexing includes p = eight 1:2 symbol demultiplexing operations, as shown in Figure 5(b). Each 1:2 symbol demultiplexing operation uses a round-robin method, distributing 40 bits at a time, to demultiplex the input one first data stream to obtain two output second data streams.

[0130] The 16 second data streams with q=16 alignment identifier locking are multiplexed using a 16:8 symbol multiplexing process to obtain p=8 third data streams. Based on the obtained four-symbol boundaries, the p=8 third data streams undergo a second data processing process including internal code encoding and PAM4 modulation to obtain p=8 PAM4 modulated data streams. This second data processing includes convolutional interleaving, 1:8 120-bit distribution, cyclic shifting, internal code (128,120) encoding, 8:1 bit-pair interleaving, padding insertion, and PAM4 modulation.

[0131] The convolutional interleaver contains r = 3 delay lines, with a difference of Q = 24 between the number of storage units in each pair of adjacent delay lines. Each storage unit stores d = 40 bits. Based on the obtained four-symbol boundaries, the d = 40 bits stored in each storage unit during convolutional interleaving correspond to 4 RS symbols. Furthermore, based on the obtained four-symbol boundaries, the cyclic shift is performed on 12 symbols out of 120 information bits at a symbol-level granularity.

[0132] It should be noted that, in this embodiment, as Figure 9 As shown, in the second data processing, p=8 first data streams are processed to obtain p=8 PAM4 data streams. For each first data stream, the 1024-bit padding insertion is performed after the internal code encoding operation, or it can be performed before the internal code encoding. In this case, each of the 8 data streams before internal code encoding periodically inserts 120 bits of padding. Each group of 120 bits, after internal code encoding, yields 128 bits of encoded padding. After 8:1 bit pair interleaving, a total of 128 × 8 = 1024 bits of padding are obtained.

[0133] In this embodiment, before internal code encoding, four symbol boundaries are obtained, and the second data processing utilizes the symbol boundaries to make the 120 information bits in the internal code (128,120) encoding come from 12 different RS codewords, thereby enabling the cascaded FEC scheme to have better error correction performance and be applicable to a wide range of transmission scenarios.

[0134] Example 4: Consider 1.6TBASE-R code encoding, p = 4 and q = 4 × p = 16.

[0135] like Figure 10 As shown, the four AUI data streams of 1.6TAUI-4 are processed by 1.6TBASE-R 4:4SM-PMA to obtain p = 4 first data streams. The p = 4 first data streams are then demultiplexed using 4:16 symbols and aligned identifiers are locked to obtain the four symbol boundaries (also called the four symbol boundaries) of the p = 4 first data streams and to obtain q = 16 second data streams. The 4:16 symbol demultiplexing includes p = 4 1:4 symbol demultiplexing operations, as shown in Figure 5(c). Each 1:4 symbol demultiplexing operation uses a round-robin method, distributing 40 bits at a time, to demultiplex the input one first data stream to obtain four output second data streams.

[0136] The 16 second data streams with q=16 alignment identifier locking are multiplexed using a 16:4 symbol multiplexing process to obtain p=4 third data streams. Based on the obtained four-symbol boundaries, the p=4 first data streams undergo a second data processing process including internal code encoding and PAM4 modulation to obtain p=4 PAM4 modulated data streams. This second data processing includes convolutional interleaving, 1:8 120-bit distribution, cyclic shifting, internal code (128,120) encoding, 8:1 bit-pair interleaving, padding insertion, and PAM4 modulation.

[0137] The convolutional interleaver contains r = 3 delay lines, with a difference of Q = 24 between the number of storage units in each pair of adjacent delay lines. Each storage unit stores d = 40 bits. Based on the obtained four-symbol boundaries, the d = 40 bits stored in each storage unit during convolutional interleaving correspond to 4 RS symbols. Furthermore, based on the obtained four-symbol boundaries, the cyclic shift is performed on 12 symbols out of 120 information bits at a symbol-level granularity.

[0138] It should be noted that, in this embodiment, as Figure 10As shown, in the second data processing, p=4 first data streams are processed to obtain p=4 PAM4 data streams. For each first data stream, the 1024-bit padding insertion is performed after the internal code encoding operation, or it can be performed before the internal code encoding. In this case, each of the eight data streams before internal code encoding periodically inserts 120 bits of padding. Each group of 120 bits, after internal code encoding, yields 128 bits of encoded padding. After 8:1 bit pair interleaving, a total of 128 × 8 = 1024 bits of padding are obtained.

[0139] In this embodiment, before internal code encoding, a four-symbol boundary is obtained, and the four-symbol boundary is used to make the 120 information bits of the internal code (128,120) come from 12 different RS codewords, so that the cascaded FEC scheme has good error correction performance and can be applied to a variety of transmission scenarios.

[0140] Figure 11 This is a schematic diagram of a data processing device according to an embodiment of this application. Figure 11 As shown, the data processing device includes a first processing unit 1101 and a second processing unit 1102; wherein the first processing unit 1101 is used to perform the first data processing described in the previous embodiments, and the second processing unit 1102 is used to perform the second data processing described in the previous embodiments. The specific data processing methods have been described in detail in the previous embodiments and will not be repeated here.

[0141] It should be understood that the data processing apparatus provided in this application can also be implemented in other ways. For example, the unit division in the above apparatus is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system. In addition, the functional units in the various embodiments of this application may be integrated into one processing unit, or they may be independent physical units, or two or more functional units may be integrated into one processing unit. The integrated units described above can be implemented in hardware or as software functional units.

[0142] Figure 12 This is a schematic diagram of one structure of the optical module in an embodiment of this application. Figure 12As shown, the optical module includes a processor 1201 and an interface 1202. The processor 1201 is used to perform the operations performed by the data processing device in the above embodiments. The interface 1202 can be a transceiver or an input / output interface. The interface 1202 is used to receive signals from other devices and transmit them to the processor 1201 or to send signals from the processor 1201 to other devices. As an example, after the processor 1201 performs the internal code encoding process to obtain an encoded data stream, it sends the encoded data stream through the interface 1202. In this example, the interface 1202 can specifically refer to an electrical interface. As another example, after the processor 1201 performs the internal code encoding process to obtain an encoded data stream, it performs symbol mapping (also known as modulation mapping) to obtain a symbol stream to be transmitted. The modulator in the optical module performs signal processing such as electro-optic conversion according to the symbol stream to be transmitted to obtain an optical signal, and then sends the optical signal through the interface 1202. In this example, the interface 1202 can specifically refer to an optical interface. Optionally, the optical module may also include a memory 1203, wherein the memory 1203 is used to store program instructions and / or data.

[0143] Typically, an optical module consists of optoelectronic devices, a processor, and an interface. The optoelectronic devices include transmitting and receiving devices. The transmitting end of the optical module converts electrical signals into optical signals and transmits them through optical fibers. The receiving end of the optical module receives the optical signals and converts them back into electrical signals.

[0144] It should be noted that the types of optical modules in this application embodiment include, but are not limited to, normal optical modules, near package optics (NPO) modules, and co-packaged optics (CPO) modules. Normal optical modules can perform functions including, but not limited to, digital signal processing (DSP) and clock data recovery (CDR). For example, a normal optical module converts analog signals to digital signals, performs DSP on the digital signals, and then converts them back to analog signals before sending them to the host device. Because DSP requires retiming, a normal optical module can also be called a retimed module. Normal optical modules connect to the host device via an attachment unit interface (AUI). NPO and CPO modules do not have pluggable physical packages and are closer to the host device. NPO and CPO modules can also be called optical engines. NPO or CPO technology is a technology that "packages" the host device (or host chip) and the optical engine. When NPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called an NPO module. When CPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called a CPO module.

[0145] Figure 13 This is a schematic diagram of the structure of a communication device in an embodiment of this application. Figure 13 As shown, the communication device includes a host-side device 1301 and an optical module 1302. The host-side device 1301 sends data to the optical module 1302, and the optical module 1302 generates an optical signal based on the data sent by the host-side device 1301 and transmits the optical signal through the channel. For example, the host-side device can be a switch, router, or server. This communication device can be a communication device that includes the host-side device 1301 and the optical module 1302.

[0146] This application also provides an Optical Transport Network (OTN) device, which includes line-side equipment and client-side equipment. The client-side equipment may also be referred to as a tributary-side equipment in some scenarios. The line-side equipment includes a processor and an interface. The processor is used to execute the data processing methods described in the above embodiments. The interface can be a transceiver or an input / output interface, used to receive signals from other devices outside the line-side equipment and transmit them to the processor, or to send signals from the processor to other devices outside the line-side equipment.

[0147] This application also provides a chip. The chip integrates circuitry for implementing the functions of the aforementioned processor and one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, it can be connected to an external memory via the interface. The chip can perform the method steps of any one or more of the foregoing embodiments. Alternatively, the chip can implement the actions performed by the data processing device in the foregoing embodiments based on program code stored in the memory.

[0148] As an example, the chip in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0149] This application also provides a computer-readable storage medium, including a program or instructions that, when run on a computer, cause the data processing method as described in the above embodiments to be implemented.

[0150] It should be understood that the processor mentioned in the embodiments of this application can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0151] As an example, the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0152] In embodiments of this application, the memory may be random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and storage medium may reside in an ASIC. Additionally, the ASIC may reside in a network device or a terminal device. Alternatively, the processor and storage medium may exist as discrete components in the network device or terminal device.

[0153] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof.

[0154] When implemented in hardware, the data processing method provided in this application embodiment may be implemented without reading software code or instructions. For example, it may be implemented by CPU, DSP, ASIC, FPGA, other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0155] When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, all or part of the processes or functions of the embodiments of this application are performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable device. The computer program or instructions can be stored in or transmitted through a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server integrating one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a Digital Versatile Disc (DVD); or it can be a semiconductor medium, such as a solid-state disk (SSD).

[0156] Finally, it should be noted that the above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data processing method, characterized by, The method comprises: to Reed-Solomon RS encoded a first data stream symbol demultiplexing and alignment identification lock to obtain a four-symbol boundary and q second data streams, wherein, is an integer greater than or equal to 1, is an integer, and ; Perform on q second data streams Symbol reuse is used to obtain p third data streams; According to the acquired four-symbol boundary, the third data stream is subjected to convolution interleaving processing. The third data stream is subjected to convolution interleaving processing. performing 1:8 distribution of 120 bits on each of the p data streams after convolution interleaving to obtain 8p fourth data streams; performing inner code encoding on the 8p fourth data streams respectively.

2. The method of claim 1, wherein, The pair of Reed-Solomon RS encoded The first data stream is subjected to a pair of Reed-Solomon RS encoding Symbol demultiplexing and alignment identification lock, specifically comprising: The method comprises the following steps: The first data stream is subjected to Symbol demultiplexing to obtain q second data streams; performing alignment and identification locking on each of the q second data streams to obtain a four-symbol boundary.

3. The method of claim 1, wherein, The p:q symbol demultiplexing comprises p 1:2 symbol demultiplexings, wherein the p 1:2 symbol demultiplexings correspond to the p first data streams one by one.

4. The method of claim 3, wherein, The 1:2 symbol demultiplexing adopts a round-robin manner of distributing 40 bits each time to demultiplex the corresponding one first data stream to obtain two second data streams.

5. The method of claim 4, wherein, The four-symbol boundary is p, and corresponds to the p first data streams one by one.

6. The method of claim 5, wherein, All the second data streams obtained in the 1:2 symbol demultiplexing are subjected to alignment and identification locking, and the 40-bit boundary of the distribution is a four-symbol boundary.

7. The method according to any one of claims 4-6, characterized in that, Within a threshold time interval, at least one of the two second data streams does not achieve alignment and identification locking, the 40-bit boundary of the distribution in the 1:2 symbol demultiplexing is shifted, and 1:2 symbol demultiplexing is performed again to obtain two second data streams again; performing alignment and identification locking on the two second data streams obtained again to obtain a four-symbol boundary.

8. The method of claim 7, wherein, The granularity of shifting the 40-bit boundary of the distribution is 1 bit; or The granularity of shifting the boundary of the 40 bits of the distribution is m+1 bits, where m is an integer greater than 0.

9. The method according to any one of claims 1-6, characterized in that, ， 。 10. The method according to any one of claims 1-6, characterized in that, The method further comprises: performing 8:1 bit pair interleaving on each of the 8p data streams after encoding.

11. The method according to any one of claims 1-6, characterized in that, The code word length of the inner code is 128 bits, wherein the information bits are 120 bits, and the check bits are 8 bits.

12. The method of any one of claims 1-6, wherein, The code word length of the RS is 544 symbols, wherein the information length is 514 symbols, and each symbol contains 10 bits.

13. The method of any one of claims 1-6, wherein, The convolution interleaving comprises delaying the input data stream according to r delay lines, the r is an integer greater than 1, each delay line comprises a different number of storage units, the delay line comprising the smallest number of storage units comprises 0 storage units, the difference between the number of storage units of each adjacent two delay lines is Q, each storage unit is used to store 40 bits, and the Q is an integer greater than or equal to 1.

14. The method of claim 13, wherein, Each delay line inputs 40 bits at a time and outputs 40 bits at a time, and the output data stream after convolution interleaving has continuous r The 40 bits include the 40 bits output by each delay line, and the 40 bits stored by the storage unit are 4 RS symbols.

15. The method of claim 13, wherein, r=3，Q=24。 16. A data processing apparatus, characterized by: The method comprises: a first processing unit and a second processing unit; The first processing unit is configured to perform Reed-Solomon RS encoding on the first data stream to obtain a second data stream. The first processing unit is configured to perform Reed-Solomon RS encoding on the first data stream to obtain a second data stream. The first processing unit is configured to perform Reed-Solomon RS encoding on the first data stream to obtain a second data stream. is an integer greater than or equal to 1, is an integer, and ; The second processing unit is configured to perform symbol multiplexing on the q second data streams to obtain p third data streams, and perform convolution interleaving on the p third data streams according to the obtained four-symbol boundary. The symbol multiplexing is performed on the q second data streams to obtain p third data streams. The convolution interleaving is performed on the p third data streams according to the obtained four-symbol boundary. The 1:8 120-bit distribution is performed on the p data streams after the convolution interleaving to obtain 8p fourth data streams. The inner code encoding is performed on the 8p fourth data streams.

17. The apparatus of claim 16, wherein, The first processing unit is specifically configured to: The first data stream is Reed-Solomon RS encoded The first data stream is Reed-Solomon RS encoded Symbol demultiplexing is performed on the first data stream to obtain q second data streams perform alignment and identification locking on each of the q second data streams to obtain a four-symbol boundary.

18. The apparatus of claim 16, wherein, The p:q symbol demultiplexing comprises p 1:2 symbol demultiplexings, wherein the p 1:2 symbol demultiplexings correspond to the p first data streams one by one.

19. The apparatus of claim 18, wherein, The 1:2 symbol demultiplexing adopts a round-robin manner of distributing 40 bits each time to demultiplex the corresponding one first data stream to obtain two second data streams.

20. The apparatus of claim 19, wherein, The four-symbol boundary is p, and corresponds to the p first data streams one by one.

21. The apparatus of claim 20, wherein, All the second data streams obtained in the 1:2 symbol demultiplexing are subjected to alignment and identification locking, and the 40-bit boundary of the distribution is a four-symbol boundary. Within a threshold time interval, at least one of the two second data streams does not achieve alignment and identification locking, the 40-bit boundary of the distribution in the 1:2 symbol demultiplexing is shifted, and 1:2 symbol demultiplexing is performed again to obtain two second data streams again; performing alignment and identification locking on the two second data streams obtained again to obtain a four-symbol boundary. The granularity of shifting the 40-bit boundary of the distribution is 1 bit; or 22. The apparatus of any one of claims 19-21, wherein, In a threshold time interval, at least one of the two second data streams does not achieve alignment mark locking, and the first processing unit is further configured to shift the 40-bit boundary of the distributed 1:2 symbol demultiplexing, re-perform 1:2 symbol demultiplexing to re-obtain two second data streams, and perform alignment mark locking on the re-obtained two second data streams respectively to obtain one four-symbol boundary.

23. The apparatus of claim 22, wherein, The granularity of the shift of the distributed 40-bit boundary is 1 bit. The granularity of shifting the boundary of the 40 bits of the distribution is m+1 bits, where m is an integer greater than 0.

24. The apparatus of any one of claims 16-21, wherein, ， 。 25. The apparatus of any one of claims 16-21, wherein, The second processing unit is further configured to perform 8:1 bit pair interleaving on each of the 8p encoded data streams.

26. The apparatus of any one of claims 16-21, wherein, The code word length of the inner code is 128 bits, wherein the information bits are 120 bits and the check bits are 8 bits.

27. The apparatus of any one of claims 16-21, wherein, The code word length of the RS is 544 symbols, wherein the information length is 514 symbols, and each symbol contains 10 bits.

28. The apparatus of any one of claims 16-21, wherein, The convolution interleaving includes delaying the input data stream according to r delay lines, wherein r is an integer greater than 1, each delay line includes a different number of storage units, the delay line including the smallest number of storage units includes 0 storage units, the difference between the number of storage units of each adjacent two delay lines is Q, each storage unit is used to store 40 bits, and Q is an integer greater than or equal to 1.

29. The apparatus of claim 28, wherein, Each delay line inputs 40 bits at a time and outputs 40 bits at a time, and the output data stream after convolution interleaving has continuous r The 40 bits include the 40 bits output by each delay line, and the 40 bits stored by the storage unit are 4 RS symbols.

30. The apparatus of claim 28, wherein, r=3，Q=24。 31. A chip, characterized by The chip is configured to perform the method of any one of claims 1-15.

32. An optical module, characterized by comprising: The optical module includes a processor and an interface, the processor is configured to perform the method of any one of claims 1-15, and the interface is configured to transmit and receive signals.

33. A communications device, characterized by The communication device includes a host-side device and the optical module of claim 32, and the optical module is connected to the host-side device.

34. A communication system, characterized by The communication device includes a host-side device and the optical module of claim 32, and the optical module is connected to the host-side device. The communication device includes a host-side device and the optical module of claim 32, and the optical module is connected to the host-side device. The communication device includes a host-side device and the optical module of claim 32, and the optical module is connected to the host-side device. The communication device includes a host-side device and the optical module of claim 32, and the optical module is connected to the host-side device.

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