A data receiving method and device based on a PHY chip

Abstract

The application provides a PHY chip-based data receiving method and device, and relates to the technical field of data transmission. In the method, a first synchronization data is sampled by using a sampling clock, so that a pulse enable is generated at a rising edge position of the first synchronization data, wherein the pulse enable is used to determine a counter value of a counter, the counter value is a reset value or a count value, and the first synchronization data is obtained by sampling an enable mark by using the sampling clock. In the transmission of a first data frame, the first synchronization data and second synchronization data are sampled according to the reset value, wherein the second synchronization data is obtained by sampling a data signal by using the sampling clock. In the transmission of a second data frame, a sampling object is determined according to a clock source, and the sampling object is sampled based on the counter value. In this way, the sampling time of data is accurately controlled in the transmission of a data frame, and thus the data receiving effect of the PHY chip is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data transmission, in particular to a data receiving method and device based on a PHY chip. BACKGROUND

[0002] The MII interface is a specification of providing data transmission interface between MAC (Media Access Control) layer and PHY (Physical Layer) layer. The signals sent from MAC to PHY chip are CLK25, TXENA, TXD[3:0], MDC; the signals sent from PHY chip to MAC are TX_CLK, RX_CLK, RXDV, RXD[3:0], etc. CLK25 is the input main clock of the PHY chip, TXENA and TXD[3:0] are the enable signal and data signal sent from MAC to the PHY chip, and TX_CLK is the synchronous clock of sending enable and data. In the existing MII interface scheme, in order to reduce the number of MAC interfaces, the input of TX_CLK is usually removed, and other schemes are used for data synchronization to prevent sampling errors.

[0003] In the prior art, the sampling error is generally prevented by the following ways: 1. the clock CLK25 of the PHY is provided by the MAC, that is, the sampling clock inside the PHY is guaranteed to be synchronized with the data sent by the MAC; 2. the phase offset configuration of MII_TXENA and MII_TXD[3:0] is added in the MAC, and the phase of MII_TXENA and MII_TXD[3:0] sent by the MAC is modified in units of 10ns, and if the phase of the sampling clock of the PHY and the data sent by the MAC does not meet the requirements, the offset can be modified to meet the synchronous sampling of the PHY. However, the data receiving effect is still not ideal.

[0004] In summary, how to improve the data receiving effect of the PHY chip is a problem to be solved by those skilled in the art. SUMMARY

[0005] Therefore, the present application provides a data receiving method and device based on a PHY chip, which aims to improve the data receiving effect of the PHY chip.

[0006] In a first aspect, the present application provides a data receiving method based on a PHY chip, comprising:

[0007] The first synchronous data is sampled by using the sampling clock to generate a pulse enable at the rising edge position of the first synchronous data; the pulse enable is used to determine the counter value of the counter; the counter value is a reset value or a count value; the first synchronous data is obtained by sampling the enable flag by using the sampling clock;

[0008] sampling the first synchronization data and the second synchronization data according to the reset value when transmitting the first data frame; the second synchronization data is obtained by sampling a data signal with the sampling clock;

[0009] determining a sampling object according to a clock source when transmitting the second data frame, and sampling the sampling object based on the counter value.

[0010] Optionally, before sampling the first synchronization data with the sampling clock, the method further comprises:

[0011] sampling the enable flag twice with the sampling clock to obtain third synchronization data and the first synchronization data respectively;

[0012] sampling the data signal twice with the sampling clock to obtain fourth synchronization data and the second synchronization data respectively.

[0013] Optionally, when transmitting the first data frame, if the pulse enable is high, resetting the counter, and the counter value is the reset value; if the pulse enable is low, the counter is incremented by one cycle, and the counter value is the count value.

[0014] Optionally, if the clock source is not provided by the MAC, the determining a sampling object according to a clock source when transmitting the second data frame, and sampling the sampling object based on the counter value, comprises:

[0015] if the pulse enable is the high level, resetting the counter, and the counter value is the reset value;

[0016] sampling the first synchronization data and the second synchronization data based on the reset value.

[0017] Optionally, if the clock source is provided by the MAC, the determining a sampling object according to a clock source when transmitting the second data frame, and sampling the sampling object based on the counter value, comprises:

[0018] sampling the third synchronization data and the fourth synchronization data based on a first count value; the count value comprises the first count value; and the first count value is in a previous cycle of the reset value.

[0019] Optionally, after the determining a sampling object according to a clock source when transmitting the second data frame, and sampling the sampling object based on the counter value, the method further comprises:

[0020] sampling the enable flag and the data signal based on a second count value; the count values comprise the second count value; the second count value is located in a previous cycle of the first count value.

[0021] In a second aspect, the present application provides a PHY chip-based data receiving device, comprising:

[0022] a pulse enable generation module, configured to sample first synchronous data by using a sampling clock, so as to generate a pulse enable at a rising edge position of the first synchronous data; the pulse enable is used to determine a counter value of a counter; the counter value is a reset value or a count value; the first synchronous data is obtained by sampling an enable flag by using the sampling clock;

[0023] a first transmission module, configured to sample the first synchronous data and second synchronous data based on the reset value when a first data frame is transmitted; the second synchronous data is obtained by sampling a data signal by using the sampling clock;

[0024] a second transmission module, configured to determine a sampling object according to a clock source when a second data frame is transmitted, and sample the sampling object based on the counter value.

[0025] Optionally, the device further comprises:

[0026] a first synchronization module, configured to sample the enable flag twice by using the sampling clock, to obtain third synchronous data and the first synchronous data respectively;

[0027] a second synchronization module, configured to sample the data signal twice by using the sampling clock, to obtain fourth synchronous data and the second synchronous data respectively.

[0028] Optionally, when the first data frame is transmitted, if the pulse enable is high, the counter is reset, and the counter value is the reset value; if the pulse enable is low, the counter is incremented by one, and the counter value is the count value.

[0029] Optionally, if the clock source is not provided by a MAC, the second transmission module comprises:

[0030] a reset unit, configured to reset the counter if the pulse enable is high, and the counter value is the reset value;

[0031] a first sampling unit, configured to sample the first synchronous data and the second synchronous data based on the reset value.

[0032] Optionally, if the clock source is provided by the MAC, the second transmission module comprises:

[0033] a second sampling unit, configured to sample the third synchronization data and the fourth synchronization data based on a first count value; the count value comprises the first count value; the first count value is located in a previous period of the reset value;

[0034] Optionally, the apparatus further comprises:

[0035] a third sampling unit, configured to sample the enable flag and the data signal based on a second count value; the count value comprises the second count value; the second count value is located in a previous period of the first count value.

[0036] The application provides a data receiving method based on a PHY chip. In the execution of the method, first synchronization data is sampled by using a sampling clock, so that a pulse enable is generated at a rising edge position of the first synchronization data, wherein the pulse enable is used to determine a counter value of a counter, the counter value is a reset value or a count value, and the first synchronization data is obtained by sampling an enable flag by using the sampling clock. In the transmission of a first data frame, first synchronization data and second synchronization data are sampled according to the reset value, wherein the second synchronization data is obtained by sampling a data signal by using the sampling clock. In the transmission of a second data frame, a sampling object is determined according to a clock source, and the sampling object is sampled based on the counter value. In this way, the counter value of the counter is determined based on the pulse enable generated at the rising edge position of the first synchronization data, and in the transmission of a data frame, the sampling time of data is accurately controlled, that is, the data is sampled at a middle position of the data, so that the data is received at a correct time point, and thus the data receiving effect of the PHY chip is improved. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0038] Figure 1 It is a circuit schematic diagram of an MII interface connecting a MAC layer and a PHY layer;

[0039] Figure 2 It is another circuit schematic diagram of an MII interface connecting a MAC layer and a PHY layer;

[0040] Figure 3 It is a sampling waveform diagram;

[0041] Figure 4 It is a flowchart of a data receiving method based on a PHY chip provided by an embodiment of the present application.

[0042] Figure 5 A schematic diagram of the sampling waveform of a data receiving method based on a PHY chip provided in an embodiment of this application;

[0043] Figure 6 A waveform diagram showing the phase shift of MII_TXENA provided in this application embodiment;

[0044] Figure 7 A schematic diagram of the sampling waveform of another data receiving method based on a PHY chip provided in this application embodiment;

[0045] Figure 8 A schematic diagram of the sampling waveform of another data receiving method based on a PHY chip provided in this application embodiment;

[0046] Figure 9 This is a schematic diagram of a data receiving device based on a PHY chip, provided in an embodiment of this application. Detailed Implementation

[0047] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. This application provides a data receiving method and apparatus based on a PHY chip, relating to the field of data transmission technology. The above are merely examples and do not limit the application field of the method and apparatus provided in this application.

[0048] like Figure 1 As shown, Figure 1 This is a circuit diagram illustrating a MII interface connecting the MAC layer and the PHY layer. The MII interface is a specification that provides a data transmission interface between the MAC (Media Access Control) layer and the PHY (Physical Layer). Signals sent from the MAC to the PHY chip (to perform PHY layer functions) include CLK25, TXENA, TXD[3:0], and MDC; signals sent from the PHY chip to the MAC include TX_CLK, RX_CLK, RXDV, and RXD[3:0]. CLK25 is the main input clock of the PHY chip, TXENA and TXD[3:0] are the enable and data signals sent from the MAC to the PHY chip, respectively, and TX_CLK is the synchronization clock for transmitting the enable and data.

[0049] In existing MII interface schemes, due to the large number of MAC interfaces, the TX_CLK input is typically removed to reduce the number of MAC interfaces, and data synchronization is performed using other methods to prevent sampling errors. The existing solution is:

[0050] 1. The clock CLK25 of the PHY is provided by the MAC, that is, the sampling clock inside the PHY and the sending data of the MAC are guaranteed to be synchronous;

[0051] 2. The phase offset configuration of MII_TXENA and MII_TXD[3:0] is added in the MAC, the phase of MII_TXENA and MII_TXD[3:0] sent by the MAC is modified in units of 10ns, and if the phase of the sampling clock of the PHY and the sending data of the MAC does not meet the requirements, the offset can be modified to meet the synchronous sampling of the PHY.

[0052] The specific circuit connection is shown in Figure 2 , Figure 2 is another circuit schematic diagram of the connection between the MAC layer and the PHY layer.

[0053] The specific process of the prior art is as follows: first, the PCB is completed according to the above scheme, then the TX_CLK output by the PHY is tested, the TX shift of the MAC, that is, the above phase offset, is set according to the actual tested clock phase, to meet the synchronous sampling of the PHY chip to the sending data of the MAC. The sampling waveform is shown in Figure 3 , Figure 3 is a sampling waveform diagram.

[0054] The above technical scheme requires that the clock of the PHY is provided by the MAC, the purpose is to guarantee that the sampling clock is a synchronous clock, then the phase offset is realized in the MAC, to ensure that the PHY can sample the correct data, and therefore has the following disadvantages:

[0055] 1. When the 25M clock of the PHY is provided by other clock sources, that is, the sampling clock frequencies of the MAC and the PHY are the same but the phases are different and uncertain, the above scheme cannot be solved;

[0056] 2. The operation process is too complicated, and the offset time needs to be modified according to the PCB design;

[0057] 3. If the PCB design is modified, the offset time needs to be modified again;

[0058] 4. With the change of temperature or environment, the setting of the TX shift may need to be modified;

[0059] 5. Because the shift is added in the MAC, that is, the TXENA and TXD[3:0] are delayed, the transmission delay of the data frame is increased.

[0060] Therefore, in the prior art, there is a problem of poor data receiving effect of the PHY chip.

[0061] The inventors propose the technical solution of the application through research. First, the first synchronization data is sampled by using a sampling clock, so that a pulse enable is generated at the rising edge position of the first synchronization data, wherein the pulse enable is used to determine a counter value of a counter, the counter value is a reset value or a count value, and the first synchronization data is obtained by sampling an enable flag by using the sampling clock. When the first data frame is transmitted, the first synchronization data and the second synchronization data are sampled according to the reset value, wherein the second synchronization data is obtained by sampling a data signal by using the sampling clock. When the second data frame is transmitted, a sampling object is determined according to a clock source, and the sampling object is sampled based on the counter value. In this way, based on the pulse enable generated at the rising edge position of the first synchronization data, the counter value of the counter is determined, and when the data frame is transmitted, the sampling time of the data is accurately controlled, that is, the data is sampled at the middle position of the data, so that the data is received at the correct time point, and the data receiving effect of the PHY chip is improved.

[0062] As shown in Figure 4 , Figure 4 a flowchart of a data receiving method based on a PHY chip provided by an embodiment of the application, comprising:

[0063] S401: The first synchronization data is sampled by using a sampling clock, so that a pulse enable is generated at the rising edge position of the first synchronization data.

[0064] First, before the implementation in step S401 is performed, the enable flag needs to be sampled twice in succession by using the sampling clock, wherein the third synchronization data is obtained by sampling the first time, and the first synchronization data is obtained by sampling the second time. The data signal is sampled twice in succession by using the sampling clock, wherein the fourth synchronization data is obtained by sampling the first time, and the second synchronization data is obtained by sampling the second time. The third synchronization data is an intermediate product in the process of generating the first synchronization data, and the fourth synchronization data is an intermediate product in the process of generating the second synchronization data.

[0065] Then, the first synchronization data is sampled by using the sampling clock, so that a high-level pulse is generated at the rising edge position (corresponding to the same time) of the first synchronization data, thereby obtaining the pulse enable.

[0066] S402: When the first data frame is transmitted, the first synchronization data and the second synchronization data are sampled according to the reset value.

[0067] First of all, it should be noted that the first data frame and the second data frame are consecutive data frames, that is, the first data frame is the first data frame in the consecutive data frames, the second data frame is the second data frame in the consecutive data frames, and so on, and the third data frame is the third data frame in the consecutive data frames.

[0068] When the first data frame is transmitted, it is needed to determine whether the pulse enable is high first. If the pulse enable is high, the counter is reset, and the counter value of the counter is the reset value. If the pulse enable is low, the counter is added one by one, and the counter value is the count value. When the counter value is the reset value, the first synchronous data and the second synchronous data are sampled by using the sampling clock, so as to complete the reception of the data.

[0069] S403: When the second data frame is transmitted, the sampling object is determined according to the clock source, and the sampling object is sampled based on the counter value.

[0070] Before step S403 is executed, it is needed to determine whether the clock source of the PHY is provided by the MAC.

[0071] If the clock source is not provided by the MAC, when the counter value is the reset value, the first synchronous data and the second synchronous data are sampled, so as to complete the reception of the data. When the third data frame and the data frames after the third data frame are transmitted, the first synchronous data and the second synchronous data are sampled by using the sampling clock when the counter value is the reset value, so as to complete the reception of the data.

[0072] If the clock source is provided by the MAC, when the counter value is the first count value in the period before the reset value, the third synchronous data and the fourth synchronous data are sampled by using the sampling clock, so as to complete the reception of the data. When the third data frame and the data frames after the third data frame are transmitted, the enable flag and the data signal are marked when the counter value is the second count value in the period before the first count value, so as to complete the reception of the data. In this way, the transmission of the subsequent data frames is more stable by reducing the delay through twice sampling in advance. If only once sampling in advance is used, the interval between the two data frames is suddenly reduced by 20 ns, which is easy to affect the subsequent data frames.

[0073] In the embodiment of the application, the first synchronous data is sampled by using the sampling clock first, so that the pulse enable is generated at the rising edge position of the first synchronous data, wherein the pulse enable is used to determine the counter value of the counter, the counter value is the reset value or the count value, and the first synchronous data is obtained by sampling the enable flag by using the sampling clock. When the first data frame is transmitted, the first synchronous data and the second synchronous data are sampled according to the reset value, wherein the second synchronous data is obtained by sampling the data signal by using the sampling clock. When the second data frame is transmitted, the sampling object is determined according to the clock source, and the sampling object is sampled based on the counter value. In this way, based on the pulse enable generated at the rising edge position of the first synchronous data, the counter value of the counter is determined, and when the data frame is transmitted, the sampling time of the data is accurately controlled, that is, the data is sampled at the middle position of the data, so that the data is received at the correct time point, and the data reception effect of the PHY chip is improved.

[0074] The above introduces the data receiving method based on the PHY chip provided by the embodiment of the application, and the method is exemplarily described in combination with a specific application scenario.

[0075] First, the data enable flag MII_TXENA and the data signal MII_TXD[3:0] are synchronized, and the specific steps are as follows: Since the data enable flag MII_TXENA, the data signal MII_TXD[3:0] and the 100M clock inside the chip are non-identical clocks, when sampling the data enable flag MII_TXENA and the data signal MII_TXD[3:0], in order to avoid generating a metastable state, a synchronization operation is needed, and the 100M clock, that is, the sampling clock, is used to sample twice continuously, as shown in Figure 7 . Figure 7 The sampling waveform diagram of another data receiving method based on the PHY chip provided by the embodiment of the application is shown in the figure, and the data enable flag MII_TXENA and the data signal MII_TXD[3:0] are sampled once by using the 100M clock to obtain the third synchronization data TXENA_SYN1 and the fourth synchronization data TXD_SYN1[3:0]. As shown in Figure 5 . Figure 5 The sampling waveform diagram of a data receiving method based on the PHY chip provided by the embodiment of the application is shown in the figure, and the data enable flag MII_TXENA and the data signal MII_TXD[3:0] are sampled twice continuously by using the 100M clock to obtain the first synchronization data TXENA_SYN2 and the second synchronization data TXD_SYN2[3:0].

[0076] MII_TXENA is a data enable flag, and if it is high, it indicates that the data MII_TXD[3:0] is valid, that is, a data frame transmission is performed, and if it is low, it indicates that the data frame transmission is completed, that is, one high level stage of MII_TXENA indicates one data frame transmission stage.

[0077] As shown in Figure 5 , the first synchronization data TXENA_SYN2 is sampled by using the 100M clock inside the PHY chip, and at the rising edge position (corresponding to the same time) of the first synchronization data TXENA_SYN2, that is, at the T3 moment, a high level pulse is generated, so as to obtain the pulse enable, that is, TXENA_POS in Figure 5 .

[0078] The embodiment of the application further comprises a 2-bit counter, the value of the counter is determined according to the frequency / period of the 100M sampling clock inside the PHY chip and the data signal MII_TXD[3:0], since the data signal MII_TXD[3:0] is generated by a 25M clock domain, the period of each data signal is 40ns, and the period of the 100M data sampling clock is 10ns, i.e. the period of each data signal MII_TXD[3:0] is 1 / 4 of the period of the data sampling clock, so the value of the counter can be set to 0, 1, 2 and 3, totally four counter values, and the reset value of the counter is set to 0. As shown in FIG. 4, when the pulse enable is detected as high at T3~T4, the counter is reset at T4~T5, at this time the counter value is the reset value 0; when the pulse enable is detected as low after T4, the counter performs the cycle counting of self-incrementing, at this time the counter value is 1, 2, 3, 0, 1, 2 cycles. Figure 5

[0079] If the clock source of the PHY is not provided by the MAC but a 25M clock provided by other clock sources, i.e. the phase of the data sent by the MAC and the phase of the sampling clock of the PHY exist uncertainty. If the clock source of the PHY is provided by the MAC, i.e. the phase of the data sent by the MAC and the phase of the sampling clock of the PHY exist synchronization. Therefore, it is needed to judge whether the clock source of the PHY chip is provided by the MAC chip.

[0080] If the clock source of the PHY is not provided by the MAC, the following steps are performed:

[0081] When the pulse enable is high, the value of the counter is reset to 0; when the pulse enable is low, the counter performs the cycle counting of self-incrementing; as shown in FIG. 4, when the value of the counter (CNT) is 0 at T4~T5, the first synchronization data TXENA_SYN2 and the second synchronization data TXD_SYN2[3:0] are sampled by using the 100M sampling clock at T5; when the value of the counter is 1 or 2 or 3, the sampling of the first synchronization data TXENA_SYN2 and the second synchronization data TXD_SYN2[3:0] is stopped, and the data remains unchanged. Figure 5 In this case, i.e. the clock source of the PHY is not provided by the MAC, the counter needs to be reset by using the pulse enable TXENA_POS when transmitting each data frame, to ensure the correct sampling of the data, therefore in this application environment, each data frame exists a transmission delay of 20ns, although the transmission delay of 20ns is lost, the data can still be accurately sampled, and the overall data frame transmission is not affected.

[0082]

[0083] ​​It should be noted here that the data signal MII_TXD[3:0] is generated in a 25M clock domain, and the period length of each data is 40ns. For a 100M clock with a period of 10ns, the counter value can be set to 0~3. The reason for setting the reset value to 0 is that the subsequent sampling circuit samples at 0, and at this time, the sampling position is in the middle of the second synchronization data TXD_SYN2[3:0], that is, at this time, the signal is stable, and the sampling result is the most accurate.

[0084] In some cases, if the phase of MII_TXENA is offset, the pulse enable is also offset, thereby automatically modifying the position of subsequent sampling, realizing automatic shift, as shown in Figure 6 Figure 6 The waveform diagram when the phase of MII_TXENA is offset is provided for the embodiment of the application. When the phase of MII_TXENA is offset, the pulse enable is also offset, thereby automatically modifying the position of subsequent sampling, corresponding to Figure 5 and Figure 6 That is, when the phase of MII_TXENA is offset, the corresponding TXENA_SYN2 after synchronization is also offset, the rising edge is changed from T3 time to T6 time, thereby the rising edge of the generated high-level pulse enable is also changed from T3 time to T6 time, and the sampling position is also changed from T5 time to T8 time, realizing automatic shift.

[0085] If the clock source of the PHY is provided by the MAC, the following steps are performed:

[0086] First, it is necessary to determine that the data frame to be received is the nth data frame after power-on, wherein n is a positive integer.

[0087] 1. When n is equal to 1, the specific receiving steps are as follows:

[0088] As shown in Figure 5 When the value of the counter (CNT) is 0 at T4~T5 time, the first synchronization data TXENA_SYN2 and the second synchronization data TXD_SYN2[3:0] are sampled at T5 time; when the value of the counter is 1 or 2 or 3, the sampling of the first synchronization data TXENA_SYN2 and the second synchronization data TXD_SYN2[3:0] is stopped, and the data remains unchanged.

[0089] 2. When n is equal to 2, the specific receiving steps are as follows:

[0090] As shown in Figure 7 ​As shown, when the pulse enable TXENA POS is low, i.e. before T3 moment and after T4 moment, the counter performs a self-increment cycle count, when the pulse enable TXENA POS is high, i.e. T3~T4 moment, no reset is performed, and the counter maintains the synchronous count. When the value of the counter is 3, i.e. the first count value of the previous period, the third synchronous data TXENA SYN1 and the fourth synchronous data TXD SYN1 [3:0] are sampled at T4 moment, i.e. 1 period in advance, and the sampling object is also 1 period in advance, thus the delay is reduced by 10ns, i.e. the delay is 10ns; when the value of the counter is 0 or 1 or 2, the sampling of the third synchronous data TXENA SYN1 and the fourth synchronous data TXD SYN1 [3:0] is stopped, and the data remains unchanged.

[0091] 3. When n is greater than or equal to 3, the specific receiving steps are as follows:

[0092] As shown in the figure, Figure 8 As shown in the figure, Figure 8 The figure is a waveform diagram of sampling of another data receiving method based on a PHY chip provided by the embodiment. When the pulse enable TXENA POS is low, i.e. before T3 moment and after T4 moment, the counter performs a self-increment cycle count, when the pulse enable TXENA POS is high, i.e. T3~T4 moment, no reset is performed, and the counter maintains the synchronous count. When the value of the counter is 2, i.e. the second count value of the previous period, the data enable marker MII_TXENA and the data signal MII_TXD [3:0] are sampled at T3 moment, i.e. 1 period in advance, and the sampling object is also 1 period in advance, thus the delay is reduced by 10ns again, i.e. the delay is 0ns. When the value of the counter is 0 or 1 or 3, the sampling of the data enable marker MII_TXENA and the data signal MII_TXD [3:0] is stopped, and the data remains unchanged.

[0093] In this case, i.e. the clock source of the PHY is provided by the MAC, the phase of the data sent by the MAC is synchronous with the phase of the sampling clock of the PHY, and the synchronization operation is only performed when the first data frame is transmitted, i.e. the counter is reset by using the pulse enable TXENA POS, and the synchronization can be maintained in the subsequent data frames, at this time, the subsequent sampling moment can also be modified to reduce the transmission delay of the subsequent data frames and improve the data transmission efficiency, meanwhile, the sampling moment can be automatically adjusted with the offset of MII_TXENA, automatic shift is realized, and thus the data receiving accuracy is improved.

[0094] In the field of industrial Ethernet, in order to reduce the port usage, the TX CLK port is removed, which causes the problem of synchronous sampling of MAC to PHY data transmission, the present application solves many problems existing in the prior art, and widens the applicability, at the same time, the clock source of the PHY is not provided by the MAC and the case of being provided by the MAC is taken into account, the accurate sampling of the data sent by the PHY to the MAC is ensured, the complete application process is simplified, and the complexity of the chip application is reduced.

[0095] The above is some specific implementation manners of the data receiving method based on the PHY chip provided by the embodiment of the present application, based on which, the present application further provides a corresponding device. The device provided by the embodiment of the present application will be introduced from the perspective of functional modularization.

[0096] As shown in Figure 9 , Figure 9 The structure diagram of the data receiving device based on the PHY chip provided by the embodiment of the present application is shown in the figure, the data receiving device 900 based on the PHY chip comprises:

[0097] The pulse enable generation module 910 is configured to sample the first synchronous data by using the sampling clock, so as to generate a pulse enable at the rising edge position of the first synchronous data; the pulse enable is used to determine the counter value of the counter; the counter value is a reset value or a count value; the first synchronous data is obtained by sampling the enable flag by using the sampling clock;

[0098] The first transmission module 920 is configured to sample the first synchronous data and the second synchronous data according to the reset value when transmitting the first data frame; the second synchronous data is obtained by sampling the data signal by using the sampling clock;

[0099] The second transmission module 930 is configured to determine the sampling object according to the clock source when transmitting the second data frame, and sample the sampling object based on the counter value.

[0100] Optionally, the device 900 further comprises:

[0101] The first synchronization module is configured to sample the enable flag twice by using the sampling clock, and obtain the third synchronous data and the first synchronous data respectively;

[0102] The second synchronization module is configured to sample the data signal twice by using the sampling clock, and obtain the fourth synchronous data and the second synchronous data respectively.

[0103] Optionally, when transmitting the first data frame, if the pulse enable is high, resetting the counter, the counter value being the reset value; if the pulse enable is low, the counter value is the count value.

[0104] Optionally, if the clock source is not provided by the MAC, the second transmission module 930 comprises:

[0105] a resetting unit, configured to reset the counter if the pulse enable is high, the counter value being the reset value;

[0106] a first sampling unit, configured to sample the first synchronous data and the second synchronous data based on the reset value.

[0107] Optionally, if the clock source is provided by the MAC, the second transmission module 930 comprises:

[0108] a second sampling unit, configured to sample the third synchronous data and the fourth synchronous data based on a first count value; the count value comprising the first count value; the first count value being in a previous period of the reset value.

[0109] Optionally, the apparatus 900 further comprises:

[0110] a third sampling unit, configured to sample the enable flag and the data signal based on a second count value; the count value comprising the second count value; the second count value being in a previous period of the first count value.

[0111] It should be noted that, in the present document, the terms such as first and second, etc. are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Also, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, so that a process, method, article, or apparatus that comprises a list of elements does not include only those elements, but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by the statement "comprising a..." does not exclude the existence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0112] It should be further noted that each of the various embodiments described in the specification are described using a progressive format, and the same or similar parts among the various embodiments can be mutually referred to, and each of the embodiments focuses on the differences from other embodiments. In particular, for the device and apparatus embodiments, since they are basically similar to the method embodiments, they are described more simply, and the relevant parts can be referred to the part of the description of the method embodiments. The apparatus embodiments described above are merely illustrative, and the units described as separate components can or can not be physically separated, and the components indicated as units can or can not be physical units, i.e., they can be located in one place, or distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiments according to the actual needs. Those skilled in the art can understand and implement it without creative labor.

[0113] The above describes only one specific implementation of the present application, but the protection scope of the present application is not limited to this. Any skilled person in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A data receiving method based on a PHY chip, characterized in that, include: The enable flag is sampled twice consecutively using a sampling clock to obtain the third synchronization data and the first synchronization data, respectively. The data signal is sampled twice consecutively using the sampling clock to obtain the fourth synchronization data and the second synchronization data, respectively. The first synchronization data is sampled using the sampling clock, so that a pulse enable is generated at the rising edge of the first synchronization data. The pulse enable is used to determine the counter value of the counter; The counter value is either a reset value or a count value; When receiving the first data frame, the first synchronization data and the second synchronization data are sampled according to the reset value; When receiving the second data frame, if the clock source is not provided by the MAC, then the first synchronization data and the second synchronization data are determined to be the sampling objects; If the clock source is provided by the MAC, then the third synchronization data and the fourth synchronization data are determined to be the sampling objects; The sampling object is sampled based on the counter value.

2. The method according to claim 1, characterized in that, When receiving the first data frame, if the pulse enable is high, the counter is reset and the counter value is the reset value; if the pulse enable is low, the counter increments by one cycle and the counter value is the count value.

3. The method according to claim 2, characterized in that, If the clock source is not provided by the MAC, the sampling of the sampling object based on the counter value includes: If the pulse enable is at the high level, the counter is reset, and the counter value is the reset value; The first synchronization data and the second synchronization data are sampled based on the reset value.

4. The method according to claim 2, characterized in that, If the clock source is provided by a MAC, the sampling of the sampling object based on the counter value includes: The third and fourth synchronization data are sampled based on a first count value; the count value includes the first count value; the first count value is located in the previous cycle of the reset value.

5. The method according to claim 4, characterized in that, After sampling the sampled object based on the counter value, the method further includes: The enable flag and the data signal are sampled based on a second count value; the count value includes the second count value; the second count value is located in the previous cycle of the first count value.

6. A data receiving device based on a PHY chip, characterized in that, include: The first synchronization module is used to sample the enable flag twice consecutively using the sampling clock to obtain the third synchronization data and the first synchronization data respectively. The second synchronization module is used to continuously sample the data signal twice using the sampling clock to obtain the fourth synchronization data and the second synchronization data respectively. A pulse enable generation module is used to sample the first synchronization data using the sampling clock, so that a pulse enable is generated at the rising edge of the first synchronization data. The pulse enable is used to determine the counter value of the counter; The counter value is either a reset value or a count value; The first transmission module is configured to sample the first synchronization data and the second synchronization data according to the reset value when receiving the first data frame; The second transmission module is used to determine the first synchronization data and the second synchronization data as sampling objects if the clock source is not provided by the MAC when receiving the second data frame. If the clock source is provided by the MAC, then the third synchronization data and the fourth synchronization data are determined to be the sampling objects; The sampling object is sampled based on the counter value.

7. The apparatus according to claim 6, characterized in that, When receiving the first data frame, if the pulse enable is high, the counter is reset and the counter value is the reset value; if the pulse enable is low, the counter increments by one cycle and the counter value is the count value.

8. The apparatus according to claim 7, characterized in that, If the clock source is not provided by the MAC, the second transmission module includes: A reset unit is configured to reset the counter if the pulse enable is high, wherein the counter value is the reset value. The first sampling unit is used to sample the first synchronization data and the second synchronization data based on the reset value.

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