Real-time Ethernet communication card implementation method based on advanced physical layer technology

Abstract

The invention relates to a real-time Ethernet communication card implementation method based on an advanced physical layer technology. A core control processing unit, a serial interface 1, a serial interface 2, a CAN (Controller Area Network) interface, a standard Ethernet interface, a real-time Ethernet interface 1, a real-time Ethernet interface 2, a high-precision clock external interface, an EEPROM (Electrically Erasable Programmable Read-Only Memory) external storage interface and a PCIE (Peripheral Component Interconnect Express) backboard bus interface are included; the core control processing unit is used for realizing clock synchronization with main clock equipment in a system control network and protocol conversion and data transmission among PCIE (Peripheral Component Interface Express) backboard data, CAN (Controller Area Network) sensor data, serial port sensor data and real-time Ethernet data; the clock synchronization method adopts a gPTP point-to-point high-precision clock synchronization method, and two paths of real-time Ethernet interfaces adopt two-wire Ethernet interfaces based on an advanced physical layer technology, so that the networking cost of the system is effectively reduced, and the reliability of data transmission is ensured. The real-time Ethernet communication card designed by the method has the advantages of high real-time performance, high bandwidth and high reliability.

Description

Technical Field

[0001] The invention belongs to the field of industrial control communication, and in particular relates to a design method of a real-time Ethernet communication card based on advanced physical layer technology. Background Art

[0002] With the rapid development of industrial automation and intelligent manufacturing, intelligent industrial production has increasingly higher requirements for communication technology. Traditional data communications face the following major problems:

[0003] First, in intelligent industrial production, such as robot control and automated production lines, precise real-time data transmission is required to ensure the synchronization and coordinated operation of equipment. Traditional communication cards (such as Modbus and serial communication) mostly use NTP clock synchronization, which has low clock synchronization accuracy. In addition, the local clock accuracy of traditional communication cards is low, and the clock deviation between communication cards is large, which cannot meet the needs of high-frequency real-time data transmission.

[0004] Secondly, in modern industrial production, the amount of data generated by various new types of equipment, including high-definition video surveillance and multimodal sensors, is growing exponentially. The data bandwidth of the original communication card can no longer support the real-time transmission of large amounts of data.

[0005] Furthermore, with the continuous expansion of intelligent industrial production, devices supporting multiple industrial standard protocols (such as EtherNet / IP, Modbus-TCP, and OPC UA) exist within the same control network. This leads to poor communication between devices within the control network, easily forming information silos and hindering the unified management of intelligent industrial production automation systems. While traditional communication cards have been developed to support conversion between multiple industrial standard protocols, these conversions have significant delays and limitations, making it impossible to achieve seamless, real-time data communication between various types of industrial equipment.

[0006] Finally, with the rise of artificial intelligence technology, industrial control systems have put forward intelligent requirements for communication cards, such as supporting remote monitoring of equipment, predictive maintenance, and intelligent decision-making. However, traditional communication cards lack support for industrial Internet of Things and big data analysis and cannot meet the above intelligent needs. Summary of the Invention

[0007] In response to the above-mentioned deficiencies in the prior art, the present invention aims to provide a real-time Ethernet communication card design method based on advanced physical layer technology, which is mainly used to design and implement a real-time Ethernet communication card with high real-time performance, high bandwidth, and high reliability. The method first introduces and implements a high-precision clock synchronization mechanism and a real-time Ethernet protocol to ensure the real-time performance of data communication of the real-time Ethernet communication card designed and implemented by the method; then, the data communication bandwidth of the industrial network communication card is expanded by replacing the traditional communication technologies such as CAN and RS-485 with advanced physical layer Ethernet technology; finally, a redundant data communication mechanism is designed and implemented according to the 802.1CB protocol in the TSN real-time Ethernet protocol group, thereby improving the reliability of data communication of the real-time Ethernet communication card designed and implemented by the method.

[0008] The technical solution adopted by the present invention to achieve the above-mentioned purpose is: a real-time Ethernet communication card based on advanced physical layer technology, comprising: a core control processing unit equipped with a PCIE backplane bus interface, a CAN interface, a serial interface, a standard Ethernet interface, a real-time Ethernet interface 1, and a real-time Ethernet interface 2; the core control processing unit is connected to a crystal oscillator circuit; the core control processing unit is used to:

[0009] Receive the time signal from the master clock device in the system control network through the standard Ethernet interface, and adjust the local clock according to the time signal from the master clock device to achieve clock synchronization with the master clock device in the system control network;

[0010] It communicates with the system mainboard through the PCIE backplane bus interface, receives control instructions sent by the system mainboard, collects field sensor data obtained through the CAN interface and serial interface according to the control instructions, and organizes the sensor collected data into real-time Ethernet data frames according to the TSN real-time Ethernet protocol, and sends them to the system control network through real-time Ethernet interface 1 and real-time Ethernet interface 2, as well as receives real-time Ethernet data frames from the system control network and extracts data messages.

[0011] The real-time Ethernet interface 1 and the real-time Ethernet interface 2 use a two-wire Ethernet interface based on an advanced physical layer for data transmission.

[0012] The real-time Ethernet interface 1 and the real-time Ethernet interface 2 serve as redundancy backup for each other, and the real-time Ethernet interface 1 and the real-time Ethernet interface 2 are respectively connected to a redundant sub-network in the system control network.

[0013] The core control processing unit is used to copy the real-time Ethernet data frame to be sent into two real-time Ethernet redundant data frames according to the TSN real-time Ethernet protocol, and send them to their respective redundant subnetworks through real-time Ethernet interface 1 and real-time Ethernet interface 2 respectively; when the real-time Ethernet redundant data frames are received through real-time Ethernet interface 1 and real-time Ethernet interface 2, the first received real-time Ethernet redundant data frame is retained and the duplicate real-time Ethernet redundant data frames are discarded.

[0014] The clock circuit uses a digital-to-analog converter, a negative feedback regulation amplifier circuit, and a constant temperature crystal oscillator chip:

[0015] The digital signal input terminal DIN of the digital-to-analog converter is connected to the clock offset data output from the clock external interface DATA terminal of the core control processing unit, the clock terminal CLK is connected to the clock frequency signal output from the CLK terminal of the core control processing unit, and the synchronization signal terminal SYNC is connected to the control signal from the level trigger control terminal SYNC of the core control unit; the voltage output terminal is connected to the input terminal of the negative feedback regulation amplifier circuit through the resistor R12; the output terminal of the negative feedback regulation amplifier circuit is connected to the voltage signal control terminal VCTL of the constant temperature crystal oscillator chip, and the output terminal of the constant temperature crystal oscillator chip is connected to the system clock frequency signal output terminal OUT serving as the output frequency port of the real-time Ethernet communication card;

[0016] The negative feedback regulation amplifier circuit includes: resistors R13, R14 and an operational amplifier; the positive input end of the operational amplifier serves as the input end of the negative feedback regulation amplifier circuit and is grounded through a capacitor C25; the negative input end of the operational amplifier is connected to the output end of the operational amplifier through the resistor R14 and is also grounded through the resistor R13, and the output end of the operational amplifier serves as the output end of the negative feedback regulation amplifier circuit.

[0017] A method for implementing a real-time Ethernet communication card based on advanced physical layer technology comprises the following steps:

[0018] The core control processing unit receives the time signal from the master clock device in the system control network through the Ethernet interface, and adjusts the local clock according to the time signal from the master clock device to achieve clock synchronization with the master clock device in the system control network;

[0019] It communicates with the system mainboard through the PCIE backplane bus interface, receives control instructions sent by the system mainboard, collects field sensor data obtained through the CAN interface and serial interface according to the control instructions, and organizes the sensor collected data into real-time Ethernet data frames according to the TSN real-time Ethernet protocol, and sends them to the system control network through real-time Ethernet interface 1 and real-time Ethernet interface 2, receives real-time Ethernet data frames from the system control network and extracts data messages.

[0020] The core control processing unit copies the real-time Ethernet data frame to be sent into two real-time Ethernet redundant data frames according to the TSN real-time Ethernet protocol, and sends them to their respective redundant sub-networks through real-time Ethernet interface 1 and real-time Ethernet interface 2 respectively; when the real-time Ethernet redundant data frames are received through real-time Ethernet interface 1 and real-time Ethernet interface 2, the first received real-time Ethernet redundant data frame is retained and the duplicate real-time Ethernet redundant data frames are discarded.

[0021] The clock circuit works as follows:

[0022] The output voltage of the digital-to-analog converter is input to the positive input terminal of the operational amplifier, and high-frequency noise interference in the output voltage of the digital-to-analog converter is filtered out through a low-pass filter composed of resistor R12 and capacitor C25. The output voltage of the digital-to-analog converter is amplified from 0-3.3V to 0-5V by a negative feedback regulation amplifier circuit composed of resistors R13 and R14 and the operational amplifier, and high-frequency noise interference in the operating voltage of the operational amplifier is filtered out through capacitor C26. The operational amplifier inputs the amplified regulation voltage to the voltage signal control terminal VCTL of the constant temperature crystal oscillator for clock adjustment, and high-frequency noise interference and low-frequency noise interference in the operating voltage of the crystal oscillator are filtered out through capacitors C27 and C28.

[0023] The method of adjusting the local clock according to the timing time of the master clock device to achieve clock synchronization with the master clock device in the system control network adopts a constant temperature crystal oscillator adjustment method, including the following steps:

[0024] Clock phase adjustment: When the calculated clock deviation between the core control processing unit and the master clock device in the control network is greater than s seconds, the digital value of the clock deviation is directly input into the clock circuit's digital-to-analog converter through the core control processing unit's clock external interface DATA. After being converted into a voltage signal, it is input into the voltage signal control terminal VCTL of the oven-controlled crystal oscillator to adjust the crystal oscillator's clock phase, thereby achieving clock adjustment.

[0025] Clock frequency adjustment: When the clock deviation is less than or equal to s seconds, the calculated clock deviation between the core control processing unit and the master clock device in the control network is converted into a frequency difference, and the clock frequency of the crystal oscillator is adjusted to achieve clock synchronization.

[0026] The present invention has the following beneficial effects and advantages:

[0027] 1. High real-time performance. The method of the present invention uses the gPTP point-to-point clock synchronization method specified in the 802.1AS protocol to ensure that the real-time Ethernet communication card designed and implemented by this method is based on the same clock reference as the devices in the system control network. Data transmission on the real-time Ethernet interface is scheduled according to the TSN real-time Ethernet protocol, reducing the delay and jitter of data transmitted by the real-time Ethernet interface. Furthermore, the high-precision crystal oscillator adjustment circuit designed by the method of the present invention uses a high-precision operational amplifier to form a negative feedback amplifier circuit to perform secondary amplification of the adjustment voltage, thereby improving the adjustment accuracy of the high-precision crystal oscillator and ultimately enhancing the real-time performance of data transmission on the industrial network communication card designed and implemented by this method.

[0028] 2. High bandwidth. This method replaces the CAN and RS-485 communication technologies used in traditional industrial network communication cards with advanced physical layer Ethernet communication technology. Compared to the maximum transmission rate of 10Mbps for CAN and RS-485 communication technologies, advanced physical layer Ethernet communication technology can achieve a stable transmission rate of 100Mbps over the same transmission distance, effectively increasing the data transmission bandwidth of the real-time Ethernet communication card designed and implemented by this method.

[0029] 3. High reliability. This method introduces a data redundancy management mechanism. The core control processing unit copies the real-time Ethernet data frame to be sent into two identical real-time Ethernet redundant data frames. These frames are then sent to their respective redundant sub-networks via real-time Ethernet interface 1 and real-time Ethernet interface 2. This ensures that if a real-time Ethernet interface or redundant control network fails, the real-time Ethernet data can still be sent to the destination node via the other real-time Ethernet interface, thereby improving the reliability of data transmission for the industrial network communication card designed and implemented by this method.

[0030] 4. Support for multiple industrial communication protocols. In the method of the present invention, the physical layer of the designed real-time Ethernet communication card is based on advanced physical layer Ethernet communication technology, and the data link layer is designed using TSN real-time Ethernet protocol technology. These two technologies make the designed real-time Ethernet communication card fully compatible with multiple existing industrial communication protocols including EtherNet / IP and PROFINET. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a simplified structural diagram of a real-time Ethernet communication card based on advanced physical layer technology in the method of the present invention;

[0032] Figure 2 This is a flow chart of the gPTP point-to-point clock synchronization method in an implementation example of the method of the present invention;

[0033] Figure 3This is a schematic diagram of a high-precision crystal oscillator circuit for a real-time Ethernet communication card in an implementation example of the method of the present invention;

[0034] Figure 4 It is a schematic diagram of a redundancy mechanism implemented by a real-time Ethernet communication card based on the 802.1CB protocol in an implementation example of the method of the present invention. DETAILED DESCRIPTION

[0035] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0036] A method for designing a real-time Ethernet communication card based on advanced physical layer technology. The real-time Ethernet communication card based on advanced physical layer technology includes a core control processing unit, a serial interface 1, a serial interface 2, a CAN interface, a standard Ethernet interface, a real-time Ethernet interface 1, a real-time Ethernet interface 2, a high-precision clock external interface, an EEPROM external storage interface, and a PCIE backplane bus interface.

[0037] The core control processing unit is mainly responsible for realizing the following two functions: first, receiving the timing of the master clock device in the system control network through the standard Ethernet interface, and adjusting the local high-precision clock according to the timing of the master clock device to achieve high-precision clock synchronization with the master clock device in the system control network.

[0038] Then it communicates with the system mainboard through the PCIE backplane bus interface, receives the control instructions sent by the system mainboard, collects data from the field sensors connected through the CAN interface and serial interface 2 according to the control instructions, and organizes the sensor collected data into real-time Ethernet data frames according to the TSN real-time Ethernet protocol, and sends them to the system control network through real-time Ethernet interface 1 and real-time Ethernet interface 2.

[0039] The serial interface 1 is responsible for outputting the operating status of the real-time Ethernet communication card based on advanced physical layer technology according to the serial communication protocol. The monitoring computer also performs basic configuration of the real-time Ethernet communication card based on advanced physical layer technology through the serial interface 1.

[0040] The serial interface 2 is responsible for connecting to sensors on site that output signals using a serial communication protocol.

[0041] The CAN interface is responsible for connecting to sensors that use the CAN communication protocol to output signals on site. The CAN interface supports communicating with up to two sensors that use the CAN communication protocol to output signals at the same time.

[0042] The standard Ethernet interface is responsible for receiving the time service time of the master clock device in the system and performing message exchange of clock synchronization messages with the master clock device.

[0043] The real-time Ethernet interface 1 and the real-time Ethernet interface 2 are responsible for sending the real-time Ethernet data frames formed by the core control processing unit to the system control network, and receiving the real-time Ethernet data frames from the system control network and extracting the data packets to transmit to the core processing unit.

[0044] The high-precision clock external interface is responsible for connecting to an external high-precision crystal oscillator to provide system time for a real-time Ethernet communication card based on advanced physical layer technology.

[0045] The EEPROM external storage interface is responsible for connecting to the EEPROM storage chip, storing the real-time operating system boot program and image running by the core control processing unit and basic configuration status information of the real-time Ethernet communication card based on advanced physical layer technology.

[0046] The PCIE backplane bus interface is responsible for data communication between the core control processing unit and the system mainboard.

[0047] The core control processing unit is designed with an ARM architecture processor as the core, and the specific ARM processor chip model is LS2K1000-I. The real-time operating system running on the core control processing unit is the Yihui embedded real-time operating system.

[0048] The core control processing unit performs clock synchronization with the master clock device in the system control network through a standard Ethernet interface, specifically according to the gPTP point-to-point clock synchronization method specified in the 802.1AS protocol in the TSN real-time Ethernet protocol group, and the standard Ethernet interface supports the hardware timestamp function.

[0049] The real-time Ethernet interface 1 and the real-time Ethernet interface 2 use a two-wire Ethernet interface based on advanced physical layer technology for data transmission. Compared with the standard Ethernet which requires two pairs of data signal lines for data transmission, the two-wire to Ethernet uses a single twisted pair for data transmission.

[0050] The real-time Ethernet interface 1 and the real-time Ethernet interface 2 serve as redundant backups for each other. The real-time Ethernet interface 1 and the real-time Ethernet interface 2 are respectively connected to redundant sub-networks in the system control network. The core control processing unit copies the real-time Ethernet data frame to be sent into two real-time Ethernet redundant data frames according to the 802.1CB protocol in the TSN real-time Ethernet protocol group, and then sends them to their respective redundant sub-networks through the real-time Ethernet interface 1 and the real-time Ethernet interface 2 respectively. When processing the real-time Ethernet redundant data frames received through the real-time Ethernet interface 1 and the real-time Ethernet interface 2, the core control processing unit retains the first received real-time Ethernet redundant data frame according to the 802.1CB protocol and discards the duplicate real-time Ethernet redundant data frames.

[0051] The PCIE backplane bus interface is 2 PCIE × 4 interfaces, the transmission rate is PCIE2.0, that is, the maximum bandwidth is 16GB / S, and the PCIE backplane bus interface can be modified according to the system motherboard slot type by modifying the PCIE backplane bus interface software driver, while ensuring that the transmission rate remains unchanged. × 4 interfaces can be adjusted to 2 PCIE × 2 interfaces or 4 PCIE × 1 interface.

[0052] The specific model of the high-precision crystal oscillator connected to the high-precision clock external interface is OC5SC36AWO high-precision constant-temperature crystal oscillator, the crystal oscillator output frequency is 10MHz, and in the absence of a master clock device for timing synchronization, the high-precision constant-temperature crystal oscillator has a clock offset of less than 55us per hour.

[0053] The specific model of the EEPROM memory chip connected to the EEPROM external storage interface is C2688466. The EEPROM memory chip stores the Yihui embedded real-time operating system image and boot program run by the core control processing unit, as well as the status information of the real-time Ethernet communication card based on advanced physical layer technology when it works abnormally, in the form of logs.

[0054] Figure 1 This is a specific implementation example of the method of the present invention. A simplified structural diagram of a real-time Ethernet communication card based on advanced physical layer technology: The real-time Ethernet communication card based on advanced physical layer technology includes: a core control processing unit, serial interface 1, serial interface 2, a CAN interface, a standard Ethernet interface, a real-time Ethernet interface 1, a real-time Ethernet interface 2, a high-precision clock external interface, an EEPROM external storage interface, and a PCIE backplane bus interface.

[0055] The core control processing unit selects the domestic ARM architecture processor Loongson LS2K1000-I as the core. The LS2K1000 chip integrates two 64-bit LA264 processor cores with a main frequency of up to 1GHz, which can meet the processor computing power requirements of the complex computing tasks of the real-time Ethernet communication card designed by this method. In addition, the LS2K1000-I provides a variety of peripheral interfaces including standard Ethernet, CAN interface, RS485 / RS422, PCIE, etc., which can realize the interconnection between the real-time Ethernet communication card designed by this method and various types of external devices. The LS2K1000-I processor can still work stably and reliably in a wide temperature range (-40℃~85℃) and complex electromagnetic environment, meeting the processor reliability requirements of the real-time Ethernet communication card designed by this method. The core control processing unit LS2K1000-I processor is equipped with the Yihui real-time operating system. The Yihui real-time operating system uses a hard real-time kernel and supports priority-based preemptive task scheduling to ensure that the system can maintain efficient real-time response under high load. It meets the requirements of this method for designing and implementing real-time Ethernet communication cards for low latency determinism in real-time communication. In addition, the Yihui real-time operating system supports the LoongArch architecture used by the core control processing unit LS2K1000-I, and is highly compatible with the LS2K1000-I processor.

[0056] The standard Ethernet interface uses the Ethernet physical layer (PHY) chip RTL8211E as the core. The core control processing unit LS2K1000-I processor is connected to the standard Ethernet interface through the GMAC1 interface and then synchronizes with the master clock device in the system control network according to the gPTP point-to-point clock synchronization method specified in the 802.1AS protocol in the TSN real-time Ethernet protocol group. The specific clock synchronization process is as follows: Figure 2 As shown:

[0057] First, the core control processing unit of the real-time Ethernet communication card sends the Pdelay_req message to the master clock device in the system control network through the standard Ethernet interface. The core control processing unit records and stores the time t1 when the Pdelay_req message leaves the standard Ethernet interface. After the master clock device receives the Pdelay_req message through the system control network, it records and stores the time t2 when the Pdelay_req message is received. Then the master clock device sends the Pdelay_resp message containing the time t2 when the Pdelay_req message is received to the real-time Ethernet communication card through the system control network. After sending the Pdelay_resp message, the master clock stores the sending time t3 of the Pdelay_resp message in the Pdelay_resp_follow_up message and sends it to the real-time Ethernet communication card through the system control network; after receiving the Pdelay_resp message, the standard Ethernet interface of the real-time Ethernet communication card uses the standard Ethernet interface hardware timestamp function to record and store the receiving time t4 of the Pdelay_resp message, and finally reads the sending time t3 of the Pdelay_resp message in the received Pdelay_resp_follow_up message. Figure 4 The formula shown calculates the clock offset and network delay between the real-time Ethernet communication card and the master clock device in the system control network. The core control processing unit then adjusts the high-precision crystal oscillator connected to the high-precision clock external interface based on the clock offset, ensuring that the real-time Ethernet communication card and the master clock device in the system control network are on the same clock reference.

[0058] The real-time Ethernet communication card PCIE backplane bus interface uses 2 PCIEs in the LS2K1000-I processor × 4 interfaces PCIE0 and PCIE1, the transmission rate is PCIE2.0, that is, the maximum bandwidth is 16GB / S. The PCIE backplane bus interface can be modified according to the system motherboard slot type by modifying the PCIE backplane bus interface software driver. Under the condition of ensuring the unchanged transmission rate, each PCIE × 4 interfaces can be adjusted to 2 PCIE × 2 interfaces or 4 PCIE × 1 interface.

[0059] The CAN interface part is based on the CAN transceiver chip SN65HVD232D. The core control processing unit realizes data acquisition with the sensors that support the CAN communication protocol at the control site through the pins LS2K_CAN0_TX, LS2K_CAN0_RX, LS2K_CAN1_TX, and LS2K_CAN1_RX.

[0060] There are two main types of serial interfaces: Serial Interface 2, which communicates data with on-site sensors that support the serial communication protocol; and Serial Interface 1, which outputs the operating status of the real-time Ethernet communication card according to the serial communication protocol and configures basic information about the real-time Ethernet communication card. Serial Interface 2 is designed and implemented around the RS-232 transceiver chip SP3232ECY-L. The UART0_TXD and UART0_RXD pins of the core control processing unit are connected to the RS-232 transceiver chip SP3232ECY-L for data communication. The serial interface of the RS-232 transceiver chip SP3232ECY-L uses a DB9 serial connector package. On-site sensors that support the serial communication protocol are physically connected to Serial Interface 2 via a DB9 serial communication cable. Serial interface 1 is designed and implemented with the USB-to-serial port chip CH430G as the main chip. The core control processing unit outputs the configuration information of the core processor to the USB-to-serial port chip CH430G through the CPU_UART_RXD and CPU_UART_TXD pins, and then transmits it to the monitoring computer through the USB transmission line. At the same time, the monitoring computer can configure the real-time Ethernet communication card through the USB transmission line.

[0061] The specific model of the EEPROM memory chip connected to the EEPROM external storage interface is C2688466. This chip uses the IIC communication interface for data communication. Therefore, the core control processing unit of the real-time Ethernet communication card communicates data with the EEPROM memory chip C2688466 through the IIC communication interface pins LS2K_I2C0_SCL and LS2K_I2C0_SDA. The EEPROM memory chip C2688466 is mainly responsible for storing the Yihui embedded real-time operating system image and boot program run by the core control processing unit, as well as storing the status information of the real-time Ethernet communication card based on advanced physical layer technology when it works abnormally in the form of logs, which can provide effective data support for the maintenance and status analysis of the subsequent real-time Ethernet communication card during use.

[0062] Figure 3This is the schematic diagram of the high-precision crystal oscillator circuit in this implementation example. The specific model of the high-precision crystal oscillator connected to the high-precision clock external interface is the OC5SC36AWO high-precision constant-temperature crystal oscillator. The crystal oscillator output frequency is 10MHz. In the absence of a master clock device for timing synchronization, the high-precision constant-temperature crystal oscillator has a clock offset of less than 55us per hour. The core control processing unit transmits the calculated clock offset to the high-precision crystal oscillator through the high-precision clock external interface DATA. First, the TPC116S1 digital-to-analog converter converts the calculated clock offset from a digital signal into a voltage signal and outputs it through the VOUT pin. Capacitors C23 and C24 are responsible for The power supply voltage of the TPC116S1 digital-to-analog converter is filtered to ensure that the TPC116S1 digital-to-analog converter works stably and accurately. However, the high-precision constant-temperature crystal oscillator has high requirements on the accuracy of the adjustment voltage. The input range of the adjustment voltage is 0-5V, while the output voltage range of the TPC116S1 digital-to-analog converter is 0-3.3V, and the resolution is low. Therefore, a high-precision zero-drift operational amplifier TP5552 is used to form a negative feedback amplifier circuit to perform secondary amplification on the adjustment voltage output by the TPC116S1 digital-to-analog converter, thereby improving the output range and resolution of the adjustment voltage, thereby improving the adjustment accuracy of the high-precision crystal oscillator.

[0063] The output voltage of the TPC116S1 digital-to-analog converter is input to the positive input terminal of the operational amplifier TP5552. Resistor R12 and capacitor C25 form a low-pass filter to filter out high-frequency noise interference in the output voltage of the TPC116S1 digital-to-analog converter. Resistors R13 and R14 are connected to the negative input and output terminals of the operational amplifier TP5552 to form a negative feedback regulation amplifier circuit, which amplifies the output voltage of the TPC116S1 digital-to-analog converter from 0-3.3V to 0-5V. The function of capacitor C26 is to filter out high-frequency noise interference in the operating voltage of the operational amplifier TP5552, ensuring that the operational amplifier TP5552 is in a stable and accurate operating state.

[0064] The operational amplifier TP5552 inputs the amplified regulated voltage to the VCTL pin of the OC5SC36AWO high-precision oven-controlled crystal oscillator for clock adjustment. The capacitors C27 and C28 are responsible for filtering out high-frequency and low-frequency noise interference in the operating voltage of the high-precision crystal oscillator. The OC5SC36AWO high-precision oven-controlled crystal oscillator adjustment method is mainly divided into the following clock phase adjustment and clock frequency adjustment. Clock phase adjustment is when the calculated clock deviation between the real-time Ethernet communication card core control processing unit and the master clock device in the system control network is greater than 1 second, the digital value of the clock deviation is directly input through the DATA pin into the digital-to-analog converter in the high-precision crystal oscillator circuit, and then converted into a voltage signal, which is then input into the VCTL pin of the OC5SC36AWO high-precision oven-controlled crystal oscillator to adjust the clock phase of the high-precision crystal oscillator, thereby achieving clock adjustment; when the clock deviation is less than 1 second, if the clock phase adjustment is still used, it will cause clock overshoot and it will be impossible to achieve a clock adjustment accuracy of less than 1 second. Therefore, the clock frequency adjustment method is used to adjust the high-precision crystal oscillator. The specific method is to convert the calculated clock deviation between the real-time Ethernet communication card core control processing unit and the master clock device in the system control network into a frequency difference, and gradually achieve clock synchronization by adjusting the clock frequency of the high-precision crystal oscillator. The clock frequency adjustment method achieves high precision.

[0065] However, this method takes a long time to adjust the clock, and cannot quickly adjust clock deviations greater than 1 second. The core control processing unit collects data from field sensors received via the CAN interface and serial communication interface, constructs real-time Ethernet data frames according to the TSN real-time Ethernet protocol, and sends them to the system control network via Real-Time Ethernet Interface 1 and Real-Time Ethernet Interface 2, two-wire Ethernet interfaces based on advanced physical layer technology. Compared to traditional standard Ethernet, the two-wire Ethernet interface based on advanced physical layer technology uses twisted-pair cables for data transmission and supports inline power supply, which can reduce the number of cables required during system control network construction, thereby effectively reducing system networking costs. Figure 4This is a schematic diagram of the redundancy mechanism implemented by the real-time Ethernet communication card based on the 802.1CB protocol. In the diagram, the core control processing unit of each real-time Ethernet communication card copies the real-time Ethernet data frame to be sent into two real-time Ethernet redundant data frames according to the 802.1CB protocol in the TSN real-time Ethernet protocol group, and then sends them to control network A and control network B through real-time Ethernet interface 1 and real-time Ethernet interface 2 respectively. Control network A and control network B are independent of each other and there is no physical connection. The real-time Ethernet interface 1 and real-time Ethernet interface 2 of the real-time Ethernet communication card respectively receive the real-time Ethernet redundant data frames from their respective connected control networks and transmit them to the core control processing unit for processing. The core control processing unit retains the first received real-time Ethernet redundant data frame according to the 802.1CB protocol and discards the duplicate real-time Ethernet redundant data frames.

Claims

1. A real-time Ethernet communication card based on advanced physical layer technology, characterized in that: include: A core control processing unit is provided with a PCIE backplane bus interface, a CAN interface, a serial interface, a standard Ethernet interface, a real-time Ethernet interface 1, and a real-time Ethernet interface 2; the core control processing unit is connected to a crystal oscillator circuit; the core control processing unit is used to: Receive the time signal from the master clock device in the system control network through the standard Ethernet interface, and adjust the local clock according to the time signal from the master clock device to achieve clock synchronization with the master clock device in the system control network; It communicates with the system mainboard through the PCIE backplane bus interface, receives control instructions sent by the system mainboard, collects field sensor data obtained through the CAN interface and serial interface according to the control instructions, and organizes the sensor collected data into real-time Ethernet data frames according to the TSN real-time Ethernet protocol, and sends them to the system control network through real-time Ethernet interface 1 and real-time Ethernet interface 2, as well as receives real-time Ethernet data frames from the system control network and extracts data messages.

2. A real-time Ethernet communication card based on advanced physical layer technology according to claim 1, characterized in that: The real-time Ethernet interface 1 and the real-time Ethernet interface 2 use a two-wire Ethernet interface based on an advanced physical layer for data transmission.

3. A real-time Ethernet communication card based on advanced physical layer technology according to claim 1, characterized in that: The real-time Ethernet interface 1 and the real-time Ethernet interface 2 serve as redundancy backup for each other, and the real-time Ethernet interface 1 and the real-time Ethernet interface 2 are respectively connected to a redundant sub-network in the system control network.

4. A real-time Ethernet communication card based on advanced physical layer technology according to claim 1, characterized in that: The core control processing unit is used to copy the real-time Ethernet data frame to be sent into two real-time Ethernet redundant data frames according to the TSN real-time Ethernet protocol, and send them to their respective redundant subnetworks through real-time Ethernet interface 1 and real-time Ethernet interface 2 respectively; when the real-time Ethernet redundant data frames are received through real-time Ethernet interface 1 and real-time Ethernet interface 2, the first received real-time Ethernet redundant data frame is retained and the duplicate real-time Ethernet redundant data frames are discarded.

5. The real-time Ethernet communication card based on advanced physical layer technology according to claim 1, characterized in that: The clock circuit uses a digital-to-analog converter, a negative feedback regulation amplifier circuit, and a constant temperature crystal oscillator chip: The digital signal input terminal DIN of the digital-to-analog converter is connected to the clock offset data output from the clock external interface DATA terminal of the core control processing unit, the clock terminal CLK is connected to the clock frequency signal output from the CLK terminal of the core control processing unit, and the synchronization signal terminal SYNC is connected to the control signal from the level trigger control terminal SYNC of the core control unit; the voltage output terminal is connected to the input terminal of the negative feedback regulation amplifier circuit through the resistor R12; the output terminal of the negative feedback regulation amplifier circuit is connected to the voltage signal control terminal VCTL of the constant temperature crystal oscillator chip, and the output terminal of the constant temperature crystal oscillator chip is connected to the system clock frequency signal output terminal OUT serving as the output frequency port of the real-time Ethernet communication card; The negative feedback regulation amplifier circuit includes: resistors R13, R14 and an operational amplifier; the positive input end of the operational amplifier serves as the input end of the negative feedback regulation amplifier circuit and is grounded through a capacitor C25; the negative input end of the operational amplifier is connected to the output end of the operational amplifier through the resistor R14 and is also grounded through the resistor R13, and the output end of the operational amplifier serves as the output end of the negative feedback regulation amplifier circuit.

6. A method for implementing a real-time Ethernet communication card based on advanced physical layer technology, characterized in that: The following steps are involved: The core control processing unit receives the time signal from the master clock device in the system control network through the Ethernet interface, and adjusts the local clock according to the time signal from the master clock device to achieve clock synchronization with the master clock device in the system control network; It communicates with the system mainboard through the PCIE backplane bus interface, receives control instructions sent by the system mainboard, collects field sensor data obtained through the CAN interface and serial interface according to the control instructions, and organizes the sensor collected data into real-time Ethernet data frames according to the TSN real-time Ethernet protocol, and sends them to the system control network through real-time Ethernet interface 1 and real-time Ethernet interface 2, receives real-time Ethernet data frames from the system control network and extracts data messages.

7. A method for implementing a real-time Ethernet communication card based on advanced physical layer technology according to claim 6, characterized in that: The core control processing unit copies the real-time Ethernet data frame to be sent into two real-time Ethernet redundant data frames according to the TSN real-time Ethernet protocol, and sends them to their respective redundant sub-networks through real-time Ethernet interface 1 and real-time Ethernet interface 2 respectively; when the real-time Ethernet redundant data frames are received through real-time Ethernet interface 1 and real-time Ethernet interface 2, the first received real-time Ethernet redundant data frame is retained and the duplicate real-time Ethernet redundant data frames are discarded.

8. The method for implementing a real-time Ethernet communication card based on advanced physical layer technology according to claim 6, characterized in that: The clock circuit works as follows: The output voltage of the digital-to-analog converter is input to the positive input terminal of the operational amplifier, and high-frequency noise interference in the output voltage of the digital-to-analog converter is filtered out through a low-pass filter composed of resistor R12 and capacitor C25. The output voltage of the digital-to-analog converter is amplified from 0-3.3V to 0-5V by a negative feedback regulation amplifier circuit composed of resistors R13 and R14 and the operational amplifier, and high-frequency noise interference in the operating voltage of the operational amplifier is filtered out through capacitor C26. The operational amplifier inputs the amplified regulation voltage to the voltage signal control terminal VCTL of the constant temperature crystal oscillator for clock adjustment, and high-frequency noise interference and low-frequency noise interference in the operating voltage of the crystal oscillator are filtered out through capacitors C27 and C28.

9. The method for implementing a real-time Ethernet communication card based on advanced physical layer technology according to claim 6, characterized in that: The method of adjusting the local clock according to the timing time of the master clock device to achieve clock synchronization with the master clock device in the system control network adopts a constant temperature crystal oscillator adjustment method, including the following steps: Clock phase adjustment: When the calculated clock deviation between the core control processing unit and the master clock device in the control network is greater than s seconds, the digital value of the clock deviation is directly input into the clock circuit's digital-to-analog converter through the core control processing unit's clock external interface DATA. After being converted into a voltage signal, it is input into the voltage signal control terminal VCTL of the oven-controlled crystal oscillator to adjust the crystal oscillator's clock phase, thereby achieving clock adjustment. Clock frequency adjustment: When the clock deviation is less than or equal to s seconds, the calculated clock deviation between the core control processing unit and the master clock device in the control network is converted into a frequency difference, and the clock frequency of the crystal oscillator is adjusted to achieve clock synchronization.

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