PCM conversion device supporting multivariate data fusion

Abstract

The invention provides PCM (pulse code modulation) conversion equipment supporting multivariate data fusion, which belongs to the technical field of aircraft data acquisition systems, can reduce the occupied space of an airborne test environment to the greatest extent on the basis of a miniaturized Mini VPX case architecture, and adopts a modularization mode to design a PCM data conversion board card to realize the most important data format conversion function. The ZYNQ-based PCM data conversion board card can work in three working modes and can be compatible with most of data acquisition equipment on a current machine; according to the invention, the respective advantages of the PS end and the PL end of the ZYNQ are fully exerted, and the peripheral connection and the data processing are reasonably designed; the PS end completes Ethernet development, network packet processing, PCM data frame integration and the like, the PL end completes PCM data flow receiving, analysis, extraction and other work, the PS and the PL conduct data communication through an AXI bus, and it is guaranteed that data processing is efficient.

Description

Technical Field

[0001] The present invention belongs to the technical field of aircraft data acquisition systems, and in particular relates to a PCM conversion device supporting multivariate data fusion. Background Art

[0002] In a certain aircraft data acquisition system, a PCM conversion device supporting multi-data fusion serves as a gateway device for the onboard test system. It connects the data acquisition chassis and the telemetry transmission system. It selects or integrates the data streams from the data acquisition system to generate a PCM data stream that supports the telemetry transmission device. To improve the adaptability of PCM data streams in scenarios with diverse data sources, PCM conversion devices supporting multi-data fusion are a hot topic for research.

[0003] Since there are many types of data that need to be converted into data formats on the current aircraft, such as PCM data packets, IPv4 packets, TCP data packets, UDP data packets, etc., and each has a customized format at the application layer, traditional PCM telemetry gateway devices only support input processing of synchronous parameter stream data formats and cannot achieve compatibility with multiple asynchronous data types. Summary of the Invention

[0004] Therefore, the present invention proposes a PCM conversion device that supports multi-data fusion. In order to take into account the needs of miniaturization and versatility at the same time, the device is designed based on the MiniVPX chassis architecture and adopts a modular design of the ZYNQ-based PCM data conversion board. It has the characteristics of convenient configuration, strong compatibility, and low data conversion delay, and is therefore very suitable for current airborne test applications.

[0005] The present invention is implemented by the following technical solutions: PCM conversion equipment supporting multivariate data fusion:

[0006] The PCM conversion device is based on the MiniVPX chassis and includes a PCM data conversion board, a main control board, a power supply board and a chassis backplane connector;

[0007] The chassis backplane connector includes P0, P1, and P2 connectors, wherein the P0 connector is connected to the power board, and the P1 and P2 connectors are used to realize data PCIe connection;

[0008] The PCM data conversion board integrates a ZYNQ chip, receives configuration parameters issued by the main control board, receives multiple PCM data streams and network data packets, performs format conversion on the PCM data and network data according to the configuration parameters, generates a target PCM data stream, and transmits the target PCM data stream and device status data back to the main control board through the PCIe interface;

[0009] The main control board establishes a PCIe communication link with the PCM data conversion board through the P1 and P2 connectors of the chassis backplane connector, which is used to send configuration data and return monitoring data.

[0010] Furthermore, the PCM data conversion board includes a board control module, a communication interface module, a PCIe data transmission module, a DDR3 data cache module and a power supply module;

[0011] The board control module includes a ZYNQ chip, EEPROM, FLASH, a temperature sensor, and JTAG and UART interfaces for debugging;

[0012] The communication interface module sends the received data to ZYNQ for data format conversion according to the data processing requirements of the current PCM gateway device in the airborne test network;

[0013] The PCIe data transmission module is used for communication between the PCM data conversion board and the main control board in the chassis, so that the PCM data conversion board can receive configuration information from the main control board via PCIe and complete parameter configuration for data format conversion. It can also be used to monitor the return data of the PCM data conversion board and monitor the working status of the board;

[0014] The power module converts the 12V backplane power supply voltage into the voltage required by each module chip in the PCM data conversion board and meets the power-on sequence requirements of ZYNQ.

[0015] Furthermore, the communication interface module is designed with an RS-485 interface and an Ethernet interface, wherein the RS-485 interface is used to receive PCM data streams, and the Ethernet interface is used to receive network packets in various data formats that need to be processed.

[0016] Furthermore, the resource connection planning of the board control module ZYNQ is specifically as follows:

[0017] Connect the two pairs of high-speed differential signal lines of the PCIe backplane connector to ZYNQ's GTP Quad high-speed I / O port; hang a multi-channel full-duplex RS-485 transceiver on the PL end; connect Ethernet to the PS end; hang EEPROM and FLASH on the PS end; and mount a DDR3 chip on each of the PS end and PL end.

[0018] Furthermore, the PCM conversion device has three different working modes, namely:

[0019] PCM combining working mode: In this mode, multiple RS-485 bus interfaces receive multiple PCM data, combine them into one PCM data channel and send it out. The input and output PCM data comply with the IRIG-106 Chapter 4 standard.

[0020] Network packet parameter selection mode: In this mode, Ethernet packets are received and some parameters are selected according to the known Ethernet packet protocol to generate one or more channels of PCM data for transmission. The output PCM data complies with the IRIG-106 Chapter 4 standard.

[0021] Network telemetry integration mode: In this mode, different network packets are received and multiple data packets are integrated and sent according to the standards of Chapter 7 of IRIG-106.

[0022] Furthermore, in the PCM combining working mode, the PCM combining logic is implemented on the PL side of the PCM data conversion board. The RS-485 chip receives multiple PCM data from other data acquisition chassis. The PCM receiving and decoding module PCM_rx obtains the input PCM encoding type, subframe word length, and bit rate information according to the configuration information, receives the multiple PCM data streams, and sends the received PCM data to the PCM combining logic module Merge.

[0023] The Merge module extracts the parameters that need to be combined from the PCM data according to the configuration information, and places the parameters in the specified position of the PCM frame; then the sending module encodes the newly generated PCM frame according to the requirements of the configuration information and sends it out.

[0024] Furthermore, in the network packet parameter selection mode, the PCM data conversion board needs to receive the Ethernet packet at the PS end, parse and extract the payload therein, and obtain the flight test data in the network packet; then the parameter selection part program obtains the location information of the parameters to be selected according to the configuration information, extracts and selects the required parameters;

[0025] The framing program uses the selected parameter values to place each parameter in the specified position of the PCM frame according to the configuration information, and merges the extracted parameters into a new PCM frame according to the IRIG-106 Chapter 4 standard. The PS-PL data transmission module sends the PCM frame to be sent via the AXI bus to the PL end, and then passes through the data buffer module and is finally sent by the PCM transmission module.

[0026] Furthermore, in the networked telemetry integration mode, the PCM data conversion board receives multiple different IPv4 data packets from different data acquisition chassis at the PS end, adds EP headers and TP headers to these data packets in accordance with the standards of Chapter 7 of IRIG-106, and decides whether to insert TP into the PCM frame based on the configuration information; the PS-PL data transmission module transmits the processed data to the PL end, and then uses the PCM sending logic to send the data out in the form of a bus via RS-485.

[0027] Furthermore, the configuration data sent by the main control board is specifically: receiving an XML configuration file sent by the host computer, parsing it into configuration parameters in the form of a spreadsheet, and writing it into the EEPROM of the PCM data conversion board through the PCIe interface.

[0028] Furthermore, the return monitoring data of the main control board is specifically: receiving the device status and real-time parameters of the PCM data stream sent by the PCM data conversion board through PCIe, and uploading them to the host computer based on a dedicated Ethernet data transmission protocol.

[0029] Beneficial effects of the present invention

[0030] The present invention is designed based on the chassis architecture of MiniVPX, aiming to develop a PCM conversion device that supports multi-data fusion and realizes format conversion of multiple different data types, solving the defect that traditional PCM gateways only support synchronous parameter streams and are not compatible with asynchronous multi-source data.

[0031] (1) The equipment adopts MiniVPX chassis architecture and a modular pluggable design.

[0032] (2) The PCM data conversion board is designed based on ZYNQ. PS and PL play their respective advantages to complete different functions. The PS side is responsible for Ethernet transmission and reception, and the PL side is responsible for PCM data stream transmission and reception. PS and PL are transmitted at high speed through AXI to improve the efficiency of data format conversion.

[0033] (3) The RS-485 transceiver can achieve full-duplex communication and integrates an isolated power supply, reducing the circuit design area.

[0034] (4) The RS-485 bus interface includes circuit protection circuits, which are suitable for airborne test environments and effectively prevent surges.

[0035] (5) The RS-485 transceiver has a data transmission and reception rate of up to 20Mbps.

[0036] (6) Ethernet interface 10 / 100 / 1000Mbps adaptive.

[0037] (7) It can realize the three data format conversion working modes commonly used in airborne test networks (PCM combining, network packet selection, and network telemetry integration).

[0038] (8) PS and PL each have a DDR3 data cache chip to meet the needs of large-scale data caching, high-speed and large-capacity caching, reduce data format conversion delay and improve real-time performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 The overall structure of the PCM conversion device supporting multivariate data fusion of the present invention;

[0040] Figure 2 It is the hardware structure of PCM data conversion board;

[0041] Figure 3 Power tree structure for PCM data conversion board;

[0042] Figure 4 Program logic for PCM combining mode;

[0043] Figure 5 Designed for PCM combining logic module;

[0044] Figure 6 Send logic state machine jump diagram for PCM encoding;

[0045] Figure 7 Design the program logic for the network packet selection working mode;

[0046] Figure 8 Flowchart of the program for selecting parameters and framing network packets;

[0047] Figure 9 It is the PS-PLPCM data transmission module inside ZYNQ;

[0048] Figure 10 It is the data cache module structure;

[0049] Figure 11 Integrate working mode program logic design for IRIG-106 Chapter 7;

[0050] Figure 12 Integrate procedural flow charts for IRIG-106 Chapter 7;

[0051] Figure 13 Configure data flow for PCM conversion equipment;

[0052] Figure 14 Configure data access solutions for Zynq;

[0053] Figure 15 Flowchart of the program for obtaining configuration data for the PS side;

[0054] Figure 16 Monitor data flow for devices. DETAILED DESCRIPTION

[0055] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0056] The experimental methods used in the following examples are conventional methods unless otherwise specified. The materials, reagents, methods, and instruments used are conventional in the art and can be obtained commercially by those skilled in the art unless otherwise specified.

[0057] The device of the present invention comprises a PCM data conversion board, a main control board, a power supply board, a chassis backplane connector and other parts of the structure as shown in FIG. Figure 1 The PCM data conversion board, based on the ZYNQ design, is used to implement various data format conversion modes. The main control board and configuration management software are used to accurately configure the PCM conversion board. Due to the large amount of data involved and the large number of parameters in the airborne test environment, a relatively reasonable configuration scheme was designed.

[0058] The hardware architecture of the ZYNQ-based PCM data conversion board is as follows: Figure 2 The PCM data conversion board includes a board control module, a communication interface module, a PCIe data transmission module, a DDR3 data cache module, and a power module.

[0059] The board control module is designed around the ZYNQ chip and includes the ZYNQ chip, EEPROM, FLASH, a temperature sensor, and JTAG and UART interfaces for debugging. This module plays a key role in data format conversion and controlling board operation. Compared to traditional FPGAs, the ZYNQ integrates both an FPGA and a processor, leveraging the advantages of both parallel processing on the PL side and high-speed data processing on the PS side. It can directly run bare-metal programs, making development more flexible and efficient. Peripherals connected to the ZYNQ PS side require no interface logic design, enabling fast data read and write access. The PS and PL sides are connected via a high-speed AXI bus, enabling efficient internal data transmission.

[0060] The communication interface module is designed with RS-485 interface and Ethernet interface based on the data processing requirements of the current PCM gateway equipment in the airborne test network. The RS-485 interface is used to receive PCM data streams, and the Ethernet interface is used to receive network packets in various data formats that need to be processed. After receiving the data, the communication interface module sends it to ZYNQ for data format conversion.

[0061] Since the PCM data conversion board needs to process a large amount of data, a DDR3 data cache module is designed to reduce the data cache pressure generated by ZYNQ during data format conversion and ensure the continuity and accuracy of data conversion.

[0062] The PCIe data transmission module is used for communication between the PCM data conversion board and the main control board in the chassis, so that the PCM data conversion board can receive configuration information from the main control board through PCIe.

[0063] The power module converts the 12V backplane power supply voltage into the voltage required by each module chip in the PCM data conversion board and meets the complex power-on sequence requirements of ZYNQ.

[0064] (1) Board control module: In order to give full play to the advantages and resources of ZYNQ chip in data processing at the PS and PL ends, a reasonable connection plan of BANK resources is carried out in the embodiment. The two pairs of high-speed differential signal lines of the PCIe backplane connector are connected to the high-speed I / O port of the GTP Quad to give full play to the high-speed transmission performance advantage of the port, and the PL end can use the XDMA IP core provided by Xilinx for efficient development of PCIe; the full-duplex RS-485 transceiver is hung on the PL end, which can give full play to the advantages of FPGA parallel processing and precise timing; and the Ethernet is connected to the PS end, which is convenient for using the LwIP protocol stack for Ethernet development during bare metal development at the PS end; EEPROM and FLASH are hung on the PS end, which can conveniently use the SPI read and write functions provided by Xilinx to read and write configuration data to the EEPROM; a DDR3 chip is mounted on each of the PS and PL ends. This is because both the PS and PL ends have data format conversion processing tasks and require data cache modules. This design architecture has been verified and optimized many times to ensure that the functional modules can work closely together and the data exchange is smooth, providing hardware support for the PCM conversion board to efficiently and stably implement core functions such as data processing and transmission.

[0065] (2) Communication interface module: The communication interface module includes RS-485 bus interface and Ethernet interface.

[0066] The board's RS-485 bus module is composed of multiple RS-485 communication chips. Conventional RS-485 chips require a separate isolated power supply, resulting in a large power circuit area around the chip, hindering the miniaturization of the present invention. Therefore, to achieve high integration of the PCM conversion board, a full-duplex enhanced RS-485 bus transceiver with an isolated power supply was selected. The TD(H)541S485S-F1 DFN packaged RS485 isolated transceiver, manufactured by Guangzhou Jinshengyang Technology Co., Ltd., was selected.

[0067] The physical layer protocol specifications and standards for network packets entering the PCM board are essentially consistent with IEEE 802.3. This widely used standard provides the technical foundation for the design of the PCM board's physical interface. To effectively implement physical layer functions, the PCM board uses a PHY chip that supports the IEEE 802.3 protocol as the physical interface transceiver. Microchip's KSZ9031RNX is used as the Ethernet physical layer transceiver.

[0068] (3) PCIe data transmission module

[0069] The PCIe data transmission module implements PCIe communication between the main control computer and the board, and is used for communication between the PCM data conversion board and the main control board in the chassis. This allows the PCM data conversion board to receive configuration information from the main control board via PCIe and complete parameter configuration for data format conversion. It can also send the board's currently output PCM data stream and board health status information to the main control board via PCIe to facilitate real-time monitoring of the board's output data and operating status. The ZYNQ used in this invention has a universal high-speed serial port. The board is connected to the backplane via a MiniVPX connector. According to the VITA73 standard, the connector between a MiniVPX unit module and the backplane is divided into three sections: P0, P1, and P2 connector positions from top to bottom.

[0070] 1) The P0 connector connects the power supply and reference ground. It uses ERNI's MicroSpeed series connector 364704RA. Each connector has 5 terminals. Terminals 1-3 are reference grounds, terminal 4 is for +12V power supply, and terminal 5 is not used.

[0071] 2) The P1 and P2 connectors are used to connect data channels, establish subordinate relationships between devices, and realize information transmission. Both use ERNI's MicroSpeed series connector 374722RA. Each connector has 50 pins and a data transmission rate of up to 25Gbit / s. Among them, A1 and A2 are PCIe receive pins, B1 and B2 are PCIe transmit pins, A13 and A14 are PCIe 100MHz reference differential clocks, and the remaining pins include SMBus bus pins, trigger pins, etc.

[0072] (4) DDR3 cache module

[0073] The Zynq chip features a Micron MT41K256M16TW-107 DDR3 chip mounted on each of the PS and PL terminals. This 4Gb x 16-bit DDR3L SDRAM chip plays a crucial role in data caching during PCM data conversion. With a storage capacity of 4Gb and a 32Meg x 16 x 8-bank architecture, it can meet the storage needs of larger data volumes. The chip operates at 1.35V, maintains stable operation within the 1.283-1.45V range, and is backwards compatible with 1.5V applications. It utilizes a 96-ball FBGA (Pb-free) package, which offers excellent electrical performance and mechanical stability, meeting the stringent chip reliability requirements of airborne test equipment.

[0074] (5) Power module

[0075] The PCM board is initially powered by 12V from the fourth node of the P0 connector. However, the data interface chip and various functional modules on the board, such as ZYNQ, have specific supply voltage requirements, so voltage conversion is necessary.

[0076] The board's power supply system is designed as a two-stage power architecture, using power chips LTM4622, TPS74801, and TPS51206. It's worth noting that the ZYNQ chip, as the core processing unit of the board, has extremely strict requirements for power-on sequencing.

[0077] In order to accurately meet the power-on sequence requirements of the ZYNQ chip, this design uses the PG (PowerGood) pin and enable pin of the power chip to determine the power-on sequence of the power supply. By properly configuring the logic level changes of these pins, precise control of each power output is achieved. The power tree structure of the power supply module is as follows Figure 3 shown.

[0078] Program and logic design for data format conversion

[0079] The PCM conversion board is designed with three different operating modes to support data conversion requirements in different application scenarios. The first is PCM combining mode, in which multiple RS-485 bus interfaces receive multiple channels of PCM data, combine them into a single channel, and transmit it. The second is network packet parameter selection mode, which receives Ethernet packets, selects certain parameters according to a known protocol, and generates PCM data for transmission. The third is network telemetry integration mode, which receives different network packets and combines and transmits multiple data packets according to the IRIG-106 Chapter 7 standard.

[0080] (1) PCM combining

[0081] PCM combining logic is as follows Figure 4 All of this is implemented on the PL side. The RS-485 chip receives multiple PCM data streams from other data acquisition chassis, all of which comply with IRIG-106, Section 4 standards. The PCM receive and decode module, PCM_rx, receives the multiple PCM data streams and sends them to the PCM combining logic module, Merge. The Merge module extracts the parameters required for combining from the PCM data according to the configuration information and regenerates a new PCM frame. The transmitter then encodes the newly generated PCM frame according to the configuration information and transmits it. Configuration information for the three aforementioned logic modules is extracted from the EEPROM on the PS side and sent to the PL side via the AXI bus. Both PCM data reception and transmission comply with IRIG-106, Section 4 standards and support six code types: NRZ-L, NRZ-M, NRZ-S, Manchester-L, Manchester-M, and Manchester-S.

[0082] The design of PCM combining logic module Merge is as follows Figure 5 As shown in the figure, the two channels of PCM data extracted by the PCM decoding module are placed into two FIFOs. Frame synchronization is then performed. After the synchronization word is extracted, the parameters in each subframe are extracted. Parameter extraction is performed based on the location information for each parameter specified in the configuration information. Different parameters are placed in different FIFO partitions to facilitate subsequent parameter extraction. The PCM combiner generation module then uses all parameters to generate a new PCM data frame.

[0083] The PCM encoding and sending module needs to input the framed PCM data from the FIFO, and encode and output the PCM data according to the configuration information such as the PCM code type and the transmission bit rate, and can output the bit synchronization, word synchronization, subframe synchronization and main frame synchronization signals of the PCM data frame. The state jump of the PCM encoding and sending module is related to the amount of data in the read FIFO. When the amount of data in the read FIFO reaches or exceeds the main frame length pcm_length, the state machine switches from the idle state idle to the transmission state trans and starts the data encoding and sending operations. In the transmission state, if a frame of data is sent and the amount of readable data in the FIFO is less than a frame of data, the state machine will return to the idle state; if the amount of data in the FIFO is still greater than a frame of data, the transmission state will continue to be maintained to achieve continuous data transmission. The state transition diagram of the PCM encoding and sending module is shown as follows Figure 6 .

[0084] (2) Network packet selection

[0085] Network packet parameter selection module such as Figure 7 Ethernet packets need to be received on the PS side. Using the Vitis bare-metal development platform, the data packets are parsed and parameters are extracted using C language. These extracted parameters are then combined into new PCM frames according to IRIG-106 Chapter 4. The PS-PL data transmission module sends the PCM frames to the PL side via the AXI bus. After passing through the data buffer module, the PCM transmission module completes the transmission.

[0086] The flow chart of the network packet selection and framing program is as follows Figure 8 As shown, the network packet must first be received and parsed, extracting the payload and acquiring the flight test data contained within. The parameter selection process then determines the location of the parameters to be selected based on the configuration information, extracting and selecting the required parameters. The framing process then uses the selected parameter values to place them in the designated locations within the PCM frame according to the configuration information. In the network packet parameter selection mode, the output PCM data frame format complies with IRIG-106 Chapter 4, while the input network packet supports IPv4 packets, TCP datagrams, UDP datagrams, and other protocols, parsing the parameters according to the application layer protocol.

[0087] The generated PCM data frame is transmitted from the PS end to the PL end mainly through the AXI bus. The Block Design diagram of the PCM data transmission module is as follows Figure 9 As shown in the figure, you need to open the M_AXI_GP0 interface of the ZYNQ7Processing System IP core in the Vivado Block Design, write the AXI slave logic module pcm_data_recv, place the module in the Block Design, and use the AXI Interconnect module to connect the ZYNQ7 Processing System and pcm_data_recv.

[0088] After the PCM data is transmitted to the PL end, it needs to enter the data cache module. The logical structure of the data cache module is as follows: Figure 10As shown in the figure, after PCM data enters the data cache module, it first flows into the write FIFO. Considering that PCM words are typically 16 bits, the write data bit width of the write FIFO is set to 16 bits to accommodate the PCM data format. To significantly improve cache efficiency, the read data bit width is set to 128 bits when connecting to the subsequent DDR3 read / write control module. This difference in bit width is intended to leverage DDR3's high read / write speed, increasing the amount of data transferred per transaction and reducing the number of data transfers, thereby improving overall cache efficiency. The DDR3 read / write control module implements efficient connectivity and collaboration between the read / write FIFO and the MIG IP core. The read FIFO path design is consistent with the write path, and the read FIFO's buffering function accommodates the data transfer rate differences between the DDR3 and PCM transmit modules.

[0089] (3) Networked telemetry integration

[0090] Networked telemetry integration modules such as Figure 11 The PS receives multiple IPv4 packets from different data acquisition chassis. The integration program adds EP (Encapsulation Packet) and TP (Transport Packet) headers to these packets in accordance with IRIG-106 Section 7. Depending on the configuration, the TP is inserted into the PCM frame, which complies with IRIG-106 Section 4. The PS-PL data transmission module transmits the processed data to the PL, which then uses PCM transmit logic to transmit the data via the RS-485 bus.

[0091] The program is developed using the LwIP protocol stack on the Vitis bare metal development platform, such as Figure 12 To integrate the program flow chart for networked telemetry, first initialize the LwIP protocol stack and set up the network, register the udp_recv function, and automatically call the callback function when the board receives the correct network packet. The UDP payload is received and the source IP address and source port number are obtained. Since SP is an IPv4 datagram according to Chapter 7 of the IRIG-106 standard, the UDP payload needs to be encapsulated into an IPv4 datagram, and the EP header and TP header are added in sequence, and finally loaded into the PCM frame.

[0092] Device configuration data flow

[0093] Due to the particularity of the ZYNQ architecture, the process of implementing device configuration is also a key content of this invention. The overall configuration data flow of the device is as follows Figure 13 First, the host computer sends the XML file, the main control parses the XML into a configuration spreadsheet, and then transmits it to the board through the PCIe backplane connector. The XDMA hard core of the board receives the PCIe data.

[0094] In order to use the SPI read and write functions provided by Xilinx on the PS side to quickly read and write EEPROM configuration data, the EEPROM is hung on the PS side, and the configuration data is received by the high-speed transceiver on the PL side as PCIe data. Therefore, it is necessary to perform PL-PS configuration data transmission inside ZYNQ. The configuration logic and data flow inside ZYNQ are as follows: Figure 14 As shown. After ZYNQ receives PCIe configuration data using the XDMA IP core on the PL side, it needs to transfer the data to the EEPROM on the PS side via the AXI bus for storage of the configuration data. The process of transferring configuration data from the PL side to the PS side is achieved by setting the AXI HP (Advanced Extensible Interface High Performance) port of the ZYNQ7 IP core in the Vivado development environment. In this invention, the DDR3 memory mounted on the PS side is used as shared memory for the PS and PL sides. The PL side can directly store data in the shared memory, and the PS side can also directly read it.

[0095] After transferring the data to the shared memory, the configuration data in the shared memory is stored in the EEPROM through the SPI write function. In this process, attention should be paid to the cache consistency problem of the ARM architecture on the PS side. For this purpose, the following is designed: Figure 15 The program continuously invalidates the cache, detects that the configuration data is transferred to the shared memory, and obtains the data to perform the SPI read and write operations of the EEPROM in the next step.

[0096] Device monitoring data flow

[0097] In order to monitor the output data value of the PCM conversion board and the health status information of the board in real time, it is necessary to transmit the monitoring flow through the PCIe backplane connector, such as Figure 16 shown.

[0098] First, the XDMAIP core of the PCM converter board transmits the data to be monitored to the PCIe backplane connector via the AXI bus, where it is received by the main control. The main control then uses SNMP to receive the monitoring data from the upper computer configuration management software, and then parses the data and displays it to the user.

[0099] The PCM conversion device supporting multi-data fusion proposed in the present invention is introduced in detail above, and the principle and implementation mode of the present invention are explained. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. PCM conversion equipment supporting multi-data fusion, characterized by: The PCM conversion device is based on the MiniVPX chassis and includes a PCM data conversion board, a main control board, a power supply board and a chassis backplane connector; The chassis backplane connector includes P0, P1, and P2 connectors, wherein the P0 connector is connected to the power board, and the P1 and P2 connectors are used to implement PCIe connection; The PCM data conversion board integrates a ZYNQ chip, receives configuration parameters issued by the main control board, receives multiple PCM data streams and network data packets, performs format conversion on the PCM data and network data according to the configuration parameters, generates a target PCM data stream, and transmits the target PCM data stream and device status data back to the main control board through the PCIe interface; The main control board establishes a PCIe communication link with the PCM data conversion board through the P1 and P2 connectors of the chassis backplane connector, which is used to send configuration data and return monitoring data.

2. The PCM conversion device according to claim 1, characterized in that: The PCM data conversion board includes a board control module, a communication interface module, a PCIe data transmission module, a DDR3 data cache module, and a power supply module; The board control module includes a ZYNQ chip, EEPROM, FLASH, a temperature sensor, and JTAG and UART interfaces for debugging; The communication interface module sends the received data to ZYNQ for data format conversion according to the data processing requirements of the current PCM gateway device in the airborne test network; The PCIe data transmission module is used for communication between the PCM data conversion board and the main control board in the chassis, so that the PCM data conversion board can receive configuration information from the main control board via PCIe and complete parameter configuration for data format conversion. It can also send the PCM data stream currently being output by the board and the health status information of the board to the main control board via PCIe for real-time monitoring of the output data and working status of the board; The power module converts the 12V backplane power supply voltage into the voltage required by each module chip in the PCM data conversion board and meets the power-on sequence requirements of ZYNQ.

3. The PCM conversion device according to claim 2, characterized in that: The communication interface module is designed with an RS-485 interface and an Ethernet interface, wherein the RS-485 interface is used to receive PCM data streams, and the Ethernet interface is used to receive network packets in various data formats that need to be processed.

4. The PCM conversion device according to claim 2, characterized in that: The resource connection planning of the board control module ZYNQ is specifically as follows: Connect the two pairs of high-speed differential signal lines of the PCIe backplane connector to the ZYNQ GTP Quad high-speed I / O port; hang a multi-channel full-duplex RS-485 transceiver on the PL end; and connect Ethernet to the PS end. EEPROM and FLASH are mounted on the PS end; a DDR3 chip is mounted on the PS end and the PL end respectively.

5. The PCM conversion device according to claim 2, characterized in that: The PCM conversion device has three different working modes: PCM combining working mode: In this mode, multiple RS-485 bus interfaces receive multiple PCM data, combine them into one PCM data channel and send it out. The input and output PCM data comply with the IRIG-106 Chapter 4 standard. Network packet parameter selection mode: In this mode, Ethernet packets are received and some parameters are selected according to the known Ethernet packet protocol to generate one or more channels of PCM data for transmission. The output PCM data complies with the IRIG-106 Chapter 4 standard. Network telemetry integration mode: In this mode, different network packets are received and multiple data packets are integrated and sent according to the standards of Chapter 7 of IRIG-106.

6. The PCM conversion device according to claim 5, characterized in that: In the PCM combining working mode, the PCM combining logic is implemented on the PL side of the PCM data conversion board. The RS-485 chip receives multi-channel PCM data from other data acquisition chassis. The PCM receiving and decoding module PCM_rx obtains the input PCM encoding type, subframe word length, and bit rate information according to the configuration information, receives the multi-channel PCM data stream, and sends the received PCM data to the PCM combining logic module Merge. The Merge module extracts the parameters that need to be combined from the PCM data according to the configuration information, and places the parameters in the specified position of the PCM frame; then the sending module encodes the newly generated PCM frame according to the requirements of the configuration information and sends it out.

7. The PCM conversion device according to claim 5, characterized in that: In the network packet parameter selection mode, the PCM data conversion board needs to receive the Ethernet packet at the PS end, parse and extract the payload therein, and obtain the flight test data in the network packet; then the parameter selection part program obtains the location information of the parameters to be selected based on the configuration information, extracts and selects the required parameters; The framing program uses the selected parameter values to place each parameter in the specified position of the PCM frame according to the configuration information, and merges the extracted parameters into a new PCM frame according to the IRIG-106 Chapter 4 standard. The PS-PL data transmission module sends the PCM frame to be sent via the AXI bus to the PL end, and then passes through the data buffer module and is finally sent by the PCM transmission module.

8. The PCM conversion device according to claim 5, characterized in that: In the networked telemetry integration mode, the PCM data conversion board receives multiple different IPv4 data packets from different data acquisition chassis on the PS side, adds EP headers and TP headers to these data packets in accordance with the standards of Chapter 7 of IRIG-106, and decides whether to insert TP into the PCM frame based on the configuration information; the PS-PL data transmission module transmits the processed data to the PL side, and then uses the PCM transmission logic to send the data out in the form of a bus via RS-485.

9. The PCM conversion device according to claim 1, characterized in that: The configuration data sent by the main control board is specifically: receiving the XML configuration file sent by the host computer, parsing it into configuration parameters in the form of a spreadsheet, and writing it into the EEPROM of the PCM data conversion board through the PCIe interface.

10. The PCM conversion device according to claim 1, characterized in that: The return monitoring data of the main control board is specifically: receiving the device status and real-time parameters of the PCM data stream sent by the PCM data conversion board through PCIe, and uploading them to the host computer based on a dedicated Ethernet data transmission protocol.

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