Semiconductor device and manufacturing method thereof, and chip

Abstract

The present disclosure provides a semiconductor device and a preparation method thereof, and a chip, which relate to the technical field of semiconductor chips and aim to solve the problem that in an enhancement-mode semiconductor device, the 2DEG concentration in the region between the gate and the channel layer is high, making it difficult to deplete it. The semiconductor structure comprises: a substrate, a channel layer and a barrier layer, a p-GaN layer, a source, a drain, a gate, and a functional layer; the substrate, the channel layer, and the barrier layer are stacked in sequence; the p-GaN layer is arranged on a side of the barrier layer away from the channel layer; the gate is arranged between the source and the drain, and the gate is arranged on a side of the p-GaN layer away from the substrate; the source and the drain are arranged on a side of the barrier layer or the channel layer away from the substrate; the functional layer is arranged on a side of the barrier layer away from the channel layer, and is arranged between the p-GaN layer and the drain, and the functional layer is also in contact with the p-GaN layer; wherein the material of the functional layer comprises: Al y Ga (1‑y) N; the barrier layer materials include: Al x Ga (1‑x) N; x>y, and y can be 0.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor chips, and in particular to a semiconductor device and a manufacturing method thereof, and a chip. Background Art

[0002] A high electron mobility transistor (HEMT) is a field-effect transistor based on a heterojunction structure. It utilizes the differences in the energy band structures between different semiconductor materials. The bottom of its conduction band forms an energy band ladder at the heterojunction interface, which in turn forms a quantum well. Electrons are distributed in the quantum well, forming a high-concentration, high-mobility two-dimensional electron gas (2DEG) that moves freely along the heterojunction interface but is restricted in movement in the direction perpendicular to the interface, thereby achieving high-performance electron transport.

[0003] Enhancement-mode semiconductor devices can remain in the off state when there is no gate voltage and only start conducting when a positive gate voltage is applied, which reduces energy consumption and improves the safety of semiconductor devices. Enhancement-mode semiconductor devices can be realized by introducing a p-GaN (p-type gallium nitride) layer between the barrier layer and the gate. However, in such semiconductor devices, the 2DEG concentration in the area between the gate and the drain is high, making it difficult to deplete electrons in the semiconductor device during rapid switching. This results in a higher electric field and a larger current at the gate edge of the semiconductor device, which in turn causes the 2DEG in the channel layer that is not depleted in time to bombard weak areas such as the gate, drain, and dielectric layer under a higher field, causing damage to the semiconductor device and an increase in trap states, thereby causing reliability risks. Summary of the Invention

[0004] The embodiments of the present disclosure provide a semiconductor device, a method for manufacturing the same, and a chip, aiming to solve the problem in an enhancement-mode semiconductor device where the 2DEG concentration in the region between the gate and the channel layer is high, making it difficult to deplete the 2DEG.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] In one aspect, a semiconductor device is provided, comprising: a substrate, a channel layer and a barrier layer, a p-GaN layer, a source electrode, a drain electrode, a gate electrode, and a functional layer.

[0007] The substrate, channel layer, and barrier layer are stacked in sequence. The p-GaN layer is located on the side of the barrier layer away from the channel layer. The gate is located between the source and drain electrodes, and the gate is located on the side of the p-GaN layer away from the substrate. The source and drain electrodes are located on the side of the barrier layer or the channel layer away from the substrate.

[0008] The functional layer is arranged on a side of the barrier layer away from the channel layer and between the p-GaN layer and the drain electrode. The functional layer is also in contact with the p-GaN layer.

[0009] Among them, the materials of the functional layer include: Al y Ga (1-y) N (aluminum gallium nitride). The barrier layer materials include: Al x Ga (1-x) N; x>y, and y can be 0.

[0010] In the semiconductor device provided by the above-mentioned embodiments of the present disclosure, x>y, that is, the content of Al atoms in the barrier layer material AlGaN is relatively high, and the resulting polarization difference is relatively large, resulting in a large amount of polarization charges appearing at the interface between the barrier layer and the channel layer, and easily forming a high concentration of 2DEG at the interface. The content of Al atoms in the functional layer material AlGaN is set to be less than the content of Al atoms in the barrier layer material AlGaN, so that the resulting polarization difference is smaller, which can neutralize the polarization charges generated by the barrier layer, thereby reducing the polarization effect, thereby effectively reducing the 2DEG concentration in the channel layer, reducing the 2DEG concentration in the area between the gate and the drain, making it easier to deplete and making the switch more agile; it can also reduce the polarization charge density in the heterojunction in the gate edge area, thereby reducing the peak value of the electric field on the gate-drain side, thereby improving the reliability of the semiconductor device.

[0011] In some embodiments, the functional layer includes: a plurality of functional sublayers. The plurality of functional sublayers are stacked along a first direction, which is a thickness direction of the substrate.

[0012] In some embodiments, the multilayer functional sublayer includes: a first functional sublayer and a second functional sublayer arranged arbitrarily adjacent to each other, and the second functional sublayer is arranged on a side of the first functional sublayer away from the barrier layer;

[0013] Among them, the first functional sub-layer material includes: Al y1 Ga (1-y1) N. The second functional sublayer material includes: Al y2 Ga (1-y2) N; and y1≥y2.

[0014] In some embodiments, the material of the functional layer further includes: GaN.

[0015] In some embodiments, a size of the first functional sublayer along the second direction is greater than a size of the second functional sublayer along the second direction, and the second direction is an arrangement direction from the gate to the drain.

[0016] In some embodiments, the size of the first functional sublayer and / or the second functional sublayer along a first direction ranges from 1 nm to 20 nm, and the first direction is the thickness direction of the substrate.

[0017] In some embodiments, a dimension of the functional layer along a first direction is less than or equal to a dimension of the p-GaN layer along a second direction, and the first direction is a thickness direction of the substrate.

[0018] In some embodiments, in the second direction, the p-GaN layer partially overlaps with the functional layer, and the second direction is an arrangement direction from the gate to the drain.

[0019] In some embodiments, the first functional sublayer includes a first sidewall and a second sidewall disposed along the second direction, and the second functional sublayer includes a third sidewall and a fourth sidewall disposed along the second direction.

[0020] The first side wall and the third side wall are coplanarly arranged, and in the second direction, the distance between the second side wall and the drain is smaller than the distance between the fourth side wall and the drain.

[0021] In some embodiments, the p-GaN layer partially overlaps the barrier layer.

[0022] In some embodiments, the semiconductor device further comprises an auxiliary layer, wherein the auxiliary layer is disposed on a side of the barrier layer away from the channel layer.

[0023] The material of the auxiliary layer includes: AlN.

[0024] In another aspect, a method for preparing a semiconductor device is provided. The method for preparing a semiconductor device comprises:

[0025] A channel layer is formed on one side of the substrate.

[0026] A barrier layer is formed on a side of the channel layer away from the substrate. And,

[0027] A functional layer is formed on a side of the barrier layer away from the channel layer.

[0028] A p-GaN layer is formed on a side of the barrier layer away from the channel layer.

[0029] A source, a drain and a gate disposed between the source and the drain are formed. The gate is disposed on a side of the p-GaN layer away from the substrate. The source and the drain are disposed on a side of the barrier layer or the channel layer away from the substrate. The functional layer is disposed between the p-GaN layer and the drain, and the functional layer is also in contact with and connected to the p-GaN layer.

[0030] Among them, the materials of the functional layer include: Al y Ga (1-y) N. The barrier layer materials include: Al x Ga (1-x) N; x>y, and y can be 0.

[0031] It can be understood that the beneficial effects achieved by the method for preparing the semiconductor device provided by the above embodiment of the present disclosure can be referred to the beneficial effects of the semiconductor device described above, and will not be repeated here.

[0032] In another aspect, a chip is provided, comprising: a semiconductor device.

[0033] It can be understood that the beneficial effects that can be achieved by the chip provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor device mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0035] Figure 1 is a schematic structural diagram of a semiconductor device according to some embodiments;

[0036] Figure 2 is a schematic structural diagram of a semiconductor device according to yet other embodiments;

[0037] Figure 3 is a schematic structural diagram of a semiconductor device according to yet other embodiments;

[0038] Figure 4 is a schematic structural diagram of a semiconductor device according to yet other embodiments;

[0039] Figure 5 is a schematic structural diagram of a semiconductor device according to yet other embodiments;

[0040] Figure 6 is a schematic structural diagram of a semiconductor device according to yet other embodiments;

[0041] Figure 7 is a flow chart of manufacturing a semiconductor device according to some embodiments;

[0042] Figure 8 is a structural diagram corresponding to each step in a method for manufacturing a semiconductor device according to some embodiments;

[0043] Figure 9 are structural diagrams corresponding to various steps in a method for manufacturing a semiconductor device according to yet other embodiments;

[0044] Figure 10 is a schematic structural diagram of a semiconductor device according to yet other embodiments;

[0045] Figure 11 1 is an energy band structure diagram of the semiconductor device according to Examples 1 to 4;

[0046] Figure 12 1 is an electron density diagram of the semiconductor device according to Example 1 to Example 4;

[0047] Figure 13 2DEG concentration diagram of the channel layer of the semiconductor device according to Example 1 to Example 4;

[0048] Figure 14 1 is an energy band structure diagram of the semiconductor device according to Example 2 and Example 5 to Example 13;

[0049] Figure 15 1 is an electron density diagram of the semiconductor device according to Example 2 and Example 5 to Example 13;

[0050] Figure 16 2DEG concentration diagrams of the channel layers of the semiconductor devices according to Example 6, Example 8, Example 9, Example 11, and Example 13. DETAILED DESCRIPTION

[0051] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0052] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0053] In the context of this disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers, and “over” or “over” means not only “over” or “above” something, but also includes “over” or “above” something with no intervening features or layers (i.e., directly on something).

[0054] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0055] As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0056] The following are the technical terms used in the embodiments of the present disclosure:

[0057] Semiconductor: A semiconductor is a material with electrical conductivity between that of a conductor and an insulator at room temperature. Semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor free of impurities and defects, with equal concentrations of electrons and holes, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an impurity semiconductor or an extrinsic semiconductor. Impurities added to an impurity semiconductor can provide a certain concentration of carriers (such as holes or electrons). Impurity semiconductors doped with electron-providing impurities (such as pentavalent phosphorus) are also called electron-type semiconductors or N (negative) semiconductors, while impurity semiconductors doped with hole-providing impurities (such as trivalent boron) are also called hole-type semiconductors or P (positive) semiconductors). This improves the conductivity of the intrinsic semiconductor. Generally, a higher carrier concentration results in a lower resistivity and better conductivity. In the embodiments of the present disclosure, this type of impurity semiconductor is also referred to as a conductive semiconductor. For example, conductive silicon carbide material is doped with impurities such as nitrogen (N), boron (B), and aluminum (Al). Furthermore, when impurities introduced into an impurity semiconductor are capable of impurity compensation for the impurity semiconductor, the donor electrons are just sufficient to fill the acceptor energy levels, but are unable to contribute electrons and holes to the conduction and valence bands. This results in a wide-bandgap semiconductor material having a resistivity similar to that of an insulator. For example, in the embodiments of the present disclosure, doping a silicon carbide material with a transition metal achieves impurity compensation for the silicon carbide material, thereby increasing the resistivity of the silicon carbide material. This type of impurity semiconductor is also referred to as a semi-insulating semiconductor or semi-insulator, or possesses semi-insulating properties.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as those known to those of ordinary skill in the art. In the present disclosure, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, in the embodiments of the present disclosure, words such as "first" and "second" do not limit the quantity and order.

[0059] In addition, in the present disclosure, directional terms such as "upper" and "lower" are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to changes in the orientation of the components in the drawings.

[0060] It should be noted that in this disclosure, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this disclosure as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0061] The technical solutions disclosed herein can be applied to electronic devices, including various types of user equipment or terminal devices, such as computers, mobile phones, tablet computers, wearable devices, and in-vehicle devices. These electronic devices can also be network devices, such as base stations. The electronic devices can also be devices such as power amplifiers used in these electronic devices. The embodiments of this disclosure do not impose any particular limitations on the specific form of these electronic devices.

[0062] like Figure 1 and Figure 2 As shown, a p-GaN layer 16 is introduced between the barrier layer 12 and the gate 14 to realize an enhancement mode semiconductor device 100. The semiconductor device 100 includes: a substrate 10, a channel layer 11 and a barrier layer 12, a p-GaN layer 16, a source 15, a drain 13 and a gate 14.

[0063] A substrate 10, a channel layer 11, and a barrier layer 12 are stacked in sequence. A p-GaN layer 16 is disposed on the side of the barrier layer 12 away from the channel layer 11. A gate 14 is disposed between a source 15 and a drain 13, and the gate 14 is disposed on the side of the p-GaN layer 16 away from the substrate 10. The source 15 and the drain 13 are disposed on the side of the barrier layer 12 or the channel layer 11 away from the substrate 10.

[0064] For example, Figure 1 As shown, the source 15 and the drain 13 are arranged on a side of the barrier layer 12 away from the substrate 10 .

[0065] For example, Figure 2 As shown, the source 15 and the drain 13 are arranged on a side of the channel layer 11 away from the substrate 10 .

[0066] The substrate 10 is the foundation of the semiconductor device 100 . The substrate 10 provides physical and electrical support and is typically made of silicon, gallium arsenide, or other semiconductor materials.

[0067] The source electrode 15 and the drain electrode 13 are electrodes of the semiconductor device 100 , and voltages can be applied thereto to regulate the flow of carriers in the channel layer 11 .

[0068] Gate 14 controls the flow of carriers at the heterojunction interface between channel layer 11 and barrier layer 12. When a voltage is applied, a channel is formed in channel layer 11 that promotes electrons or holes, thereby enabling the switching function of semiconductor device 100. Channel layer 11 can be made of GaN (gallium nitride).

[0069] The material of the barrier layer 12 can be AlGaN, which is an ultra-wide bandgap semiconductor material with the dual advantages of AlN (aluminum nitride) and GaN, such as good chemical stability, extremely high melting point, high thermal conductivity, hard texture, and high luminous efficiency.

[0070] The channel layer 11 and the barrier layer 12 can form a heterojunction structure, such as an AlGaN / GaN heterojunction structure. The polarization charge (generated by the polarization difference of the material) of the barrier layer 12 (such as AlGaN) causes a large electric field, causing electrons to accumulate near the interface between the channel layer 11 and the barrier layer 12 to form a 2DEG (such as Figure 1 In the AlGaN / GaN heterostructure, the higher the Al atomic content, the greater the polarization difference, the stronger the polarization effect, and the stronger the generated polarization electric field, which increases the polarization charge and thus the higher the 2DEG concentration.

[0071] The p-GaN layer 16 generates positive charges through p-type doping, which can reduce the 2DEG concentration in the channel layer 11 and make the semiconductor device 100 in an off state when there is no bias.

[0072] In some examples, a buffer layer is further included between the substrate 10 and the channel layer 11, which can buffer the stress that may be generated between the substrate 10 and the channel layer 11 materials, enable lattice matching between the substrate 10 and the channel layer 11 materials, reduce thermal stress and physical strain caused by temperature changes, and thus reduce the formation of defects.

[0073] In some examples, the barrier layer 12 further includes a passivation layer 19 on a side away from the substrate 10 (see Figure 10 ), which can effectively protect the surface of the semiconductor device 100, prevent environmental factors (such as oxygen and moisture) from affecting the semiconductor device 100, and reduce the impact of surface defects and impurities, thereby improving the stability and long-term reliability of the semiconductor device 100.

[0074] However, in this enhancement-mode semiconductor device 100, the 2DEG concentration in the region between the gate 14 and the channel layer 11 is relatively high, making it difficult to deplete it. This, on the one hand, results in a lower threshold voltage; on the other hand, it causes the semiconductor device 100 to experience a higher electric field and a larger current, which in turn causes the 2DEG in the channel layer 11 that has not been depleted in time to bombard weak regions such as the gate 14 and the drain 13 under a higher field, causing damage to the enhancement-mode semiconductor device 100 and an increase in trap states, thereby causing reliability risks.

[0075] The following description will be based on the semiconductor device 100 in which the source 15 and the drain 13 are located on the side of the channel layer 11 away from the substrate 10 . The same description is applicable to the semiconductor device 100 in which the source 15 and the drain 13 are located on the side of the barrier layer 12 away from the substrate 10 .

[0076] Based on this, an embodiment of the present disclosure provides a semiconductor device 100. Figure 3 As shown, the semiconductor device 100 includes a substrate 10 , a channel layer 11 and a barrier layer 12 , a p-GaN layer 16 , a source 15 , a drain 13 , a gate 14 and a functional layer 17 .

[0077] Here, the arrangement and description of the substrate 10, the channel layer 11 and the barrier layer 12, the p-GaN layer 16, the source 15, the drain 13, and the gate 14 are consistent with the arrangement of the substrate 10, the channel layer 11 and the barrier layer 12, the p-GaN layer 16, the source 15, the drain 13, and the gate 14 in the above text, and are not repeated here.

[0078] The functional layer 17 is disposed on a side of the barrier layer 12 away from the channel layer 11 and between the p-GaN layer 16 and the drain electrode 13 . The functional layer 17 is also in contact with the p-GaN layer 16 .

[0079] The material of the functional layer 17 includes: Al y Ga (1-y) N. The materials of the barrier layer 12 include: Al x Ga (1-x) N; x>y, and y can be 0.

[0080] It can be understood that x>y, that is, the content of Al atoms in the AlGaN material of the barrier layer 12 is higher, and the polarization difference generated is larger, resulting in a large amount of polarization charges at the interface between the barrier layer 12 and the channel layer 11, which easily forms a high concentration of 2DEG at the interface. The content of Al atoms in the AlGaN material of the functional layer 17 is set to be less than the content of Al atoms in the AlGaN material of the barrier layer 12, so that the polarization difference generated is smaller, which can neutralize the polarization charge generated by the barrier layer 12, thereby reducing the polarization effect, thereby effectively reducing the 2DEG concentration in the channel layer 11, and reducing the 2DEG concentration in the area between the gate 14 and the channel layer 11, which is easier to deplete and the switching is more agile; it can also reduce the polarization charge density in the heterojunction in the edge area of ​​the gate 14, thereby reducing the peak value of the electric field on the gate 14 and the drain 13 side, avoiding electrons from bombarding the dielectric layer of the semiconductor device 100 under the action of a high field, thereby improving the reliability of the semiconductor device 100.

[0081] y can be 0, that is, the content of Al atoms in the material of the functional layer 17 is 0, which is quite different from the content of Al atoms in the barrier layer 12. It can better neutralize the polarization charge generated by the barrier layer 12, thereby effectively reducing the 2DEG concentration in the channel layer 11, so that the 2DEG concentration in the area between the gate 14 and the channel layer 11 is reduced, which is easier to deplete and the switching is more agile; it can also reduce the polarization charge density in the heterojunction in the edge area of ​​the gate 14, thereby reducing the peak value of the electric field on the gate 14 and the drain 13 side, avoiding electrons from bombarding the dielectric layer of the semiconductor device 100 under the action of high field, and further improving the reliability of the semiconductor device 100.

[0082] like Figure 2 As shown, in the semiconductor device 100, the polarization charge is distributed in the region of the channel layer 11 corresponding to the gate 14 and the drain 13, and the depletion region adjacent to the region is less distributed; Figure 3 As shown, after the functional layer 17 is set in the area between the p-GaN layer 16 and the drain 13, the polarization charge distribution in the semiconductor device 100 is diffused, which can neutralize the polarization charge generated by the barrier layer 12, and then neutralize the polarization effect, so that the depletion region is widened, the electric lines are smoothed, and no longer concentrated on the edge of the gate 14, thereby effectively reducing the 2DEG concentration in the channel layer 11, so that the 2DEG concentration in the area between the gate 14 and the channel layer 11 is reduced, and it is easier to deplete.

[0083] In some embodiments, as Figure 4 As shown, the functional layer 17 includes a plurality of functional sublayers 17X. The plurality of functional sublayers 17X are stacked along a first direction Y. The first direction Y is the thickness direction of the substrate 10 .

[0084] Exemplarily, the number of the multi-layer functional sub-layers 17X may be 2, 3, 4 or 5, etc., which is not limited here.

[0085] It can be understood that the multi-layer functional sublayer 17X can reduce the polarization charge density in the heterojunction in the edge area of ​​the gate 14, thereby reducing the peak value of the electric field on the gate 14 and drain 13 sides, preventing electrons from bombarding the dielectric layer of the semiconductor device 100 under the action of a high field, thereby improving the reliability of the semiconductor device 100.

[0086] In some embodiments, the multi-layer functional sublayer 17X includes a first functional sublayer 171 and a second functional sublayer 172 that are arbitrarily adjacent to each other, and the second functional sublayer 172 is disposed on a side of the first functional sublayer 171 away from the barrier layer 12 .

[0087] The material of the first functional sub-layer 171 includes: Al y1 Ga (1-y1) N. The second functional sublayer 172 material includes: Al y2 Ga (1-y2) N; and y1≥y2.

[0088] It can be understood that y1≥y2, that is, the content of Al atoms in the second functional sublayer 172 material is less than the content of Al atoms in the first functional sublayer 171 material. This gradient of Al atom content can be used to adjust the polarization difference, so that the 2DEG concentration in the area between the gate 14 and the channel layer 11 is reduced, which is easier to deplete and the switching is more agile; it can also reduce the polarization charge density in the heterojunction in the edge area of ​​the gate 14, thereby reducing the peak value of the electric field on the gate 14 and the drain 13 side, avoiding electrons from bombarding the dielectric layer of the semiconductor device 100 under the action of high field, thereby improving the reliability of the semiconductor device 100.

[0089] In some embodiments, a dimension L1 of the first functional sublayer 171 along the second direction X is greater than a dimension L2 of the second functional sublayer 172 along the second direction X, that is, L1>L2. The second direction X is the arrangement direction from the gate 14 to the drain 13.

[0090] It can be understood that L1>L2 indicates that the first functional sublayer 171 extends longer in the second direction X, so that the polarization effect is better in the area near the gate 14, so that the 2DEG near the gate 14 is less, and the electron concentration in the area near the gate 14 can be reduced, thereby avoiding higher field spikes caused by high electron density, reducing damage to the semiconductor device 100 under higher fields, and improving the stability and reliability of the semiconductor device 100.

[0091] In some embodiments, a dimension D1 of the first functional sublayer 171 along the first direction Y ranges from 1 nm to 20 nm. The first direction Y is the thickness direction of the substrate 10 .

[0092] Exemplarily, the dimension D1 of the first functional sublayer 171 along the first direction Y may be 1 nm, 4 nm, 8 nm, 12 nm, 14 nm, or 20 nm, etc., which is not limited here.

[0093] In some embodiments, a dimension D2 of the second functional sublayer 172 along the first direction Y ranges from 1 nm to 20 nm. The first direction Y is the thickness direction of the substrate 10 .

[0094] Exemplarily, the dimension D2 of the second functional sublayer 172 along the first direction Y may be 1 nm, 4 nm, 8 nm, 12 nm, 14 nm, or 20 nm, etc., which is not limited here.

[0095] It can be understood that by setting the value range of the dimension D1 of the first functional sublayer 171 along the first direction Y to be within 1nm~20nm and the value range of the dimension D2 of the second functional sublayer 172 along the first direction Y to be within 1nm~20nm, the polarization effect of the barrier layer 12 can be neutralized, the distribution of the interface electric field can be adjusted, and mechanical stress can be improved, defects can be reduced, and the electron migration path can be adjusted, thereby improving the high voltage resistance and high-speed switching performance of the semiconductor device 100.

[0096] In some embodiments, a dimension D of the functional layer 17 along the first direction Y is less than or equal to a dimension H of the p-GaN layer 16 along the first direction Y, that is, D<H. The first direction Y is the thickness direction of the substrate 10 .

[0097] It can be understood that when the functional layer 17 includes the first functional sublayer 171 and the second functional sublayer 172, D1+D2<H, and the dimension in the first direction Y can be understood as the thickness of the film layer, that is, the thickness D of the functional layer 17 cannot exceed the thickness H of the p-GaN layer 16. This ensures that the functional layer 17 is completely within the p-GaN layer 16 or flush with it and does not exceed it, and ensures good contact and interface continuity between the functional layer 17 and the p-GaN layer 16, reduces interface defects, and ensures the structural integrity and connection reliability of the semiconductor device 100.

[0098] In some embodiments, as Figure 5 As shown, in the second direction X, the p-GaN layer 16 partially overlaps with the functional layer 17 . The second direction X is the arrangement direction from the gate 14 to the drain 13 .

[0099] As can be understood, on the one hand, the p-GaN layer 16 and the functional layer 17 have a certain overlap area in the arrangement direction of the gate 14 and the drain 13, which can ensure good contact between the p-GaN layer 16 and the functional layer 17, improve the interface quality, and help neutralize the polarization effect of the barrier layer 12. On the other hand, it facilitates the preparation process of the p-GaN layer 16 and the functional layer 17, improving the process feasibility.

[0100] In some embodiments, the first functional sublayer 171 includes a first sidewall 1711 and a second sidewall 1712 disposed along the second direction X, and the second functional sublayer 172 includes a third sidewall 1721 and a fourth sidewall 1722 disposed along the second direction X.

[0101] The first side wall 1711 and the third side wall 1721 are coplanar. In the second direction X, the distance P1 between the second side wall 1712 and the drain 13 is smaller than the distance P2 between the fourth side wall 1722 and the drain 13 , that is, P1 < P2.

[0102] It can be understood that the first side wall 1711 and the third side wall 1721 are arranged in the same plane, and P1<P2, which means that the functional layer 17 near the gate 14 area is wider, which can reduce the electron density in the area near the edge of the gate 14, further deplete it faster, make the switch more agile, and reduce energy consumption.

[0103] In some embodiments, the p-GaN layer 16 partially overlaps the barrier layer 12 .

[0104] It can be understood that when the p-GaN layer 16 partially overlaps with the barrier layer 12, the thickness of the barrier layer 12 is reduced, so that the polarization charge is reduced, resulting in a decrease in the 2DEG concentration in this region, weakening the polarization effect of the barrier layer 12, reducing the polarization charge, and reducing the interface electron density, making it difficult to achieve the on state at the same voltage, so that a larger bias voltage is required, which increases the threshold voltage of the semiconductor device 100.

[0105] In some embodiments, as Figure 6 As shown, the semiconductor device 100 further includes an auxiliary layer 18 . The auxiliary layer 18 is disposed on a side of the barrier layer 12 away from the channel layer 11 .

[0106] The material of the auxiliary layer 18 includes AlN.

[0107] Exemplarily, the dimension A of the auxiliary layer 18 in the first direction Y ranges from 0.5 nm to 1.5 nm. The first direction Y is the thickness direction of the substrate 10 .

[0108] It is understandable that, on the one hand, during the manufacturing process, the auxiliary layer 18 can block or slow down etching, thereby preventing damage to the barrier layer 12. On the other hand, compared to the AlGaN material of the barrier layer 12 and the AlGaN or GaN material of the functional layer 17, AlN has a higher polarization constant and a higher polarization charge density, providing a higher potential barrier, making it difficult for electrons to migrate directly from the channel layer 11 to the gate 14 region. Electrons are more likely to migrate along the channel layer 11 rather than penetrate the auxiliary layer 18 to the gate 14, effectively reducing current leakage (leakage current) and improving the voltage resistance of the semiconductor device 100.

[0109] In another aspect, a method for manufacturing a semiconductor device 100 is provided. Figure 8 ,like Figure 7 As shown, the method for manufacturing the semiconductor device 100 includes: S1 to S5.

[0110] S1 : forming a channel layer 11 on one side of a substrate 10 .

[0111] S2 : forming a barrier layer 12 on a side of the channel layer 11 away from the substrate 10 .

[0112] S3 : forming a functional layer 17 on a side of the barrier layer 12 away from the channel layer 11 .

[0113] S4 : forming a p-GaN layer 16 on the side of the barrier layer 12 away from the channel layer 11 .

[0114] S5: forming a source 15, a drain 13, and a gate 14 disposed between the source 15 and the drain 13. The gate 14 is disposed on the side of the p-GaN layer 16 away from the substrate 10. The source 15 and the drain 13 are disposed on the side of the barrier layer 12 or the channel layer 11 away from the substrate 10. The functional layer 17 is disposed between the p-GaN layer 16 and the drain 13. The functional layer 17 is also in contact with the p-GaN layer 16. The material of the functional layer 17 includes: Al y Ga (1-y) N. The materials of the barrier layer 12 include: Al x Ga (1-x) N; x>y, and y can be 0.

[0115] It can be understood that the beneficial effects achieved by the method for preparing the semiconductor device 100 provided in the above embodiment of the present disclosure can be referred to the beneficial effects of the semiconductor structure described above, and will not be repeated here.

[0116] In some embodiments, as Figure 9 As shown, S4 forms a p-GaN layer 16 on a side of the barrier layer 12 away from the channel layer 11 , including: S4.1 to S4.3.

[0117] S4.1: Depositing a mask material on a side of the barrier layer 12 away from the channel layer 11 and a side of the functional layer 17 away from the barrier layer 12 .

[0118] Exemplarily, the mask material includes silicon nitride, silicon oxide, etc., and the mask thickness is between 100 nm and 1000 nm.

[0119] S4.2: removing the mask material in the region of the pre-formed p-GaN layer 16 and the mask material in the region of the functional layer 17 close to the pre-formed p-GaN layer 16 on the side away from the barrier layer 12 .

[0120] S4.3: depositing p-GaN layer 16 material in the pre-formed p-GaN layer 16 region and in the region of the functional layer 17 close to the pre-formed p-GaN layer 16 on the side away from the barrier layer 12 to form the p-GaN layer 16 .

[0121] Here, the thickness of the p-GaN layer 16 is not greater than the thickness of the mask. P-type doping can be achieved by, but not limited to, Mg. After deposition is complete, the mask is retained and the metal material of the gate 14 can be directly deposited on the p-GaN layer 16.

[0122] In some embodiments, S3 forms a functional layer 17 on a side of the barrier layer 12 away from the channel layer 11, including:

[0123] A first functional sublayer 171 and a second functional sublayer 172 are formed. The first functional sublayer 171 and the second functional sublayer 172 are arranged adjacent to each other, and the second functional sublayer 172 is arranged on the side of the first functional sublayer 171 away from the barrier layer 12. The content of Al atoms in the material of the first functional sublayer 171 is greater than or equal to the content of Al atoms in the material of the first functional sublayer 171.

[0124] For example, combined Figure 7 To form the first functional sublayer 171 and the second functional sublayer 172 , the initial first functional sublayer 171A and the initial second functional sublayer 172A can be formed first, and then the initial first functional sublayer 171A and the initial second functional sublayer 172A are etched to obtain the first functional sublayer 171 and the second functional sublayer 172 .

[0125] An embodiment of the present disclosure further provides a chip, which includes a semiconductor device 100 .

[0126] It can be understood that the beneficial effects that can be achieved by the chip provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor device 100 mentioned above, and will not be repeated here.

[0127] Example 1

[0128] Embodiment 1 provides a semiconductor device 100, see Figure 10, the semiconductor device 100 includes:

[0129] (1) Substrate 10.

[0130] (2) The channel layer 11 on one side of the substrate 10 has a thickness of 300 nm and is made of GaN.

[0131] (3) The barrier layer 12 on the side of the channel layer 11 away from the substrate 10 has a thickness of 10 nm and is made of Al x Ga (1-x) N,x is 0.2.

[0132] (4) The functional layer 17 on the side of the barrier layer 12 away from the channel layer 11 has a thickness of 5 nm and is made of Al y Ga (1-y) N,y is 0.15.

[0133] (5) The passivation layer 19 on the side of the barrier layer 12 and the functional layer 17 away from the channel layer 11 has a thickness of 50 nm and is made of SiOx.

[0134] (6) The p-GaN layer 16 on the side of the barrier layer 12 away from the channel layer 11 .

[0135] (7) A source electrode 15 , a drain electrode 13 , and a gate electrode 14 disposed between the source electrode 15 and the drain electrode 13 . The gate electrode 14 is disposed on a side of the p-GaN layer 16 away from the substrate 10 . The source electrode 15 and the drain electrode 13 are disposed on a side of the barrier layer 12 or the channel layer 11 away from the substrate 10 . A functional layer 17 is disposed between the p-GaN layer 16 and the drain electrode 13 , and the functional layer 17 is also in contact with and connected to the p-GaN layer 16 .

[0136] Here, the thickness of each film layer of the channel layer 11 , the barrier layer 12 , the functional layer 17 and the passivation layer 19 is the size of each film layer along the first direction Y, and the first direction Y is the thickness direction of the substrate 10 .

[0137] Example 2

[0138] Embodiment 2 provides a semiconductor device 100, see Figure 10 The film layer arrangement of the semiconductor device 100 is the same as that of the semiconductor device 100 in Example 1, except that the material of the functional layer 17 is Al y Ga (1-y) N,y is 0.1.

[0139] Example 3

[0140] Embodiment 3 provides a semiconductor device 100, see Figure 10 The film layer arrangement of the semiconductor device 100 is the same as that of the semiconductor device 100 in Example 1, except that the material of the functional layer 17 is Aly Ga (1-y) N,y is 0.05.

[0141] Example 4

[0142] Embodiment 4 provides a semiconductor device 100, see Figure 10 The film layer configuration of the semiconductor device 100 is the same as that of the semiconductor device 100 in Example 1, with the only difference being that the material of the functional layer 17 is GaN, ie, y is 0.

[0143] Example 5

[0144] Embodiment 5 provides a semiconductor device 100, see Figure 10 The film layer configuration of the semiconductor device 100 is the same as that of the semiconductor device 100 in Example 2, with the only difference being that the thickness of the functional layer 17 is 1 nm.

[0145] Example 6

[0146] Embodiment 6 provides a semiconductor device 100, see Figure 10 The film layer configuration of the semiconductor device 100 is the same as that of the semiconductor device 100 in Example 2, with the only difference being that the thickness of the functional layer 17 is 2 nm.

[0147] Example 6

[0148] Embodiment 6 provides a semiconductor device 100, see Figure 10 The film layer configuration of the semiconductor device 100 is the same as that of the semiconductor device 100 in Example 2, with the only difference being that the thickness of the functional layer 17 is 2 nm.

[0149] Example 7

[0150] Embodiment 7 provides a semiconductor device 100, see Figure 10 The film layer configuration of the semiconductor device 100 is the same as that of the semiconductor device 100 in Example 2, with the only difference being that the thickness of the functional layer 17 is 3 nm.

[0151] Example 8

[0152] Embodiment 8 provides a semiconductor device 100, see Figure 10 The film layer configuration of the semiconductor device 100 is the same as that of the semiconductor device 100 in Example 2, with the only difference being that the thickness of the functional layer 17 is 4 nm.

[0153] Example 9

[0154] Embodiment 9 provides a semiconductor device 100, see Figure 10The film layer configuration of the semiconductor device 100 is the same as that of the semiconductor device 100 in Example 2, with the only difference being that the thickness of the functional layer 17 is 6 nm.

[0155] Example 10

[0156] Embodiment 10 provides a semiconductor device 100, see Figure 10 The film layer configuration of the semiconductor device 100 is the same as that of the semiconductor device 100 in Example 2, with the only difference being that the thickness of the functional layer 17 is 7 nm.

[0157] Example 11

[0158] Embodiment 11 provides a semiconductor device 100, see Figure 10 The film layer configuration of the semiconductor device 100 is the same as that of the semiconductor device 100 in Example 2, with the only difference being that the thickness of the functional layer 17 is 8 nm.

[0159] Example 12

[0160] Embodiment 12 provides a semiconductor device 100, see Figure 10 The film layer configuration of the semiconductor device 100 is the same as that of the semiconductor device 100 in Example 2, with the only difference being that the thickness of the functional layer 17 is 9 nm.

[0161] Example 13

[0162] Embodiment 13 provides a semiconductor device 100, see Figure 10 The film layer configuration of the semiconductor device 100 is the same as that of the semiconductor device 100 in Example 2, with the only difference being that the thickness of the functional layer 17 is 10 nm.

[0163] From Figure 10 In the direction indicated by the dotted arrow, the 2DEG concentration of the channel layer 11 of the embodiment of the simulation test is as follows: Figures 11 to 13 As shown, Figure 11 is an energy band structure diagram of the semiconductor device 100 according to Examples 1 to 4, the difference between the horizontal axes is the thickness of the corresponding film layer, the vertical axis is the conduction band, E f represents the Fermi level, according to Figure 11 get Figure 12 , Figure 12 is an electron density diagram of the semiconductor device 100 according to Embodiment 1 to Embodiment 4; Figure 12 Points obtained Figure 13 , Figure 132DEG concentration diagram of the channel layer 11 of the semiconductor device 100 according to Examples 1 to 4; it can be seen that as the Al atom content in the functional layer 17 between the channel layer 11 and the barrier layer 12 decreases, the electron density of the semiconductor device 100 decreases, and the 2DEG concentration of the channel layer 11 of the semiconductor device 100 also decreases.

[0164] like Figures 14 to 16 As shown, Figure 14 is an energy band structure diagram of the semiconductor device 100 according to Example 2, Example 5 to Example 13, the difference between the horizontal axes is the thickness of the corresponding film layer, the vertical axis is the conduction band, E f represents the Fermi level, according to Figure 14 get Figure 15 , Figure 15 According to the electron density diagram of the semiconductor device 100 of embodiment 2, embodiment 5 to embodiment 13; Figure 15 Points obtained Figure 16 , Figure 16 This is a 2DEG concentration diagram of the channel layer 11 of the semiconductor device 100 according to Example 6, Example 8, Example 9, Example 11, and Example 13; it can be seen that as the thickness of the functional layer 17 between the channel layer 11 and the barrier layer 12 increases, the electron density of the semiconductor device 100 decreases, and the 2DEG concentration of the channel layer 11 of the semiconductor device 100 also decreases.

[0165] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate, a channel layer, and a barrier layer are stacked in sequence; as well as, A p-GaN layer is provided on a side of the barrier layer away from the channel layer; a source electrode, a drain electrode, and a gate electrode disposed between the source electrode and the drain electrode, wherein the gate electrode is disposed on a side of the p-GaN layer away from the substrate, and the source electrode and the drain electrode are disposed on a side of the barrier layer or the channel layer away from the substrate; a functional layer, disposed on a side of the barrier layer away from the channel layer and between the p-GaN layer and the drain electrode, the functional layer also being in contact with and connected to the p-GaN layer; Wherein, the material of the functional layer includes: Al y Ga (1-y) N; the material of the barrier layer includes: Al x Ga (1-x) N; x>y, and y≥0; The functional layer includes: a plurality of functional sublayers; the plurality of functional sublayers are stacked along a first direction; the first direction is the thickness direction of the substrate; the plurality of functional sublayers include: a first functional sublayer and a second functional sublayer arranged arbitrarily adjacent to each other, and the second functional sublayer is arranged on the side of the first functional sublayer away from the barrier layer; the size of the first functional sublayer along the second direction is larger than the size of the second functional sublayer along the second direction, and the second direction is the arrangement direction from the gate to the drain.

2. The semiconductor device according to claim 1, wherein The first functional sub-layer material includes: Al y1 Ga (1-y1) N, the second functional sublayer material includes: Al y2 Ga (1-y2) N; and y1≥y2.

3. The semiconductor device according to claim 1, wherein The size of the first functional sublayer and / or the second functional sublayer along a first direction ranges from 1 nm to 20 nm, and the first direction is the thickness direction of the substrate.

4. The semiconductor device according to claim 1, wherein A dimension of the functional layer along a first direction is smaller than or equal to a dimension of the p-GaN layer along the first direction, and the first direction is a thickness direction of the substrate.

5. The semiconductor device according to claim 1, wherein In a second direction, the p-GaN layer partially overlaps with the functional layer, and the second direction is an arrangement direction from the gate to the drain.

6. The semiconductor device according to claim 4, wherein The first functional sublayer includes a first sidewall and a second sidewall arranged along the second direction, and the second functional sublayer includes a third sidewall and a fourth sidewall arranged along the second direction; The first side wall and the third side wall are coplanarly arranged, and in the second direction, the distance between the second side wall and the drain is smaller than the distance between the fourth side wall and the drain.

7. The semiconductor device according to claim 1, wherein The p-GaN layer partially overlaps the barrier layer.

8. The semiconductor device according to claim 1, wherein Also includes: an auxiliary layer, disposed on a side of the barrier layer away from the channel layer; The material of the auxiliary layer includes: AlN.

9. A method for preparing a semiconductor device, characterized in that: include: forming a channel layer on one side of the substrate; forming a barrier layer on a side of the channel layer away from the substrate; as well as, forming a functional layer on a side of the barrier layer away from the channel layer; forming a p-GaN layer on a side of the barrier layer away from the channel layer; A source, a drain, and a gate disposed between the source and the drain are formed, wherein the gate is disposed on a side of the p-GaN layer away from the substrate, the source and the drain are disposed on a side of the barrier layer or the channel layer away from the substrate, and the functional layer is disposed between the p-GaN layer and the drain, and the functional layer is also in contact with the p-GaN layer; wherein the material of the functional layer includes: Al y Ga (1-y) N; the material of the barrier layer includes: Al x Ga (1-x) N; x>y, and y≥0; the functional layer includes: a plurality of functional sublayers; the plurality of functional sublayers are stacked along a first direction; the first direction is the thickness direction of the substrate; the plurality of functional sublayers include: a first functional sublayer and a second functional sublayer arranged arbitrarily adjacent to each other, and the second functional sublayer is arranged on the side of the first functional sublayer away from the barrier layer; the size of the first functional sublayer along the second direction is larger than the size of the second functional sublayer along the second direction, and the second direction is the arrangement direction from the gate to the drain.

10. A chip, characterized in that: include: The semiconductor device according to any one of claims 1 to 8.

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