A silicon carbide MOS structure and its preparation method

Abstract

The present invention relates to the field of MOS semiconductor technology and discloses a silicon carbide MOS structure and a preparation method thereof. The structure comprises a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain, a semiconductor epitaxial layer, a source, and a gate; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P+ layer, an N well layer, and a P well layer; a lightly doped N layer is provided in the middle of the N drift layer of a single MOS cell; the present invention provides a lightly doped N layer in the middle of the N drift layer, introduces a top-tilted arc-shaped profile design on both sides, and uses a photolithography process to precisely control the injection region to effectively disperse the electric field concentration phenomenon at the edge of the N drift layer. This makes the electric field distribution more uniform, improves the breakdown voltage, reduces the local electric field concentration, and significantly improves the breakdown voltage. In addition, the contact between the laterally symmetrical P-layer and the N substrate layer enhances the charge balancing capability and reduces the leakage current.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a silicon carbide MOS structure and a preparation method thereof. Background Art

[0002] Silicon carbide (SiC) VDMOS devices have attracted much attention in the field of power electronics due to their high breakdown voltage, low on-resistance and excellent high-temperature performance.

[0003] An existing patent discloses a semiconductor device and a method for manufacturing a semiconductor device (publication number CN108538732B), which discloses a semiconductor substrate comprising a plurality of semiconductor dies with saw streets between the semiconductor dies. A plurality of bumps are formed on the first surface of the semiconductor dies. An insulating layer is formed between the bumps on the first surface of the semiconductor dies. A portion of the second surface of the semiconductor dies is removed, and a conductive layer is formed on the remaining second surface. The semiconductor substrate is placed on a dicing tape, cut through the saw streets while maintaining the position of the semiconductor dies, and the dicing tape is expanded to allow the semiconductor dies to move and increase the space between the semiconductor dies. An encapsulant is deposited on the semiconductor dies and enters the space between the semiconductor dies. A trench is formed between the semiconductor dies through the encapsulant to separate the semiconductor dies.

[0004] In the technology disclosed in this patent, its planar gate structure is prone to cause local electric field concentration, reducing the breakdown voltage and causing reliability problems; and the drift region doping concentration needs to be balanced between the on-resistance and the breakdown voltage, which is difficult to take into account with existing technologies; high-concentration N-type doping is prone to cause parasitic bipolar conduction, resulting in a latch-up effect, which limits device reliability. Summary of the Invention

[0005] In order to solve the existing technical problems, the present invention provides a silicon carbide MOS structure and a preparation method thereof, which solves the problems in the above-mentioned background technology.

[0006] To solve the above technical problems, according to one aspect of the present invention, more specifically, a silicon carbide MOS structure is provided, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain, a semiconductor epitaxial layer, a source, and a gate; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P+ layer, an N well layer, and a P well layer; a lightly doped N layer is provided in the middle of the N drift layer of a single MOS cell;

[0007] Laterally symmetric P-layers are provided inside a single MOS cell and on the left and right sides of the N drift layer, and the corresponding side cross-sectional profiles of the laterally symmetric P-layers on both sides are arc-shaped; the bottom end of the laterally symmetric P-layer contacts the N substrate layer, and the top ends of the laterally symmetric P-layers on both sides are relatively inclined.

[0008] Furthermore, a heavily doped N layer is formed at the inner bottom of the lightly doped N layer by ion implantation, the bottom of the heavily doped N layer contacts the N substrate layer, and the cross-sectional profile of the heavily doped N layer is semi-elliptical.

[0009] Furthermore, a rectangular N+ layer is formed in the middle area of ​​the lightly doped N layer by ion implantation, and the bottom end of the rectangular N+ layer is in contact with the N substrate layer.

[0010] Furthermore, a heavily doped N-type half layer is formed at the inner bottom of the lightly doped N layer by ion implantation, and the bottom of the heavily doped N-type half layer contacts the N substrate layer; the top middle part of the cross-sectional profile of the heavily doped N-type half layer is semicircular, and both sides of the top are inclined.

[0011] Furthermore, a complementary P-layer is formed on the outer edge of the heavily doped N-type layer by ion implantation, the bottom of the complementary P-layer contacts the N substrate layer, and the opposite sides of the two complementary P-layers are complementary to the two sides of the heavily doped N layer.

[0012] Furthermore, gradient P- layers are formed on both sides of the rectangular N+ layer by ion implantation, and the opposite sides of the two gradient P- layers are in contact with the two sides of the rectangular N+ layer respectively. The cross-sectional profiles of the opposite sides of the two gradient P- layers are arc-shaped and increase from top to bottom.

[0013] Furthermore, a concave P-layer is formed in the middle area of ​​the heavily doped N-type half layer by ion implantation, the bottom of the concave P-layer contacts the N substrate layer, and the top of the cross-section of the concave P-layer is a concave arc surface.

[0014] Furthermore, lightly doped trapezoidal N layers are formed on both sides of the concave P-layer by ion implantation, the top of the lightly doped trapezoidal N layer is an inclined surface, and the top of the lightly doped trapezoidal N layer is parallel to both sides of the bottom of the lightly doped N layer.

[0015] A silicon carbide MOS structure and a preparation method thereof, comprising:

[0016] S1. epitaxially growing an N substrate layer, an N drift layer, a P+ layer, an N well layer, and a P well layer in sequence on the semiconductor epitaxial layer by chemical vapor deposition;

[0017] S2, forming a lightly doped N layer in the middle region of the N drift layer by low-dose nitrogen ion implantation, followed by high-temperature annealing to activate the doped ions;

[0018] S3. Using a photolithography process, arc-shaped mask windows with tilted tops are defined on both sides of the N drift layer. Boron ion implantation is then performed to form a laterally symmetrical P-layer, ensuring that its bottom end is in contact with the N substrate layer. An annealing process is performed after the ion implantation to repair lattice damage.

[0019] S4, forming a heavily doped N layer in the bottom region of the lightly doped N layer by high-dose nitrogen ion implantation, and performing high-temperature annealing after the ion implantation to activate the impurities;

[0020] S5. In the bottom area of ​​the heavily doped N layer, boron ions are implanted using a concave arc mask window to form a concave P-layer, followed by annealing.

[0021] S6. Implanting nitrogen ions into the bottom region of the heavily doped N layer and on both sides of the concave P-layer using photolithography and ion implantation processes to form a lightly doped N-type half layer, and performing annealing after the implantation.

[0022] S7. Deposit and pattern the metal layers in sequence through photolithography or sputtering process to form ohmic contacts and Schottky contacts of the drain, source and gate.

[0023] The present invention provides a silicon carbide MOS structure and a preparation method thereof. Compared with the prior art, the present method achieves the following effects:

[0024] 1. The present invention arranges a lightly doped N layer in the middle of the N drift layer and introduces an arc-shaped profile design with an inclined top on both sides. The injection area is precisely controlled by the photolithography process to effectively disperse the electric field concentration phenomenon at the edge of the N drift layer. This makes the electric field distribution more uniform, improves the breakdown voltage, reduces the local electric field concentration, and significantly improves the breakdown voltage. In addition, the contact between the laterally symmetrical P-layer and the N substrate layer enhances the charge balance capability and reduces the leakage current.

[0025] 2. The present invention introduces a heavily doped N layer at the bottom of the lightly doped N layer and forms a low-resistance channel through high-dose nitrogen ion implantation, thereby increasing the carrier concentration, reducing the on-resistance, and significantly reducing energy loss. The high-temperature annealing process ensures that the impurities are fully activated and the stability of the low-resistance channel is enhanced.

[0026] 3. The present invention optimizes the internal electric field of the heavily doped N-type half layer by implanting a concave P-layer with a partially arc-shaped top in the heavily doped N layer, thereby achieving local charge compensation, suppressing the parasitic bipolar effect, and enhancing the device's anti-latch capability while maintaining low on-resistance. The top inclined surfaces of the lightly doped trapezoidal N layers on both sides are matched with the electric field direction to reduce electric field distortion, further improve the breakdown voltage, and maintain low on-resistance characteristics.

[0027] 4. The present invention adopts a special composite profile with a top semicircle of a heavily doped N-type half layer and inclined profiles on both sides, which shortens the carrier migration path and reduces the switching time, making it suitable for high-frequency applications. At the same time, the complementary P-layer enhances the charge balance capability and reduces the minority carrier storage effect. The gradient P-layer optimizes the electric field distribution, reduces the reverse recovery charge, and reduces the switching loss by 20%-30%, thereby improving efficiency.

[0028] 5. The present invention adopts a rectangular P-layer to neutralize high-concentration electrons, thereby suppressing the parasitic bipolar effect and improving the anti-latch capability, thereby avoiding accidental failure of the device and being suitable for high-reliability scenarios such as automotive electronics. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Schematic diagram of the structure of implementation 1 of the present invention;

[0030] Figure 2 Schematic diagram of the structure of implementation 2 of the present invention;

[0031] Figure 3 Schematic diagram of the structure of implementation 3 of the present invention;

[0032] Figure 4 It is a structural diagram of implementation 4 of the present invention;

[0033] Figure 5 Schematic diagram of the structure of implementation 5 of the present invention;

[0034] Figure 6 Schematic diagram of the structure of implementation 6 of the present invention;

[0035] Figure 7 Schematic diagram of the structure of implementation 7 of the present invention;

[0036] Figure 8 Schematic diagram of the structure of implementation 8 of the present invention.

[0037] In the figure: 1. Drain; 2. N substrate layer; 3. N drift layer; 4. Source; 5. Gate; 6. Lightly doped N layer; 7. Laterally symmetrical P-layer; 8. P+ layer; 9. N well layer; 10. P well layer; 11. Heavily doped N layer; 12. Rectangular N+ layer; 13. Heavily doped N-type half layer; 14. Complementary P-layer; 15. Gradient P-layer; 16. Concave P-layer; 17. Lightly doped trapezoidal N layer. DETAILED DESCRIPTION

[0038] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] like Figures 1-8According to one aspect of the present invention, a silicon carbide MOS structure and a method for preparing the same are provided, including:

[0040] Step 1: Epitaxially grow an N substrate layer 2, an N drift layer 3, a P+ layer 8, an N well layer 9, and a P well layer 10 in sequence on the semiconductor epitaxial layer by chemical vapor deposition; epitaxially grow an N substrate layer 2, an N drift layer 3, a P+ layer 8, an N well layer 9, and a P well layer 10 in sequence by chemical vapor deposition to construct the basic epitaxial structure of the device, ensuring that the thickness and doping concentration of each functional layer are controllable.

[0041] Step 2: Low-dose nitrogen ion implantation (energy: 80-150 keV, dose: 5×10¹²-2×10¹³cm⁻²) is performed in the middle region of the N drift layer 3 to form a lightly doped N layer 6, followed by high-temperature annealing at 1600-1800°C in an inert gas environment to activate the doped ions; low-dose nitrogen ion implantation + high-temperature annealing is performed in the middle region of the N drift layer 3 to reduce the drift region resistance and optimize the conduction characteristics.

[0042] Step 3: Use the photolithography process to define arc-shaped mask windows with tilted tops on both sides of the N drift layer 3, and form a laterally symmetrical P-layer 7 through boron ion implantation (energy: 120-250keV, dose: 8×10¹²-3×10¹³cm⁻²) to ensure that its bottom end is in contact with the N substrate layer. After the ion implantation, an annealing process of 1500-1700°C is performed to repair lattice damage; boron ions are implanted through the arc-shaped mask windows with tilted tops on both sides of the N drift layer 3 to form a laterally symmetrical P-layer 7, evenly dispersing the electric field to avoid local electric field concentration, while at the same time contacting the N substrate layer to enhance the charge balance capability.

[0043] Step 4: In the bottom area of ​​the lightly doped N layer 6, high-dose nitrogen ion implantation (energy: 250-350keV, dose: 1×10¹) is performed. 5 -5×10¹ 5 cm⁻²) to form a heavily doped N layer 13, and after ion implantation, high-temperature annealing at 1700-1900°C is performed to activate the impurities; a high-dose nitrogen ion is implanted at the bottom of the lightly doped N layer 6 to form a heavily doped N layer 13, thereby increasing the carrier concentration and reducing the on-resistance, and the impurities are activated by high-temperature annealing.

[0044] Step 5. In the bottom area of ​​the heavily doped N layer 13, a concave arc mask window is used to perform boron implantation (ion implantation energy: 70-120keV, dose: 3×10¹²-1×10¹³cm⁻²) to form a concave P-layer 16, and annealing is performed at 1600-1800°C; the concave P-layer 16 is implanted at the bottom of the heavily doped N layer 13 to neutralize excess electrons, suppress the parasitic bipolar effect, and improve the anti-latch capability.

[0045] Step 6: Nitrogen ions are implanted (energy: 150-200 keV, dose: 5×10¹²-2×10¹³cm⁻²) into the bottom area of ​​the heavily doped N layer 13 and on both sides of the concave P- layer 16 using photolithography and ion implantation processes to form a lightly doped N-type half layer 17. After the implantation, the layer is annealed at 1600-1800°C. Lightly doped N-type half layers 17 are implanted on both sides of the bottom of the heavily doped N layer 13 to form a concentration gradient, optimize the carrier migration path, and reduce conduction loss.

[0046] Step 7: Deposit and pattern the metal layers in sequence through photolithography or sputtering process to form ohmic contacts and Schottky contacts of the drain 1, source 4 and gate 5; form ohmic contacts and Schottky contacts of the drain 1, source 4 and gate 5 through photolithography or sputtering process to achieve electrical connection of the device and ensure good electrical performance and stability.

[0047] Example 1

[0048] like Figure 1 As shown, a variable doping planar gate silicon carbide VDMOS device comprises a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain 1, a semiconductor epitaxial layer, a source 4, and a gate 5; the semiconductor epitaxial layer comprises an N substrate layer 2, an N drift layer 3, a P+ layer 8, an N well layer 9, and a P well layer 10; a lightly doped N layer 6 is provided in the middle of the N drift layer 3 of the single MOS cell; a laterally symmetrical P- layer 7 is provided inside the single MOS cell and on the left and right sides of the N drift layer 3; the corresponding side cross-sectional profiles of the laterally symmetrical P- layers 7 on both sides are arc-shaped; the bottom end of the laterally symmetrical P- layer 7 contacts the N substrate layer 2, and the top ends of the laterally symmetrical P- layers 7 on both sides are relatively inclined;

[0049] The lightly doped N-layer 6 is formed by low-dose nitrogen ion implantation to reduce drift region resistance. The arc-shaped, laterally symmetrical P-layer 7, with its tilted top, is formed by boron ion implantation through a mask window defined by photolithography. Photolithography enables highly precise pattern transfer, ensuring the shape and position of the P-layer meet design requirements. Following boron ion implantation, a high-temperature annealing process repairs lattice defects, effectively activates the doped ions, and ensures stable performance of the P-layer.

[0050] This structure optimizes the device's electric field distribution by placing a lightly doped N layer 6 within the N drift layer and introducing arc-shaped, laterally symmetric P-layers 7 with tilted tops on either side. This significantly improves the localized electric field concentration often seen in conventional devices, effectively increasing the device's breakdown voltage. Furthermore, the contact between the laterally symmetric P-layer 7 and the N substrate layer 2 enhances charge balance, reduces leakage current, and improves device reliability and stability.

[0051] Example 2

[0052] like Figure 2 As shown, a heavily doped N layer 11 is formed at the inner bottom of the lightly doped N layer 6 by ion implantation. The bottom of the heavily doped N layer 11 contacts the N substrate layer 2. The cross-sectional profile of the heavily doped N layer 11 is semi-elliptical.

[0053] High-dose nitrogen ion implantation is used to form a heavily doped N layer 11 at the bottom of the lightly doped N layer. High-dose implantation can significantly increase carrier concentration, which is crucial for reducing on-resistance. After implantation, a high-temperature annealing treatment at 1700-1900°C fully activates the impurities, forming a low-resistance channel within the device. During operation, this low-resistance channel effectively reduces energy loss caused by current flow, thereby reducing conduction losses and improving the device's energy conversion efficiency.

[0054] The introduction of a heavily doped N layer 11 at the bottom of the lightly doped N layer 6 not only further reduces the on-resistance, but also improves the carrier injection efficiency through high-concentration doping. The improvement in carrier injection efficiency enables the device to respond to signal changes more quickly during the switching process, significantly improving the switching performance of the device and making it perform better in high-frequency application scenarios.

[0055] Example 3

[0056] like Figure 3 As shown, a rectangular N+ layer 12 is formed in the middle area of ​​the lightly doped N layer 6 by ion implantation, and the bottom end of the rectangular N+ layer 12 contacts the N substrate layer 2. Boron ions are implanted through a rectangular mask window to form a rectangular P- layer 12 in the middle of the heavily doped N layer.

[0057] During the operation of semiconductor devices, the presence of high-concentration electrons may lead to an imbalance in charge distribution and produce adverse effects;

[0058] This structure achieves local charge compensation by implanting a rectangular P-layer 12 into the heavily doped N-layer 11 and using hole injection to neutralize high-concentration electrons.

[0059] Charge compensation effectively suppresses the parasitic bipolar effect, which may cause device performance degradation or even failure. Suppressing this effect can enhance the device's anti-latch capability. At the same time, since the previous structural design has reduced the on-resistance, this improvement further improves the device's overall performance and stability while maintaining low on-resistance.

[0060] Example 4

[0061] like Figure 4 As shown, a heavily doped N-type half layer 13 is formed at the bottom of the lightly doped N-layer 6 by ion implantation, and the bottom of the heavily doped N-type half layer 13 contacts the N substrate layer 2; the top middle portion of the cross-sectional profile of the heavily doped N-type half layer 13 is semicircular, and both sides of the top are inclined;

[0062] This unique shape design can further optimize the current conduction path when the heavily doped N-type half layer 13 cooperates with the surrounding structure;

[0063] After the structure is formed by ion implantation, it is combined with high-temperature annealing treatment to fully activate the doping ions and stably distribute them;

[0064] The heavily doped N-type half layer 13 increases the carrier concentration at the bottom of the lightly doped N-layer 6, thereby reducing the on-resistance to a certain extent without affecting other device performance. At the same time, it also plays a role in fine-tuning the electric field distribution, so that the device can maintain good performance under different operating conditions.

[0065] Example 5

[0066] like Figure 5 As shown, a complementary P-layer 14 is formed on the outer edge of the heavily doped N-type layer 11 by ion implantation. The bottom of the complementary P-layer 14 contacts the N substrate layer 2, and the opposite sides of the two complementary P-layers 14 are complementary to the two sides of the heavily doped N-layer 11.

[0067] The introduction of the complementary P-layer 14 further optimizes the charge distribution within the device. Through ion implantation and high-temperature annealing processes, the doping concentration and performance stability of the complementary P-layer 14 are ensured.

[0068] The complementary P-layer 14 cooperates with the heavily doped N-type half layer 13 and the heavily doped N layer 11 to enhance the charge balance capability and effectively suppress the generation of leakage current. At the same time, this structural design improves the electric field distribution of the device to a certain extent, improves the breakdown voltage and reliability of the device, and enables the device to operate stably even in a high-voltage working environment.

[0069] Example 6

[0070] like Figure 6 As shown, gradient P-layers 15 are formed on both sides of the rectangular N+ layer 12 by ion implantation. The opposite sides of the two gradient P-layers 15 are in contact with the two sides of the rectangular N+ layer 12 respectively. The cross-sectional profiles of the opposite sides of the two gradient P-layers 15 are arc-shaped and increase in size from top to bottom.

[0071] The gradient P-layer 15 is formed by precisely controlling the ion implantation dose and process parameters. Its unique gradient doping characteristics can more flexibly adjust the electric field and charge distribution inside the device;

[0072] During device operation, the gradient P-layer 15 effectively disperses the electric field near the rectangular N+ layer 12, preventing localized electric field concentration and further increasing the device's breakdown voltage. Furthermore, the gradient P-layer 15 and the rectangular N+ layer 12 work synergistically to optimize charge compensation, suppress parasitic bipolar effects, and enhance the device's latch-up resistance and overall performance, ensuring excellent stability and reliability even under complex operating conditions.

[0073] Example 7

[0074] like Figure 7 As shown, a concave P-layer 16 is formed in the middle region of the heavily doped N-type half layer 13 by ion implantation. The bottom of the concave P-layer 16 contacts the N substrate layer 2, and the top of the cross-sectional profile of the concave P-layer 16 is a concave arc surface.

[0075] The special shape design of the concave P-layer 16 enables it to generate unique electric field and charge interactions with the surrounding structures inside the device;

[0076] Through ion implantation and high temperature annealing process, the doping uniformity and performance stability of the concave P-layer 16 are guaranteed;

[0077] The concave P-layer 16 can effectively adjust the electric field distribution inside the heavily doped N-type half layer 13, further optimize the charge balance, and reduce leakage current. At the same time, this structural design also has a certain effect on suppressing parasitic effects, improving the anti-interference ability and reliability of the device, and enabling the device to maintain good performance in different working environments.

[0078] Example 8

[0079] like Figure 8 As shown, lightly doped trapezoidal N layers 17 are formed on both sides of the concave P-layer 16 by ion implantation. The top of the lightly doped trapezoidal N layer 17 is an inclined surface, and the top of the lightly doped trapezoidal N layer 17 is parallel to both sides of the bottom of the lightly doped N layer 6.

[0080] The introduction of the lightly doped trapezoidal N layer 17 further improves the internal structural design of the device.

[0081] By precisely controlling the ion implantation process, a lightly doped trapezoidal N layer 17 with a specific doping concentration and shape is formed.

[0082] This structure cooperates with the concave P-layer 16, the heavily doped N-type half layer 13, etc. to optimize the current conduction path and reduce the on-resistance. At the same time, the lightly doped trapezoidal N layer 17 also plays a further regulatory role in the electric field distribution of the device, thereby improving the breakdown voltage and switching performance of the device, enabling the device to exert better performance advantages in high-voltage, high-frequency and other application scenarios.

[0083] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A silicon carbide MOS structure, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain (1), a semiconductor epitaxial layer, a source (4) and a gate (5); the semiconductor epitaxial layer comprises an N substrate layer (2), an N drift layer (3), a P+ layer (8), an N well layer (9) and a P well layer (10), characterized in that: A lightly doped N layer (6) is provided in the middle of the N drift layer (3) of a single MOS cell; A lateral symmetrical P-layer (7) is provided inside a single MOS cell and on the left and right sides of the N drift layer (3), and the corresponding side cross-sectional profiles of the lateral symmetrical P-layer (7) on both sides are arc-shaped; the bottom end of the lateral symmetrical P-layer (7) contacts the N substrate layer (2), and the top ends of the lateral symmetrical P-layer (7) on both sides are relatively inclined; The bottom end of the lightly doped N layer (6) is formed with a heavily doped N-type half layer (13) by ion implantation, and the bottom end of the heavily doped N-type half layer (13) is in contact with the N substrate layer (2); the top middle portion of the cross-sectional profile of the heavily doped N-type half layer (13) is semicircular, and both sides of the top are inclined; A concave P-layer (16) is formed in the middle region of the heavily doped N-type half layer (13) by ion implantation, the bottom of the concave P-layer (16) contacts the N substrate layer (2), and the top of the cross-sectional profile of the concave P-layer (16) is a concave arc surface; Lightly doped trapezoidal N layers (17) are formed on both sides of the concave P-layer (16) by ion implantation, the top of the lightly doped trapezoidal N layer (17) is an inclined surface, and the top of the lightly doped trapezoidal N layer (17) is parallel to both sides of the bottom of the lightly doped N layer (6).

2. A silicon carbide MOS structure, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain (1), a semiconductor epitaxial layer, a source (4) and a gate (5); the semiconductor epitaxial layer comprises an N substrate layer (2), an N drift layer (3), a P+ layer (8), an N well layer (9) and a P well layer (10), characterized in that: A lightly doped N layer (6) is provided in the middle of the N drift layer (3) of a single MOS cell; A lateral symmetrical P-layer (7) is provided inside a single MOS cell and on the left and right sides of the N drift layer (3), and the corresponding side cross-sectional profiles of the lateral symmetrical P-layer (7) on both sides are arc-shaped; the bottom end of the lateral symmetrical P-layer (7) contacts the N substrate layer (2), and the top ends of the lateral symmetrical P-layer (7) on both sides are relatively inclined; A heavily doped N layer (11) is formed at the inner bottom of the lightly doped N layer (6) by ion implantation, the bottom of the heavily doped N layer (11) is in contact with the N substrate layer (2), and the cross-sectional profile of the heavily doped N layer (11) is in a semi-elliptical shape; A complementary P-layer (14) is formed on the outer edge of the heavily doped N layer (11) by ion implantation, the bottom of the complementary P-layer (14) is in contact with the N substrate layer (2), and the opposite sides of the two complementary P-layers (14) are complementary to the two sides of the heavily doped N layer (11).

3. A silicon carbide MOS structure, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain (1), a semiconductor epitaxial layer, a source (4) and a gate (5); the semiconductor epitaxial layer comprises an N substrate layer (2), an N drift layer (3), a P+ layer (8), an N well layer (9) and a P well layer (10), characterized in that: A lightly doped N layer (6) is provided in the middle of the N drift layer (3) of a single MOS cell; A lateral symmetrical P-layer (7) is provided inside a single MOS cell and on the left and right sides of the N drift layer (3), and the corresponding side cross-sectional profiles of the lateral symmetrical P-layer (7) on both sides are arc-shaped; the bottom end of the lateral symmetrical P-layer (7) contacts the N substrate layer (2), and the top ends of the lateral symmetrical P-layer (7) on both sides are relatively inclined; A rectangular N+ layer (12) is formed in the inner middle region of the lightly doped N layer (6) by ion implantation, and the bottom end of the rectangular N+ layer (12) is in contact with the N substrate layer (2); Gradient P-layers (15) are formed on both sides of the rectangular N+ layer (12) by ion implantation, and the opposite sides of the two gradient P-layers (15) are in contact with the two sides of the rectangular N+ layer (12) respectively. The cross-sectional profiles of the opposite sides of the two gradient P-layers (15) are in an arc shape and increase in order from top to bottom.

4. A method for preparing a silicon carbide MOS structure, characterized in that: The silicon carbide thick bottom oxide layer trench MOS structure according to claim 1 comprises the following steps: S1. epitaxially growing an N substrate layer (2), an N drift layer (3), a P+ layer (8), an N well layer (9), and a P well layer (10) in sequence on a semiconductor epitaxial layer by chemical vapor deposition; S2, forming a lightly doped N layer (6) in the middle region of the N drift layer (3) by low-dose nitrogen ion implantation, followed by high-temperature annealing to activate the doped ions; S3, using a photolithography process to define arc-shaped mask windows with tilted tops on both sides of the N drift layer (3), forming a side-symmetrical P-layer (7) by boron ion implantation to ensure that its bottom end contacts the N substrate layer, and performing an annealing process after the ion implantation to repair lattice damage; S4, forming a heavily doped N layer (13) in the bottom region of the lightly doped N layer (6) by high-dose nitrogen ion implantation, and performing high-temperature annealing after the ion implantation to activate the impurities; S5, in the bottom area of ​​the heavily doped N layer (13), using a concave arc mask window to perform boron ion implantation to form a concave P-layer (16), and annealing treatment; S6, using photolithography and ion implantation processes, implanting nitrogen ions into the bottom region of the heavily doped N layer (13) and on both sides of the concave P-layer (16) to form a lightly doped N-type half layer (17), and performing annealing after the implantation; S7. Depositing and patterning metal layers in sequence through photolithography or sputtering process to form ohmic contacts and Schottky contacts of the drain (1), source (4) and gate (5).

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