Display device

Abstract

A display device according to one example includes: a substrate including a display area including a plurality of pixels and a non-display area surrounding the display area; a protruding pattern disposed on the substrate and located at a boundary of adjacent pixels; an anode electrode disposed on each of the pixels on the substrate; a bank disposed on the anode electrode and exposing the protruding pattern; and an organic layer disposed on the anode electrode and the bank, in which the organic layer is separated at a boundary of the pixel.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0021109, filed on February 14, 2024. Technical Field

[0003] The present application relates to a display device, and more particularly, to a display device capable of preventing lateral leakage current generated at a boundary between adjacent pixels. Background Art

[0004] With the development of the information society, various demands on display devices for displaying images are increasing, and various types of display devices such as liquid crystal display (LCD) devices and organic light emitting diode (OLED) display devices are used.

[0005] Among display devices, self-luminous OLED displays offer advantages over LCDs in that they have wider viewing angles, higher contrast, are lighter and thinner, and consume less power because they do not require a separate backlight. OLED displays also have the advantages of being capable of DC low-voltage drive, having a fast response time, and, in particular, being inexpensive to manufacture.

[0006] Recently, there has been a trend to increase the resolution of OLED display devices to obtain clearer image quality. Summary of the Invention

[0007] The present application aims to provide a display device in which the lateral leakage current between adjacent pixels can be minimized.

[0008] The present application also aims to provide a display device in which an organic layer can be easily separated / discontinuous by a protrusion pattern located at a boundary between pixels and a protrusion of a first passivation layer.

[0009] The present application also aims to provide a display device in which an organic layer can be easily separated / discontinuous by removing a bank, a planarization layer, etc. from a boundary between pixels to expose a protruding pattern.

[0010] The purpose of this application is not limited to the above-mentioned purpose, and other technical purposes can be inferred from the following examples.

[0011] According to one example, a display device for achieving the purpose includes: a substrate, the substrate including a display area and a non-display area, the display area including a plurality of pixels, and the non-display area surrounding the display area; a protruding pattern, the protruding pattern being arranged on the substrate and located at the boundary of adjacent pixels; an anode electrode, the anode electrode being arranged on each pixel on the substrate; a partition bank, the partition bank being arranged on the anode electrode and exposing the protruding pattern; and an organic layer, the organic layer being arranged on the partition bank, wherein the organic layer is separated (discontinuous) at the boundary of the pixel.

[0012] According to one example, a display device for achieving the purpose includes: a substrate, the substrate including a display area and a pad area, the display area including a plurality of pixels, the pad area being close to the display area; a first conductive layer on the substrate, the first conductive layer including a data line and a light blocking layer; a semiconductor layer on the first conductive layer, the semiconductor layer overlapping the light blocking layer; a gate insulating layer on the semiconductor layer; a second conductive layer on the gate insulating layer, the second conductive layer including a first pad electrode arranged in the pad area, a gate electrode overlapping with a channel area of the semiconductor layer, a source electrode connected to a source area of the semiconductor layer, and a drain electrode connected to a drain area of the semiconductor layer; a first passivation layer, the first passivation layer being arranged on the second conductive layer; and a third conductive layer, the third conductive layer being arranged on the first passivation layer and including a second pad electrode on the first pad electrode arranged in the pad area and a protruding pattern located at a boundary of the pixel.

[0013] The display device according to the example may include a protruding pattern located at the boundary between adjacent pixels. When forming the second pad electrode, etc., the protruding pattern can be formed together and can have a width greater than the protrusion of the first passivation layer, using the protruding pattern as a mask to form the protrusion of the first passivation layer. The organic layer of the organic light-emitting element of the display device is deposited integrally on all pixels, and due to the steps formed by the protrusion and the protruding pattern / layer, the organic layer can be separated / discontinuous at the boundary between adjacent pixels. Therefore, the lateral leakage current leaking between adjacent pixels can be minimized.

[0014] The method of manufacturing a display device according to the examples described herein can expose the protruding pattern by removing the second passivation layer, the planarization layer, and the bank on the protruding pattern provided at the boundary between adjacent pixels. Therefore, the organic layer at the boundary between adjacent pixels is easily separated due to the exposed protruding pattern, thereby preventing lateral leakage current.

[0015] In the display device according to the example, it is possible to prevent lateral leakage current leaking between adjacent pixels, thereby increasing a color gamut and preventing display quality defects, thereby increasing the lifespan of the display device.

[0016] However, effects obtainable from the present application are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood from the following description by those skilled in the art to which the present application pertains. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a plan view of a display device according to a first example.

[0018] Figure 2 is a cross-sectional view of a display device according to a first example.

[0019] Figure 3 yes Figure 2 An enlarged cross-sectional view of region Q1 in FIG.

[0020] Figure 4 is a cross-sectional view of a display device according to a second example.

[0021] Figure 5 yes Figure 4 An enlarged cross-sectional view of region Q2 in FIG.

[0022] Figure 6 yes Figure 5 An enlarged cross-sectional view of region Q3 in FIG.

[0023] Figures 7 to 17 are cross-sectional views illustrating each process of a method of manufacturing a display device according to a second example. DETAILED DESCRIPTION

[0024] Hereinafter, examples will be described with reference to the accompanying drawings. In this specification, when a first component (or region, layer, portion, etc.) is described as being "on," "connected," or "coupled" to a second component, it may mean that the first component is directly connected / coupled to the second component, or a third component may be provided between the first and second components.

[0025] The same reference numerals denote the same components. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated in order to effectively describe the technical content. The term "and / or" includes all one or more combinations that can be defined by the associated configurations.

[0026] Terms such as first and second can be used to describe various components, but the components are not limited by the terms. These terms are used only to distinguish one component from another. For example, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component without departing from the scope of the examples. Singular expressions include plural expressions unless the context clearly dictates otherwise.

[0027] Terms such as "lower," "lower side," "upper side," and "lower side" are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described with respect to directions marked in the drawings.

[0028] It should be understood that terms such as “include” or “have” are intended to specify the existence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, and do not exclude the possibility of the pre-existence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0029] Figure 1 is a plan view of a display device according to a first example.

[0030] refer to Figure 1 The display device 10 according to the first example may be an organic light emitting diode display device, but is not limited thereto and may also be a liquid crystal display device or an inorganic light emitting display device. The following description will focus on the case where the display device according to the first example is an organic light emitting diode display device. The organic light emitting diode display device may include a display panel 100. The display panel 100 may include a display area DA and a non-display area NDA located near the display area DA. That is, the display area DA and the non-display area NDA located near the display area DA may be defined in the display panel 100. All areas described below may be described as being included in the display panel 100 and as being defined in the display panel 100.

[0031] The display area DA may include a plurality of pixels PX. The plurality of pixels PX may be arranged in a matrix, but is not limited thereto. The plurality of pixels PX may each be connected to a gate line SL and a data line DL. The gate line SL may extend in a first direction DR1, and the data line DL may extend in a second direction DR2. The display area DA may have a rectangular shape with short sides extending in the first direction DR1 and long sides extending in the second direction DR2, but is not limited thereto.

[0032] The non-display area NDA may surround the display area DA in a plan view. For example, the non-display area NDA may be disposed to surround all long sides (or sides extending in the second direction DR2 ) and short sides (or sides extending in the first direction DR1 ) of the display area DA, but is not limited thereto.

[0033] The gate driver GIP may be disposed in the non-display area NDA on one side and the other side of the display area DA in the first direction DR1. The gate driver GIP may be formed in the form of an integrated circuit on the substrate 101 of the display panel 100 (see FIG. Figure 2 ), but not limited thereto, it can also be formed in the form of a driver chip. Figure 1 The gate driver GIP is shown to be disposed on each of the left and right sides of the display area DA, but is not limited thereto and may be disposed on only either side of the left and right sides. The gate lines SL may each extend from the gate driver GIP.

[0034] The non-display area NDA may include a pad area PA. The pad area PA may be disposed at an end portion of the other side of the non-display area NDA in the second direction DR2.

[0035] A printed circuit film COF may be attached to the pad area PA. A driving chip DIC may be mounted on the printed circuit film COF. Figure 1 The printed circuit film COF is shown as being provided only, but the present application is not limited thereto, and there may be a plurality of printed circuit films COF. The printed circuit film COF may have one end connected to the pad area PA and the other end connected to the printed circuit board PCB.

[0036] Figure 2 is a cross-sectional view of a display device according to a first example. Figure 2 The image is taken in the second direction DR2. Figure 1 The cross-sectional structure of the display device. Figure 2 Only two pixels PX of the display area DA are shown, so Figure 1 The area ratio between the display area DA and the non-display area NDA can be Figure 2 The area ratio between the display area DA and the non-display area NDA is different. Figure 2 Two adjacent pixels PX are shown, and each pixel PX may include a light emitting area EA and a non-light emitting area NEA near the light emitting area EA. The light emitting area EA may be provided in each pixel PX and may be a central portion of the anode electrode 151 of each pixel PX. For example, the light emitting area EA may indicate an area of the anode electrode 151 exposed by the bank 154. On the other hand, the non-light emitting area NEA may indicate an area of the pixel PX that is not the light emitting area EA. The bank 154 may be provided according to Figure 2 The bank 154 is located in the non-emission area NEA of the display panel 100. That is, the area where the bank 154 is provided may be defined as the non-emission area NEA.

[0037] refer to Figure 1 and Figure 2 The display panel 100 may include a substrate 101, a first conductive layer CL1, a buffer layer 102, a semiconductor layer ACT, a gate insulating layer 103, a second conductive layer CL2, a first passivation layer 104, a third conductive layer CL3, a second passivation layer 105, a planarization layer 106, a light emitting element 150 and an encapsulation portion 170.

[0038] The substrate 101 may include one or more plastic materials. For example, the substrate 101 may be a multi-substrate including multiple plastic materials such as polyimide, but is not limited thereto. The substrate 101 may be a rigid substrate made of glass, quartz, etc.

[0039] The first conductive layer CL1 may be disposed on the substrate 101. The first conductive layer CL1 may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but is not limited thereto. The first conductive layer CL1 may include a light blocking layer LS and a data line DL.

[0040] The buffer layer 102 may be formed on the first conductive layer CL1. The buffer layer 102 may minimize or delay the diffusion of moisture or oxygen penetrating the substrate 101. The buffer layer 102 may be formed by alternately stacking silicon nitride (SiN x ) and silicon oxide (SiO x ) at least once to form the buffer layer 102.

[0041] The semiconductor layer ACT may be disposed on the buffer layer 102. The semiconductor layer ACT may include, but is not limited to, a metal oxide semiconductor such as indium gallium zinc oxide (IGZO) and a silicon-based semiconductor material such as amorphous silicon or polycrystalline silicon. The semiconductor layer ACT may include a channel region, a source region, and a drain region. The semiconductor layer ACT may overlap the light blocking layer LS.

[0042] Since a polycrystalline semiconductor layer has higher mobility than an amorphous semiconductor layer and an oxide semiconductor layer, power consumption is low and reliability is excellent. Therefore, the driving transistor can be formed of a polycrystalline semiconductor layer.

[0043] The gate insulating layer 103 may be provided on the semiconductor layer ACT. The gate insulating layer 103 may prevent a short circuit between the semiconductor layer ACT and the gate electrode GE of the second conductive layer CL2 provided on the semiconductor layer ACT. The gate insulating layer 103 may be made of the same material as the buffer layer 102, but is not limited thereto. For example, the gate insulating layer 103 may be made of a material such as silicon nitride (SiN x ) or silicon oxide (SiO x ) is made of inorganic materials, but is not limited thereto.

[0044] Figure 2The gate insulating layer 103 is shown as being provided only in the region overlapping the low potential power line EVSL, the gate electrode GE, the source electrode SE, the drain electrode DE, and the first pad electrode PAD1 of the second conductive layer CL2. However, the present application is not limited thereto, and the gate insulating layer 103 may be formed throughout the display area DA and the non-display area NDA.

[0045] The second conductive layer CL2 may be disposed on the gate insulating layer 103. The second conductive layer CL2 may include a low potential power line EVSL, a gate electrode GE, a source electrode SE, a drain electrode DE, and a first pad electrode PAD1.

[0046] The low potential power line EVSL may be provided in the non-display area NDA. The low potential power line EVSL is shown as being provided in the non-display area NDA opposite to the pad area PA with the display area DA interposed therebetween, but is not limited thereto.

[0047] The gate electrode GE may overlap with the channel region of the semiconductor layer ACT. The source electrode SE may be connected to the source region of the semiconductor layer ACT, and the drain electrode DE may be connected to the drain region of the semiconductor layer ACT. The semiconductor layer ACT, the gate electrode GE, the drain electrode DE, and the source electrode SE may form a thin film transistor T. Although Figure 2 The gate electrode GE, the drain electrode DE, and the source electrode SE are shown to be coplanar, but the present application is not limited thereto. For example, the drain electrode DE and the source electrode SE may be disposed on the third conductive layer CL3, and the gate electrode GE may be disposed on the second conductive layer CL2.

[0048] The first pad electrode PAD1 may be disposed on the pad area PA. The first pad electrode PAD1 may be connected to the data line DL, the low potential power line EVSL, or the high potential power line, but is not limited thereto.

[0049] The second conductive layer CL2 may be formed of a single layer or multiple layers made of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or compounds thereof, but is not limited thereto.

[0050] The gate electrode GE may be provided together with the gate line SL.

[0051] The first passivation layer 104 may be disposed on the second conductive layer CL2. The first passivation layer 104 may include at least one of the exemplary materials of the gate insulating layer 103, but is not limited thereto. The first passivation layer 104 may be formed throughout the display area DA and the non-display area NDA. The first passivation layer 104 may have a uniform thickness t1 for each area.

[0052] The third conductive layer CL3 may be disposed on the first passivation layer 104. The third conductive layer CL3 may include an auxiliary electrode AXE and a second pad electrode PAD2. The auxiliary electrode AXE may be disposed in the non-display area NDA and may overlap with the low potential power line EVSL. The second pad electrode PAD2 may be disposed in the pad area PA and may overlap with the first pad electrode PAD1. The first passivation layer 104 may partially expose the upper surface of the low potential power line EVSL and the upper surface of the first pad electrode PAD1. The auxiliary electrode AXE and the second pad electrode PAD2 may be in direct contact with the upper surface of the partially exposed low potential power line EVSL and the upper surface of the first pad electrode PAD1. The first pad electrode PAD1 and the second pad electrode PAD2 may form a pad electrode PAD. Although Figure 2 The pad electrode PAD is shown as being formed of a double layer of a first pad electrode PAD1 and a second pad electrode PAD2, but the present application is not limited thereto. The third conductive layer CL3 may be formed of a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof, but is not limited thereto.

[0053] A second passivation layer 105 may be disposed on the third conductive layer CL3. The second passivation layer 105 may include at least one of the exemplary materials of the gate insulating layer 103, but is not limited thereto. The second passivation layer 105 may be disposed in the display area DA and the non-display area NDA. The second passivation layer 105 may partially expose the upper surfaces of the auxiliary electrode AXE and the second pad electrode PAD2.

[0054] A planarization layer 106 may be provided on the second passivation layer 105. The planarization layer 106 may flatten the upper portion of the thin film transistor T and protect the thin film transistor T. The planarization layer 106 may be made of an organic material. For example, the planarization layer 106 may be made of an organic material including, but not limited to, acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. The planarization layer 106 may expose the auxiliary electrode AXE and the pad area PA.

[0055] A printed circuit film (COF) may be attached to the pad area PA. A bump may be provided on the lower surface of the printed circuit film (COF). An anisotropic conductive film (ACF) may be provided between the bump and the pad electrode (PAD). The ACF may include a resin and conductive balls dispersed in the resin. The bump and the pad electrode (PAD) may be electrically connected via the conductive balls.

[0056] The anode electrode 151 may be disposed on the planarization layer 106. The anode electrode 151 may be electrically connected to the drain electrode DE of the thin film transistor T through a contact hole formed in the planarization layer 106, the second passivation layer 105, and the first passivation layer 104. The anode electrode 151 may be a reflective electrode that reflects light, but is not limited thereto. The anode electrode 151 may include a metal material having high reflectivity, such as a stacked structure (Ti / Al / Ti) of aluminum (Al) and titanium (Ti), a stacked structure (ITO / Al / ITO) of aluminum (Al) and indium tin oxide (ITO), or an APC alloy, and may be formed of a single layer or multiple layers, but is not limited thereto.

[0057] The organic layer 152 may be provided on the anode electrode 151. The organic layer 152 may include a first stack, a second stack, and a first charge generation layer provided on the anode electrode 151. The first stack may be provided on the anode electrode 151 and configured in a structure in which a hole injection layer (HIL), a hole transport layer (HTL), a blue (B) light emitting layer (EML1), and an electron transport layer (ETL) are sequentially stacked, but is not limited thereto.

[0058] The first charge generation layer is configured to supply charges to the first stack and the second stack. The first charge generation layer may include an N-type charge generation layer for supplying electrons to the first stack and a P-type charge generation layer for supplying holes to the second stack. The N-type charge generation layer may include a metal material as a dopant.

[0059] The second stack may be disposed on the first stack and configured in a structure in which a hole transport layer (HTL), a yellow-green (YG) light emitting layer (EML2), an electron transport layer (ETL), and an electron injection layer (EIL) are sequentially stacked.

[0060] Results, such as Figure 2 As shown, the organic layer 152 may be provided as a common layer in all adjacent pixels PX. For example, the organic layer 152 may be a white organic layer emitting white light, but is not limited thereto and may also be one of a red organic layer, a green organic layer, and a blue organic layer.

[0061] In some examples, the organic layer 152 may include a first stack disposed on the anode electrode 151 , a second stack, a third stack, a first charge generation layer between the first and second stacks, and a second charge generation layer between the second and third stacks.

[0062] The first stack may be disposed on the anode electrode 151 and configured in a structure in which a hole injection layer (HIL), a hole transport layer (HTL), a blue (B) emission layer (EML1), and an electron transport layer (ETL) are sequentially stacked.

[0063] The first charge generation layer is configured to supply charges to the first stack and the second stack. The first charge generation layer may include an N-type charge generation layer for supplying electrons to the first stack and a P-type charge generation layer for supplying holes to the second stack. The N-type charge generation layer may include a metal material as a dopant.

[0064] The second stack may be disposed on the first stack and configured in a structure in which a hole transport layer (HTL), a green (G) light emitting layer (EML2), and an electron transport layer (ETL) are sequentially stacked.

[0065] The second charge generation layer is configured to supply charges to the second stack and the third stack. The second charge generation layer may include an N-type charge generation layer configured to supply electrons to the second stack and a P-type charge generation layer configured to supply holes to the third stack. The N-type charge generation layer may include a metal material as a dopant.

[0066] The third stack may be disposed on the second stack and configured in a structure in which a hole transport layer (HTL), a red (R) light emitting layer (EML3), an electron transport layer (ETL), and an electron injection layer (EIL) are sequentially stacked.

[0067] Figure 3 yes Figure 2 An enlarged cross-sectional view of region Q1 in FIG.

[0068] refer to Figures 1 to 3 As described above, the organic layer 152 may include a first charge generation layer or a second charge generation layer. Since the organic layer 152 is formed in all pixels PX, when any pixel PX emits light, a lateral leakage current may be generated through the first charge generation layer or the second charge generation layer to an adjacent pixel PX. This lateral leakage current generated between adjacent pixels PX may deteriorate display quality.

[0069] Return Reference Figure 2 , the bank 154 may be provided to expose the anode electrode 151 . The bank 154 may be provided to cover an edge portion of the anode electrode 151 .

[0070] Encapsulation portion 170 may be disposed on bank 154 or light-emitting element 150. Encapsulation portion 170 may include one or more insulating layers. For example, encapsulation portion 170 may include a first encapsulation layer 171, a second encapsulation layer 172 disposed on first encapsulation layer 171, and a third encapsulation layer 173 disposed on second encapsulation layer 172. Encapsulation portion 170 may include one or more inorganic layers and one or more organic layers. For example, first encapsulation layer 171 and third encapsulation layer 173 may include an inorganic material, and second encapsulation layer 172 may include an organic material.

[0071] Hereinafter, a second example for solving / minimizing the lateral leakage current of the display device 10 according to the first example will be described. Figures 4 to 6 The display device 10_1 according to the second example will be described, and the descriptions already made in the second example will be omitted. Figures 1 to 3 A detailed description of the components described in .

[0072] Figure 4 is a cross-sectional view of a display device according to a second example. Figure 5 yes Figure 4 An enlarged cross-sectional view of region Q2 in FIG. Figure 6 yes Figure 5 An enlarged cross-sectional view of region Q3 in FIG.

[0073] refer to Figures 4 to 6 The display panel 100_1 of the display device 10_1 according to the second example is different from the display panel 100_1 according to the embodiment of the present invention. Figure 2 and Figure 3 The display device 10 is different in that it further includes a protruding pattern (layer) PT.

[0074] More specifically, the third conductive layer CL3_1 of the display panel 100_1 may further include a protruding pattern PT. The protruding pattern PT may be provided at the boundary between adjacent pixels PX, where the boundary is the area between adjacent pixels. The protruding pattern, or "layer," may define the width of the boundary. The protruding pattern PT may be provided in the non-emission area NEA.

[0075] The first passivation layer 104_1 disposed between the protruding pattern PT and the second conductive layer CL2 can have different thicknesses for each region. For example, the first passivation layer 104_1 can include a protrusion 104_1P that overlaps the protruding pattern PT and has a second thickness t2 greater than the first thickness t1 in the non-emission area NEA, and can also include other regions having the first thickness t1 in the non-emission area NEA. The width W2 of the protrusion 104_1P can be smaller than the width W1 of the protruding pattern PT. The reason why the width of the protrusion 104_1P is smaller than the width of the protruding pattern PT is that the protrusion 104_1P is formed in the non-emission area NEA using the protruding pattern PT as a mask. This will be described in detail below in the method of manufacturing the display device 10_1 according to the second example.

[0076] Additionally, the second passivation layer 105_1 and the planarization layer 106_1 disposed on the protruding pattern PT can each be removed from the non-emission area NEA. Hereinafter, the portions of the second passivation layer 105_1 and the planarization layer 106_1 removed from the non-emission area NEA will be referred to as "first through holes TH1." The first through holes TH1 can completely penetrate the second passivation layer 105_1 and the planarization layer 106_1 in the thickness direction. Removing the second passivation layer 105_1 and the planarization layer 106_1 from the non-emission area NEA increases the distance between the surface of the protruding pattern PT and the surface of the bank 154_1. This has the advantage of facilitating the patterning process. The second passivation layer 105_1 and the planarization layer 106_1 can be removed from the non-emission area NEA to expose the protruding pattern PT.

[0077] As described above, since the second passivation layer 105_1 and the planarization layer 106_1 are removed from the non-emission area NEA, the bank 154_1 may be in direct contact with the upper surface of the first passivation layer 104_1 in the non-emission area NEA.

[0078] In addition, similar to the second passivation layer 105_1 and the planarization layer 106_1, the bank 154_1 can be removed from the non-emission area NEA. Hereinafter, the portion of the bank 154_1 removed from the non-emission area NEA will be referred to as a "second through hole TH2." The second through hole TH2 can completely pass through the bank 154_1 in the thickness direction.

[0079] like Figure 4 As shown, the width of the second through hole TH2 of the bank 154_1 may be smaller than the width of the first through hole TH1 of the second passivation layer 105_1 and the planarization layer 106_1. That is, the inner surface of the bank 154_1 facing the protrusion pattern PT may be positioned closer to the protrusion pattern PT than the inner surfaces of the second passivation layer 105_1 and the planarization layer 106_1 facing the protrusion pattern PT.

[0080] The organic layer 152_1 can be disposed on and directly contact the upper surface of the anode electrode 151, the outer surface of the bank 154_1, the upper surface of the bank 154_1, and the inner surface of the bank 154_1. As described above, since the bank 154_1 is in direct contact with the upper surface of the first passivation layer 104_1 in the non-emission area NEA, the length of the inner surface of the bank 154_1 can be increased in the non-emission area NEA. The length of the inner surface of the bank 154_1 can be greater than the length of the outer surface of the bank 154_1. The bank 154_1 can have a regular tapered shape. Therefore, the organic layer 152_1 directly disposed on the inner surface of the bank 154_1 is likely to be separated from the inner surface of the bank 154_1. This increased length / path reduces leakage current effects.

[0081] Additionally, as described above, the protrusion pattern PT may have a greater width than the protrusion 104_1P. The side surface of the protrusion pattern PT may extend further outward than the side surface of the protrusion 104_1P. Therefore, the side surface of the protrusion 104_1P and the side surface of the protrusion pattern PT may form a stepped structure. The organic layer 152_1 may extend through the inner surface of the dam 154_1 to the upper surface of the first passivation layer 104_1. However, due to the stepped structure formed by the side surface of the protrusion 104_1P and the side surface of the protrusion pattern PT, the organic layer 152_1 may be separated. In other words, the organic layer 152_1 may be divided into a portion disposed on the protrusion pattern PT and a portion that does not overlap with the protrusion pattern PT. The portion of the organic layer 152_1 disposed on the protrusion pattern PT and the portion of the organic layer 152_1 that does not overlap with the protrusion pattern PT may be physically separated.

[0082] Furthermore, as described above, the inner surface of the bank 154_1 facing the protruding pattern PT can be positioned closer to the protruding pattern PT than the inner surfaces of the second passivation layer 105_1 and the planarization layer 106_1 facing the protruding pattern PT. That is, the organic layer 152_1 disposed on the upper surface of the first passivation layer 104_1 exposed by the bank 154_1 can be minimized. When the first through hole TH1 and the second through hole TH2 have the same width, the organic layer 152_1 contacts the side surfaces of the bank 154_1, the side surfaces of the planarization layer 106_1, the side surfaces of the second passivation layer 105_1, and the side surfaces of the first passivation layer 104_1, and then extends to the upper surface of the first passivation layer 104_1. In this case, because the area (or length) of the upper surface of the first passivation layer 104_1 exposed by the bank 154_1 is large, even if the organic layer 152_1 has a stepped structure formed by the protrusion pattern PT and the protrusion 104_1P, the organic layer 152_1 can extend to the upper surface of the protrusion pattern PT while contacting the side surfaces of the protrusion 104_1P and the side surfaces of the protrusion pattern PT. Therefore, when the widths of the first through hole TH1 and the second through hole TH2 are the same, the organic layer 152_1 is not separated by the stepped structure and can extend to the adjacent pixel PX. This also has the advantage of minimizing the negative impact of any leakage current.

[0083] However, in the case of the display device 10_1 according to the second example, the inner surface of the bank 154_1 facing the protruding pattern PT can be positioned closer to the protruding pattern PT than the inner surfaces of the second passivation layer 105_1 and the planarization layer 106_1 facing the protruding pattern PT, thereby minimizing the organic layer 152_1 disposed on the upper surface of the first passivation layer 104_1 exposed by the bank 154_1. Therefore, the possibility of the organic layer 152_1 being separated by the stepped structure can be further increased.

[0084] At the same time, if Figure 5 and Figure 6 As shown, in the non-emission area NEA, the surface roughness (smoothness / flatness) of the first passivation layer 104_1 can be different for each region. As described above, the first passivation layer 104_1 can have a protrusion 104_1P that overlaps with the protrusion pattern PT and has a second thickness t2 greater than the first thickness t1 in the non-emission area NEA, and can have other regions having the first thickness t1 in the non-emission area NEA. The upper surface of the protrusion 104_1P will be referred to as "upper surface 104_1a," and the side surface of the protrusion 1041_P will be referred to as "side surface 104_1c." Additionally, the upper surface of the first passivation layer 104_1 will be referred to as "upper surface 104_1b." Comparing the roughness of each surface, the roughness of the upper surface 104_1a can be less than that of the side surface 104_1c (e.g., having a smaller vertical height). The roughness of the upper surface 104_1a can be less than that of the upper surface 104_1b. When the roughness of the upper surface 104_1a of the protrusion 104_1P having the second thickness t2 is smaller than each of the roughness of the upper surface 104_1b of the first passivation layer 104_1 in the non-emission area NEA having the first thickness t1 and the roughness of the side surface 104_1c of the first passivation layer 104_1 connecting the upper surface of the first passivation layer 104_1 in the non-emission area NEA having the first thickness t1 and the upper surface of the protrusion 104_1P, as will be described below Figure 12 As described in , during the formation of the second passivation layer 105_1 , the side surface 104_1 c and the upper surface 104_1 b of the first passivation layer 104_1 ′ exposed by the protrusion pattern PT are in contact with etching gas or etchant, resulting in changes in physical properties of the surface.

[0085] Hereinafter, a method of manufacturing the display device 10_1 according to the second example will be described. Figures 7 to 17 The method of manufacturing the display device 10_1 will be described, and the method of manufacturing the display device 10_1 will be omitted. Figures 1 to 6 A detailed description of the components described in .

[0086] Figures 7 to 17 is a cross-sectional view showing each process of the method for manufacturing the display device according to the second example. Figures 7 to 17 Describes the manufacturing process of the display device 10_1 (see Figure 4 ) method, you can refer to it together Figures 4 to 6 .

[0087] refer to Figure 4 and Figure 7A first passivation layer 104_1' is formed on the second conductive layer CL2. The first passivation layer 104_1' may include at least one of the exemplary materials of the gate insulating layer 103, but is not limited thereto. The first passivation layer 104_1' may be formed throughout the display area DA and the non-display area NDA. The first passivation layer 104_1' may have a uniform thickness t1 for each area. The first passivation layer 104_1' may partially expose the upper surface of the low potential power line EVSL and the upper surface of the first pad electrode PAD1.

[0088] Then, if Figure 4 and Figure 8 As shown, a third conductive layer CL3_1 is formed on the first passivation layer 104_1'. The third conductive layer CL3_1 may include an auxiliary electrode AXE, a second pad electrode PAD2, and a protruding pattern PT. The auxiliary electrode AXE may be disposed in the non-display area NDA and may overlap with the low potential power line EVSL. The second pad electrode PAD2 may be disposed in the pad area PA and may overlap with the first pad electrode PAD1. The first passivation layer 104_1' may partially expose the upper surface of the low potential power line EVSL and the upper surface of the first pad electrode PAD1. The auxiliary electrode AXE and the second pad electrode PAD2 may be in direct contact with the partially exposed upper surface of the low potential power line EVSL and the upper surface of the first pad electrode PAD1. The protruding pattern PT may be disposed at a boundary between adjacent pixels PX or in the non-emission area NEA.

[0089] The third conductive layer CL3_1 may be formed of a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or alloys thereof, but is not limited thereto.

[0090] Then, if Figure 4 and Figure 9 As shown, a second passivation layer 105_1' is formed on the third conductive layer CL3_1. The second passivation layer 105_1' may include at least one of the exemplary materials of the gate insulating layer 103, but is not limited thereto. The second passivation layer 105_1' may be disposed in the display area DA and the non-display area NDA. The second passivation layer 105_1' may partially expose the upper surfaces of the auxiliary electrode AXE and the second pad electrode PAD2.

[0091] Then, if Figure 4 and Figure 10As shown, a planarization layer 106_1' is formed on the second passivation layer 105_1'. The planarization layer 106_1' can flatten the upper portion of the thin film transistor T and protect the thin film transistor T. The planarization layer 106_1' can be made of an organic material. For example, the planarization layer 106_1' can be made of an organic material including, but not limited to, acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. The planarization layer 106_1' can expose the auxiliary electrode AXE and the pad area PA.

[0092] Then, if Figure 4 and Figure 11 As shown, in Figure 10 A first through hole TH1 is formed in the planarization layer 106_1' to form the planarization layer 106_1. The planarization layer 106_1 may expose the second passivation layer 105'_1 on the auxiliary electrode AXE and the pad area PA. The process for forming the planarization layer 106_1 may be an etching process, but is not limited thereto. The etching process may include dry etching or wet etching. Furthermore, since the first through hole TH1 in the planarization layer 106_1 exposes the second passivation layer 105-1' on the protruding pattern PT, it is preferable that the etching gas or etchant used to etch the planarization layer 106_1' have a high etching selectivity between the planarization layer 106_1' and the second passivation layer 105-1'. For example, the etching rate of the etching gas or etchant on the planarization layer 106_1' may be greater than the etching rate of the etching gas or etchant on the second passivation layer 105-1'.

[0093] Then, if Figure 4 and Figure 12 As shown, in Figure 11 A first through hole TH1 is formed in the second passivation layer 105_1' to form the second passivation layer 105_1. The second passivation layer 105_1 may expose an upper surface of the auxiliary electrode AXE and an upper surface of the second pad electrode PAD2.

[0094] The process of forming the second passivation layer 105_1 may be an etching process, but is not limited thereto. The etching process may include dry etching or wet etching. Meanwhile, as described above, in the process of forming the second passivation layer 105_1, the first passivation layer 104-1' (see FIG. 1 ) overlapping the protruding pattern PT is formed. Figure 11 Since the protruding pattern PT may not be etched, during the formation of the second passivation layer 105_1, the protrusion 104_1P having the first thickness t1 and the region having the second thickness t2 near the protrusion 104_1P of the first passivation layer 104_1 in the non-emission area NEA may be formed.

[0095] Meanwhile, in the process of forming the second passivation layer 105_1, the protrusion pattern PT is not substantially etched, but the first passivation layer 104-1' may be partially etched (see FIG. 1 ). Figure 11 That is, the etching gas or etchant for etching the second passivation layer 105_1' is used to etch the second passivation layer 105_1' and the first passivation layer 104_1' (see Figure 11 ) may be smaller than the etching selectivity of the etching gas or etchant between the second passivation layer 105_1′ and the protruding pattern PT. In addition, the etching rate of the etching gas or etchant used to etch the second passivation layer 105_1′ on the second passivation layer 105_1′ may be greater than the etching rate of the etching gas or etchant on the first passivation layer 104_1′ (see Figure 11 ) and the etching rate of the protruding pattern PT, and the etching gas or etchant has an effect on the first passivation layer 104_1 '(see Figure 11 ) may have an etching rate greater than an etching rate of the protrusion pattern PT by the etching gas or the etchant.

[0096] Then, if Figure 4 and Figure 13 As shown, an anode electrode layer 151' is formed on the planarization layer 106_1. The anode electrode layer 151' is provided throughout the display area DA and the non-display area NDA. The anode electrode layer 151' may include a reflective material that reflects light, but is not limited thereto. The anode electrode layer 151' may include a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stacked structure of aluminum (Al) and ITO (ITO / Al / ITO), and a metal material with high reflectivity such as an APC alloy, and may be formed of a single layer or multiple layers, but is not limited thereto.

[0097] Then, if Figure 4 and Figure 14 As shown, the anode electrode layer 151' is etched (see Figure 13 ) to form the anode electrode 151. The process of forming the anode electrode 151 may be an etching process, but is not limited thereto. The etching process may include dry etching or wet etching. Meanwhile, in the process of forming the anode electrode 151, the protruding pattern PT may not be substantially etched. Therefore, it is preferred that the method for etching the anode electrode layer 151' (see Figure 13 ) has a high etching selectivity between the anode electrode layer 151' and the protruding pattern PT. For example, the etching gas or etchant for etching the anode electrode layer 151' (see Figure 13 ) of the etching gas or etchant to the anode electrode layer 151 '(see Figure 13 ) may have an etching rate greater than an etching rate of the protrusion pattern PT by the etching gas or the etchant.

[0098] Then, if Figure 4 and Figure 15 As shown, a bank layer 154_1 ′ is formed on the anode electrode 151 .

[0099] Then, if Figure 4 and Figure 16 As shown, the bank layer 154_1′ is etched (see Figure 15 ) to form a bank 154_1. The bank 154_1 may expose the pad area PA, and a second through hole TH2 may be formed in the non-emission area NEA to expose the protrusion pattern PT. The width of the second through hole TH2 of the bank 154_1 may be smaller than the width of the first through hole TH1 of the second passivation layer 105_1 and the planarization layer 106_1. That is, the inner surface of the bank 154_1 facing the protrusion pattern PT may be positioned closer to the protrusion pattern PT than the inner surfaces of the second passivation layer 105_1 and the planarization layer 106_1 facing the protrusion pattern PT. Since the second passivation layer 105_1 and the planarization layer 106_1 are removed from the non-emission area NEA, the bank 154_1 may be in direct contact with the upper surface of the first passivation layer 104_1 in the non-emission area NEA.

[0100] Then, if Figure 4 and Figure 17 As shown, an organic layer 152_1 is formed on the bank 154_1, the anode electrode 151, and the first passivation layer 104_1. The organic layer 152_1 may include a first stack, a second stack, and a first charge generation layer disposed on the anode electrode 151, or may include a first stack, a second stack, a third stack, a first charge generation layer between the first stack and the second stack, and a second charge generation layer between the second stack and the third stack disposed on the anode electrode.

[0101] As mentioned above Figure 4 and Figure 5 As described above, the organic layer 152_1 can be disposed on and directly contact the upper surface of the anode electrode 151, the outer surface of the bank 154_1, the upper surface of the bank 154_1, and the inner surface of the bank 154_1. Because the bank 154_1 is in direct contact with the upper surface of the first passivation layer 104_1 in the non-emission area NEA, the inner surface of the bank 154_1 can be increased in the non-emission area NEA. The inner surface of the bank 154_1 can be longer than the outer surface of the bank 154_1. The bank 154_1 can have a regular tapered shape. Therefore, the organic layer 152_1 disposed directly on the inner surface of the bank 154_1 is likely to be separated from the inner surface of the bank 154_1.

[0102] Additionally, as described above, the protrusion pattern PT may have a greater width than the protrusion 104_1P. The side surface of the protrusion pattern PT may extend further outward than the side surface of the protrusion 104_1P. Therefore, the side surface of the protrusion 104_1P and the side surface of the protrusion pattern PT may form a stepped structure. The organic layer 152_1 may extend through the inner surface of the dam 154_1 to the upper surface of the first passivation layer 104_1. However, due to the stepped structure formed by the side surface of the protrusion 104_1P and the side surface of the protrusion pattern PT, the organic layer 152_1 may be separated. In other words, the organic layer 152_1 may be divided into a portion disposed on the protrusion pattern PT and a portion that does not overlap with the protrusion pattern PT. The portion of the organic layer 152_1 disposed on the protrusion pattern PT and the portion of the organic layer 152_1 that does not overlap with the protrusion pattern PT may be physically separated.

[0103] Furthermore, as described above, the inner surface of the bank 154_1 facing the protruding pattern PT can be positioned closer to the protruding pattern PT than the inner surfaces of the second passivation layer 105_1 and the planarization layer 106_1 facing the protruding pattern PT. That is, the organic layer 152_1 disposed on the upper surface of the first passivation layer 104_1 exposed by the bank 154_1 can be minimized. When the first through hole TH1 and the second through hole TH2 have the same width, the organic layer 152_1 contacts the side surfaces of the bank 154_1, the side surfaces of the planarization layer 106_1, the side surfaces of the second passivation layer 105_1, and the side surfaces of the first passivation layer 104_1, and then extends to the upper surface of the first passivation layer 104_1. In this case, because the area (or length) of the upper surface of the first passivation layer 104_1 exposed by the bank 154_1 is large, even if the organic layer 152_1 has a stepped structure formed by the protrusion pattern PT and the protrusion 104_1P, the organic layer 152_1 can extend to the upper surface of the protrusion pattern PT while contacting the side surfaces of the protrusion 104_1P and the side surfaces of the protrusion pattern PT. Therefore, when the first through hole TH1 and the second through hole TH2 have the same width, the organic layer 152_1 is not separated by the stepped structure and can extend to the adjacent pixel PX.

[0104] However, in the case of the display device 10_1 according to the second example, the inner surface of the bank 154_1 facing the protruding pattern PT can be positioned closer to the protruding pattern PT than the inner surfaces of the second passivation layer 105_1 and the planarization layer 106_1 facing the protruding pattern PT, thereby minimizing the organic layer 152_1 disposed on the upper surface of the first passivation layer 104_1 exposed by the bank 154_1. Therefore, the possibility of the organic layer 152_1 being separated by the stepped structure can be further increased.

[0105] A display device according to various examples of the present application can be described as follows.

[0106] A display device includes: a substrate, the substrate including a display area and a non-display area, the display area including a plurality of pixels, the non-display area surrounding the display area; a protruding pattern, the protruding pattern being arranged on the substrate and located at a boundary between adjacent pixels; an anode electrode, the anode electrode being arranged on each pixel on the substrate; a partition bank, the partition bank being arranged on the anode electrode and exposing the protruding pattern; and an organic layer, the organic layer being arranged on the anode electrode and the partition bank, wherein the organic layer is separated at the boundary between the pixels.

[0107] The bank may partially expose an upper surface of the anode electrode and include a through hole at a boundary of the pixel, and the through hole may overlap the protrusion pattern.

[0108] The organic layer may cover the upper surface and the side surface of the bank, and may be disconnected on the end portion of the protruding pattern (not covering the end portion / separated from the end portion).

[0109] The organic layer may be further disposed on an upper surface of the protruding pattern, and the organic layer disposed on the upper surface of the protruding pattern and the organic layer disposed on the upper and side surfaces of the bank may be separated.

[0110] The display device may further include a first passivation layer between the substrate and the protruding pattern, wherein, at a boundary of the pixel, a second thickness of the first passivation layer overlapping the protruding pattern may be greater than a first thickness of the first passivation layer not overlapping the protruding pattern.

[0111] A width of the first passivation layer having the second thickness may be smaller than a width of the protrusion pattern.

[0112] A surface roughness of the first passivation layer having the first thickness may be greater than a surface roughness of the first passivation layer having the second thickness.

[0113] The display device may further include a second passivation layer disposed between the substrate and the anode electrode, wherein the second passivation layer may not be disposed at a boundary of the pixel.

[0114] The display device may further include a planarization layer between the second passivation layer and the anode electrode, wherein the planarization layer may not be provided at a boundary of the pixel.

[0115] The pixels may include white pixels.

[0116] The display device may further include a cathode electrode on the organic layer, wherein the cathode electrode may be in direct contact with a side surface of the protrusion pattern.

[0117] A display device comprises: a substrate, the substrate comprising a display area and a pad area, the display area comprising a plurality of pixels, the pad area being adjacent to the display area; a first conductive layer on the substrate, the first conductive layer comprising a data line and a light blocking layer; a semiconductor layer on the first conductive layer, the semiconductor layer overlapping the light blocking layer; a gate insulating layer on the semiconductor layer; a second conductive layer on the gate insulating layer, the second conductive layer comprising a first pad electrode arranged in the pad area, a gate electrode overlapping a channel area of the semiconductor layer, a source electrode connected to a source area of the semiconductor layer, and a drain electrode connected to a drain area of the semiconductor layer; a first passivation layer, the first passivation layer being arranged on the second conductive layer; and a third conductive layer, the third conductive layer being arranged on the first passivation layer and comprising a second pad electrode arranged on the first pad electrode in the pad area and a protruding pattern located at a boundary of the pixel.

[0118] The display device may further include an anode electrode disposed on the third conductive layer and in each pixel, and a bank disposed on the anode electrode and exposing the protrusion pattern.

[0119] The display device may further include an organic layer disposed on the anode electrode and the bank, wherein the organic layer may be divided at a boundary of the pixel.

[0120] The bank may partially expose an upper surface of the anode electrode and include a through hole at a boundary of the pixel, and the through hole may overlap the protrusion pattern.

[0121] The organic layer may cover the upper surface and side surfaces of the bank and may be disconnected at the end of the protruding pattern (not covering the end).

[0122] The organic layer may be further disposed on an upper surface of the protruding pattern, and the organic layer disposed on the upper surface of the protruding pattern and the organic layer disposed on an upper surface and a side surface of the bank may be separated.

[0123] The first passivation layer may be disposed between the substrate and the protruding pattern, wherein, at a boundary of the pixel, a second thickness of the first passivation layer overlapping the protruding pattern may be greater than a first thickness of the first passivation layer not overlapping the protruding pattern.

[0124] A width of the first passivation layer having the second thickness may be smaller than a width of the protrusion pattern.

[0125] A surface roughness of the first passivation layer having the first thickness may be greater than a surface roughness of the first passivation layer having the second thickness.

[0126] Additional examples are set forth in the following clauses:

[0127] A1. A display device comprising:

[0128] a substrate, the substrate comprising a display area and a non-display area, the display area comprising a plurality of pixels, and the non-display area surrounding the display area;

[0129] a protruding pattern, the protruding pattern being provided on the substrate and located at a boundary between adjacent pixels;

[0130] an anode electrode, the anode electrode being disposed on each pixel on the substrate;

[0131] a bank disposed on the anode electrode and exposing the protruding pattern; and

[0132] an organic layer, the organic layer being disposed on the anode electrode and the bank,

[0133] The organic layer is divided by the protruding pattern at the boundary of the pixel.

[0134] 1. A display device comprising:

[0135] a substrate, the substrate comprising a display area and a non-display area, the display area comprising a plurality of pixels, and the non-display area surrounding the display area;

[0136] a protruding pattern, the protruding pattern being provided on the substrate and located at a boundary between adjacent pixels;

[0137] an anode electrode, the anode electrode being disposed on each pixel on the substrate;

[0138] a bank disposed on the anode electrode and exposing the protruding pattern; and

[0139] an organic layer, the organic layer being disposed on the anode electrode and the bank,

[0140] The organic layer is discontinuous at the boundary of the pixel.

[0141] 2. The display device according to clause 1, wherein the organic layer is divided by the protrusion pattern at the boundary of the pixel.

[0142] 3. The display device according to clause 1 or 2, wherein the bank partially exposes an upper surface of the anode electrode and includes a through-hole at a boundary of the pixel, the through-hole overlapping the protrusion pattern.

[0143] 4. The display device according to clause 3, wherein the organic layer covers upper and side surfaces of the bank and does not cover end portions of the protruding pattern.

[0144] 5. The display device according to any one of the preceding clauses, wherein the organic layer is further provided on an upper surface of the protruding pattern, and the organic layer provided on the upper surface of the protruding pattern is separated from the organic layer not provided on the upper surface of the protruding pattern.

[0145] 6. The display device according to any one of clauses 3 to 5 when dependent on clause 3, further comprising a first passivation layer between the substrate and the protruding pattern, wherein, at the boundary of the pixel, the second thickness of the first passivation layer overlapping with the protruding pattern is greater than the first thickness of the first passivation layer not overlapping with the protruding pattern.

[0146] 7. The display device according to clause 6, wherein a width of the first passivation layer having the second thickness is smaller than a width of the protruding pattern.

[0147] 8. The display device according to clause 6 or 7, wherein a surface roughness of an upper surface of the first passivation layer having the first thickness is greater than a surface roughness of an upper surface of the first passivation layer having the second thickness.

[0148] 9. The display device according to any one of clauses 5 to 7, further comprising: a second passivation layer, the second passivation layer being provided between the substrate and the anode electrode, the second passivation layer not being provided at a boundary of the pixel; and

[0149] A planarization layer is provided between the second passivation layer and the anode electrode, and the planarization layer is not provided at a boundary of the pixel.

[0150] 10. The display device according to any one of the preceding clauses, wherein the pixel comprises a light-emitting region and a non-light-emitting region, and the protruding pattern is provided in the non-light-emitting region.

[0151] 11. The display device according to any one of the preceding clauses, further comprising a cathode electrode on the organic layer, the cathode electrode being in direct contact with a side surface of the protruding pattern.

[0152] 12. The display device according to any one of the preceding clauses, wherein a portion of the organic layer is disposed on the protruding pattern, and a remaining portion of the organic layer not disposed on the protruding pattern is physically separated from a portion disposed on the protruding pattern.

[0153] 13. A display device comprising:

[0154] a substrate, the substrate comprising a display area and a pad area, the display area comprising a plurality of pixels, and the pad area being close to the display area;

[0155] a first conductive layer on the substrate, wherein the first conductive layer includes a data line and a light blocking layer;

[0156] a semiconductor layer on the first conductive layer, the semiconductor layer overlapping the light blocking layer;

[0157] a gate insulating layer on the semiconductor layer;

[0158] a second conductive layer on the gate insulating layer, the second conductive layer comprising a first pad electrode disposed in the pad region, a gate electrode overlapping the channel region of the semiconductor layer, a source electrode connected to the source region of the semiconductor layer, and a drain electrode connected to the drain region of the semiconductor layer;

[0159] a first passivation layer, the first passivation layer being disposed on the second conductive layer;

[0160] a third conductive layer disposed on the first passivation layer and including a second pad electrode disposed on the first pad electrode in the pad region and a protrusion pattern located at a boundary of the pixel; and

[0161] An organic layer is discontinuous at a boundary of the pixel due to the protruding pattern.

[0162] 14. The display device according to clause 13, wherein the organic layer is divided by the protrusion pattern at the boundary of the pixel.

[0163] 15. The display device according to any one of clauses 13 to 14, further comprising an anode electrode provided on the third conductive layer and in each pixel; and a bank provided on the anode electrode and exposing the protrusion pattern.

[0164] 16. The display device according to any one of clauses 13 to 15, wherein the organic layer is provided on the anode electrode and the bank.

[0165] 17. The display device according to any one of clauses 13 to 15, wherein the bank partially exposes an upper surface of the anode electrode and includes a through-hole at a boundary of the pixel, the through-hole overlapping the protrusion pattern.

[0166] 18. The display device according to clause 16, wherein the organic layer covers upper and side surfaces of the bank and does not cover end portions of the protruding pattern.

[0167] 19. The display device according to any one of clauses 13 to 18, wherein the organic layer is further provided on an upper surface of the protruding pattern, and the organic layer provided on the upper surface of the protruding pattern and the organic layer provided on the upper surface and side surfaces of the bank are separated.

[0168] 20. The display device according to clause 19, further comprising a first passivation layer between the substrate and the protruding pattern, wherein, at a boundary of the pixel, a second thickness of the first passivation layer overlapping the protruding pattern is greater than a first thickness of the first passivation layer not overlapping the protruding pattern.

[0169] 21. The display device according to clause 20, wherein a width of the first passivation layer having the second thickness is smaller than a width of the protruding pattern.

[0170] 22. The display device according to clause 20 or 21, wherein a surface roughness of an upper surface of the first passivation layer having the first thickness is greater than a surface roughness of an upper surface of the first passivation layer having the second thickness.

[0171] Although examples have been described above with reference to the accompanying drawings, those skilled in the art will appreciate that the above technical configurations can be implemented in other specific forms without changing their characteristics. Therefore, it should be understood that the above examples are illustrative and not restrictive in all aspects. In addition, the scope of this application is described by the claims to be described below rather than by the specific embodiments. In addition, the meaning and scope of the claims and all changes or modifications derived from equivalent concepts should be interpreted as being included within the scope of this application.

[0172] Description of Reference Numerals

[0173] 10.10_1: Display device

[0174] 100, 100_1: Display panel

[0175] CL1: First conductive layer

[0176] CL2: Second conductive layer

[0177] CL3, CL3_1: third conductive layer

[0178] PT: Highlight Pattern

Claims

1. A display device comprising: a substrate, the substrate comprising a display area and a non-display area, the display area comprising a plurality of pixels, and the non-display area surrounding the display area; a protruding pattern, the protruding pattern being provided on the substrate and located at a boundary between adjacent pixels; an anode electrode, the anode electrode being disposed on each pixel on the substrate; a bank disposed on the anode electrode and exposing the protruding pattern; as well as an organic layer, the organic layer being disposed on the anode electrode and the bank, The organic layer is discontinuous at the boundary of the pixel.

2. The display device according to claim 1, wherein The organic layer is divided by the protrusion pattern at the boundary of the pixel.

3. The display device according to claim 1, wherein The bank partially exposes an upper surface of the anode electrode and includes a through hole at a boundary of the pixel, the through hole overlapping the protrusion pattern.

4. The display device according to claim 3, wherein The organic layer covers upper and side surfaces of the bank and does not cover end portions of the protruding pattern.

5. The display device according to claim 4, wherein The organic layer is further disposed on an upper surface of the protruding pattern, and the organic layer disposed on the upper surface of the protruding pattern is separated from the organic layer disposed on an upper surface and a side surface of the bank.

6. The display device according to claim 3, further comprising a first passivation layer between the substrate and the protruding pattern, in, At a boundary of the pixel, a second thickness of the first passivation layer overlapping the protrusion pattern is greater than a first thickness of the first passivation layer not overlapping the protrusion pattern.

7. The display device according to claim 6, wherein: A width of the first passivation layer having the second thickness is smaller than a width of the protruding pattern.

8. The display device according to claim 6, wherein: A surface roughness of an upper surface of the first passivation layer having the first thickness is greater than a surface roughness of an upper surface of the first passivation layer having the second thickness.

9. The display device according to claim 6, further comprising: a second passivation layer, the second passivation layer being disposed between the substrate and the anode electrode, and the second passivation layer being not disposed at a boundary of the pixel; as well as A planarization layer is provided between the second passivation layer and the anode electrode, and the planarization layer is not provided at a boundary of the pixel.

10. The display device according to claim 1, wherein The pixel includes a light-emitting area and a non-light-emitting area, and the protruding pattern is provided in the non-light-emitting area. 11 . The display device of claim 1 , further comprising a cathode electrode on the organic layer, the cathode electrode directly contacting a side surface of the protrusion pattern.

12. The display device according to claim 1, wherein A portion of the organic layer is disposed on the protrusion pattern, and a remaining portion of the organic layer not disposed on the protrusion pattern is physically separated from a portion disposed on the protrusion pattern.

13. A display device comprising: a substrate, the substrate comprising a display area and a pad area, the display area comprising a plurality of pixels, and the pad area being close to the display area; a first conductive layer on the substrate, wherein the first conductive layer includes a data line and a light blocking layer; a semiconductor layer on the first conductive layer, the semiconductor layer overlapping the light blocking layer; a gate insulating layer on the semiconductor layer; a second conductive layer on the gate insulating layer, the second conductive layer comprising a first pad electrode disposed in the pad region, a gate electrode overlapping the channel region of the semiconductor layer, a source electrode connected to the source region of the semiconductor layer, and a drain electrode connected to the drain region of the semiconductor layer; a first passivation layer, the first passivation layer being disposed on the second conductive layer; a third conductive layer disposed on the first passivation layer and including a second pad electrode disposed on the first pad electrode in the pad region and a protrusion pattern located at a boundary of the pixel; as well as An organic layer is discontinuous at a boundary of the pixel due to the protruding pattern.

14. The display device according to claim 13, wherein: The organic layer is divided by the protrusion pattern at the boundary of the pixel.

15. The display device according to claim 13, further comprising: an anode electrode, the anode electrode being disposed on the third conductive layer and in each pixel; as well as A bank is provided on the anode electrode and exposes the protruding pattern.

16. The display device according to claim 15, wherein The organic layer is disposed on the anode electrode and the bank.

17. The display device according to claim 15, wherein: The bank partially exposes an upper surface of the anode electrode and includes a through hole at a boundary of the pixel, the through hole overlapping the protrusion pattern.

18. The display device according to claim 16, wherein: The organic layer covers upper and side surfaces of the bank and does not cover end portions of the protruding pattern.

19. The display device according to claim 18, wherein The organic layer is further disposed on an upper surface of the protruding pattern, and the organic layer disposed on the upper surface of the protruding pattern is separated from the organic layer disposed on an upper surface and a side surface of the bank.

20. The display device according to claim 19, wherein The first passivation layer is disposed between the substrate and the protruding pattern, Wherein, at a boundary of the pixel, a second thickness of the first passivation layer overlapping the protruding pattern is greater than a first thickness of the first passivation layer not overlapping the protruding pattern.

21. The display device according to claim 20, wherein A width of the first passivation layer having the second thickness is smaller than a width of the protruding pattern.

22. The display device according to claim 20, wherein A surface roughness of an upper surface of the first passivation layer having the first thickness is greater than a surface roughness of an upper surface of the first passivation layer having the second thickness.

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