Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes: an insulating layer; an electrode portion provided on the insulating layer; a protective layer disposed on the electrode portion; and a plurality of conductive bonding portions disposed on the protective layer, in which each of the plurality of conductive bonding portions includes a through electrode penetrating the protective layer, in which an upper surface of the protective layer includes a concave surface disposed between the plurality of through electrodes, a separation distance in the vertical direction between the concave surface and the electrode portion is smaller than a thickness of at least one of the plurality of through electrodes.

Description

Technical Field

[0001] Embodiments relate to a circuit board and a semiconductor package including the same. Background Art

[0002] As the performance of electrical and electronic products improves, technologies for arranging more semiconductor devices on a limited-size semiconductor package circuit board are being proposed and studied. However, since typical semiconductor packages are based on mounting a single semiconductor device, there are limitations in achieving ideal performance.

[0003] Therefore, semiconductor packages have recently been developed that use multiple circuit boards to mount multiple semiconductor devices. This semiconductor package has a structure in which multiple semiconductor devices are connected to each other horizontally and / or vertically on the circuit board. Consequently, the semiconductor package has the advantages of efficiently utilizing the mounting area of the semiconductor devices and transmitting high-speed signals through short signal transmission paths between the semiconductor devices.

[0004] Furthermore, due to the trend toward higher integration, semiconductor packages used in products such as the Internet of Things (IoT), autonomous vehicles, and high-performance servers are increasing in the number of semiconductor devices and / or the size of each semiconductor device. However, due to limitations in masks and other techniques, the concept is expanding to include semiconductor chiplets that separate the functional parts of semiconductor devices.

[0005] Therefore, mutual communication between semiconductor devices and / or semiconductor chiplets is becoming important, and therefore, there is a trend to provide an interposer between a circuit board of a semiconductor package and the semiconductor device.

[0006] The interposer can be used as a redistribution layer, which gradually increases the width or depth of the circuit pattern from the semiconductor device to the semiconductor package to facilitate mutual communication between semiconductor devices and / or semiconductor chiplets, or interconnect the semiconductor device and the semiconductor package circuit board, thereby smoothly transmitting electrical signals between the semiconductor device and the semiconductor package circuit board having a larger circuit pattern than the circuit pattern of the semiconductor device.

[0007] At the same time, as the number of input terminals and output terminals of the semiconductor device increases, the miniaturization of the leads and / or bumps becomes important. Therefore, the intervals between the bumps become narrower. In addition, the circuit board includes an electrode portion electrically connected to the semiconductor device and / or semiconductor chiplet, and a protective layer provided on the electrode portion. At this time, the electrode portion, the protective layer, and the semiconductor device and / or semiconductor chiplet are each made of different materials. Therefore, the thermal expansion coefficients of the electrode portion, the thermal expansion coefficients of the protective layer, and the thermal expansion coefficients of the semiconductor device and / or semiconductor chiplet are different from each other.

[0008] The thermal expansion coefficient of the protective layer is greater than the thermal expansion coefficient of the electrode portion, the semiconductor device and / or the semiconductor chiplet. Therefore, due to the thermal stress applied in the use environment of the semiconductor package, the protective layer may expand and / or contract more than the electrode portion, the semiconductor device and / or the semiconductor chiplet.

[0009] In addition, if the protective layer repeatedly expands and / or contracts due to thermal stress, cracks may appear at the electrical connection points between the electrode portion and the semiconductor device and / or semiconductor chiplet, and stress may be applied to leads or bumps with fine pitch, which may cause problems such as cracks in the leads or bumps. As a result, the mechanical reliability and / or electrical reliability of the semiconductor package may deteriorate. Summary of the Invention

[0010] Technical issues

[0011] The embodiment provides a circuit board having a novel structure and a semiconductor package including the same.

[0012] Furthermore, the embodiment provides a circuit board capable of improving reliability of electrical connection between semiconductor devices and a semiconductor package including the same.

[0013] Furthermore, the embodiment provides a circuit board including a protection layer capable of alleviating thermal deformation caused by thermal stress, and a semiconductor package including the same.

[0014] The technical problems to be solved by the proposed embodiments are not limited to the above-mentioned technical problems, and those skilled in the art in the art to which the proposed embodiments pertain may clearly understand other technical problems not mentioned from the following description.

[0015] Technical Solution

[0016] According to an embodiment, a circuit board includes: an insulating layer; an electrode portion arranged on the insulating layer; a protective layer arranged on the electrode portion; and a plurality of conductive joining portions arranged on the protective layer, wherein each of the plurality of conductive joining portions includes a through-electrode penetrating the protective layer, wherein the upper surface of the protective layer includes a concave surface arranged between the plurality of through-electrodes, wherein a separation distance between the concave surface and the electrode portion in a vertical direction is less than a thickness of at least one through-electrode among the plurality of through-electrodes.

[0017] Furthermore, each of the plurality of conductive joining portions further includes a protruding electrode provided on the through-electrode.

[0018] Furthermore, the width of the concave surface in the horizontal direction is smaller than the separation pitch between the plurality of protruding electrodes.

[0019] Furthermore, the concave surface does not overlap with each of the protruding electrodes of the plurality of conductive joining portions in the vertical direction.

[0020] Furthermore, the width of the concave surface in the horizontal direction is equal to the separation pitch between the plurality of protruding electrodes.

[0021] In addition, the width of the concave surface in the horizontal direction is greater than the separation pitch between the plurality of protruding electrodes.

[0022] In addition, the width of the concave surface in the horizontal direction is equal to the separation pitch between the plurality of through electrodes.

[0023] Furthermore, the protruding electrode of each of the plurality of conductive joining portions includes a convex portion that overlaps with the concave surface in the vertical direction and corresponds to the concave surface.

[0024] In addition, the concave surface includes an arc surface from the upper surface to the lower surface of the protective layer.

[0025] Furthermore, the depth of the concave surface is smaller than the thickness of the through electrode.

[0026] Furthermore, the depth of the concave surface is the same as the thickness of the through electrode.

[0027] Furthermore, the depth of the concave surface is greater than the thickness of the through electrode, and at least a portion of the concave surface is positioned lower than the upper surface of the electrode portion.

[0028] Meanwhile, a semiconductor package according to an embodiment includes: the above-mentioned circuit board; contacts provided on a plurality of conductive joints of the above-mentioned circuit board; and a semiconductor device attached to the contacts, wherein the concave surface overlaps the semiconductor device in a vertical direction.

[0029] In addition, the semiconductor package also includes a connecting member embedded in the insulating layer, and the semiconductor device includes a first semiconductor device and a second semiconductor device, the first semiconductor device includes a first terminal overlapping with the connecting member in a vertical direction, and the second semiconductor device is spaced apart from the first semiconductor device in a horizontal direction and includes a second terminal overlapping with the connecting member in the vertical direction.

[0030] Furthermore, the concave surface includes a first concave surface overlapping with the connection member in the vertical direction and a second concave surface not overlapping with the connection member in the vertical direction, and the first concave surface and the second concave surface have different widths in the horizontal direction.

[0031] In addition, the width of the first concave surface in the horizontal direction is smaller than the width of the second concave surface in the horizontal direction.

[0032] Furthermore, at least a portion of the electrode portion is embedded in the insulating layer, and the contact member is embedded in the insulating layer and provided between the electrode portion and the pad portion of the connection member.

[0033] Beneficial effects

[0034] Embodiments may improve mechanical reliability and / or physical reliability of a circuit board and a semiconductor package including the same.

[0035] Specifically, the semiconductor package includes an insulating layer, an electrode portion disposed on the insulating layer, a protective layer disposed on the electrode portion, and a plurality of conductive bonding portions disposed on the protective layer. Furthermore, each of the plurality of conductive bonding portions includes a through-electrode penetrating the protective layer. Furthermore, the upper surface of the protective layer includes a concave surface disposed between the plurality of through-electrodes.

[0036] Furthermore, the concave surface provided on the upper surface of the protective layer may serve to buffer thermal deformation such as expansion and / or contraction of the protective layer due to thermal stress acting on the protective layer.

[0037] That is, the concave surface is used to increase the surface area of the upper surface of the protective layer. The concave surface is used to increase the surface area of the upper surface of the protective layer provided between a plurality of conductive joints. Thus, the embodiment can solve the problem of electrical open circuits between the conductive joints, the contact portions and the semiconductor device that may occur due to thermal stress acting on the semiconductor package. For example, the embodiment can prevent cracks from occurring in the conductive joints and / or the electrode portions by using the concave surface provided on the upper surface of the protective layer. In addition, the embodiment can prevent stress from being applied to the electrode portions and / or the conductive joints having a fine pitch by using the concave surface provided on the upper surface of the protective layer. Thus, the embodiment can improve the mechanical reliability and / or electrical reliability of the semiconductor package.

[0038] Specifically, when thermal stress is applied to the protective layer, thermal deformation such as expansion and / or contraction of the protective layer may occur, and the stress caused by the thermal deformation of the protective layer may be transmitted to the conductive joint. Here, thermal deformation can mean that the volume of the protective layer changes due to the expansion and / or contraction of the protective layer. In addition, when the stress caused by the thermal deformation of the protective layer is continuously applied to the conductive joint, cracks may occur in the joint portion between the conductive joint and the electrode portion or in the joint portion between the conductive joint and the contact portion. This may lead to an electrical open circuit problem between the circuit board and the semiconductor device.

[0039] In contrast, the upper surface of the protective layer of an embodiment includes a concave surface disposed between the conductive joints. The concave surface disposed on the upper surface of the protective layer can be used to mitigate expansion and / or contraction of the protective layer due to thermal stress and further minimize thermal deformation (e.g., volume change) of the protective layer due to thermal stress.

[0040] Thus, the multiple concave surfaces can minimize the transfer of stress due to thermal stress to the conductive joint, contact portion, and semiconductor device. Consequently, embodiments can stably attach the semiconductor device to the circuit board, thereby improving the mechanical and electrical reliability between the circuit board and the semiconductor device. Furthermore, embodiments can stably operate the semiconductor device, thereby improving the operational reliability of electronic products, such as servers, that utilize semiconductor packaging.

[0041] Furthermore, the protective layer, the conductive joint, and the semiconductor device are made of different materials and therefore have different coefficients of thermal expansion. Therefore, due to the difference in thermal expansion coefficients between them, the protective layer with the relatively large thermal expansion coefficient may experience the greatest thermal deformation. In this case, embodiments can minimize thermal deformation of the protective layer, such as expansion and / or contraction, by providing multiple concave surfaces in the protective layer to buffer thermal deformation, thereby improving the mechanical and / or electrical reliability of the semiconductor package.

[0042] In addition, the concave surface provided in the protective layer has a circular arc surface from the upper surface to the lower surface of the protective layer. Thus, the embodiment can further improve the effect of preventing stress by the concave surface. For example, when the concave surface has a square shape, stress may be concentrated at the corners of the concave surface, which may lead to problems of mechanical reliability or electrical reliability degradation. In contrast, the embodiment can provide a concave surface with a circular arc surface, thereby preventing stress from being concentrated in a specific part of the concave surface. Therefore, the embodiment can further improve the physical reliability and / or electrical reliability of the semiconductor package.

[0043] At the same time, the protective layer includes a plurality of first concave surfaces that overlap with the connecting member in the vertical direction and a plurality of second concave surfaces that do not overlap with the connecting member in the vertical direction. At this time, the width of the first concave surface in the horizontal direction is different from the width of the second concave surface in the horizontal direction. That is, the width of the first concave surface in the horizontal direction is smaller than the width of the second concave surface in the horizontal direction. Thus, the embodiment can prevent the height deviation between the plurality of conductive joints through the first concave surface and the second concave surface, and further prevent the contact area between the through-electrode of the conductive joint and the protective layer from being reduced. Therefore, the embodiment can improve the mechanical reliability and / or electrical reliability of the semiconductor package. In addition, compared with the case where the width of the second concave surface is the same as the width of the first concave surface, the embodiment can increase the surface area of the protective layer by making the width of the second concave surface greater than the width of the first concave surface, and can maximize the effect of preventing stress caused by thermal deformation.

[0044] Furthermore, the concave surface provided in the protective layer can address electrical short circuits that may occur due to horizontal expansion of the contact portion in response to heat and pressure applied to the contact portion. For example, when the contact portion expands horizontally in response to heat and pressure applied to the contact portion, the concave surface of the protective layer can act as a dam to prevent expansion and movement of the contact portion. Thus, embodiments can further improve the electrical reliability of the semiconductor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a cross-sectional view showing a semiconductor package according to a first embodiment.

[0046] Figure 2 It shows Figure 1 An enlarged view of an enlarged area A of a semiconductor package.

[0047] Figure 3 It shows Figure 1 FIG. 1 is an enlarged view of a first variation of an enlarged region A of a semiconductor package.

[0048] Figure 4 It shows Figure 1 FIG. 1 is an enlarged view of a second variation of an enlarged region A of a semiconductor package.

[0049] Figure 5 It shows Figure 1 FIG1 is an enlarged view of a third modified example of an enlarged region A of a semiconductor package.

[0050] Figure 6 It shows Figure 1 FIG. 1 is an enlarged view of a fourth variation of an enlarged region A of a semiconductor package.

[0051] Figure 7 is a diagram showing a semiconductor package according to a second embodiment.

[0052] Figure 8 is a diagram showing a semiconductor package according to a third embodiment.

[0053] Figures 9 to 17 It shows the manufacturing process in order Figure 1 A method of semiconductor packaging is shown in FIG. DETAILED DESCRIPTION

[0054] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein the same reference numerals are used to represent the same or similar elements, and redundant descriptions thereof will be omitted. The suffixes "module" and "part" of the components used in the following description are given or mixed only in consideration of ease of preparation of the description, and have no meaning or function to be distinguished from each other. In addition, in the following description of the embodiments of the present invention, when it is determined that the key points of the embodiments disclosed herein may be vague, the detailed description of the related art will be omitted. In addition, the accompanying drawings are included to provide a further understanding of the present invention, and the accompanying drawings are incorporated into and constitute a part of this specification, and it should be understood that the present invention is intended to cover all modifications, equivalents or substitutes that fall within the spirit and scope of the present invention.

[0055] Terms including ordinal numbers (such as first, second, etc.) may be used to describe various components, but the elements are not limited to these terms. These terms are only used to distinguish one component from another.

[0056] When a component is referred to as being "connected" or "in contact with" another component, it may be directly connected or joined to the other component, but it should be understood that other components may exist between them. When a component is referred to as being "directly connected" or "directly in contact with" another component, it should be understood that other components may not exist between them.

[0057] A singular expression includes a plural expression unless the context clearly implies otherwise.

[0058] In this application, terms such as "include" or "have" are used to specify the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification. However, it should be understood that these terms do not exclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0059] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0060] electronic devices

[0061] Before describing the embodiments, an electronic device to which the semiconductor package of the embodiments is applied will be briefly described. The electronic device includes a mainboard (not shown). The mainboard can be physically and / or electrically connected to various components. For example, the mainboard can be connected to the semiconductor package of the embodiments. Various semiconductor devices can be mounted on the semiconductor package.

[0062] Semiconductor devices may include active devices and / or passive devices. An active device may be a semiconductor chip in the form of an integrated circuit (IC), in which hundreds to millions of devices are integrated into one semiconductor device. A semiconductor device may be a logic chip, a memory chip, or the like. A logic chip may be a central processing unit (CPU), a graphics processing unit (GPU), or the like. For example, a logic chip may be an application processor (AP) chip including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an ASIC (application-specific IC), or a chipset including a specific combination of those listed so far.

[0063] The memory chip may be a stacked memory such as HBM. The memory chip may also include a memory chip such as a volatile memory (eg, DRAM), a non-volatile memory (eg, ROM), a flash memory, or the like.

[0064] Furthermore, the semiconductor device may be an integrated passive device (IPD), a multilayer ceramic capacitor (MLCC), or a silicon-based capacitor.

[0065] On the other hand, the product group of the semiconductor package to which the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package) and SIP (System In Package), but is not limited thereto.

[0066] Furthermore, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet computer, a laptop computer, a netbook computer, a television, a video game console, a smart watch, an automobile, etc. However, the embodiment is not limited thereto, and in addition to these, it may be any other electronic device that processes data.

[0067] semiconductor packaging

[0068] Figure 1 is a cross-sectional view showing a semiconductor package according to a first embodiment, Figure 2 It shows Figure 1 An enlarged view of an enlarged area A of a semiconductor package.

[0069] refer to Figure 1 and Figure 2 , the semiconductor package includes a circuit board 100 .

[0070] In one embodiment, circuit board 100 represents a packaged circuit board. For example, circuit board 100 is disposed on a main circuit board of an electronic device and semiconductor devices 320 and 330, and can electrically couple them. Specifically, circuit board 100 can electrically connect semiconductor devices 320 and 330 horizontally, while also electrically connecting semiconductor devices 320 and 330 vertically to the main circuit board of the electronic device.

[0071] In another embodiment, circuit board 100 represents a relay circuit board disposed between the package circuit board and semiconductor devices 320 and 330. For example, the relay circuit board may represent an interposer. In other words, circuit board 100 may be electrically connected horizontally between semiconductor devices 320 and 330, and vertically between semiconductor devices 320 and 330 and the package circuit board.

[0072] The semiconductor package includes semiconductor devices 320 , 330 electrically connected to the circuit board 100 .

[0073] The semiconductor devices 320 , 330 may include a first semiconductor device 320 and a second semiconductor device 330 , but are not limited thereto. As an example, three or more semiconductor devices may be provided on the circuit board 100 .

[0074] The semiconductor devices 320 and 330 include contact portions 310 disposed between the semiconductor devices 320 and 330 and the circuit board 100. The contact portions 310 electrically connect the terminals 325 and 335 of the semiconductor devices 320 and 330 to the electrode portions of the circuit board 100.

[0075] The contact portion 310 electrically connects the electrode portion of the circuit board 100 and the terminals 325 and 335 of the semiconductor devices 320 and 330 by using at least one bonding method of wire bonding, solder bonding, and direct metal bonding.

[0076] The wire bonding method refers to electrically connecting the electrode portion of the circuit board 100 and the terminals 325 , 335 of the semiconductor devices 320 , 330 by using a conductor such as gold (Au).

[0077] The solder bonding method electrically connects the electrode portion of the circuit board 100 and the terminals 325 , 335 of the semiconductor devices 320 , 330 by using a material including at least one of Sn, Ag, and Cu.

[0078] The direct metal-to-metal bonding method involves applying heat and pressure between the electrode portion of circuit board 100 and the terminals 325, 335 of semiconductor devices 320, 330 to recrystallize the metal, thereby directly bonding the electrode portion of circuit board 100 and the terminals 325, 335 of semiconductor devices 320, 330, without using solder, wires, conductive adhesives, etc. In this case, contact portion 310 may represent a metal layer formed between the electrode portion of circuit board 100 and the terminals 325, 335 of semiconductor devices 320, 330 by recrystallization.

[0079] For example, by thermal compression bonding, the contact portion 310 can electrically connect the electrode portion of the circuit board 100 to the terminals 325 and 335 of the semiconductor devices 320 and 330. The thermal compression bonding method can reduce the volume of the contact portion 310 and prevent short circuits between multiple contact portions.

[0080] The semiconductor package includes a connection member 200 embedded in a circuit board 100 .

[0081] The connection member 200 partially overlaps the semiconductor devices 320 , 330 disposed on the circuit board 100 in the vertical direction.

[0082] The connection member 200 electrically connects a portion of the terminal 325 of the first semiconductor device 320 and a portion of the terminal 335 of the second semiconductor device 330 .

[0083] Semiconductor devices may be mounted on the circuit board 100 as functionally separated chiplet units, or a plurality of semiconductor devices having different functions, such as a CPU and a GPU, or a GPU and an HBM, and the connection member 200 may perform the function of electrically connecting them horizontally.

[0084] In addition, since the width of the electrode portion provided in the circuit board 100 is significantly different from the width of the terminals 325 and 335 of the semiconductor devices 320 and 330, a buffering effect is required for the electrode pattern for electrical connection. Here, buffering effect can mean having a size between the width of the electrode portion of the circuit board 100 and the width of the terminals of the semiconductor device. The connecting member 200 can have a buffering function for the electrode pattern for electrical connection.

[0085] In one embodiment, the connection member 200 is an inorganic bridge. For example, the inorganic bridge can be a silicon bridge. For example, the connection member 200 can include a silicon circuit board and a redistribution layer.

[0086] In another embodiment, the connecting member 200 is an organic bridge. For example, the connecting member 200 may include an organic material. For example, the connecting member 200 may include an organic circuit board, in which the silicon circuit board of the inorganic bridge is replaced by the organic material.

[0087] Connecting member 200 includes pad portion 210. Pad portion 210 of connecting member 200 is electrically connected to an electrode portion of circuit board 100. Furthermore, the electrode portion of circuit board 100 is electrically connected to terminals 325, 335 of semiconductor devices 320, 330. Therefore, connecting member 200 is electrically connected between terminals 325, 335 of semiconductor devices 320, 330.

[0088] The circuit board 100 electrically connected to the connection member 200 and the semiconductor devices 320 , 330 is described in detail as follows.

[0089] The circuit board 100 includes an insulating layer 110 .

[0090] The insulating layer 110 may include an organic material without a reinforcing member, which achieves excellent workability, thinning of the circuit board, and miniaturization of the electrode portion 120 provided in the circuit board 100. For example, the insulating layer 110 of the circuit board 100 may use ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric Resin), BT, etc., which are products released by Ajinomoto Co., Ltd.

[0091] The insulating layer 110 is provided in multiple layers.

[0092] The insulating layer 110 may be provided on an inner layer of the circuit board. Here, being provided on an inner layer means that another insulating layer (eg, a protective layer) may be provided on at least one of an upper portion and a lower portion of the insulating layer 110 .

[0093] For example, the insulating layer 110 may be configured as follows Figure 1 Four layers are shown, but not limited to.

[0094] In one embodiment, the multiple layers of the insulating layer 110 may be provided with the same insulating material, but the embodiment is not limited thereto, and at least one layer of the multiple layers of the insulating layer 110 may be provided with an insulating material different from at least other layers.

[0095] When the insulating layer 110 is provided as a multilayer, the interfaces between the multiple layers may not be easily distinguishable. In this case, the interfaces between the layers can be distinguished by the electrode portion 120 provided in the insulating layer 110. The electrode portion 120 includes a wiring electrode portion 121 and a via electrode portion 122. The wiring electrode portion 121 is provided at the interface between the multiple layers of the insulating layer 110. The wiring electrode portion 121 includes a pad and / or a trace, etc. In addition, the via electrode portion 122 electrically connects the wiring electrode portions 121 provided in different layers in the vertical direction. The via electrode portion 122 includes a via electrode. At this time, the width of the wiring electrode portion 121 in the horizontal direction is different from the width of the via electrode portion 122 in the horizontal direction. Therefore, the difference between the width of the wiring electrode portion 121 in the horizontal direction and the width of the via electrode portion 122 in the horizontal direction can be used to distinguish the interfaces between the multiple layers of the insulating layer 110. In addition, the slope of the side surface of the wiring electrode portion 121 is different from the slope of the side surface of the via electrode portion 122. Therefore, the difference between the slope of the side surface of the wiring electrode part 121 and the slope of the side surface of the via electrode part 122 may be used to distinguish the interface between the multiple layers of the insulating layer 110 .

[0096] However, even if the multiple layers of the insulating layer 110 include the same insulating material, interfaces between the multiple layers may be distinguished.

[0097] Through the stacked structure of the insulating layer 110 , the circuit board 100 of the embodiment can be electrically connected between the semiconductor devices 320 , 330 and the package circuit board and / or the main circuit board.

[0098] In one embodiment, at least one of the multiple layers of insulation layer 110 includes a reinforcement member. In one embodiment, the reinforcement member may be glass fiber. In another embodiment, the reinforcement member may be GCP (Glass Core Primer). When the reinforcement member is glass fiber, at least one of the multiple layers of insulation layer 110 is configured as a core layer, and thus circuit board 100 is configured as a core circuit board.

[0099] In addition, the rigidity of the circuit board 100 can be improved by including at least one layer of a reinforcing member in the multiple layers of the insulating layer 110. For example, the reinforcing member can have a function of preventing the circuit board 100 and the semiconductor package from being significantly bent in a specific direction. Therefore, the insulating layer 110 can be prevented from bending during the manufacturing process of the circuit board 100, thereby improving the position accuracy of the electrode portion 120 and further improving the alignment therebetween. In addition, while ensuring the rigidity of the circuit board 100, the semiconductor devices 320, 330 can be coupled to the circuit board 100, and the semiconductor devices 320, 330 can operate stably. In addition, electronic products such as servers to which the semiconductor package of the embodiment is applied can operate stably, and thus product reliability can be improved.

[0100] Furthermore, when at least one of the multiple layers of insulating layer 110 includes a reinforcement member, the layer including the reinforcement member is provided with insulating member 110A. Insulating member 110A penetrates the insulating layer including the reinforcement member. Insulating member 110A may be provided with a hole-blocking ink, but is not limited thereto. Insulating member 110A is surrounded by via-hole electrode portion 122 that penetrates electrode portion 120 of the layer including the reinforcement member. Insulating member 110A can resolve electrical and / or mechanical reliability issues that may arise due to the through-hole of the layer including the reinforcement member not being completely filled with via-hole electrode portion 122.

[0101] The electrode portion 120 of the circuit board 100 includes a wiring electrode portion 121 and a via electrode portion 122 .

[0102] The wiring electrode portion 121 may be horizontally disposed between the multiple layers of the insulating layer 110 , and the via electrode portion 122 may be vertically disposed to penetrate each of the multiple layers of the insulating layer 110 .

[0103] The electrode portions 120 are divided into multiple groups. The electrode portions 120 include first electrode portions 120A that overlap with the semiconductor devices 320, 330 and the connection member 200 in the vertical direction. Furthermore, the electrode portions 120 include second electrode portions 120B that overlap with the first electrode portions 120A in the horizontal direction and do not overlap with the connection member 200 in the vertical direction. The second electrode portions 120B overlap with the semiconductor devices 320, 330 in the vertical direction. In other words, the first electrode portions 120A overlap with the connection member 200 and the semiconductor devices 320, 330 in the vertical direction, respectively, while the second electrode portions 120B overlap with the semiconductor devices 320, 330 in the vertical direction and do not overlap with the connection member 200 in the vertical direction.

[0104] At least one of the width of the wiring electrodes of the first electrode portion 120A, the width of the via electrodes of the first electrode portion 120A, and the spacing between the plurality of wiring electrodes spaced apart in the horizontal direction of the first electrode portion 120A may be different from the width of the wiring electrodes of the second electrode portion 120B, the width of the via electrodes of the second electrode portion 120B, and the spacing between the plurality of wiring electrodes spaced apart in the horizontal direction of the second electrode portion 120B. For example, at least one of the width of the wiring electrodes of the first electrode portion 120A, the width of the via electrodes, and the spacing between the plurality of wiring electrodes spaced apart in the horizontal direction may be smaller than the width of the wiring electrodes of the second electrode portion 120B, the width of the via electrodes, and the spacing between the plurality of wiring electrodes spaced apart in the horizontal direction.

[0105] Thus, the embodiment can arrange the wiring electrodes and the via electrodes of the first electrode portion 120A in a limited space, and can stably electrically connect the semiconductor devices 320 and 330 and the connection member 200 .

[0106] The circuit board 100 includes a conductive bonding portion 130. The conductive bonding portion 130 is provided on the electrode portion 120. For example, the conductive bonding portion 130 is provided on the uppermost wiring electrode portion among the wiring electrode portions provided on the respective layers of the insulating layer 110.

[0107] The conductive bonding portion 130 penetrates a first protective layer 140 described later. The conductive bonding portion 130 protrudes above the first protective layer 140 described later. The conductive bonding portion 130 may be referred to as a bump.

[0108] The conductive joint portion 130 protrudes above the first protective layer 140 of the circuit board 100 to stably connect with the terminals 325 and 335 of the semiconductor devices 320 and 330 using the contact portion 310. Therefore, the conductive joint portion 130 can separate the contact portion 310 and the circuit board 100 by a certain distance and improve the positional alignment between the conductive joint portion 130 and the terminals of the semiconductor devices 320 and 330.

[0109] The conductive bonding portion 130 includes a through electrode that penetrates the first protective layer 140 and a protruding electrode that protrudes above the first protective layer 140. The through electrode of the conductive bonding portion 130 is provided on the electrode portion 120 and penetrates the first protective layer 140. The through electrode of the conductive bonding portion 130 may refer to an area that overlaps with the first protective layer 140 in a horizontal direction in the entire area in the thickness direction of the conductive bonding portion 130.

[0110] The protruding electrode of the conductive joint 130 is disposed on the through-electrode of the conductive joint 130. Furthermore, the protruding electrode of the conductive joint 130 is disposed on the first protective layer 140. For example, the protruding electrode of the conductive joint 130 is disposed so as to extend horizontally on the through-electrode of the conductive joint 130. For example, the horizontal width of the protruding electrode of the conductive joint 130 is greater than the horizontal width of the through-electrode of the conductive joint 130. Therefore, the protruding electrode of the conductive joint 130 includes a first region that vertically overlaps with the through-electrode, and a second region that vertically overlaps with the first protective layer 140 but does not overlap with the through-electrode.

[0111] The conductive bonding part 130 is provided in plural. The conductive bonding part 130 is provided in plural and is spaced apart from the electrode part 120 in the horizontal direction. The conductive bonding part 130 includes a first conductive bonding part 130A provided on the first electrode part 120A and a second conductive bonding part 130B provided on the second electrode part 120B.

[0112] The first conductive bonding portion 130A is provided between the first electrode portion 120A on the connection member 200 and the terminals of the semiconductor devices 320 and 330 . The second conductive bonding portion 130B is provided between the second electrode portion 120B and the terminals of the semiconductor devices 320 and 330 .

[0113] In addition, each of the first conductive joint portion 130A and the second conductive joint portion 130B includes a through electrode and a protruding electrode. The first conductive joint portion 130A includes a first through electrode 130a1 and a first protruding electrode 130a2. The second conductive joint portion 130B includes a second through electrode 130b1 and a second protruding electrode 130b2.

[0114] The spacing between the plurality of first through-electrodes 130a1 of the first conductive joint 130A is different from the spacing between the plurality of second through-electrodes 130b1 of the second conductive joint 130B. For example, the spacing between the plurality of first through-electrodes 130a1 is smaller than the spacing between the plurality of second through-electrodes 130b1. Furthermore, the spacing between the plurality of first protruding electrodes 130a2 of the first conductive joint 130A is different from the spacing between the plurality of second protruding electrodes 130b2 of the second conductive joint 130B. Furthermore, the spacing between the plurality of first protruding electrodes 130a2 of the first conductive joint 130A is smaller than the spacing between the plurality of second protruding electrodes 130b2 of the second conductive joint 130B. In other words, the first conductive joint 130A is connected to terminals of the semiconductor devices 320 and 330 that have a relatively fine width and / or fine pitch. Furthermore, the second conductive joint 130B is connected to terminals of the semiconductor devices 320 and 330 that have a relatively larger width and / or larger pitch than the first conductive joint 130A. Therefore, the embodiment allows the intervals between the first through electrodes 130 a 1 of the plurality of first conductive bonding portions 130A to be smaller than the intervals between the second through electrodes 130 b 1 of the plurality of second conductive bonding portions 130B, thereby stably connecting the connection member 200 and the semiconductor devices 320 , 330 .

[0115] The circuit board 100 includes a protective layer, which includes a first protective layer 140 disposed above the insulating layer 110 and a second protective layer 150 disposed below the insulating layer 110 .

[0116] The first protective layer 140 protects the upper surface of the insulating layer 110 and the wiring electrode portion 121 provided on the uppermost side of the insulating layer 110. The second protective layer 150 protects the lower surface of the insulating layer 110 and the wiring electrode portion provided on the lowermost side of the insulating layer 110.

[0117] In one embodiment, the first protection layer 140 and the second protection layer 150 may include the same insulating material as the insulating layer 110 .

[0118] In another embodiment, the first protection layer 140 and the second protection layer 150 may include an insulating material different from the insulating layer 110 and may be, for example, a solder resist.

[0119] The first protective layer 140 and the second protective layer 150 may be solder resist layers including an organic polymer material. For example, the first protective layer 140 and the second protective layer 150 may include epoxy acrylate resin. In addition, the first protective layer 140 and the second protective layer 150 may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, the embodiment is not limited thereto, and the first protective layer 140 and the second protective layer 150 may be any one of a photo solder resist layer, a cover layer (cover-lay) and a polymer material.

[0120] The upper surface of the first protection layer 140 includes a concave surface 140CP.

[0121] The concave surface 140CP is disposed between the plurality of conductive joining portions 130 .

[0122] The concave surface 140CP is provided concavely from the upper surface toward the lower surface of the first protective layer 140. Furthermore, the concave surface 140CP is provided on the upper surface of the first protective layer 140 between the plurality of conductive bonding portions 130. For example, the concave surface 140CP is provided between the through-electrodes of the plurality of conductive bonding portions 130. Furthermore, the concave surface 140CP can prevent stress caused by thermal deformation from being transferred to the conductive bonding portions 130, and in particular, can prevent stress from being transferred to the through-electrodes of the conductive bonding portions 130 having relatively small widths.

[0123] The concave surface 140CP has the function of increasing the surface area of the upper surface of the first protective layer 140. The concave surface 140CP is used to increase the surface area of the upper surface of the first protective layer 140 disposed between the plurality of conductive bonding portions 130. That is, when the concave surface 140CP is disposed on the upper surface of the first protective layer 140, the surface area between the plurality of conductive bonding portions 130 can be increased according to the horizontal width and vertical depth of the concave surface 140CP compared to a case where the upper surface of the first protective layer 140 is a flat surface.

[0124] Thus, embodiments can solve the problem of electrical open circuits between the conductive joint 130, the contact portion 310, and the semiconductor devices 320 and 330 that may be caused by thermal stress acting on the semiconductor package. For example, embodiments can prevent cracks from occurring in the conductive joint 130 and / or the electrode portion 120 by using the concave surface 140CP provided on the upper surface of the first protective layer 140. In addition, embodiments can prevent stress from being applied to the electrode portion 120 and / or the conductive joint 130 having a fine pitch by using the concave surface 140CP provided on the upper surface of the first protective layer 140. Thus, embodiments can improve the mechanical and / or electrical reliability of the semiconductor package.

[0125] Specifically, the semiconductor devices 320, 330 are electrically connected to the conductive bonding portion 130 through the contact portion 310. In addition, the conductive bonding portion 130 protrudes above the first protective layer 140 while penetrating the first protective layer 140.

[0126] At this time, when thermal stress is applied to the first protective layer 140, thermal deformation such as expansion and / or contraction of the first protective layer 140 may occur, and stress caused by the thermal deformation of the first protective layer 140 may be applied to the conductive bonding portion 130 penetrating the first protective layer 140. Thermal deformation may mean that the volume of the first protective layer 140 changes due to the expansion and / or contraction of the first protective layer 140.

[0127] If thermal deformation of the first protective layer 140 is repeated, stress may be applied to the conductive bonding portion 130 provided in the first protective layer 140, and due to the stress, cracks may occur in the electrical connection portion between the conductive bonding portion 130 and the electrode portion 120. As a result, the conductive bonding portion 130 may be peeled off from the electrode portion 120, which may cause mechanical reliability and / or electrical reliability problems.

[0128] In addition, if thermal deformation of the first protective layer 140 is repeated, stress may be applied to the contact portion 310 provided on the conductive joint portion 130, and thus cracks may occur in the contact portion 310. As a result, an electrical open circuit problem may occur between the semiconductor devices 320, 330 and the conductive joint portion 130.

[0129] The concave surface 140CP provided on the upper surface of the first protective layer 140 is used to increase the surface area of the upper surface of the first protective layer 140, thereby reducing the degree of thermal deformation (e.g., expansion and / or contraction) of the first protective layer 140 caused by thermal stress. Thus, the concave surface 140CP provided on the upper surface of the first protective layer 140 can prevent stress caused by thermal deformation of the first protective layer 140 from acting on the conductive bonding portion 130. For example, the concave surface 140CP can reduce stress caused by thermal stress and prevent stress from being transmitted in the direction toward the conductive bonding portion 130.

[0130] Furthermore, the concave surface 140CP may prevent impact due to stress from being transferred to the conductive bonding portion 130 , the contact portion 310 , and the terminals 325 , 335 of the semiconductor devices 320 , 330 .

[0131] Therefore, embodiments can stably attach semiconductor devices 320, 330 to circuit board 100, thereby improving mechanical and electrical reliability between circuit board 100 and semiconductor devices 320, 330. Furthermore, embodiments can stably operate semiconductor devices 320, 330, thereby improving operational reliability of electronic products, such as servers, to which semiconductor packages are applied.

[0132] In addition, the concave surface 140CP is provided with a circular arc surface from the upper surface to the lower surface of the first protective layer 140. Thus, the embodiment can further improve the stress prevention effect of the concave surface 140CP. For example, when the concave surface 140CP has a square shape, stress may be concentrated in the corners, which may lead to problems such as reduced mechanical reliability or reduced electrical reliability. In contrast, the embodiment can allow the concave surface 140CP to have an arc curve, thereby preventing stress from being concentrated in a specific portion of the concave surface 140CP. Therefore, the embodiment can further improve the physical reliability and / or electrical reliability of the semiconductor package.

[0133] Furthermore, the first protective layer 140, the conductive joint 130, and the semiconductor devices 320 and 330 may be made of different materials. For example, the first protective layer 140 may be made of solder resist, the conductive joint 130 may be made of a metal material such as copper, and the semiconductor devices 320 and 330 may be made of silicon. In this case, the first protective layer 140, the conductive joint 130, and the semiconductor devices 320 and 330 may have different coefficients of thermal expansion. For example, the first protective layer 140 may have a greater coefficient of thermal expansion than the conductive joint 130 and the semiconductor devices 320 and 330. Therefore, when the same thermal stress is applied to the first protective layer 140, the conductive joint 130, and the semiconductor devices 320 and 330, the first protective layer 140 may be subjected to the greatest degree of thermal deformation compared to the conductive joint 130 and the semiconductor devices 320 and 330.

[0134] Therefore, the embodiment can prevent stress caused by thermal deformation such as expansion and / or contraction from acting on the electrical joint between the circuit board 100 and the semiconductor devices 320, 330 by providing a concave surface 140CP on the upper surface of the first protective layer 140, thereby improving the mechanical reliability and / or electrical reliability of the semiconductor package.

[0135] Furthermore, the concave surface 140CP of the first protective layer 140 has a certain depth on the upper surface of the first protective layer 140. At this time, in the region that does not overlap with the electrode portion 120 in the vertical direction, the depth of the concave surface 140CP is less than the thickness of the first protective layer 140. For example, in the region that does not overlap with the electrode portion 120 in the vertical direction, the concave surface 140CP does not penetrate the first protective layer 140.

[0136] The concave surface 140CP is separated from the electrode portion 120 provided on the insulating layer 110 in the vertical direction. For example, the concave surface 140CP is separated from the electrode portion 120 provided on the insulating layer 110 by a separation distance T1 in the vertical direction. In this case, the separation distance T1 in the vertical direction between the electrode portion 120 and the concave surface 140CP is less than the thickness of the through-electrode of the conductive bonding portion 130. If the separation distance T1 in the vertical direction between the electrode portion 120 and the concave surface 140CP is greater than the thickness of the through-electrode of the conductive bonding portion 130, the stress prevention effect exhibited by the concave surface 140CP may be insufficient, and thus, stress caused by thermal deformation may be applied to the conductive bonding portion 130.

[0137] The concave surface 140CP is provided between the plurality of conductive bonding parts 130. At this time, the concave surface 140CP of the first protective layer 140 has different widths in the horizontal direction and is provided in plural.

[0138] The concave surface 140CP includes a first concave surface 140CP1 disposed between the plurality of first conductive joints 130A. Furthermore, the concave surface 140CP includes a second concave surface 140CP2 disposed between the plurality of second conductive joints 130B. The second concave surface 140CP2 is disposed between the first conductive joint 130A and the second conductive joint 130B disposed adjacent to each other.

[0139] For example, the first concave surface 140CP1 overlaps with the connection member 200 in the vertical direction. In addition, the second concave surface 140CP2 does not overlap with the connection member 200 in the vertical direction.

[0140] At this time, the horizontal width W1 of the first concave surface 140CP1 is different from the horizontal width W2 of the second concave surface 140CP2. For example, the horizontal width W1 of the first concave surface 140CP1 is smaller than the horizontal width W2 of the second concave surface 140CP2.

[0141] That is, the first concave surface 140CP1 is disposed between the plurality of first through-electrodes 130a1 of the first conductive joint 130A having a relatively fine pitch. In addition, the second concave surface 140CP2 is disposed between the plurality of second through-electrodes 130b1 of the second conductive joint 130B having a relatively large pitch. Therefore, the embodiment allows the width of the first concave surface 140CP1 in the horizontal direction to be different from the width of the second concave surface 140CP2 in the horizontal direction. Therefore, the embodiment can solve the problem of physical rigidity degradation caused by the reduction of the contact area between the through-electrode and the first protective layer 140 due to the first concave surface 140CP1 and the second concave surface 140CP2 in the process of forming the conductive joint 130, especially in the process of forming the through-electrode of the conductive joint 130.

[0142] Furthermore, the first concave surface 140CP1 and the second concave surface 140CP2 of the first protective layer 140 can address the electrical issue of electrically shorting multiple adjacent conductive joints 130 due to the expansion of the contacts 310 disposed on the conductive joint 130. For example, when heat and pressure are applied to the contacts 310 disposed on the conductive joint 130 and the contacts 310 expand horizontally, the first concave surface 140CP1 and the second concave surface 140CP2 of the first protective layer 140 can act as dams to prevent the contacts 310 from expanding and / or moving horizontally. Thus, embodiments can further improve the electrical reliability of the semiconductor package.

[0143] Hereinafter, various modifications of the concavity provided in the protective layer will be described.

[0144] Figure 3 It shows Figure 1 An enlarged view of a first modified example of an enlarged region A of a semiconductor package, Figure 4 It shows Figure 1 An enlarged view of a second modified example of an enlarged region A of a semiconductor package, Figure 5 It shows Figure 1 An enlarged view of a third modified example of an enlarged region A of a semiconductor package, Figure 6 It shows Figure 1 FIG. 1 is an enlarged view of a fourth variation of an enlarged region A of a semiconductor package.

[0145] first, Figure 2 The width of each of the first concave surface 140CP1 and the second concave surface 140CP2 in the horizontal direction is smaller than the separation distance between the plurality of conductive bonding parts 130 in the horizontal direction. Figure 2 The width of each of the first concave surface 140CP1 and the second concave surface 140CP2 in the horizontal direction is smaller than the separation pitch between the plurality of protruding electrodes of the conductive bonding portion 130 .

[0146] Reference Figure 3 , the width W1a of the first concave surface 140CP1a is equal to the spacing between the first protruding electrodes 130a2 of the first conductive joint 130A. In addition, the width W2a of the second concave surface 140CP2a is equal to the spacing between the second protruding electrodes 130b2 of the second conductive joint 130B. Therefore, each of the first concave surface 140CP1a and the second concave surface 140CP2a is completely disposed on the upper surface of the first protective layer 140 that does not vertically overlap with the protruding electrodes of the conductive joint 130. Figure 2 compared to, Figure 3 The first modification can further increase the width of the concave surface in the horizontal direction, thereby further increasing the surface area of the first protection layer 140 , thereby further improving the physical reliability and / or electrical reliability of the semiconductor package.

[0147] Reference Figure 4 The width W1b of the first concave surface 140CP1b is greater than the spacing between the first protruding electrodes 130a2' of the first conductive joint portion 130A. For example, the width W1b of the first concave surface 140CP1b is equal to the spacing between the first protruding electrodes 130a2' of the first conductive joint portion 130A. Therefore, the first protruding electrode 130a2' of the first conductive joint portion 130 vertically overlaps with the first concave surface 140CP1b provided in the first protective layer 140. For example, the first protruding electrode 130a2' of the first conductive joint portion 130A contacts the first concave surface 140CP1b. For example, the first protruding electrode 130a2' of the first conductive joint portion 130A includes a convex portion that contacts the first concave surface 140CP1b. Thus, embodiments can increase the contact area between the first conductive joint portion 130A and the first protective layer 140 by allowing the convex portion of the first protruding electrode 130a2' of the first conductive joint portion 130A to contact the first concave surface 140CP1b of the first protective layer 140. Thus, the embodiment can improve the bonding strength between the first conductive bonding portion 130A and the first protective layer 140. For example, the convex portion of the first protruding electrode 130a2' of the first conductive bonding portion 130A can serve as an anchor to increase the bonding strength with the first protective layer 140.

[0148] Furthermore, the width W2b of the second concave surface 140CP2b is greater than the spacing between the second protruding electrodes 130b2' of the second conductive joint 130B. For example, the width W2b of the second concave surface 140CP2b is equal to the spacing between the second protruding electrodes 130b2' of the second conductive joint 130B. Therefore, the second protruding electrodes 130b2' of the second conductive joint 130B vertically overlap with the second concave surface 140CP2b provided in the first protective layer 140. For example, the second protruding electrodes 130b2' of the second conductive joint 130B are in contact with the second concave surface 140CP2b. For example, the second protruding electrodes 130b2' of the second conductive joint 130B include a convex portion that contacts the second concave surface 140CP2b. Thus, embodiments can increase the contact area between the second conductive joining portion 130B and the first protective layer 140 by allowing the convex portion of the second protruding electrode 130b2′ of the second conductive joining portion 130B to contact the second concave surface 140CP2b of the first protective layer 140. Thus, embodiments can improve the bonding strength between the second conductive joining portion 130B and the first protective layer 140. For example, the convex portion of the second protruding electrode 130b2′ of the second conductive joining portion 130B can serve as an anchor to increase the bonding strength with the first protective layer 140.

[0149] Reference Figure 5The first protective layer 140 includes a first concave surface 140CP1c and a second concave surface 140CP2c. Each of the first concave surface 140CP1c and the second concave surface 140CP2c may have a thickness greater than Figure 2 The greater the depth of the concave surface.

[0150] For example, the depths of the first concave surface 140CP1c and the second concave surface 140CP2c of the first protective layer 140 are the same as the thickness T2 of the through-electrode of the conductive bonding portion 130. Thus, the embodiment can further maximize the effects of the first concave surface 140CP1c and the second concave surface 140CP2c and further improve the degree of design freedom by varying the concave surface depths.

[0151] Reference Figure 6 The first protective layer 140 includes a first concave surface 140CP1d and a second concave surface 140CP2d. Each of the first concave surface 140CP1d and the second concave surface 140CP2d may have a thickness greater than Figure 2 The greater the depth of the concave surface.

[0152] For example, the depth T3 of the first concave surface 140CP1d and the second concave surface 140CP2d of the first protective layer 140 is greater than the thickness T2 of the through-electrode of the conductive bonding portion 130. For example, at least a portion of the first concave surface 140CP1d and the second concave surface 140CP2d is positioned lower than the upper surface of the electrode portion 120. Thus, embodiments can further maximize the effects of the first concave surface 140CP1d and the second concave surface 140CP2d and further increase design freedom by varying the concave surface depths.

[0153] Figure 7 is a diagram showing a semiconductor package according to a second embodiment.

[0154] Reference Figure 7 , compared with the semiconductor package of the first embodiment, the semiconductor package of the second embodiment may have a structure in which the connection member 200 is omitted.

[0155] The semiconductor package of the second embodiment includes a circuit board 1100 including an insulating layer 1110, an electrode portion 1120, a conductive bonding portion 1130, a first protective layer 1140, and a second protective layer 1150. Furthermore, the upper surface of the first protective layer 1140 includes concave surfaces 1440CP2 disposed between the conductive bonding portions 1130.

[0156] Furthermore, the semiconductor package includes a contact portion 1310 and a semiconductor device 1320 provided on the conductive bonding portion 1130 of the circuit board 1100 .

[0157] For example, the circuit board 1100 of the semiconductor package of the second embodiment may be a 2D circuit board without including the connection member 200 embedded in the circuit board 1100 , and at least one semiconductor device 320 may be provided on the circuit board 1100 .

[0158] Figure 8 is a diagram showing a semiconductor package according to a third embodiment.

[0159] refer to Figure 8 , compared with the semiconductor package of the first embodiment, the semiconductor package of the third embodiment may have a circuit board 2100 with a different structure.

[0160] The semiconductor package of the third embodiment includes a circuit board 2100 including an insulating layer 2110, an electrode portion 2120, a conductive bonding portion 2130, a first protective layer 2140, and a second protective layer 2150. Furthermore, the upper surface of the first protective layer 2140 includes concave surfaces 2440CP2 disposed between the conductive bonding portions 2130.

[0161] Furthermore, the semiconductor package includes a contact portion 2310 and a semiconductor device 2320 provided on the conductive bonding portion 2130 of the circuit board 2100 .

[0162] Furthermore, the semiconductor package includes a connection member 2200 embedded in the insulating layer 2110 of the circuit board 2100. Furthermore, the semiconductor package includes a second contact portion 2230 embedded in the insulating layer 2110 and electrically connecting the pad portion 2210 of the connection member 2200 and the electrode portion 2120.

[0163] For example, Figure 1 The circuit board of the first embodiment may be a core circuit board, Figure 8 The circuit board can be a coreless circuit board.

[0164] In addition, set Figure 1 Each of the uppermost and lowermost wiring electrode parts 121 in the circuit board of the first embodiment may be provided to protrude above and below the insulating layer 110 .

[0165] On the contrary, the setting Figure 8 One of the uppermost and lowermost wiring electrode portions in the circuit board of the third embodiment may have a structure embedded in the insulating layer 2110. For example, the circuit board 2100 may have an ETS (Embedded Trace Substrate) structure.

[0166] That is, the circuit board 2100 includes an electrode portion 2120 provided on the connection member 2200. The electrode portion 2120 includes a first electrode portion vertically overlapping the connection member 2200 and a second electrode portion horizontally overlapping the first electrode portion and not vertically overlapping the connection member 2200.

[0167] In addition, at least a portion of each of the first electrode portion and the second electrode portion is embedded in the insulating layer 2110. Here, embedded may mean that at least a portion of the side surface of the first electrode portion and the second electrode portion is covered by the insulating layer 2110. However, in Figure 8 , the side surfaces of the first and second electrode portions are shown as being completely covered by the insulating layer 2110, but are not limited thereto. For example, a portion of the side surfaces of the first and second electrode portions may be covered by the insulating layer 2110, and the remaining portions of the side surfaces of the first and second electrode portions may be covered by the first protective layer 2140, the conductive bonding portion 2130, or a separate metal layer between the conductive bonding portion 2130 and the electrode portions.

[0168] Embodiments may improve mechanical reliability and / or physical reliability of a circuit board and a semiconductor package including the same.

[0169] Specifically, the semiconductor package includes an insulating layer, an electrode portion disposed on the insulating layer, a protective layer disposed on the electrode portion, and a plurality of conductive bonding portions disposed on the protective layer. Furthermore, each of the plurality of conductive bonding portions includes a through-electrode penetrating the protective layer. Furthermore, the upper surface of the protective layer includes a concave surface disposed between the plurality of through-electrodes.

[0170] Furthermore, the concave surface provided on the upper surface of the protective layer may serve to buffer thermal deformation such as expansion and / or contraction of the protective layer due to thermal stress acting on the protective layer.

[0171] That is, the concave surface is used to increase the surface area of the upper surface of the protective layer. The concave surface is used to increase the surface area of the upper surface of the protective layer provided between a plurality of conductive joints. Thus, the embodiment can solve the problem of electrical open circuits between the conductive joints, the contact portions and the semiconductor device that may occur due to thermal stress acting on the semiconductor package. For example, the embodiment can prevent cracks from occurring in the conductive joints and / or the electrode portions by using the concave surface provided on the upper surface of the protective layer. In addition, the embodiment can prevent stress from being applied to the electrode portions and / or the conductive joints having a fine pitch by using the concave surface provided on the upper surface of the protective layer. Thus, the embodiment can improve the mechanical reliability and / or electrical reliability of the semiconductor package.

[0172] Specifically, when thermal stress is applied to the protective layer, thermal deformation such as expansion and / or contraction of the protective layer may occur, and the stress caused by the thermal deformation of the protective layer may be transmitted to the conductive joint. Here, thermal deformation can mean that the volume of the protective layer changes due to the expansion and / or contraction of the protective layer. In addition, when the stress caused by the thermal deformation of the protective layer is continuously applied to the conductive joint, cracks may occur in the joint portion between the conductive joint and the electrode portion or in the joint portion between the conductive joint and the contact portion. This may lead to an electrical open circuit problem between the circuit board and the semiconductor device.

[0173] In contrast, the upper surface of the protective layer of an embodiment includes a concave surface disposed between the conductive joints. The concave surface disposed on the upper surface of the protective layer can be used to mitigate expansion and / or contraction of the protective layer due to thermal stress and further minimize thermal deformation (e.g., volume change) of the protective layer due to thermal stress.

[0174] Thus, the multiple concave surfaces can minimize the transfer of stress due to thermal stress to the conductive joint, contact portion, and semiconductor device. Consequently, embodiments can stably attach the semiconductor device to the circuit board, thereby improving the mechanical and electrical reliability between the circuit board and the semiconductor device. Furthermore, embodiments can stably operate the semiconductor device, thereby improving the operational reliability of electronic products, such as servers, that utilize the semiconductor package.

[0175] Furthermore, the protective layer, the conductive joint, and the semiconductor device are made of different materials and therefore have different coefficients of thermal expansion. Therefore, due to the difference in thermal expansion coefficients between them, the protective layer with the relatively large thermal expansion coefficient may experience the greatest thermal deformation. In this case, embodiments can minimize thermal deformation of the protective layer, such as expansion and / or contraction, by providing multiple concave surfaces in the protective layer to buffer thermal deformation, thereby improving the mechanical and / or electrical reliability of the semiconductor package.

[0176] In addition, the concave surface provided in the protective layer has a circular arc surface from the upper surface to the lower surface of the protective layer. Thus, the embodiment can further improve the effect of preventing stress by the concave surface. For example, when the concave surface has a square shape, stress may be concentrated at the corners of the concave surface, which may lead to problems of mechanical reliability or electrical reliability degradation. In contrast, the embodiment can provide a concave surface with a circular arc surface, thereby preventing stress from being concentrated in a specific part of the concave surface. Therefore, the embodiment can further improve the physical reliability and / or electrical reliability of the semiconductor package.

[0177] At the same time, the protective layer includes a plurality of first concave surfaces that overlap with the connecting member in the vertical direction and a plurality of second concave surfaces that do not overlap with the connecting member in the vertical direction. At this time, the width of the first concave surface in the horizontal direction is different from the width of the second concave surface in the horizontal direction. That is, the width of the first concave surface in the horizontal direction is smaller than the width of the second concave surface in the horizontal direction. Thus, the embodiment can prevent the height deviation between the plurality of conductive joints through the first concave surface and the second concave surface, and further prevent the contact area between the through-electrode of the conductive joint and the protective layer from being reduced. Therefore, the embodiment can improve the mechanical reliability and / or electrical reliability of the semiconductor package. In addition, compared with the case where the width of the second concave surface is the same as the width of the first concave surface, the embodiment can increase the surface area of the protective layer by making the width of the second concave surface greater than the width of the first concave surface, and can maximize the effect of preventing stress caused by thermal deformation.

[0178] Furthermore, the concave surface provided in the protective layer can address electrical short circuits that may occur due to horizontal expansion of the contact portion in response to heat and pressure applied to the contact portion. For example, when the contact portion expands horizontally in response to heat and pressure applied to the contact portion, the concave surface of the protective layer can act as a dam to prevent expansion and movement of the contact portion. Thus, embodiments can further improve the electrical reliability of the semiconductor package.

[0179] Figures 9 to 17 It shows the manufacturing process in order Figure 1 A method of semiconductor packaging is shown in FIG.

[0180] Reference Figure 9 , the embodiment performs a process of preparing the insulating layer 110 , a process of forming a cavity in the insulating layer 110 , a process of embedding the connection member 200 in the cavity of the insulating layer 110 , and a process of forming the electrode part 120 in the insulating layer 110 .

[0181] Next, refer to Figure 10 In order to form the through hole 140TH of the first protection layer 140 , the embodiment performs a process of forming a dry film DF.

[0182] Next, refer to Figure 11 The embodiment performs a process of forming a dry film pattern DFP by exposing and developing the dry film DF. The dry film pattern DFP is disposed on the electrode portion 120 corresponding to a region where the through hole 140TH of the first protective layer 140 is to be formed.

[0183] Next, refer to Figure 12 , the embodiment performs a process of forming a first protective layer 140 covering the dry film pattern DFP on the insulating layer 110. Also, the embodiment performs a process of forming a second protective layer 150 under the insulating layer 110.

[0184] Next, refer to Figure 13 , embodiments perform a process of etching the first protective layer 140 to reduce the thickness of the first protective layer 140. For example, embodiments may etch the first protective layer 140 so that the thickness of the first protective layer 140 is less than or equal to the dry film pattern DFP.

[0185] Additionally, embodiments may perform a process of exposing and developing the second protective layer 150 to form a through hole in the second protective layer 150 .

[0186] Next, refer to Figure 14 In the embodiment, a process of partially etching the upper surface of the first protective layer 140 to form a concave surface 140CP is performed. At this time, the concave surface 140CP can be formed in plurality while being spaced apart from the through hole 140TH provided in the first protective layer 140 in the horizontal direction by a certain distance.

[0187] Next, refer to Figure 15 In the embodiment, a process of removing the dry film pattern DFP is performed, thereby forming a through hole 140TH corresponding to the position where the dry film pattern DFP is removed in the first protective layer 140 .

[0188] Thus, embodiments may form the through hole 140TH and the concave surface 140CP in the first protection layer 140 .

[0189] However, embodiments may be implemented by removing Figures 9 to 15 Other processes than the illustrated process form the through holes 140TH and the concave surfaces 140CP in the first protection layer 140 .

[0190] For example, embodiments may perform a process of forming the through hole 140TH by exposing and developing the first protective layer 140. In addition, after forming the through hole 140TH, a process of partially etching the upper surface of the first protective layer 140 to form the concave surface 140CP may be performed.

[0191] For another example, in an embodiment, the first protective layer 140 may be processed by a first method to form the through hole 140TH or the concave surface 140CP, and the first protective layer may be processed by a second method different from the first method to form the concave surface 140CP or the through hole 140TH. For example, the first method may be a laser method, and the second method may be a photolithography process.

[0192] Next, refer to Figure 16 In the embodiment, a process of forming the conductive joint portion 130 is performed. The conductive joint portion 130 includes a through electrode disposed in the through hole 140TH of the first protective layer 140 and a protruding electrode disposed on the through electrode. At this time, the embodiment can form the concave surface 140CP on the upper surface of the first protective layer 140 by considering the width of the protruding electrode of the conductive joint portion 130.

[0193] Next, refer to Figure 17 , embodiments perform a process of providing the contact portion 310 on the conductive joint portion 130. Thereafter, embodiments perform a process of mounting the semiconductor devices 320 and 330 on the contact portion 310. Thus, embodiments can mount the semiconductor devices 320 and 330 on the conductive joint portion 130 facing the concave surface 140CP of the first protective layer 140.

[0194] On the other hand, when a circuit board having the above-mentioned characteristics of the present invention is used in IT equipment or household appliances such as smart phones, server computers, TVs, etc., functions such as signal transmission or power supply can be stably performed. For example, when a circuit board having the characteristics of the present invention performs a semiconductor packaging function, the circuit board can be used to safely protect the semiconductor chip from external moisture or pollutants, or, problems such as leakage current, electrical short circuits between terminals, and electrical open circuits of terminals supplied to the semiconductor chip can be solved. In addition, when the function of signal transmission is dominant, noise problems can be solved. Thus, the circuit board having the above-mentioned characteristics of the present invention can maintain the stable functions of IT equipment or household appliances, so that the entire product and circuit board to which the present invention is applied can achieve functional unification or technical interlocking with each other.

[0195] When a circuit board having the above-described characteristics of the present invention is used in a transport device such as a vehicle, it can resolve issues with signal distortion transmitted to the transport device. Alternatively, it can further enhance the safety of the transport device by safely protecting the semiconductor chip controlling the transport device from external influences and resolving issues such as leakage current or electrical shorts between terminals, or electrical opens in the terminals supplying the semiconductor chip. Thus, the transport device and the circuit board employing the present invention can achieve functional integrity or technical interlocking with each other.

[0196] The characteristics, structures, and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. In addition, the characteristics, structures, and effects shown in each embodiment can be combined or modified by a person skilled in the art to which the embodiment belongs, even with respect to other embodiments. Therefore, it should be understood that the contents related to such combinations and such modifications are included in the scope of the embodiments.

[0197] The above description focuses on the embodiments, but it is merely illustrative and does not limit the embodiments. Those skilled in the art will appreciate that various modifications and applications not shown above are possible without departing from the basic features of the embodiments. For example, each component specifically shown in the embodiments may be modified and implemented. Furthermore, it should be understood that differences associated with such modifications and applications are included within the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board, comprising: Insulation layer; an electrode portion disposed on the insulating layer; a protective layer disposed on the electrode portion; and A plurality of conductive bonding portions are provided on the protective layer, wherein each of the plurality of conductive joints comprises a through electrode penetrating the protective layer, The upper surface of the protective layer includes a concave surface arranged between the plurality of through electrodes. The vertical separation distance between the concave surface and the electrode portion is smaller than the thickness of at least one through-electrode among the plurality of through-electrodes.

2. The circuit board according to claim 1, wherein Each of the plurality of conductive joining portions further includes a protruding electrode provided on the through electrode.

3. The circuit board according to claim 2, wherein: A width of the concave surface in a horizontal direction is smaller than a separation pitch between the plurality of protruding electrodes.

4. The circuit board according to claim 3, wherein: The concave surface does not overlap with each of the protruding electrodes of the plurality of conductive joining portions in a vertical direction.

5. The circuit board according to claim 2, wherein A width of the concave surface in a horizontal direction is equal to a separation pitch between the plurality of protruding electrodes.

6. The circuit board according to claim 2, wherein A width of the concave surface in a horizontal direction is greater than a separation pitch between the plurality of protruding electrodes.

7. The circuit board according to claim 6, wherein: A width of the concave surface in a horizontal direction is equal to a separation pitch between the plurality of through electrodes.

8. The circuit board according to claim 7, wherein: The protruding electrode of each of the plurality of conductive joining portions includes a convex portion that overlaps with the concave surface in a vertical direction and corresponds to the concave surface.

9. The circuit board according to claim 1, wherein The concave surface includes an arc surface from the upper surface to the lower surface of the protective layer.

10. The circuit board according to claim 1, wherein The depth of the concave surface is smaller than the thickness of the through electrode.

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