Display panel electrostatic damage improvement method based on ashing process

Abstract

The invention discloses a display panel electrostatic damage improvement method based on an ashing process, which comprises the following steps: preparing an ashing chamber, placing a display panel on a plate electrode in the ashing chamber, setting the top temperature and the side wall temperature of the ashing chamber to be 50-55 DEG C, and setting the pressure in the ashing chamber to be 2.36-2.96 pa; the ashing gas is introduced, and the ashing gas containing oxygen is introduced into the ashing chamber; radio frequency power is supplied to the plasma generation and ashing chamber, ashing gas is excited to be ionized through electric energy, plasma is generated, the plasma reacts with the photoresist on the display panel, and the reaction time is 40-45 s; and carrying out self-cleaning operation on the ashing chamber, namely carrying out self-cleaning operation on the ashing chamber after taking out the display panel after the reaction is completed. Thus, by controlling the temperature and the pressure intensity in the ashing chamber and meanwhile increasing the self-cleaning operation of the ashing chamber, damage to products caused by electrostatic damage can be prevented and reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a method for improving electrostatic damage to a display panel based on an ashing process. Background Art

[0002] LTPS, or low-temperature polysilicon, is a technology used to manufacture thin-film transistor liquid crystal displays (TFT-LCDs). In the LTPS process, the planarization layer plays a crucial role. This planarization layer typically undergoes an ashing process, which involves the use of oxygen to react with photoresist to produce CO, CO2, H2O, and other substances. This ashing process removes foreign matter from the planarization layer, improving contact between the ITO and S / D layers in the display panel (TFT array glass substrate) circuitry.

[0003] During the ashing process of the planarization layer, the static electricity removal method of the planarization layer is generally to use oxygen ions to neutralize the charge to eliminate static electricity. However, as the production time increases and the number of products increases, the display panel will continue to rub against the flat electrode in the ashing chamber, which will cause dirt on the surface of the flat electrode. Although oxygen ions can remove some of the charge, a small amount of charge will remain in the dirty area of the flat electrode. As the number of products increases, the accumulated charge cannot be effectively extracted, migrated and released, and then accumulates and instantly generates a huge current, causing the planarization layer to be damaged by static electricity, which in turn causes the circuit in the display panel to be damaged by static electricity. The damaged display panel screen will show vertical line defects and display abnormalities, and the yield rate is low. Summary of the Invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a method for improving electrostatic damage to display panels based on an ashing process, thereby reducing or eliminating the risk of electrostatic damage to the planarization layer of the display panel during production, thereby improving the yield of the display panel.

[0005] The object of the present invention is achieved through the following technical solutions:

[0006] A method for improving electrostatic damage to a display panel based on an ashing process, comprising:

[0007] Prepare the ashing chamber, place the display panel on the flat electrode in the ashing chamber, set the top temperature and side wall temperature of the ashing chamber to 50°C-55°C, and set the pressure in the ashing chamber to 2.36Pa-2.96Pa;

[0008] ashing gas is introduced, and ashing gas containing oxygen is introduced into the ashing chamber;

[0009] Plasma generation: the ashing chamber is supplied with radio frequency power, which excites the ashing gas to ionize and generate plasma. The plasma reacts with the photoresist on the display panel, and the reaction time is 40s-45s.

[0010] The ashing chamber is self-cleaned. After the display panel that has completed the reaction is taken out, the ashing chamber is self-cleaned.

[0011] In one embodiment, in the ashing chamber preparation step, the bottom temperature in the ashing chamber is set to 25° C.-35° C., and the bottom temperature is kept stable.

[0012] In one embodiment, the bottom temperature is set to 30°C.

[0013] In one embodiment, the top temperature and the side wall temperature are both set to 55°C.

[0014] In one embodiment, the pressure is set to 2.66 Pa.

[0015] In one embodiment, the flow rate of the ashing gas is 800 SCCM.

[0016] In one embodiment, the radio frequency power is 1200W.

[0017] In one embodiment, during the self-cleaning operation step of the ashing chamber, a self-cleaning gas including oxygen and argon is introduced into the ashing chamber to perform a self-cleaning operation on the ashing chamber, and the self-cleaning time is 25s-35s.

[0018] In one embodiment, a functional coating is provided on the surface of the flat electrode, and the functional coating includes an yttrium oxide layer, a tungsten layer and an yttrium oxide layer stacked in sequence from the outside to the inside.

[0019] In one embodiment, the thickness of the inner yttrium oxide layer is 550 μm-600 μm.

[0020] Compared with the prior art, the present invention has at least the following advantages:

[0021] The present invention provides a method for improving electrostatic damage to display panels based on an ashing process, which optimizes the temperature and pressure in the ashing chamber and increases the self-cleaning operation of the ashing chamber to reduce the generation and accumulation of charges, thereby preventing and reducing damage to products caused by electrostatic damage and improving product production quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments.

[0023] Figure 1 1 is a flow chart of a method for improving electrostatic damage to a display panel based on an ashing process in one embodiment of the present invention; DETAILED DESCRIPTION

[0024] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings.

[0025] See also Figure 1 As shown, a method for improving electrostatic damage of a display panel based on an ashing process includes:

[0026] Step S100: preparing an ashing chamber, placing the display panel on a flat electrode in the ashing chamber, setting the top temperature and side wall temperature of the ashing chamber to 50°C-55°C, and setting the pressure in the ashing chamber to 2.36Pa-2.96Pa;

[0027] It should be noted that:

[0028] In traditional ashing processes, the triboelectric effect is often exacerbated by the unreasonable temperature distribution within the chamber. Therefore, a more reasonable temperature distribution within the chamber is required. The following is a comparison of the temperatures:

[0029] Comparative Example (Traditional Process): The top and side wall temperatures in the ashing chamber were set to 65°C, and the triboelectric charge density was measured to be 5.1×1012 (e / cm 2 ), ESD breakdown rate 5.3%;

[0030] Example: The top temperature and side wall temperature in the ashing chamber were both set to 55°C, and the triboelectric charge density was measured to be 1.2×1012 (e / cm 2 ), ESD breakdown rate 0.4%;

[0031] Among them, the friction charge density is measured and converted by a non-contact surface potentiometer, and the calculation of the ESD breakdown rate can be performed by electrical testing and calculation using a semiconductor parameter analyzer. By comparison, when the top temperature and side wall temperature of the display panel are high, the friction charge generated by the thermal effect during the reaction process will be greater, and the static charge will accumulate more. Therefore, by lowering the top temperature and side wall temperature of the ashing chamber, the friction charge generated by the thermal effect during the reaction process is reduced, thereby reducing the accumulation of static charge, and thus reducing the damage to the display panel caused by electrostatic damage. By lowering the top temperature and side wall temperature from 65°C to below 55°C, the friction charge density and ESD breakdown rate are significantly reduced.

[0032] Furthermore, in traditional ashing processes, the pressure inside the ashing chamber is usually high. Higher pressures can lead to increased static electricity accumulation. That is, at higher pressures, the frequency of gas molecule collisions increases, the triboelectric effect is enhanced, and the triboelectric charge density between the display panel and the flat electrode can increase by 2-3 times, significantly increasing the risk of static electricity damaging the circuits on the display panel. Therefore, it is necessary to reduce the pressure inside the ashing chamber. The following is a comparison of pressures:

[0033] Comparative Example (Traditional Process): The pressure in the ashing chamber is set to 5.32 Pa, and the charge density of the display panel is measured to be 7.8×1012 (e / cm 2 ), ESD breakdown rate is 6.1%;

[0034] Example: The pressure in the ashing chamber is set at 2.66 Pa, and the charge density of the display panel is measured to be 1.8×1012 (e / cm 2 ), ESD breakdown rate is 0.7%;

[0035] In other words, the pressure is reduced from the traditional 5.32 Pa to 2.66 Pa, placing the ashing chamber at a lower pressure. This lower pressure can extend the mean free path of electrons, thereby reducing random collisions of charges and weakening the triboelectric effect, significantly improving the problem of static electricity damage to the circuits in the display panel. Furthermore, the lower pressure in the ashing chamber can further reduce the risk of contamination of the flat electrode. This lower pressure can increase the pumping speed of the ashing reaction products and reduce redeposition of reaction products.

[0036] Step S200: introducing ashing gas, introducing ashing gas containing oxygen into the ashing chamber;

[0037] Step S300: Plasma generation: RF power is applied to the ashing chamber to excite the ashing gas to ionize and generate plasma. The plasma reacts with the photoresist on the display panel. The reaction time is 40s-45s.

[0038] It should be noted that the reaction time between plasma and the photoresist on the display panel is also crucial to the elimination of static electricity. Traditional ashing processes have a relatively short ashing reaction time, resulting in a short ion neutralization time, which is not conducive to the elimination of static electricity. The following is a comparison of reaction time:

[0039] Comparative Example (Traditional Process): The ashing reaction time is 30s, and the surface charge density of the display panel is measured to be 1.5×1012 (e / cm 2 ), ESD breakdown rate 3.2%;

[0040] Example 1: The ashing reaction time is 40s, and the surface charge density of the display panel is measured to be 5.0×1011 (e / cm 2 ), ESD breakdown rate 0.8%;

[0041] Example 2: The ashing reaction time is 45s, and the surface charge density of the display panel is measured to be 3.0×1011 (e / cm 2 ), ESD breakdown rate 0.6%;

[0042] Among them, the surface charge density can be tested using a non-contact electrostatic voltmeter, and the calculation of the ESD breakdown rate can be performed by electrical testing using a semiconductor parameter analyzer; the surface charge density is significantly reduced when the ashing reaction time is 40s-45s, and the electrostatic breakdown rate is also significantly reduced; in order to ensure work efficiency, the preferred ashing reaction time is 40s. In this way, by extending the ashing reaction time from 30s to 40s, the charge neutralization efficiency can be enhanced, that is, the active oxygen free radicals and electrons in the plasma can neutralize the surface charge, and extending the reaction time can make the charge neutralization reaction more sufficient, while reducing the residual charge density; in addition, a longer ashing reaction time can gradually oxidize pollutants (such as carbides) on the surface of the flat electrode, reduce charge traps, and block the vicious cycle of "dirt-charge accumulation-electrostatic damage". At the same time, it is necessary to avoid the ashing reaction time being too long, which will cause damage to other functional layers on the display panel, and to avoid excessive loss of the flattening layer, which will affect the morphology control, so the ashing reaction time is controlled between 40s-45s, preferably 40s.

[0043] Step S400: performing a self-cleaning operation on the ashing chamber. After taking out the display panel that has completed the reaction, the ashing chamber is subjected to a self-cleaning operation.

[0044] It should be noted that by adding a self-cleaning operation to the ashing chamber, the source of static electricity accumulation can be eliminated. This means removing surface contaminants within the ashing chamber, such as by-products and carbides produced by the ashing reaction, and blocking charge traps. Furthermore, adding a self-cleaning operation can also shorten the life of the functional coating on the flat electrode, preventing accumulated contaminants on the flat electrode from accelerating wear of the flat electrode's functional coating, thereby extending the service life of the flat electrode.

[0045] It should also be noted that the self-cleaning operation is performed in a non-production state. That is, after the display panel completes the ashing process, the ashing chamber automatically starts the self-cleaning operation to remove dirt and reaction products in the ashing chamber and reduce the generation of triboelectric charges. Considering production efficiency, the self-cleaning operation can be performed once every 8 batches;

[0046] In one embodiment, during the self-cleaning operation step of the ashing chamber, a self-cleaning gas including oxygen and argon (Ar) is introduced into the ashing chamber to perform a self-cleaning operation on the ashing chamber, and the self-cleaning time is 25s-35s. The flow rate of oxygen is 1800-2500 SCCM, preferably 2000 SCCM, and the flow rate of argon is 15-40 SCCM, preferably 20 SCCM. The active oxygen free radicals generated by the oxygen plasma oxidize organic matter such as photoresist residues and carbides into volatile gases to achieve the effect of removing dirt and products. At the same time, adding a small amount of argon can further improve the effect of removing dirt and accumulated products of the flat electrode. For example, Ar+ ions can remove stubborn pollutants such as metal oxides and carbonized layers through kinetic energy sputtering, improve the self-cleaning effect, and block charge traps. The self-cleaning time is between 25s-35s, preferably 30s, which ensures the self-cleaning effect while maintaining high production efficiency.

[0047] In one embodiment, in order to further improve the improvement effect of electrostatic damage to the planarization layer, in the ashing chamber preparation step, the bottom temperature in the ashing chamber is set to 25° C.-35° C., and the bottom temperature is kept stable.

[0048] It should be noted that the bottom temperature in the ash chamber is set at 25°C-35°C, that is, the bottom temperature is kept at a relatively low temperature close to room temperature, so that the bottom temperature in the ash chamber forms a gradient temperature difference with the top temperature. Through the synergistic effect of thermodynamics and plasma physics, the stability of the process is significantly improved, thereby improving electrostatic damage. Specifically, by setting the bottom temperature at 25°C-35°C and keeping the bottom temperature stable, the deformation of the substrate in the display panel due to differences in thermal expansion coefficients can be reduced, thereby avoiding distortion of the photoresist pattern; in addition, keeping the bottom temperature stable can also avoid large temperature fluctuations, which cause the metal inner wall and substrate in the ash chamber to expand and contract with heat, produce micro cracks or protrusions, increase the surface area and adsorption points, and thus lead to excessive secondary adsorption of reaction products. That is, keeping the temperature stable can maintain surface flatness, reduce the probability of adsorption due to deformation, and thus reduce the accumulation of charge. Furthermore, maintaining a relatively low temperature at the bottom of the ashing chamber reduces the thermal expansion difference between the substrate and the flat electrodes in the display panel, lowering the triboelectric effect during contact and separation. This significantly improves the effectiveness of reducing electrostatic damage to the planarization layer. The bottom temperature is preferably 30°C.

[0049] In one embodiment, the pressure is set to 2.66 Pa. This means the pressure is reduced from the traditional 5.32 Pa by 2.66 Pa. To ensure the process temperature, the ashing gas flow rate is changed from 1000 SCCM to 800 SCCM, meaning the ashing gas flow rate is preferably 800 SCCM. The corresponding RF power is also changed from 1500 W to 1200 W, meaning the RF power is preferably 1200 W.

[0050] In one embodiment, the surface of the flat electrode is provided with a functional coating, which includes an yttrium oxide layer, a tungsten layer, and an yttrium oxide layer stacked sequentially from the outside to the inside. The outermost yttrium oxide layer acts as a plasma corrosion inhibitor, provides electrostatic insulation, and forms a wear-resistant barrier. The middle tungsten layer acts as a stress buffer, while promoting uniform heat distribution and preventing local overheating of the flat electrode. The innermost yttrium oxide layer protects the flat electrode substrate and forms a chemically inert interface with the tungsten layer to prevent the formation of metal compounds at high temperatures. In this embodiment, the thickness of the outer yttrium oxide layer is 600 μm, the thickness of the middle tungsten layer is 50 μm, and the thickness of the inner yttrium oxide layer is 550 μm-600 μm, preferably 550 μm, to ensure that the inner yttrium oxide layer has sufficient thickness. In this way, by ensuring the thickness of the functional coating, it is possible to prevent the functional coating from becoming thinner due to increased friction during production, thereby reducing the risk of electrostatic damage caused by exposed inner substrate of the flat electrode.

[0051] The above-described embodiments merely represent several implementations of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A method for improving electrostatic damage of a display panel based on an ashing process, characterized in that: include: Prepare the ashing chamber, place the display panel on the flat electrode in the ashing chamber, set the top temperature and side wall temperature of the ashing chamber to 50°C-55°C, and set the pressure in the ashing chamber to 2.36Pa-2.96Pa; ashing gas is introduced, and ashing gas containing oxygen is introduced into the ashing chamber; Plasma generation: the ashing chamber is supplied with radio frequency power, which excites the ashing gas to ionize and generate plasma. The plasma reacts with the photoresist on the display panel, and the reaction time is 40s-45s. The ashing chamber is self-cleaned. After the display panel that has completed the reaction is taken out, the ashing chamber is self-cleaned.

2. The method for improving electrostatic damage of a display panel based on an ashing process according to claim 1, characterized in that: In the ashing chamber preparation step, the bottom temperature in the ashing chamber is set to 25° C.-35° C., and the bottom temperature is kept stable.

3. The method for improving electrostatic damage of a display panel based on an ashing process according to claim 2, characterized in that: The bottom temperature was set to 30°C.

4. The method for improving electrostatic damage of a display panel based on an ashing process according to claim 1, characterized in that: The top temperature and the side wall temperature were both set to 55°C.

5. The method for improving electrostatic damage of a display panel based on an ashing process according to claim 4, characterized in that: The pressure is set to 2.66 Pa.

6. The method for improving electrostatic damage of a display panel based on an ashing process according to claim 5, characterized in that: The flow rate of the ashing gas is 800 SCCM.

7. The method for improving electrostatic damage of a display panel based on an ashing process according to claim 6, characterized in that: The radio frequency power is 1200W.

8. The method for improving electrostatic damage of a display panel based on an ashing process according to any one of claims 1 to 7, characterized in that: In the self-cleaning operation step of the ashing chamber, a self-cleaning gas including oxygen and argon is introduced into the ashing chamber to perform a self-cleaning operation on the ashing chamber, and the self-cleaning time is 25s-35s.

9. The method for improving electrostatic damage of a display panel based on an ashing process according to any one of claims 1 to 7, characterized in that: The surface of the flat electrode is provided with a functional coating, and the functional coating comprises an yttrium oxide layer, a tungsten layer and an yttrium oxide layer stacked in sequence from the outside to the inside.

10. The method for improving electrostatic damage of a display panel based on an ashing process according to claim 9, characterized in that: The thickness of the yttrium oxide layer located in the inner layer is 550 μm-600 μm.

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