Data error correction method and device, storage equipment and computer readable storage medium

Abstract

The invention relates to the field of data error correction, in particular to a data error correction method and device, storage equipment and a computer readable storage medium. The data error correction method comprises the following steps: acquiring an error correction result of performing hard decoding error correction on first read data, wherein the first read data is data obtained by reading storage data of a target storage area in a flash memory in a hard decoding mode; if the error correction result is that hard decoding error correction fails, second read data is obtained, and the second read data is data obtained by reading storage data of a target storage area in the flash memory in a soft decoding mode; if the error bit of the second read data is smaller than the pre-stored first soft solution error correction bit, soft solution error correction is conducted on the second read data, and the storage address of the stored data is kept unchanged. The data migration frequency can be reduced, so that the write amplification is reduced, and the read-write performance of the flash memory is improved.

Description

Technical Field

[0001] The present application relates to the field of data error correction, and specifically to a data error correction method, apparatus, storage device, and computer-readable storage medium. Background Art

[0002] In flash memory, the basic unit for storing data is called a cell. Each cell records different data by injecting and releasing electrons. The movement of electrons in and out of the cell causes wear and tear on the cell. As the degree of wear increases, the probability of electrons escaping from the cell increases, causing the data stored in the cell to jump and increasing the probability of read errors.

[0003] Therefore, flash memory needs to cooperate with the error correction algorithm in the main controller to perform data error detection and correction. During the error correction process, if too much erroneous data is found, it indicates that the data in the storage block is unreliable. The data in the storage block will be moved to reduce the probability of read errors when reading data.

[0004] However, frequent data movement can lead to decreased flash read performance and increased write amplification. Summary of the Invention

[0005] In view of the above, the present application provides a data error correction method, apparatus, storage device and computer-readable storage medium, which can reduce the number of data moves, thereby reducing write amplification and improving flash memory read performance.

[0006] An embodiment of the present application provides a data error correction method, which is applied to a storage device. The storage device includes at least one flash memory and a master controller. The flash memory and the master controller communicate via a bus. The master controller includes a hard decoding mode and a soft decoding mode. The data error correction method includes:

[0007] Obtaining an error correction result of performing hard error correction on first read data, where the first read data is data obtained by reading stored data in a target storage area in the flash memory in the hard decoding mode;

[0008] If the error correction result is a hard decoding error correction failure, obtaining second read data, where the second read data is data obtained by reading stored data in the target storage area in the flash memory in the soft decoding mode;

[0009] If the number of error bits of the second read data is smaller than the pre-stored first soft error correction bit number, soft error correction is performed on the second read data to obtain correct data and maintain the storage address of the stored data unchanged.

[0010] In the embodiment of the present application, after the main control enters the soft decoding mode, if the number of error bits in the second read data is less than the number of error correction bits in the first soft decoding, the storage area of the storage space (block) is not relocated, which can avoid frequent data movement of the storage device. On the basis of ensuring data reliability, it can reduce the number of data movements, reduce write amplification, and improve the read and write performance of the flash memory.

[0011] In some embodiments, the first soft-decoding error correction bit number is greater than the pre-stored hard-decoding error correction bit number, and the first soft-decoding error correction bit number is less than the pre-stored second soft-decoding error correction bit number; the hard-decoding error correction bit number is the maximum error correction bit number of the master control in the hard decoding mode; the second soft-decoding error correction bit number is the maximum error correction bit number of the master control in the soft decoding mode.

[0012] In some embodiments, the data error correction method further includes: if the number of error bits of the second read data is greater than the first soft error correction bit number, and the number of error bits of the second read data is less than the second soft error correction bit number, performing soft error correction on the second read data to obtain correct data; and performing data migration on the stored data.

[0013] The fact that the number of error bits in the second read data is greater than the number of error correction bits in the first soft decoding indicates that the reliability of the stored data is low. Therefore, the embodiment of the present application performs data migration on the stored data, which is beneficial to improving the accuracy of subsequent reading of the stored data.

[0014] In some embodiments, maintaining the storage address of the stored data unchanged includes:

[0015] The number of erasure and write times of the target storage area is obtained; if the number of erasure and write times is less than a preset threshold value, the storage address of the stored data is maintained unchanged.

[0016] The number of erase and write times can reflect the reliability of the target storage area to a certain extent. The smaller the number of erase and write times of the target storage area, the stronger the reliability of the target storage area, the smaller the probability of jumps in cell storage data, and the lower the probability of read errors. Therefore, in the embodiment of the present application, when the number of erase and write times is less than the preset threshold, data migration is not performed, which can further improve product reliability.

[0017] In some embodiments, the data error correction method further includes: if the number of erasures is greater than the number threshold, and the number of error bits of the second read data is less than the second soft error correction bit number, moving the stored data.

[0018] A large number of erase and write times indicates that the data stored in the target storage area is prone to jumps, and the probability of subsequent read errors will be greatly increased. Therefore, the embodiment of the present application performs data migration in this case, which can further improve the reliability of the storage device.

[0019] In some embodiments, the hard decoding mode is configured with a set of candidate read voltages; and obtaining an error correction result of performing hard error correction on the first read data includes:

[0020] Reading stored data in a target storage area in the flash memory based on a plurality of candidate read voltages in the candidate read voltage set to obtain a plurality of first read data;

[0021] Detecting whether the number of error bits of the plurality of first read data is greater than the number of hard error correction bits;

[0022] If the number of error bits of the plurality of first read data is greater than the number of hard error correction bits, confirming that the error correction result is a hard error correction failure;

[0023] If, among the plurality of first read data, there exists at least one first read data whose error bit number is smaller than the hard error correction bit number, the error correction result is confirmed to be a hard error correction success.

[0024] The embodiment of the present application configures multiple voltages to read data in hard decoding mode, which can improve the success rate of hard error correction. Since the efficiency and complexity of hard error correction are lower than those of soft error correction, the efficiency of storage device error correction can be improved.

[0025] In some embodiments, the candidate read voltages in the set of candidate read voltages are configured with a read priority;

[0026] The step of reading the stored data of the target storage area in the flash memory based on the plurality of candidate read voltages in the candidate read voltage set to obtain a plurality of first read data includes:

[0027] selecting, according to the read priority, an unselected read voltage from the candidate read voltage set as a current read voltage;

[0028] Reading the stored data in the target storage area in the flash memory based on the current read voltage to obtain current first read data;

[0029] The detecting whether the number of error bits of the plurality of first read data is greater than the number of hard error correction bits includes:

[0030] If the number of error bits in the current first read data is greater than the number of hard-decode error correction bits, the process again enters the step of selecting an unselected read voltage from the candidate read voltage set as the current read voltage based on the read priority, until the number of error bits in the current first read data is less than the number of hard-decode error correction bits, or until the candidate read voltage set is traversed.

[0031] The embodiment of the present application performs reading based on the order of priority, which is beneficial to improving the efficiency of hard decoding and error correction.

[0032] In some embodiments, after obtaining the error correction result of performing hard error correction on the first read data, the method further includes:

[0033] If the error correction result of the hard error correction is that the hard error correction is successful, the storage address of the stored data is maintained unchanged.

[0034] If the number of error bits in the first read data is less than the number of hard decoding error correction bits, it means that the hard decoding capability is not exceeded and the reliability of the target storage area is relatively strong. Therefore, the embodiment of the present application maintains the storage address of the stored data unchanged in this scenario, which can further reduce the number of data moves.

[0035] An embodiment of the present application provides a data error correction device, which is applied to a storage device. The storage device includes at least one flash memory and a master controller. The flash memory and the master controller communicate via a bus. The master controller includes a hard decoding mode and a soft decoding mode. The data error correction device includes:

[0036] a hard decoding module, configured to obtain an error correction result of performing hard decoding error correction on first read data, wherein the first read data is data obtained by reading stored data in a target storage area in the flash memory in the hard decoding mode;

[0037] a reading module, configured to obtain second read data if the error correction result is a hard decoding error correction failure, where the second read data is data obtained by reading the stored data in the target storage area in the flash memory in the soft decoding mode;

[0038] The soft decoding module is used to perform soft decoding and error correction on the second read data if the number of error bits of the second read data is less than the pre-stored first soft decoding error correction bit, to obtain correct data and maintain the storage address of the stored data unchanged.

[0039] An embodiment of the present application provides a storage device, which includes a master control, a memory, and a flash memory. The master control is connected to the memory and the flash memory through a bus, respectively. The memory is used to store instructions, and the master control is used to call the instructions in the memory so that the storage device executes the above-mentioned data error correction method.

[0040] An embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor and a flash memory controller, the above-mentioned data error correction method is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 The figure is a schematic diagram of the structure of a storage device provided according to an embodiment of the present application.

[0042] Figure 2 The present invention provides a flowchart of the steps of a data error correction method according to an embodiment of the present application.

[0043] Figure 3 This is a flowchart of sub-steps of step 201 provided according to an embodiment of the present application.

[0044] Figure 4 A schematic diagram of a decoding method for storage data matching provided according to an embodiment of the present application.

[0045] Figure 5 Schematic diagram of the structure of a data error correction device provided according to one embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to more clearly understand the above-mentioned objectives, features and advantages of the present application, the present application is described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features therein can be combined with each other in the absence of conflict.

[0047] In the following description, many specific details are set forth to facilitate a full understanding of the present application. The described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0049] It should be further noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0050] In this application, "at least one" means one or more, and "more than one" means two or more than two. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The terms "first", "second", "third", "fourth", etc. (if any) in the specification, claims and drawings of this application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0051] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0052] In flash memory, the basic unit for storing data is called a cell. Each cell records different data by injecting and releasing electrons. The movement of electrons in and out of the cell causes wear and tear on the cell. As the degree of wear increases, the probability of electrons escaping from the cell increases, causing the data stored in the cell to jump and increasing the probability of read errors.

[0053] Therefore, flash memory needs to cooperate with the error correction algorithm in the main controller to perform data error detection and correction. During the error correction process, if too much erroneous data is found, it indicates that the data in the storage block is unreliable. The data in the storage block will be moved to reduce the probability of read errors when reading data.

[0054] However, frequent data movement can lead to decreased flash read performance and increased write amplification.

[0055] In view of the above, embodiments of the present application provide a data error correction method, apparatus, storage device, and computer-readable storage medium.

[0056] refer to Figure 1 As shown, Figure 1 This is a structural diagram of a storage device 10 provided in an embodiment of the present application. The storage device 10 includes a main control 20 and at least one flash memory particle 30.

[0057] The storage device 10 may be an embedded memory, such as a solid-state drive, but is not limited thereto.

[0058] The main control 20 can be connected to the flash memory particles 30 through an internal bus to perform read and write control on the flash memory particles 30 .

[0059] The main control 20 can also decode the read data. The decoding mode includes a hard decoding mode and a soft decoding mode.

[0060] The hard decoding mode (hard decode) and the soft decoding mode (soft decode) can be implemented using LDPC technology, but is not limited thereto.

[0061] Generally speaking, the hard decoding error correction capability of the hard decoding mode (e.g., the maximum number of error correction bits in the hard decoding mode) is smaller than the soft decoding error correction capability of the soft decoding mode (e.g., the maximum number of error correction bits in the soft decoding mode), while the decoding efficiency of the hard decoding mode is higher than that of the soft decoding mode. Therefore, the master control of the embodiment of the present application may preferentially use the hard decoding mode for decoding and error correction of the stored data in the flash memory. If the hard decoding error correction fails, the soft decoding mode may be used for soft error correction.

[0062] The host 20 can execute computer-readable program code (eg, software or firmware). Instructions can be executed by various components of the host 20, such as the processor 23, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, embedded microcontrollers, and other components of the host 20.

[0063] In some embodiments, the main control 20 includes a processor 23 and a memory 21, the memory 21 is used to store instructions, and the processor 23 is used to call the instructions in the memory 21, so that the storage device 10 executes the data error correction method provided in the embodiment of the present application.

[0064] Figure 2 This is a flowchart of the steps of an embodiment of the data error correction method of the present application. The data error correction method can be applied to the above-mentioned storage device 10. According to different requirements, the order of the steps in the flowchart can be changed, and some steps can be omitted.

[0065] See Figure 2 As shown, the data error correction method may include the following steps.

[0066] Step 201: Obtain an error correction result of performing hard error correction on first read data.

[0067] The first read data is data obtained by reading the stored data in the target storage area in the flash memory in the hard decoding mode.

[0068] In some embodiments, the master controller is configured with a default read voltage in a hard decoding mode. The default read voltage can be used to obtain the first read data, and hard decoding and error correction can be performed on the first read data. If the number of error bits in the first read data does not exceed the hard decoding error correction capability (for example, less than the number of hard decoding error correction bits), it indicates that the first read data can be successfully decoded in the hard decoding mode. If the number of error bits in the first read data exceeds the hard decoding error correction capability, it indicates that the first read data will fail to be decoded in the hard decoding mode.

[0069] The number of error bits in the first read data is the number of read error bits when the storage data in the target storage area is read in the hard decoding mode.

[0070] In other embodiments, the hard decoding mode is configured with a set of candidate read voltages.

[0071] Step 201 may include:

[0072] Reading stored data in a target storage area in the flash memory based on a plurality of candidate read voltages in the candidate read voltage set to obtain a plurality of first read data;

[0073] Detecting whether the number of error bits of the plurality of first read data is greater than the number of hard error correction bits;

[0074] If the number of error bits of the plurality of first read data is greater than the number of hard error correction bits, the error correction result is determined to be a hard error correction failure.

[0075] If, among the plurality of first read data, there exists at least one first read data whose error bit number is smaller than the hard error correction bit number, the error correction result is confirmed to be a hard error correction success.

[0076] The hard decoding mode of this embodiment is configured with multiple candidate read voltages. The multiple candidate read voltages can be set according to actual application requirements to obtain multiple first read data, thereby attempting hard decoding multiple times, which can improve the success rate of hard decoding. Since the decoding efficiency of hard decoding is higher than that of soft decoding, based on this, the overall decoding efficiency can be improved.

[0077] Furthermore, the candidate read voltages in the candidate read voltage set are configured with read priorities, see Figure 3 As shown, step 201 may include:

[0078] Step 2010 : Select an unselected read voltage from the candidate read voltage set as the current read voltage according to the read priority.

[0079] Specifically, a read voltage is selected from the candidate read voltage set in descending order of read priority as the current read voltage.

[0080] The candidate read voltage set may include: a default read voltage (default read), a special gear re-read voltage, and a re-read voltage table (read retry table, RRT), etc. The re-read voltage table includes multiple re-read voltages.

[0081] The default read voltage, special gear reread voltage, and reread voltage table can be prioritized from high to low. The special gear reread voltage can be configured to a read voltage with a higher hard decoding success rate. However, this is not limited to this.

[0082] Step 2011 : reading the stored data in the target storage area in the flash memory based on the current read voltage to obtain current first read data.

[0083] Step 2012: Detect whether the number of error bits of the current first read data is greater than the number of hard decoding error correction bits.

[0084] That is, whether hard error correction can be successfully performed based on the current first read data.

[0085] If the number of error bits of the current first read data is greater than the number of hard error correction bits, step 2013 is executed.

[0086] If the number of error bits of the current first read data is less than the number of hard error correction bits, it means that the master controller can successfully perform hard error correction on the current first read data, and step 2015 can be executed.

[0087] Step 2013 : Determine whether there is an unselected read voltage in the candidate read voltage set.

[0088] If there is an unselected read voltage in the candidate read voltage set, continue to step 2011 .

[0089] If there is no unselected read voltage in the candidate read voltage set, it means that the number of error bits of each first read data read based on the candidate read voltage set is greater than the number of hard error correction bits, and step 2014 can be executed.

[0090] Step 2014: confirm that the error correction result of the hard error correction is error correction failure.

[0091] When the error correction result of the hard error correction is an error correction failure, soft decoding may be attempted (entering the soft decoding mode), ie, step 202 is executed.

[0092] Step 2015: confirm that the error correction result of the hard error correction is successful.

[0093] In some embodiments, if the hard error correction result of the target first read data is successful, data movement may not be performed, wherein the target first read data is data obtained by reading data in the target storage space based on the target read voltage, and the target read voltage is a read voltage in the candidate read voltage set.

[0094] The target reading voltage can be configured according to actual application requirements, such as being configured as the special gear reading voltage mentioned above, which is not limited in the embodiments of the present application.

[0095] Furthermore, if the hard error correction result of the other first read data is successful, data migration can be performed. The other first read data is the first read data other than the target first read data among the plurality of first read data.

[0096] In this embodiment, a target read voltage is configured for each candidate read voltage in the hard decoding mode. If data read based on the target read voltage is successfully decoded in the hard decoding mode, data migration is not required.

[0097] In other embodiments, when the error correction result of the hard error correction is successful, it can be determined that the target storage area is reliable and data migration is not required, that is, the storage address of the stored data is maintained unchanged.

[0098] In this embodiment, when the hard decoding and error correction are successful, the data is not moved, thereby further reducing the number of data moves.

[0099] Step 202: If the error correction result is that the hard error correction fails, obtain second read data.

[0100] The second read data is data obtained by reading the stored data in the target storage area in the flash memory in the soft decoding mode.

[0101] In the soft decoding mode, it is necessary to continuously adjust the read voltage and perform a read retry on the target storage area to obtain the second read data.

[0102] The multiple read voltages in the soft decoding mode can be configured according to actual application requirements, and the embodiments of the present application are not limited to this.

[0103] Step 203 , detecting whether the number of error bits of the second read data is smaller than the first soft-decoding error correction bit number.

[0104] In some embodiments, the first soft-decoding error correction bit number is greater than the pre-stored hard-decoding error correction bit number, and the first soft-decoding error correction bit number is less than the pre-stored second soft-decoding error correction bit number.

[0105] The hard decoding error correction bit count is the maximum error correction bit count of the master controller in the hard decoding mode. This number reflects the master controller's hard decoding capability. If the read data exceeds the hard decoding error correction bit count, it indicates that the hard decoding error correction of the read data cannot produce correct data (i.e., the hard decoding error correction has failed).

[0106] The second soft decoding error correction bit number is the maximum error correction bit number of the master in the soft decoding mode.

[0107] For example, the master's hard decoding error correction bit count can reach 40 bits / 1KB. That is, for every 1KB of data read, the master's hard decoding mode can correct up to 40 bits of data. If the master's hard decoding mode uses a normalized minimum sum algorithm (MSA), the master's hard decoding error correction bit count can reach 55 bits / 1KB. The above hard decoding error correction bit count is only an example, and the embodiments of the present application are not limited thereto.

[0108] The second soft decoding error correction bit number can reach 110 to 130 bits / 1KB, that is, for every 1KB of data read, the master's soft decoding mode can correct up to 110 to 130 bits of data. The above second soft decoding error correction bit number is only an example, and the embodiments of the present application are not limited to this.

[0109] The specific value of the first soft error correction bit number can be set according to actual application requirements, for example, it can be set to 80 bits / 1KB, but is not limited thereto.

[0110] refer to Figure 4 As shown, when the number of error bits of the second read data is within the following range: the number of hard error correction bits < the number of error bits of the second read data < the second soft error correction bits, soft error correction can be successfully performed.

[0111] That is, when the number of error bits of the second read data is smaller than the second number of soft error correction bits, it can be confirmed that soft error correction can be successfully performed based on the second read data.

[0112] In some embodiments, if the number of error bits of the second read data is smaller than the number of the first soft error correction bits, it indicates that the target storage area has a certain reliability, and step 204 may be executed.

[0113] If the number of error bits of the second read data is greater than the number of the first soft error correction bits, step 205 may be executed.

[0114] Step 204 , performing soft error correction on the second read data to obtain correct data, and maintaining the storage address of the stored data unchanged.

[0115] In some embodiments, again referring to Figure 4As shown, step 204 may include: obtaining the number of erasures and writes of the target storage area; if the number of erasures and writes is less than a preset threshold value M, maintaining the storage address of the stored data unchanged (ie, the data is not moved).

[0116] The preset number threshold M can be configured according to actual application requirements. For example, the number threshold M can be determined according to the upper limit of the erase and write times of the flash memory. This embodiment of the present application does not limit this.

[0117] The number of erase and write times can reflect the reliability of the target storage area to a certain extent. The smaller the number of erase and write times of the target storage area, the stronger the reliability of the target storage area, the smaller the probability of jumps in cell storage data, and the lower the probability of read errors. Therefore, when the number of erase and write times is less than the preset threshold, data migration is not performed, which can further improve product reliability.

[0118] In some embodiments, if the number of erasures is greater than the number threshold M, and the number of error bits of the second read data is less than the second soft error correction bit, step 205 may be executed, ie, data in the storage area is relocated.

[0119] A large number of erase and write times indicates that the data stored in the target storage area is prone to jumps, and the probability of subsequent read errors will greatly increase. Therefore, data migration can further improve the reliability of the storage device.

[0120] If the number of error bits in the second read data is greater than the number of error correction bits in the first soft decoding, it means that although correct data can be obtained in the soft decoding mode, the reliability of the target storage area is poor. Therefore, step 205 can be executed.

[0121] Step 205 , performing soft decoding and error correction on the second read data to obtain correct data and relocate the stored data to the target storage area.

[0122] Relocating the stored data may refer to reading the stored data from the target storage area and writing the correct data into the new storage area, thereby effectively reducing the error rate that occurs when reading the data.

[0123] In some embodiments, again referring to Figure 4 As shown, if the number of error bits of the second read data exceeds the second soft decoding error correction bit number, it means that a correct result cannot be obtained in the soft decoding mode, and therefore the read data will be lost.

[0124] In the embodiment of the present application, after the main control enters the soft decoding mode, if the number of error bits in the second read data is less than the number of error correction bits in the first soft decoding, the storage area of the storage space is not relocated, thereby avoiding frequent data movement of the storage device. On the basis of ensuring data reliability, it can reduce the number of data movements, reduce write amplification, and improve the flash memory read performance.

[0125] Furthermore, some embodiments can further verify the reliability of the target storage space, that is, obtain the number of erase and write times of the target storage space. When the number of erase and write times of the target storage space is less than the preset number, and the number of error bits of the second read data is less than the number of error correction bits of the first soft decoding, the storage area of the storage space is not relocated, thereby further verifying the reliability of the storage area where data is not relocated, and further ensuring the reliability of the data.

[0126] Based on the same concept as the method in the above embodiment, the present application also provides a data error correction device, which can be used to perform the above data error correction method. For ease of explanation, the structural diagram of the data error correction device embodiment only shows the parts related to the embodiment of the present application. Those skilled in the art will understand that the illustrated structure does not constitute a limitation of the device, and it may include more or fewer components than shown, or combine certain components, or arrange the components differently.

[0127] like Figure 5 As shown, the data error correction device includes a hard decoding module 501, a reading module 502, and a soft decoding module 503. In some embodiments, the above modules may be programmable software instructions stored in a memory and callable and executed by a processor. It is understood that in other embodiments, the above modules may also be program instructions or firmware fixed in the processor.

[0128] a hard decoding module 501 configured to obtain an error correction result of performing hard decoding on first read data, where the first read data is data obtained by reading stored data in a target storage area in the flash memory in the soft decoding mode;

[0129] a reading module 502 configured to obtain second read data if the error correction result is a hard decoding error correction failure, where the second read data is data obtained by reading stored data in a target storage area in the flash memory in the soft decoding mode;

[0130] The soft decoding module 503 is configured to perform soft decoding and error correction on the second read data if the number of error bits of the second read data is less than the first soft decoding error correction bit, to obtain correct data and maintain the storage address of the stored data unchanged.

[0131] Figure 1 FIG. 1 is a schematic diagram of an embodiment of a storage device 10 of the present application.

[0132] The storage device 10 includes a host controller 20 and at least one flash memory chip 30 .

[0133] The main control 20 includes a memory 21, a processor 23, and a computer program 22 stored in the memory 21 and executable by the processor 23. When the processor 23 executes the computer program 22, the steps in the above-mentioned data error correction method embodiment are implemented, such as Figure 2 Steps 201 to 205 are shown.

[0134] For example, the computer program 22 can also be divided into one or more modules / units, which are stored in the memory 21 and executed by the processor 23. The one or more modules / units can be a series of computer program 22 instruction segments that can perform specific functions, and the instruction segments are used to describe the execution process of the computer program 22 in the storage device 10. For example, it can be divided into Figure 5 The hard decoding module 501, the reading module 502 and the soft decoding module 503 are shown.

[0135] Those skilled in the art will understand that the schematic diagram is merely an example of the storage device 10 and does not constitute a limitation on the storage device 10. The storage device 10 may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the storage device 10 may also include a bus, a cache chip, etc., but is not limited to this.

[0136] The processor 23 may be an application specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0137] The memory 21 can be used to store computer programs 22 and / or modules / units. The processor 23 implements various functions of the storage device 10 by running or executing the computer programs 22 and / or modules / units stored in the memory 21 and calling data stored in the memory 21. In addition, the memory 21 can include a high-speed random access memory and a non-volatile memory.

[0138] If the modules / units integrated in the storage device 10 are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program 22. The computer program 22 can be stored in a computer-readable storage medium. When the computer program 22 is executed by the processor 23, the steps of the above-mentioned method embodiments can be implemented. Among them, the computer program 22 includes computer program 22 code, and the computer program 22 code can be in source code form, object code form, executable file or some intermediate form.

[0139] The computer-readable medium may include any entity or device capable of carrying the code of the computer program 22, a recording medium, a USB flash drive, a mobile hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electric carrier signal, a telecommunications signal, and a software distribution medium. It should be noted that the content contained in the computer-readable medium may be appropriately increased or decreased based on the requirements of legislation and patent practice in a jurisdiction. For example, in some jurisdictions, based on legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunications signals.

[0140] In the several embodiments provided in this application, it should be understood that the disclosed storage device 10 and method can be implemented in other ways. For example, the above-described embodiment of the storage device 10 is merely illustrative. For example, the division of the units is merely a logical function division, and other division methods may be used in actual implementation.

[0141] In addition, the functional units in the various embodiments of the present application may be integrated into the same processing unit, or each unit may exist physically separately, or two or more units may be integrated into the same unit. The above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0142] It is obvious to those skilled in the art that the present application is not limited to the details of the above-mentioned exemplary embodiments, and that the present application can be implemented in other specific forms without departing from the spirit or basic characteristics of the present application. Therefore, no matter from which point of view, the embodiments should be regarded as exemplary and non-restrictive. In addition, it is obvious that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. The multiple units or storage devices 10 stated in the claims of the storage device 10 can also be implemented by the same unit or storage device 10 through software or hardware. Words such as first, second, etc. are used to indicate names and do not indicate any particular order.

[0143] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present application and are not limiting. Although the present application has been described in detail with reference to the above embodiments, ordinary technicians in this field should understand that the technical solution of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present application.

Claims

1. A data error correction method, characterized in that: Applied to a storage device, the storage device includes at least one flash memory and a master controller, the flash memory and the master controller communicate via a bus, the master controller includes a hard decoding mode and a soft decoding mode, and the data error correction method includes: Obtaining an error correction result of performing hard error correction on first read data, where the first read data is data obtained by reading stored data in a target storage area in the flash memory in the hard decoding mode; If the error correction result is a hard decoding error correction failure, obtaining second read data, where the second read data is data obtained by reading stored data in the target storage area in the flash memory in the soft decoding mode; If the number of error bits of the second read data is smaller than the pre-stored first soft error correction bit number, soft error correction is performed on the second read data to obtain correct data and maintain the storage address of the stored data unchanged.

2. The data error correction method according to claim 1, wherein: The first soft-decoding error correction bit number is greater than the pre-stored hard-decoding error correction bit number, and the first soft-decoding error correction bit number is less than the pre-stored second soft-decoding error correction bit number; the hard-decoding error correction bit number is the maximum error correction bit number of the master control in the hard decoding mode; the second soft-decoding error correction bit number is the maximum error correction bit number of the master control in the soft decoding mode.

3. The data error correction method according to claim 2, wherein: The data error correction method further includes: If the number of error bits of the second read data is greater than the first soft error correction bit number, and the number of error bits of the second read data is less than the second soft error correction bit number, performing soft error correction on the second read data to obtain correct data; and performing data migration on the stored data.

4. The data error correction method according to claim 1, wherein: Maintaining the storage address of the stored data unchanged includes: Obtaining the number of erase and write times of the target storage area; If the erasing and writing times are less than a preset times threshold, the storage address of the stored data is maintained unchanged.

5. The data error correction method according to claim 4, wherein: The data error correction method further includes: If the number of erasures and writes is greater than the threshold number, and the number of error bits of the second read data is less than the number of first soft error correction bits, the stored data is moved.

6. The data error correction method according to any one of claims 2 to 5, characterized in that: The hard decoding mode is configured with a candidate read voltage set; and obtaining an error correction result of performing hard error correction on the first read data includes: Reading stored data in a target storage area in the flash memory based on a plurality of candidate read voltages in the candidate read voltage set to obtain a plurality of first read data; Detecting whether the number of error bits of the plurality of first read data is greater than the number of hard error correction bits; If the number of error bits of the plurality of first read data is greater than the number of hard error correction bits, confirming that the error correction result is a hard error correction failure; If, among the plurality of first read data, there exists at least one first read data whose error bit number is smaller than the hard error correction bit number, the error correction result is confirmed to be a hard error correction success.

7. The data error correction method according to claim 6, wherein: The candidate read voltages in the candidate read voltage set are configured with a read priority; The step of reading the stored data of the target storage area in the flash memory based on the plurality of candidate read voltages in the candidate read voltage set to obtain a plurality of first read data includes: selecting, according to the read priority, an unselected read voltage from the candidate read voltage set as a current read voltage; Reading the stored data in the target storage area in the flash memory based on the current read voltage to obtain current first read data; The detecting whether the number of error bits of the plurality of first read data is greater than the number of hard error correction bits includes: If the number of error bits in the current first read data is greater than the number of hard-decode error correction bits, the process again enters the step of selecting an unselected read voltage from the candidate read voltage set as the current read voltage based on the read priority, until the number of error bits in the current first read data is less than the number of hard-decode error correction bits, or until the candidate read voltage set is traversed.

8. The data error correction method according to any one of claims 1 to 5, characterized in that: After obtaining the error correction result of performing hard error correction on the first read data, the method further includes: If the error correction result of the hard error correction is that the hard error correction is successful, the storage address of the stored data is maintained unchanged.

9. A data error correction device, characterized in that: Applied to a storage device, the storage device includes at least one flash memory and a master controller, the flash memory and the master controller communicate via a bus, the master controller includes a hard decoding mode and a soft decoding mode, and the data error correction device includes: a hard decoding module, configured to obtain an error correction result of performing hard decoding error correction on first read data, wherein the first read data is data obtained by reading stored data in a target storage area in the flash memory in the hard decoding mode; a reading module, configured to obtain second read data if the error correction result is a hard decoding error correction failure, where the second read data is data obtained by reading the stored data in the target storage area in the flash memory in the soft decoding mode; The soft decoding module is used to perform soft decoding and error correction on the second read data if the number of error bits of the second read data is less than the pre-stored first soft decoding error correction bit, to obtain correct data and maintain the storage address of the stored data unchanged.

10. A storage device, characterized in that: The storage device includes a master control, a memory and a flash memory, the master control is connected to the memory and the flash memory via a bus respectively, the memory is used to store instructions, and the master control is used to call the instructions in the memory so that the storage device executes the data error correction method according to any one of claims 1 to 8.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor and a flash memory controller, the data error correction method according to any one of claims 1 to 8 is implemented.

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