A method for automatic balancing of PCIe SSDs

Abstract

The application discloses a PCIe SSD automatic balancing method, comprising the following steps: S1, performing SSD testing and verification on n PCs, wherein n is a positive integer; and writing the test result into a storage chip, and storing a white list in the storage chip; S2, inserting the SSD into a PC interface, defining the PC as a working PC, reading the test result of the storage chip and the information of the working PC by an embedded controller EC, and notifying the SSD to perform corresponding processes by sending an EQ_Pin to the SSD; if the working PC is in the white list of the storage chip and passes the testing and verification, setting the EQ_Pin of the embedded controller EC to 1, and the SSD directly performs high-speed balancing after bypassing low-speed balancing; if the working PC is not in the white list of the storage chip or the SSD does not pass the testing and verification, setting the EQ_Pin of the embedded controller EC to 0, and the SSD needs to perform a complete low-speed to high-speed balancing process. The application does not affect the working of the SSD; saves the working time of the SSD recovery process, provides user experience; saves the power consumption of the SSD and further saves the power consumption of the system.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic data processing, and in particular to a method for automatic balancing of a PCIe SSD. Background Art

[0002] The existing link training process for SSDs (solid-state drives), especially in PCIe SSDs, is a critical step that ensures the high-speed serial link between the SSD and the host works optimally.

[0003] The PCIe link training process is mainly controlled by the link training state machine (LTSSM), which includes multiple states that play a key role in link establishment, configuration, and optimization.

[0004] For PCIe 3.0 and higher speeds, an equalization procedure is required. During this process, the ports at both ends of the PCIe link negotiate signal parameters with each other through TS (Training Sequence) messages to achieve the best link status.

[0005] Detailed process of Equalization Procedure: Equalization Procedure is a key part of link training in PCIe 3.0 and above versions. It is divided into four phases (Phase 0 to Phase 3), such as Figure 1 As shown:

[0006] Phase 0: When a downstream port prepares to switch from a lower rate to a higher rate, it sends a TS (Training Sequence) message with a starting preset to the upstream port. Upon receiving this message, the upstream port sets its own preset parameters accordingly and responds with a TS (Training Sequence) message. If the link is already at the highest rate, it proceeds directly to Phase 1.

[0007] Phase 1: The upstream and downstream ports exchange information such as FS and LF to determine the upper and lower limits of the Tx coefficient. Once a certain number of consecutive high-speed TS (training sequence) packets are detected (meaning the bit error rate has fallen below a certain threshold), the port enters Phase 1 and begins sending TS (training sequence) packets at a higher rate.

[0008] Phase 2: Optimize the signal quality of the downstream port. The upstream port requests the downstream port to set Tx parameters (such as boost, pre-shoot, and de-emphasis) to meet the upstream port's signal electrical quality requirements. Upon receiving the request, the downstream port makes the corresponding settings and sends a TS (training sequence) message. Upon receiving the message, the upstream port evaluates the signal quality. If the requirements are not met, it requests new Tx parameter settings. This cycle repeats until the requirements are met.

[0009] Phase 3: Optimize the signal quality of the upstream port using the same method as Phase 2.

[0010] PCIe SSDs perform automatic balancing according to PCIe regulations. Current firmware design faces the following balancing time issues:

[0011] 1. Each PCIe link training must be balanced from low speed to high speed, each time taking about 100ms;

[0012] 2. The SSD frequently enters and exits the PS4 during operation, requiring balancing from low speed to high speed (GEN1->GEN2->GEN3->GEN4) each time. The time required for the SSD to recover from power failure (or low power consumption) and return to working state accumulates as the SSD switches state, thus affecting the user experience.

[0013] 3. The SSD frequently enters and exits the PS4 during operation, which also has the following effects:

[0014] 1) Increased complexity of metadata management

[0015] Mapping table rebuild: The SSD uses the Flash Translation Layer (FTL) to manage the mapping between logical and physical addresses. During each power outage, the controller saves the mapping table and other metadata to flash memory; upon recovery, it must be reloaded. With increased access to and from the PS4, the mapping table may become fragmented or increase in size, leading to increased loading times.

[0016] Metadata Verification: After frequent switching in and out of the PS4, metadata integrity verification (such as ECC error correction) may take longer due to data aging or increased write frequency.

[0017] 2) Cumulative effect of cached data

[0018] DRAM cache write latency: Before entering low power mode, the SSD must write any unsaved data in the DRAM cache to the flash memory. Frequent state switching may cause cached data to be spread across more flash blocks, requiring reads from multiple locations during recovery, leading to cumulative latency.

[0019] Garbage collection pressure: Frequent power outages or frequent entry and exit of the PS4 may interrupt background garbage collection (Garbage Collection), resulting in more invalid data blocks to be merged during the next recovery, further extending the recovery time.

[0020] 3) Cumulative burden of firmware logic

[0021] Logging and Error Handling: Frequent access to and from the PS4 may generate logs or trigger error logs. As this occurs, the firmware needs to process more historical logs during restore, slowing down the initialization process.

[0022] Unfinished background tasks: If the firmware is not optimized for frequent switching in and out of the PS4 state, unfinished maintenance tasks (such as Trim and wear leveling) may accumulate and need to be batched during recovery.

[0023] 4) Cumulative Effect of User Perception

[0024] The cumulative impact of frequent PS4 state switching: Users may trigger state switching multiple times in a short period of time (such as frequent device wakeup / sleep), resulting in a short delay in each recovery, resulting in a noticeable lag experience.

[0025] Deterioration in sudden scenarios: When the SSD is close to full capacity or highly fragmented, the cumulative effect of recovery time may be amplified, further affecting response speed. Summary of the Invention

[0026] To solve the technical problems existing in the background technology, the present invention proposes a method for automatic balancing of PCIe SSDs.

[0027] The present invention proposes a method for automatic balancing of PCIe SSDs, comprising the following steps:

[0028] S1. Perform SSD testing and verification on n PCs, where n is a positive integer.

[0029] The test results are written to the storage chip, which also stores a whitelist. The firmware of the PCs on the whitelist sets the link target rate to high speed and skips the low-speed equalization negotiation step. The whitelist PCs and SSDs pass the test and verification.

[0030] It should be noted that if a whitelisted PC passes the SSD test and verification, it means that the PC has undergone SSD test and verification and passed. If the PC has not undergone SSD test and verification, or the PC has undergone SSD test and verification but failed, then the PC is not on the whitelist.

[0031] S2. Insert the SSD into the PC interface and define the PC as the working PC. The embedded controller EC reads the test results of the storage chip and the information of the working PC. The embedded controller EC compares whether the working PC is in the whitelist. The embedded controller EC sends an EQ_Pin to the SSD based on whether the working PC is in the whitelist, notifying the SSD to perform the corresponding process.

[0032] If the working PC is in the whitelist of the storage chip, the EQ_Pin of the embedded controller EC is set to 1, and the SSD skips the low-speed balancing and goes directly to the high-speed balancing. It should be noted that in some embodiments, the high-speed balancing is Gen4. Then the SSD enters the PCIe L0 (full-speed working) working state;

[0033] If the working PC is not in the whitelist of the storage chip, the EQ_Pin of the embedded controller EC is set to 0, and the SSD needs to complete the low-speed balancing to high-speed balancing process, that is, the SSD needs to start from low-speed balancing and then enter high-speed balancing.

[0034] It should be noted that the low-speed equalization is Gen1-GenN, N is an integer greater than 1, and the high-speed equalization is GenN+1. Optionally, if N is 3, the low-speed equalization is Gen1-Gen3, and the high-speed equalization is Gen4.

[0035] Specifically, a custom link training strategy is implemented in the SSD controller firmware. When the EQ_Pin of the embedded controller (EC) is 1, the SSD skips low-speed balancing and goes directly to high-speed balancing. Specifically, through NVMe commands or private register configuration, the PHY layer is forced to skip the low-speed balancing phase (which can be Gen1-Gen3) and directly enter the high-speed balancing phase (which can be Gen4) of the link training process.

[0036] Preferably, the SSD includes a redriver (signal amplifier) ​​or retimer (signal regenerator) chip to enhance the quality of the Gen4 signal and avoid equalization failure and fallback to low-speed mode due to channel loss.

[0037] Specifically, a redriver (signal amplifier) ​​or retimer (signal regenerator) chip is provided between the interface of the SSD and the main controller.

[0038] The default link training of the PCIe protocol starts at a low rate (such as Gen1) and gradually increases to the maximum supported rate. If you want to directly start Gen4 balancing (i.e., high-speed balancing), you need to force the target rate to be set in the following way: PC firmware configuration: Set the link target rate to high-speed balancing GenN+1 in the firmware of the PC (such as the CPU or chipset), and skip the negotiation steps of Gen1-GenN (low-speed balancing). For example, by modifying the Link Capability Register in the PCIe configuration space, set the "MaxLinkSpeed" field to high-speed balancing. In some embodiments, high-speed balancing is Gen4, so the "MaxLinkSpeed" field is set to Gen4 (16GT / s). Link retraining (Link Retrain): After initialization is completed, actively trigger link retraining (for example, by setting the LTSSM state machine to enter the Recovery state), and declare in the TS (training sequence) that only Gen4 rate is supported, forcing both parties to directly negotiate balancing at the Gen4 rate.

[0039] Specifically, the whitelist includes PC manufacturers, models, firmware versions, configurations, test times, and test results. Specifically, SSD testing and verification includes compliance testing, signal quality verification, and compatibility testing;

[0040] Compatibility testing includes signal integrity (SI) testing, power integrity testing (PI) testing, and system stability testing. System stability testing includes performance stability, LinkReset (link reset) testing, DC_cycle (battery-powered) power on / off testing, AC_cycle (mains-powered) power on / off testing, and Reboot_cycle (restart) testing.

[0041] Specifically, the memory chip is an EEPROM. The definitions of the EEPROM pins are as follows: A2, A1, and A0 constitute the EEPROM address pins, VSS is the ground pin, SCL and SDA are the I2C signal group, WP is the write protection pin, and VCC is the EEPROM power pin.

[0042] Specifically, the embedded controller EC reads the test and verification results of the storage chip through I2C. Specifically, the SSD reserves three pins, which are defined as I2C_SCL, I2C_SDA, and EQ_Pin. The EQ_Pin receives the information output by the embedded controller EC.

[0043] Preferably, when the SSD skips low-speed balancing and directly performs high-speed balancing, if high-speed balancing fails, it restarts high-speed balancing. If the SSD fails high-speed balancing M times in a row, the SSD needs to complete the low-speed balancing to high-speed balancing process, where M is an integer greater than 2.

[0044] The new PCIe SSD automatic balancing method proposed in the present invention does not affect the operation of the SSD; saves the working time of the SSD recovery process, improves user experience; saves SSD power consumption and thus saves system power consumption.

[0045] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 This is an existing equalization method for PCIe in the prior art;

[0047] Figure 2 A pin definition diagram reserved for the SSD of the present invention;

[0048] Figure 3 This is the EEPROM circuit design diagram of the present invention;

[0049] Figure 4 A schematic diagram of the newly added Redriver / Retimer hardware for the SSD of the present invention;

[0050] Figure 5 This is a logic diagram for improving the SSD firmware of the present invention. DETAILED DESCRIPTION

[0051] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar symbols throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0052] like Figure 2-Figure 5 A method for automatic balancing of a PCIe SSD is shown, comprising the following steps:

[0053] S1. Perform SSD testing and verification on n PCs, where n is a positive integer.

[0054] A storage chip is added to the SSD, and a whitelist is stored in the storage chip. The target link rate is set to high speed in the firmware of the PCs on the whitelist, and the low-speed equalization negotiation step is skipped. The whitelist PCs and SSDs have passed testing and verification.

[0055] like Figure 2 The SSD shown in the figure reserves three pins, which are defined as I2C_SCL, I2C_SDA and EQ_Pin.

[0056] The memory chip is EEPROM, and the definition of each pin of EEPROM is: A2, A1, A0 constitute the address pin of EEPROM, VSS is the ground pin, SCL, SDA are I2C signal groups, WP is the write protection pin, and VCC is the power supply pin of EEPROM. Figure 3 The figure shows the circuit design of EEPROM. The SCL and SDA of EEPROM are connected to the embedded controller EC, and the embedded controller EC is connected to the EQ_Pin pin of SSD.

[0057] The PC (specifically, the host CPU or chipset) firmware sets the link target to Gen4, skipping the Gen1-Gen3 negotiation steps. For example, by modifying the Link Capability Register in the PCIe configuration space and setting the "MaxLink Speed" field to Gen4 (16GT / s).

[0058] It should be noted that the SSD controller with a storage chip needs to implement a custom link training strategy. For example, through NVMe commands or private register configuration, it can force the PHY layer to skip the low-speed equalization phase and directly enter the Gen4 training process. The SSD's PCIe PHY must support Gen4's dynamic equalization features, such as stronger CTLE (continuous time linear equalization) and 2-tap DFE (decision feedback equalization) to handle high-frequency signal attenuation and inter-symbol interference (ISI).

[0059] S2. Connect the SSD to the PC interface and define the PC as the working PC. The embedded controller EC reads the test results of the storage chip and the information of the working PC. The EC connects to the platform controller hub (PCH) through the LPC (Low Pin Count) or eSPI (Enhanced Serial Peripheral Interface) bus, accesses the BIOS configuration data (such as the ACPI table), and obtains the PC configuration information. The embedded controller EC compares whether the working PC is in the whitelist. The embedded controller EC sends the EQ_Pin to the SSD to notify the SSD to perform the corresponding process based on whether the working PC is in the whitelist. The EEPROM circuit design diagram is shown in the figure. Figure 3 As shown;

[0060] If the working PC is on the storage chip's whitelist, the PC passes the SSD test and verification, and the PC's firmware sets the link target rate to high speed and skips the low-speed equalization negotiation step, indicating that the hardware link between the SSD and the PC has reached the optimal state. The EQ_Pin of the embedded controller EC is set to 1, and the SSD skips Gen1-Gen3 equalization and goes directly to Gen4 equalization. The SSD then enters the PCIe L0 (full-speed) working state.

[0061] If the working PC is not in the storage chip's whitelist, it means that the PC and SSD have failed testing and verification, or the link target rate is not set to high speed in the PC firmware, and the low-speed equalization negotiation step is not skipped. In this case, the EQ_Pin of the embedded controller EC is set to 0, and the SSD needs to complete the low-speed equalization to high-speed equalization process. That is, the SSD needs to perform PCIe Gen1-Gen3 equalization, and then Gen4 equalization.

[0062] When the SSD skips Gen1-Gen3 and directly performs Gen4 balancing, if Gen4 balancing fails and then restarts, and if the SSD fails Gen4 balancing three times in a row, the SSD needs to complete the low-speed balancing to high-speed balancing process, that is, the SSD needs to perform Gen1-Gen3 balancing and then Gen4 balancing training.

[0063] Specifically, the embedded controller EC reads the test and verification results of the storage chip through I2C.

[0064] The testing and verification in step S1 include compliance testing, signal quality verification and compatibility testing. The compatibility testing includes signal integrity (SI) testing, power integrity testing (PI) testing and system stability testing. The system stability testing includes performance stability, LinkReset (link reset) testing, DC_cycle (battery-powered) power on / off testing, AC_cycle (power-powered) power on / off testing and Reboot_cycle (restart) testing.

[0065] The EEPROM also contains detailed configuration information of the PC, including manufacturer, model, firmware version, configuration, and test time.

[0066] By improving the SSD firmware design, the high and low states of EQ_Pin are used to execute the corresponding equalization process:

[0067] The embedded controller (EC) reads the test and verification results from the SSD EEPROM via I2C and sends EQ_Pin to the SSD to notify it to perform the corresponding balancing process. If the working PC is on the whitelist and the SSD test and verification pass (PASS), the EC sets EQ_Pin to 1 (high). At this time, Gen1-Gen3 balancing can be skipped and Gen4 balancing can be directly performed. The SSD then enters PCIe L0 (full speed operation) working state.

[0068] If the working PC is not in the whitelist, the EC sets EQ_Pin to 0 (low). At this time, the SSD needs to perform a complete low-speed equalization to high-speed equalization process (Gen1->Gen2->Gen3->Gen4).

[0069] To prevent the insertion loss of the physical channel (such as PCB traces or connectors) from exceeding the Gen4 specification (usually required to be ≤28dB@8GHz), even forced Gen4 equalization may fail. A redriver / retimer needs to be added to the SSD motherboard, such as Figure 4 As shown, the reliability of the channel is enhanced.

[0070] During PCIe link training, equalization between the SSD and the host (PC) requires gradually negotiating speeds (e.g., from Gen1 to Gen4) based on channel conditions and protocol requirements. To skip the Gen1-Gen3 equalization phase and directly initiate equalization training at the Gen4 equalization rate, optimizations are required across multiple aspects, including the protocol layer, equalization presets, signal integrity, dynamic equalization, hardware and firmware co-design, and testing and verification.

[0071] 1) Target rate mandatory setting at the protocol layer:

[0072] By default, PCIe protocol link training starts at a low rate (such as Gen1) and gradually increases to the maximum supported rate. To directly start Gen4 balancing, you need to force the target rate to be set using the following method:

[0073] PC firmware configuration: Set the link target rate to Gen4 in the firmware on the host (PC) side (such as the CPU or chipset), skipping the Gen1-Gen3 negotiation steps. For example, by modifying the Link Capability Register in the PCIe configuration space, set the "Max Link Speed" field to Gen4 (16GT / s).

[0074] Link Retrain: After initialization is completed, link retraining is actively triggered (for example, by setting the LTSSM state machine to enter the Recovery state) and declaring in the TS (training sequence) that only the Gen4 rate is supported, forcing both parties to directly perform balancing negotiation at the Gen4 rate.

[0075] 2) Equalization preset optimization and signal integrity:

[0076] The Gen4 rate (16GT / s) places extremely high demands on signal integrity. Hardware design and equalization preset optimization are required to ensure that channel conditions meet Gen4 transmission requirements:

[0077] Both host and device firmware support Gen4 preset equalization parameters: During the Gen4 equalization phase, equalizers (such as FFE, CTLE, and DFE) on both the host transmitter (Tx) and the device receiver (Rx) must use high-gain presets (such as Preset 7) to compensate for high-frequency losses. For example, the Gen4 specification allows for stronger preshoot and de-emphasis parameters to ensure that the signal eye diagram remains open at high data rates.

[0078] Redriver / Retimer chip support: In long-distance or complex channels, a redriver (signal amplifier) ​​or retimer (signal regenerator) chip can be introduced to directly enhance Gen4 signal quality and avoid equalization failure and fallback to low-speed mode due to channel loss.

[0079] 3) Adjustment of dynamic equalization (LEQ) process:

[0080] PCIe Gen4 Link Equalization (LEQ) consists of multiple phases (Phase 0-3). The process needs to be optimized to skip the low-speed phase:

[0081] Directly enter Gen4 negotiation from the initial state: In the Recovery.Equalization substate of the LTSSM state machine, both parties are forced to start the TS (training sequence) exchange in Phase 0 at the Gen4 rate, rather than gradually upgrading from a lower rate. This requires that both the host and device firmware support the preset equalization parameters for Gen4 and declare in the TS (training sequence) that only Gen4 rates are supported.

[0082] Shorten the timeout threshold: The Gen4 balancing negotiation process must complete within approximately 32ms. By adjusting the timeout counter, we can avoid triggering a fallback to low-speed mode due to poor link conditions and instead attempt Gen4 balancing as many times as possible. Only if the SSD fails Gen4 balancing three times in a row will it complete the low-speed to high-speed balancing process, meaning it must train from Gen1 to Gen3 balancing and then to Gen4 balancing.

[0083] 4) Co-design of hardware and firmware:

[0084] PHY layer support: The SSD's PCIe PHY must support Gen4's dynamic equalization features, such as enhanced CTLE (continuous time linear equalization) and 2-tap DFE (decision feedback equalization) to handle high-frequency signal attenuation and intersymbol interference (ISI).

[0085] Firmware control logic: Implement a custom link training strategy in the SSD controller firmware. For example, through NVMe commands or private register configuration, force the PHY layer to skip the low-speed equalization phase and directly enter the Gen4 link training process.

[0086] 5) Testing and verification:

[0087] Use a PCIe protocol analyzer (such as VIAVI or Tektronix) to capture the link negotiation process to verify that the Gen1-Gen3 phases have been successfully skipped. Ensure that the rate declaration and equalization parameters in the TS (training sequence) comply with the Gen4 specification. Use an oscilloscope to measure the eye height, jitter, and bit error rate (BER) of the Gen4 signal to ensure that the Gen4 link remains stable even without lower-speed negotiation.

[0088] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. A method for automatic balancing of PCIe SSD, characterized in that: The steps include: S1. Perform SSD testing and verification on n PCs, where n is a positive integer. The test results are written to the storage chip, which also stores a whitelist. The firmware of the PCs on the whitelist sets the link target rate to high speed and skips the low-speed equalization negotiation step. The whitelist PCs and SSDs pass the test and verification. S2. Insert the SSD into the PC interface and define the PC as the working PC. The embedded controller EC reads the test results of the storage chip and the information of the working PC. The embedded controller EC compares whether the working PC is in the whitelist. The embedded controller EC sends an EQ_Pin to the SSD based on whether the working PC is in the whitelist, notifying the SSD to perform the corresponding process. If the working PC is in the whitelist of the storage chip, the EQ_Pin of the embedded controller EC is set to 1, and the SSD skips the low-speed balancing and goes directly to the high-speed balancing; If the working PC is not in the whitelist of the storage chip, the EQ_Pin of the embedded controller EC is set to 0, and the SSD needs to perform a complete low-speed equalization to high-speed equalization process; A custom link training strategy is implemented in the SSD controller firmware. When the EQ_Pin of the embedded controller (EC) is 1, the SSD skips low-speed balancing and goes directly to high-speed balancing. The customized link training strategy is configured through NVMe commands or private registers, forcing the PHY layer to skip the low-speed equalization phase and directly enter the high-speed equalization phase; When the SSD fails to perform high-speed balancing directly, restart high-speed balancing; If the SSD fails high-speed balancing M times in a row, the SSD enters the complete low-speed balancing to high-speed balancing process, where M is an integer greater than 2.

2. The PCIe SSD automatic balancing method according to claim 1, wherein: SSDs include a signal amplifier redriver or signal retimer chip to enhance high-speed equalized signal quality.

3. The method for automatic balancing of PCIe SSD according to claim 2, wherein: The signal amplifier Redriver or signal regenerator Retimer chip is set between the SSD interface and the main controller.

4. The PCIe SSD automatic balancing method according to claim 1, wherein: The negotiation steps in the PC firmware to skip low-speed equalization are: modify the Link Capability Register in the PCIe configuration space and set the "Max LinkSpeed" field to high-speed equalization.

5. The PCIe SSD automatic balancing method according to claim 1, wherein: SSD testing and verification include compliance testing, signal quality verification, and compatibility testing.

6. The PCIe SSD automatic balancing method according to claim 1, wherein: The memory chip is EEPROM.

7. The PCIe SSD automatic balancing method according to claim 1, wherein: The whitelist includes PC manufacturer, model, configuration, firmware version, test time and test results.

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