Ethercat master station distributed clock synchronization method based on arm and FPGA

Abstract

The application discloses an EtherCAT master station distributed clock synchronization method based on ARM and FPGA, and relates to the technical field of industrial control, and comprises the following steps: S1, an FPGA chip integrating ARM and programmable logic resources is used to construct an EtherCAT master station distributed clock module, and ARM and the programmable logic resources interact through an internal AXI interconnection bus; S2, the programmable logic resources acquire an enabling signal sent by the ARM end, if the enabling signal is 1, the master station performs the operations of topology scanning, delay calculation, clock compensation and dynamic drift compensation on the slave station, and obtains a delay compensation value of the slave station and a local clock compensation value; S3, after the compensation is completed, the state machine of the master station automatically jumps to a synchronization signal generation module, and the SYNC parameter is acquired from the ARM end, so that the starting time of the SYNC signal of the slave station is calculated; S4, after the delay compensation value, the local clock compensation value and the starting time of the slave station are converted into message information, the message information is sent to the slave station, the address of the slave station is added by 1, and the step S1 is returned until the distributed clock configuration of all the slave stations is completed; the EtherCAT master station distributed clock synchronization method solves the problem that the synchronization (SYNC) signal generated after the start of the distributed clock algorithm is unstable, and has potential and value in the field of higher-frequency slave station synchronization.

Description

A Distributed Clock Synchronization Method for EtherCAT Master Stations Based on ARM and FPGA Technical Field

[0001] This invention relates to the field of industrial control technology, and in particular to an EtherCAT master station distributed clock synchronization method based on ARM and FPGA. Background Technology

[0002] Ethernet for Control Automation Technology (EtherCAT) is an industrial communication protocol developed by Beckhoff GmbH in Germany in 2003, primarily addressing the real-time performance limitations of traditional Ethernet in industrial control. Traditional industrial scenarios have extremely high requirements for device synchronization, response speed, and data transmission efficiency, which early Ethernet technologies, due to limitations such as communication latency and jitter, could not meet. EtherCAT, through its innovative master-slave architecture, allows data frames to be directly read or written by multiple slave devices during transmission, eliminating the need for cascading forwarding and significantly shortening the communication cycle. This technology supports standard Ethernet hardware, achieving communication rates up to 100Mbps, with synchronization accuracy controlled at the microsecond level, while also being compatible with low-cost devices, lowering the barrier to industrial network upgrades.

[0003] EtherCAT's Distributed Clocks (DC) technology is the core mechanism for high-precision device synchronization. In industrial automation scenarios, multi-device collaboration (such as motion control and multi-robotic arm linkage) requires microsecond or even nanosecond-level time synchronization, a requirement that traditional buses struggle to meet. The EtherCAT protocol defines a global clock reference, uniformly designating a reference clock and reference slave, enabling other slaves to eliminate hardware clock deviations based on this clock. It calculates delay compensation and line compensation by recording arrival and departure times through data frame transmission, and then dynamically compensates for clock drift via messages. Finally, by periodically sending a synchronization signal (SYNC), it uniformly triggers motion control across all slaves. This technology achieves high-precision synchronization of all network devices (typical accuracy up to ±100 nanoseconds) without additional hardware, and the synchronization process does not significantly consume communication bandwidth. Its advantage lies in simplifying the timing control of complex systems, such as the precise coordination of sensors and actuators in multi-axis collaborative motion or high-speed production lines, becoming a key technological foundation for EtherCAT's support of real-time industrial applications.

[0004] Patent CN117411579A mentions the general operation process of clock synchronization in the EtherCAT master station, but its description is basically the implementation process in the IGH open source code, and does not describe the detailed operation of the subsequent synchronization signal (SYNC). Patent CN114666185A mentions the specific calculation method and improvement of the synchronization signal (SYNC), but its approach does not take into account the relationship between the cycle time of the distributed clock and the frame time of the message, which may lead to a synchronization error problem where the synchronization signal (SYNC) appears before the interrupt signal.

[0005] Currently, existing EtherCAT master distributed clock algorithms suffer from the following problems: Traditional EtherCAT masters typically use open-source master IGH or SOEM software systems, which are deployed on personal computers or embedded chips. This software implementation causes jitter in the messages sent by the master, affecting the synchronization accuracy of the slave stations and consequently their correct operation. The official TwinCAT software is limited by its support for only specific network card models. Furthermore, existing methods of implementing EtherCAT masters using FPGAs suffer from the drawbacks of the FPGA's unique modification and compilation process, resulting in stringent conditions for modifying distributed clock parameters and low modification efficiency. Summary of the Invention

[0006] Based on the technical problems existing in the background technology, this invention proposes an EtherCAT master station distributed clock synchronization method based on ARM and FPGA, which solves the problem of unstable synchronization (SYNC) signal generated after the distributed clock algorithm is started, and shows potential and value in the field of higher frequency slave station synchronization.

[0007] This invention proposes an EtherCAT master station distributed clock synchronization method based on ARM and FPGA, comprising:

[0008] S1. Use an FPGA chip with integrated ARM and programmable logic resources to build an EtherCAT master station distributed clock module. The ARM and programmable logic resources interact through an internal AXI interconnect bus.

[0009] S2. The programmable logic resource obtains the enable signal sent by the ARM terminal. If the enable signal is 1, the master station performs topology scanning, delay calculation, clock compensation and dynamic drift compensation on the slave station to obtain the delay compensation value and local clock compensation value of the slave station.

[0010] S3. After the compensation is completed, the master station's state machine automatically jumps to the synchronization signal generation module and obtains the SYNC parameters from the ARM terminal to calculate the start time of the slave station's SYNC signal.

[0011] S4. Convert the delay compensation value, local clock compensation value and start time of the slave station into message information and send them to the slave station. Increment the slave station address by 1 and return to step S1 until the distributed clock configuration of all slave stations is completed.

[0012] Furthermore, the topology scan of the slave station specifically involves:

[0013] The master station obtains the distributed clock support information in register 0x0000 and the switch information of each port of the slave station in register 0x0110 through messages;

[0014] If the master station does not specify a reference slave station, the master station will use the first slave station that supports distributed clocks among the slave stations as the reference slave station based on the distributed clock support information.

[0015] Topology scan: The master station constructs the topology of the slave station based on the switch information of each port of the slave station.

[0016] Furthermore, in the delay calculation for the slave station, the specific steps are as follows:

[0017] Delay calculation: Obtain time information for different ports of each slave station by broadcasting and writing to and reading from the slave station's 0x0900 register, and send these two messages. N This process yields the delay compensation value, where N is an integer.

[0018] Clock compensation: The master station first reads the slave station's 0x0920 register. The master station then reads the slave station's 0x0910 register to obtain the current local clock of the slave station. The master station calculates the difference between the current local clock of the slave station and the master station's clock. If the difference is greater than a pre-set threshold in the master station, the 0x0920 register value is added to the difference to obtain local clock compensation. Otherwise, the 0x0920 register value is used directly as the local clock compensation value.

[0019] Increment the current slave address by 1, and repeat the above delay calculation and clock compensation steps until all slaves have completed clock compensation. The master station writes the delay compensation value and clock compensation value of each slave to the slave through the message to the 0x0920 and 0x0928 registers respectively.

[0020] Furthermore, the dynamic drift compensation specifically includes:

[0021] The master station uses a broadcast write command to inform all slave stations of the master station clock, and the message to broadcast write the master station clock is continuously sent after the distributed clock synchronization function is enabled, continuously compensating the slave stations for drift.

[0022] Furthermore, after compensation is completed, the master station's state machine automatically jumps to the synchronization signal generation module and obtains the SYNC parameters from the ARM terminal to calculate the start time of the slave station's SYNC signal, specifically:

[0023] The master station obtains the SYNC parameter from the ARM terminal and stores it in a register.

[0024] The master station writes the cycle time (cycle_time) to each slave station via a message to the 0x09A0 register.

[0025] The master station reads the 0x092C register through the message to check the difference between the master station clock and the local clock;

[0026] If the difference is less than the preset threshold in the master station, the current slave station synchronization is successful;

[0027] If not, since the dynamic drift compensation message is sent with each frame, continue to check the difference between the master station clock and the local clock until the difference is less than the threshold, thus completing the current slave station convergence and achieving successful synchronization.

[0028] Furthermore, the SYNC parameters include the cycle time of the SYNC signal, shift time, the interval between the SYNC signal and the message arrival time, and the message time frame time set by the master station.

[0029] Furthermore, after the current slave station converges, the master station calculates the start time of the SYNC signal for the current slave station as follows:

[0030] The original randomly set offset value OFFSET in the main site has been changed to 2. M *frame_time associates the delay with the message period, where M is a positive integer greater than or equal to 0, 2 M In FPGA chips, shifters are used instead of multipliers, where * represents a multiplication operation;

[0031] The new_remainder is the remainder when calculating frame_time, ensuring that the SYNC signal is always aligned with the relative offset of the IRQ, where the IRQ is the SYNC signal relative to the message arrival interrupt signal.

[0032] Furthermore, the formula for calculating the start time of the SYNC signal of the current slave station is as follows:

[0033] start_time = (app_time + 2) M*frame_time)–new_remainder+shift_time;

[0034] new_remainder=diff%frame_time;

[0035] diff = (app_time + 2) M *frame_time)–base_time;

[0036] Where app_time is the current master station time, base_time is the distributed clock synchronization enable time, and the base_time of all slave stations is the same. diff represents the current time shifted forward by 2 seconds. M The time difference between *frame_time and the Bloom clock synchronization enable time, % indicates the modulo operation.

[0037] Furthermore, after the start_time calculation is completed, the master station writes the start_time value to the current slave station by writing a message to the 0x0990 register, and then writes the first 2 bits of the 0x0981 register to 1 to enable the SYNC signal, thus completing the SYNC signal process of the current slave station. When all slave stations have completed the SYNC signal configuration process, the entire synchronous clock process operation is completed.

[0038] Furthermore, a Linux system is deployed on the ARM side, and the relevant programs for the EtherCAT master station are implemented on the Linux system.

[0039] The advantages of the distributed clock synchronization method for EtherCAT master stations based on ARM and FPGA provided by this invention are as follows: The distributed clock algorithm in the EtherCAT master station is implemented using a heterogeneous approach of ARM and FPGA. The cycle time, shift time, and frame time of the distributed clock can be modified at any time on the ARM side, and these parameters are internally exchanged with the PL side of the FPGA chip via the AXI bus. This avoids the need to recompile the FPGA chip every time parameters are modified, improving debugging and usage efficiency. Simultaneously, because the FPGA chip uses parallel logic internally, the implementation is more low-level, and the message transmission jitter is almost negligible, providing a stable message foundation for the synchronization of all slave stations. Furthermore, the distributed clock algorithm is improved to solve the problem of unstable synchronization (SYNC) signals generated after the distributed clock algorithm starts, demonstrating potential and value in the field of higher-frequency slave station synchronization. Attached Figure Description

[0040] Figure 1 is a schematic diagram of the structure of the present invention;

[0041] Figure 2 is a flowchart of the distributed clock compensation, delay and dynamic drift compensation module;

[0042] Figure 3 is a flowchart of the synchronization signal generation module;

[0043] Figure 4 is a schematic diagram of the calculation of the SYNC signal start time in the traditional scheme;

[0044] Figure 5 is a schematic diagram of the calculation of the SYNC signal start time in this embodiment;

[0045] Figure 6 is a schematic diagram of the triggering of the IRQ signal and the SYNC signal;

[0046] Figure 7 is a schematic diagram of the difference in the SYNC signal from the slave station. Detailed Implementation

[0047] The technical solution of the present invention will now be described in detail through specific embodiments. Many specific details are set forth in the following description to provide a thorough understanding of the invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0048] As shown in Figures 1 to 7, the EtherCAT master station distributed clock synchronization method proposed in this invention based on ARM and FPGA includes:

[0049] S1. Use an FPGA chip with integrated ARM and programmable logic resources to build an EtherCAT master station distributed clock module. The ARM and programmable logic resources interact through an internal AXI interconnect bus.

[0050] S2. The programmable logic resource obtains the enable signal sent by the ARM terminal. If the enable signal is 1, the master station performs topology scanning, delay calculation, clock compensation and dynamic drift compensation on the slave station to obtain the delay compensation value and local clock compensation value of the slave station.

[0051] S3. After the compensation is completed, the master station's state machine automatically jumps to the synchronization signal generation module and obtains the SYNC parameters from the ARM terminal to calculate the start time of the slave station's SYNC signal.

[0052] S4. Convert the delay compensation value, local clock compensation value and start time of the slave station into message information and send them to the slave station. Increment the slave station address by 1 and return to step S1 until the distributed clock configuration of all slave stations is completed.

[0053] Specifically, the delay compensation value and local clock compensation value obtained in step S2 are concatenated and sent to the message transceiver module in the form of a message. The SYNC signal start time value obtained in step S3 is concatenated and sent to the message transceiver module in the form of a message. Finally, the message transceiver module interacts with the slave system in the form of Ethernet messages.

[0054] This embodiment uses an FPGA chip to implement topology, compensation, and delay calculations, which improves algorithm efficiency. At the same time, it builds message splicing and sending / receiving logic to ensure the stability of messages and interrupt signals and avoid synchronization errors caused by interrupt signal jitter when the period is short.

[0055] The system that implements the above EtherCAT master station distributed clock synchronization method is roughly divided into ARM, programmable logic resources (PL) and Ethernet interface. The programmable logic resources include distributed clock compensation, delay and dynamic drift compensation modules, synchronization signal generation module and message transmission and reception module.

[0056] The main function of the message transceiver module is to interact with the distributed clock compensation, delay and dynamic drift compensation modules and synchronization signal generation module respectively, and then interact with the slave system in the form of Ethernet messages.

[0057] 1. A Linux system is deployed on the ARM side, and the relevant programs for the EtherCAT master station are implemented on this system. The enable signal and SYNC parameters can be sent to the PL side via the AXI bus. This embodiment uses a Xilinx ZYNQ heterogeneous chip combining an ARM and an FPGA. Because the Linux software is easy to modify and compile, it saves the compilation time required for each parameter modification on the PL side, improving debugging and usage efficiency. The SYNC parameters include the SYNC signal cycle time (cycle_time), the interval between the SYNC signal and the message arrival time (shift_time), and the message time (frame_time) set by the master station.

[0058] 2. The distributed clock compensation, delay, and dynamic drift compensation module is shown in Figure 2. The master station first obtains the distributed clock (DC) support information and port switch information of the slave station from registers 0x0000 and 0x0110 via messages. The master station checks if a reference slave has been specified. If specified, it directly enters the topology and delay calculation state machine. If not specified, it uses the information in register 0x0000 as the first slave among all slaves that supports distributed clock as the reference slave.

[0059] Topology scan: The master station obtains the on / off status of each slave port based on the information in register 0x0110, and uses this to obtain the topology of the entire slave system.

[0060] Delay calculation: Obtain the time information of different ports of each slave station by broadcasting and writing to and reading from the slave station's 0x0900 register, and send these two messages. N Next, the delay compensation value is obtained, where N is an integer. The purpose of this value is to facilitate the use of shift operations instead of division when calculating the average value on the FPGA side, thus saving resources and calculation time.

[0061] Clock compensation: After the delay calculation is completed, the master station first reads the slave station's 0x0920 register to obtain the register value, and then reads the slave station's 0x0910 register to obtain the slave station's current local clock. The master station calculates the difference between the current slave station's local clock and the master station's clock. If the difference is greater than a pre-set threshold in the master station, the 0x0920 register value is added to the difference to obtain local clock compensation; otherwise, the 0x0920 register value is used directly as the local clock compensation.

[0062] After calculating the clock compensation and delay of the current slave station, if there are still slave stations that have not completed, the slave station address is incremented by one, and the above delay calculation and clock compensation steps are repeated. If all slave stations have completed, the master station writes the clock compensation and delay compensation values ​​of each slave station to the 0x0920 and 0x0928 registers through a message.

[0063] Dynamic Drift Compensation: Since each slave station has a different clock crystal, clock drift may occur after long-term operation. The traditional synchronization method is to write the master station clock to the reference slave station, and then use read / write commands to read the reference slave station clock and write it to the subsequent slave stations. However, the method in this embodiment is to directly use a broadcast write command to inform all slave stations of the master station clock, enabling them to perform internal drift compensation. This saves the time of the original process from the master station to the reference slave station, and then from the reference slave station to other slave stations. The jitter of the SYNC signal of each slave station will also be smaller. Moreover, the message to broadcast the master station clock will be continuously sent after the DC synchronization function is enabled, continuously compensating the slave stations for drift.

[0064] This embodiment uses a single Broadcast Write (BWR) instruction to replace two separate Specified Write (FPWR) and Specified Read Write (FRMW) instructions, thereby improving the efficiency of dynamic drift compensation and reducing the trigger point difference between each slave synchronization signal.

[0065] 3. The synchronization signal generation module flow is shown in Figure 3. First, the master station obtains the SYNC parameters from the ARM terminal and stores them in a register for subsequent calculations. The SYNC parameters include cycle_time, shift_time, and frame_time. The master station writes the cycle_time of the distributed clock (DC) SYNC signal to each slave station via a message to the 0x09A0 register. The master station reads the 0x092C register via a message to check the difference between the master station clock and the local clock. If the difference is less than a preset threshold in the master station, the slave station is considered to have successfully synchronized. Otherwise, it continues to check the difference between the master station clock and the local clock. Since the dynamic drift compensation message is continuously sent with each frame, the difference will continue to decrease until it is less than the threshold. This completes the convergence of the current slave station.

[0066] After the slave station converges, the master station begins calculating the SYNC signal start time for that slave station. Figure 4 shows the traditional method for calculating the SYNC signal start time. The calculation method for the SYNC start time (start_time) is as follows:

[0067] start_time=(app_time+OFFSET)+cycle_time-remainder+shift_time;

[0068] remainder=diff%cycle_time;

[0069] diff=(app_time+OFFSET)–base_time;

[0070] In the formula, OFFSET is the offset value randomly set in the master station (100ms in the traditional scheme), app_time is the current master station time, base_time is the DC synchronization enable time (all slave stations have the same base_time), cycle_time is the cycle time of the SYNC signal, shift_time is the interval between the SYNC signal and the message arrival time (i.e., the SYNC signal offset parameter sent by the ARM), remainder is the remainder (% indicates modulo operation), and diff indicates shifting the current time by 2. M The time difference between *frame_time and the time when the Bloom clock synchronization is enabled.

[0071] As shown in Figure 4, the value of start_time is closely related to cycle_time. Normally, the value of cycle_time is equal to the message time frame_time set by the master station and will not affect the value of start_time. However, when cycle_time is not equal to frame_time, it may cause the set shift_time to be different from the offset of the SYNC signal relative to the interrupt signal (IRQ). The IRQ signal is a signal that will be triggered when the message arrives at the slave station. When the SYNC signal is generated before the IRQ signal, a slave station synchronization error will occur.

[0072] Therefore, this embodiment makes the following improvement to address the aforementioned slave station synchronization error problem: the offset value OFFSET, which was originally randomly set in the master station, is modified to 2. M *frame_time associates the delay with the message period, where M is a positive integer greater than or equal to 0, 2 M In FPGA chips, shifting is used instead of multipliers, which saves resources and computation time. * indicates multiplication operation; new_remainder is the remainder of frame_time, which makes the SYNC signal always consistent with the relative offset of the IRQ signal, where IRQ is the interrupt signal for the arrival of the SYNC signal relative to the message.

[0073] As shown in Figure 5, this embodiment simplifies the multiplication and division operations in the scheme by utilizing the characteristics of FPGA chips. That is, it uses powers of 2 to replace the integer parameters that require multiplication and division coefficients in the traditional master station scheme, and uses left and right shifting to replace multipliers or dividers, thus saving FPGA chip resources and computing time.

[0074] The improved calculation method is as follows:

[0075] start_time = (app_time + 2) M *frame_time)–new_remainder+shift_time;

[0076] remainder=diff%frame_time;

[0077] diff = (app_time + 2) M *frame_time)–base_time.

[0078] Once the start_time calculation is complete, the master station writes the start_time value to the current slave station via a message to register 0x0990. Then, it writes the first two bits of register 0x0981 to 1 via a message to enable the SYNC signal, completing the SYNC signal configuration process for the current slave station. Once all slave stations have completed the SYNC signal configuration process, the entire synchronization clock operation is finished.

[0079] This embodiment highly binds the offset time (shift_time) to the interrupt signal (IRQ): when calculating the start time of the SYNC signal, frame_time is used instead of the arbitrarily set OFFSET, and frame_time is also used instead of cycle_time when calculating the remainder, so that the relative offset of the SYNC signal is always consistent with that of the IRQ signal, ensuring that the trigger point of the SYNC signal is equal to the time of the interrupt signal plus the offset time, and avoiding synchronization errors when frame_time and cycle_time are not equal.

[0080] Example 1

[0081] This embodiment sets up a test system with one master station and three slave stations. As shown in Figure 6, an oscilloscope is used to capture the IRQ signal triggered by the first slave station and the SYNC signals of the three slave stations. Here, a, b, and c represent the SYNC signals of the three slave stations, respectively. It can be seen that the three SYNC signals are triggered basically synchronously. d represents the IRQ signal triggered by the first slave station's message. The message period frame_time is set to 1ms, and shift_time is set to 30% of the period. As can be seen from Figure 6, the difference between the IRQ signal and the SYNC signals of the three slave stations is about 276us, which is basically consistent with the above settings.

[0082] Figure 7 shows the SYNC and IRQ signals of three slave stations. The SYNC signals of the first two slave stations are superimposed and basically triggered synchronously. The SYNC signal of the third slave station differs from the SYNC signals of the first two slave stations by 4.4ns. It can be seen that the SYNC signals of the three slave stations are triggered synchronously, and the synchronization of the distributed clock is basically achieved.

[0083] Therefore, the EtherCAT master station distributed clock synchronization method in this embodiment is an efficient and secure synchronization method. It utilizes the parallelism of the FPGA chip to improve the efficiency and stability of message transmission and reception, ensuring minimal jitter in interrupt and synchronization signals, avoiding synchronization errors caused by jitter when the period is short. Simultaneously, it improves the calculation method for the synchronization signal start time, avoiding synchronization errors that may occur when the synchronization signal period is not equal to the message period. Furthermore, it improves the dynamic drift compensation instruction to increase synchronization efficiency, and utilizes FPGA characteristics to optimize the algorithm, reducing resource usage and algorithm time.

[0084] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A distributed clock synchronization method for EtherCAT master stations based on ARM and FPGA, comprising: S1. An EtherCAT master station distributed clock module is constructed using an FPGA chip integrating ARM and programmable logic resources. The ARM and programmable logic resources interact through an internal AXI interconnect bus. S2. The programmable logic resources obtain the enable signal sent by the ARM. If the enable signal is 1, the master station performs topology scanning, delay calculation, clock compensation, and dynamic drift compensation on the slave station to obtain the slave station's delay compensation value and local clock compensation value. S3. After the compensation is completed, the master station's state machine automatically jumps to the synchronization signal generation module and obtains the SYNC parameter from the ARM to calculate the slave station's SYNC signal start time. S4. The delay compensation value, local clock compensation value, and start time of each slave station are converted into message information and sent to the slave station. The slave station address is incremented by 1 and the process returns to step S1 until the distributed clock configuration of all slave stations is completed. Step S3 is as follows: The master station obtains the SYNC parameters from the ARM terminal and stores them in a register. The SYNC parameters include the cycle time of the SYNC signal (cycle_time), the interval between the SYNC signal and the message arrival time (shift_time), and the message time (frame_time) set by the master station. The master station writes the cycle time (cycle_time) to the 0x09A0 register through the message and writes it to each slave station. The master station reads the 0x092C register through the message to check the difference between the master station clock and the local clock. If the difference is less than the preset threshold in the master station, the current slave station synchronization is successful; If not, since the dynamic drift compensation message is continuously sent with each frame, continue to check the difference between the master station clock and the local clock until the difference is less than the threshold, thus completing the current slave station convergence and achieving successful synchronization. After the current slave station converges, the master station calculates the start time of the current slave station's SYNC signal by modifying the previously randomly set offset value OFFSET in the master station to 2. M `frame_time` associates the delay with the message period, where M is a positive integer greater than or equal to 0. M In FPGA chips, shifters are used instead of multipliers. This represents a multiplication operation; the new_remainder is the remainder after calculating frame_time, ensuring that the SYNC signal always maintains the relative offset with the IRQ, where IRQ is the SYNC signal's relative message arrival interruption signal; the formula for calculating the current slave station's SYNC signal start_time is as follows: start_time = (app_time + 2) M frame_time) – new_remainder + shift_time;new_remainder = diff % frame_time;diff = (app_time + 2 M `frame_time` – `base_time`; where `app_time` is the current master station time, `base_time` is the distributed clock synchronization enable time (all slave stations have the same `base_time`), `new_remainder` is the new remainder, and `diff` indicates shifting the current time forward by 2. M The time difference between frame_time and the Bloom clock synchronization enable time, % indicates the modulo operation.

2. The EtherCAT master station distributed clock synchronization method according to claim 1, characterized in that, In the topology scan of the slave station, the master station obtains the distributed clock support information in the slave station's 0x0000 register and the switch information of each port of the slave station in the 0x0110 register through the message. If the master station does not specify a reference slave station, the master station will use the first slave station that supports distributed clocks among the slave stations as the reference slave station based on the distributed clock support information. Topology scan: The master station constructs the topology of the slave station based on the switch information of each port of the slave station.

3. The EtherCAT master station distributed clock synchronization method according to claim 1, characterized in that, In the delay calculation for the slave station, the specific steps are as follows: Delay calculation: Time information for different ports of each slave station is obtained by broadcasting and writing to and reading from the slave station's 0x0900 register, and these two messages are then sent. N Next, the delay compensation value is obtained, where N is an integer; Clock compensation: The master station first reads the slave station's 0x0920 register. The master station obtains the local clock of the current slave station by reading the slave station's 0x0910 register. The difference between the local clock of the current slave station and the master station's clock is calculated. If the difference is greater than the threshold preset in the master station, the difference is added to the value of the 0x0920 register to obtain the local clock compensation. Otherwise, the value of the 0x0920 register is used directly as the local clock compensation value. The current slave station address is incremented by 1, and the above delay calculation and clock compensation steps are repeated until all slave stations have completed clock compensation. The master station writes the delay compensation value and clock compensation value of each slave station to the slave station through the message writing 0x0920 and 0x0928 registers respectively.

4. The EtherCAT master station distributed clock synchronization method according to claim 1, characterized in that, The dynamic drift compensation is as follows: the master station uses a broadcast write command to inform all slave stations of the master station clock, and the message to broadcast the master station clock is continuously sent after the distributed clock synchronization function is enabled, so as to continuously compensate the slave stations for drift.

5. The EtherCAT master station distributed clock synchronization method according to claim 1, characterized in that, Once start_time is calculated, the master station writes the start_time value to the current slave station via a message to register 0x0990, and then writes the first 2 bits of register 0x0981 to enable the SYNC signal, thus completing the SYNC signal process for the current slave station. When all slave stations have completed the SYNC signal configuration process, the entire synchronous clock process is completed.

6. The EtherCAT master station distributed clock synchronization method according to claim 1, characterized in that, A Linux system is deployed on the ARM side, and the relevant programs for the EtherCAT master station are implemented on the Linux system.

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