Clock synchronization system and computer cluster

Abstract

The application discloses a clock synchronization system and a computer cluster, and relates to the technical field of servers.The clock synchronization system comprises an optical clock signal source, a fiber transmission assembly, a clock signal receiving assembly and a clock signal synchronization assembly.The clock signal receiving assembly is connected with the clock signal synchronization assembly, and the clock signal receiving assembly is further connected with the optical clock signal source through the fiber transmission assembly.The optical clock signal source is used for generating an initial clock signal and sending the initial clock signal to the clock signal interface assembly through the fiber transmission assembly.The initial clock signal is an optical signal.The clock signal receiving assembly is used for converting the initial clock signal into a target clock signal.The target clock signal is an electrical signal.The clock signal synchronization assembly is used for performing clock synchronization according to the target clock signal.In the clock synchronization system, clock synchronization can be performed based on an optical signal, and the clock signal can be transmitted through an optical fiber.The clock synchronization system improves the precision of clock synchronization.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of servers, and in particular to a clock synchronization system and a computer cluster. BACKGROUND

[0002] A computer cluster can connect multiple servers together for collaborative work, and clock synchronization between the multiple servers is crucial to ensuring data consistency.

[0003] At present, the multiple servers can be clock synchronized through a network. However, the above method is susceptible to network delay and the like, resulting in poor clock synchronization accuracy. SUMMARY

[0004] The present application provides a clock synchronization system and a computer cluster to at least solve the problem of poor clock synchronization accuracy in the related art.

[0005] In a first aspect, the present application provides a clock synchronization system, which comprises an optical clock signal source, a fiber transmission assembly, a clock signal receiving assembly, and a clock signal synchronization assembly, wherein,

[0006] The clock signal receiving assembly is connected with the clock signal synchronization assembly, and the clock signal receiving assembly is further connected with the optical clock signal source through the fiber transmission assembly;

[0007] The optical clock signal source is configured to generate an initial clock signal and send the initial clock signal to the clock signal receiving assembly through the fiber transmission assembly, the initial clock signal being an optical signal;

[0008] The clock signal receiving assembly is configured to convert the initial clock signal into a target clock signal, the target clock signal being an electrical signal;

[0009] The clock signal synchronization assembly is configured to perform clock synchronization according to the target clock signal.

[0010] In a second aspect, the present application provides a computer cluster, which is deployed with the clock synchronization system provided in any one of the first aspect.

[0011] Through the technical solutions provided in the embodiments of the present application, the clock synchronization system can generate an optical signal as an initial clock signal through an optical clock signal source, and can transmit the initial clock signal through an optical fiber. In the above clock synchronization system, clock synchronization does not need to be realized through a network, and the clock synchronization process is not affected by network delay and the like, thereby improving the accuracy of clock synchronization. In addition, the optical signal is not susceptible to electromagnetic interference, and in a high electromagnetic interference environment, the clock synchronization system provided in the embodiments of the present application can resist the influence of the high electromagnetic environment, so that the stability and reliability of clock synchronization are high. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0013] Figure 1 A schematic diagram of the structure of an APD provided in an embodiment of the present application;

[0014] Figure 2 A schematic diagram of an application scenario provided in an embodiment of the present application;

[0015] Figure 3 Schematic diagram of the clock synchronization system provided in this embodiment Figure 1 ;

[0016] Figure 4 Schematic diagram of the structure of the clock signal receiving component provided in the embodiment of the present application Figure 1 ;

[0017] Figure 5 Schematic diagram of the structure of the clock signal receiving component provided in the embodiment of the present application Figure 2 ;

[0018] Figure 6 Schematic diagram of the clock synchronization system provided in this embodiment Figure 2 ;

[0019] Figure 7 Schematic diagram of the clock synchronization system provided in this embodiment Figure 3 ;

[0020] Figure 8 Schematic diagram of a computer cluster provided in an embodiment of the present application Figure 1 ;

[0021] Figure 9 Schematic diagram of a computer cluster provided in an embodiment of the present application Figure 2 . DETAILED DESCRIPTION

[0022] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0023] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0024] The embodiments of the present application relate to an avalanche photodiode (APD). For ease of understanding, the APD is first explained.

[0025] An APD is a photodetector device with an internal gain mechanism. Its core principle is to amplify photocurrent through the avalanche multiplication effect, which can also be called the impact ionization effect, thereby achieving high-sensitivity detection of weak optical signals.

[0026] Next, combine Figure 1 , the structure and working process of APD are explained.

[0027] Figure 1 This is a schematic diagram of the structure of an APD provided in an embodiment of the present application. Figure 1 , Figure 1 The upper part is a schematic diagram of the distribution of the electric field inside the APD with position. Figure 1 The middle part is the structural diagram of APD. Figure 1 The lower part is a schematic diagram of the connection between the APD and the external circuit.

[0028] like Figure 1 As shown, the APD may include an N+ region, a P region, an I region, and a P+ region. The N+ region is a heavily doped N-type semiconductor, which serves as an injection region or collection region for carriers, where carriers are also called electrons. The P region is a lightly doped or intrinsic P-type semiconductor, which forms a PN junction with the N+ region and is the main region for light absorption. The I region is also called the intrinsic region. The I region is a lightly doped or undoped semiconductor region. In the APD, the I region is usually combined with the P region to form a depletion layer, which is the main place where the avalanche multiplication effect occurs. The P+ region is a heavily doped P-type semiconductor, which serves as the carrier collection region on the other side, where the carriers on the other side are also called holes.

[0029] APD achieves high-sensitivity detection of weak light signals through the photon absorption-avalanche multiplication mechanism. Its core working process can be divided into the following steps:

[0030] 1) Photon absorption:

[0031] When a photon strikes the P or I region of an APD, the semiconductor material absorbs the photon energy, generating initial electron-hole pairs. This process is the basis of photoelectric conversion and determines the APD's ability to respond to light signals.

[0032] 2) Impact ionization under strong electric field

[0033] APDs operate under high reverse bias voltage, creating a strong electric field within the depletion region of the PN junction—typically tens to hundreds of volts. This strong electric field accelerates photogenerated carriers (electrons and holes) to high energies, where they collide violently with lattice atoms, generating new electron-hole pairs. This process, known as impact ionization, is the starting point of the avalanche effect.

[0034] 3) Avalanche multiplication effect

[0035] The newly generated carriers are also accelerated by the strong electric field, triggering more collision ionization, forming a chain reaction. The number of carriers increases exponentially, resulting in a significant amplification of the photocurrent. Figure 2 The "avalanche zone" of medium electric field distribution refers to the area of ​​high electric field and high collision ionization rate, which is the core area of ​​the avalanche multiplication effect.

[0036] 4) Depletion region and carrier collection

[0037] After the avalanche region, the electric field gradually weakens, entering the end of the "depletion region" or the low electric field region on the other side. The carriers (electrons and holes) that have undergone avalanche multiplication move to the N+ region and P+ region respectively under the action of the electric field, and are eventually collected by external circuits to form an amplified photocurrent.

[0038] To facilitate understanding, the application scenarios of the embodiments of the present application are first described.

[0039] Figure 2 This is a schematic diagram of an application scenario provided by the embodiment of this application. Figure 2 , the computer cluster may include multiple servers, and the multiple servers may be server 1, server 2, and server 3. It should be noted that, Figure 3 The application scenarios involved in the embodiments of the present application are merely illustrative and do not limit the technical solutions provided by the embodiments of the present application. The computer cluster may include more or fewer servers than shown. For example, the computer cluster may be a computer cluster in a modern data center, or a computer cluster in a distributed computing environment.

[0040] Multiple servers in a computer cluster need to work together. For example, in a computer cluster used for high-performance computing, the servers must collaborate to perform large-scale computations and numerical simulations. In a computer cluster used for big data processing and analysis, the servers must collaborate to store, clean, and analyze data. Therefore, clock synchronization between servers is crucial to ensuring data consistency.

[0041] In related technologies, servers in a computer cluster can synchronize their clocks over a network. For example, a server in the computer cluster can send a request to a time server, which responds with the current time. The server in the computer cluster can then adjust its local clock based on the time returned by the time server. However, this clock synchronization method is susceptible to network latency and jitter. If the network environment is unstable, the accuracy of the clock synchronization system will drop significantly, resulting in poor clock synchronization accuracy.

[0042] In addition, when clock synchronization is achieved through a network in related technologies, in a high electromagnetic interference environment, the clock signal is easily affected by electromagnetic interference, resulting in low stability and reliability of clock synchronization.

[0043] In view of this, the present application provides a clock synchronization system that can perform clock synchronization based on optical signals, thereby improving the accuracy of clock synchronization and improving the stability and reliability of clock synchronization.

[0044] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0045] Figure 1 Schematic diagram of the clock synchronization system provided in this embodiment Figure 3 See Figure 3 The clock synchronization system may include an optical clock signal source, an optical fiber transmission component, a clock signal receiving component, and a clock signal synchronization component. Figure 4 As shown, the clock signal receiving component is connected to the clock signal synchronization component, and the clock signal receiving component is also connected to the optical clock signal source through the optical fiber transmission component.

[0046] This embodiment does not limit the connection method between the clock signal receiving component and the clock signal synchronization component, as long as they can communicate with each other. For example, the clock signal receiving component and the clock signal synchronization component can be installed in the same server and connected via the server's motherboard; or the clock signal receiving component and the clock signal synchronization component can be installed in the same server and connected via a communication bus.

[0047] In this embodiment, the optical clock signal source is used to generate an initial clock signal. The initial clock signal can be an optical signal, which can be a time reference signal for a clock synchronization system. In other words, the optical signal source can be a device or system that can provide a time reference signal for a clock synchronization system.

[0048] The optical clock signal source may include a laser generator and a calibration component, wherein the laser generator is used to generate an optical clock pulse signal; and the calibration component is used to calibrate the clock pulse signal to obtain an initial clock signal.

[0049] The laser generator may be a femtosecond laser comb generator, a semiconductor laser, a solid-state laser, or a fiber laser.

[0050] The calibration component can include functions such as frequency measurement, power detection, and RF signal conditioning to dynamically adjust and calibrate the frequency and power of the optical clock pulse signal generated by the laser generator to ensure the stability of the optical clock pulse signal. For example, the calibration component can be a frequency counter or a phase-locked loop (PLL) circuit.

[0051] For example, assuming that the laser generator is a femtosecond laser comb generator, after the femtosecond laser comb generator generates an optical clock pulse signal, the calibration component can calibrate the optical clock pulse signal to obtain an initial clock signal.

[0052] In this embodiment, the optical clock signal source can effectively generate a high-quality initial clock signal, providing a high-quality clock signal source for the clock synchronization system.

[0053] In this embodiment, the optical fiber transmission component may be ultra-low-loss fiber (ULLFiber), which reduces the latency of the initial clock signal and enhances anti-interference performance. In this embodiment, depending on the number of ultra-low-loss fibers included in the optical fiber transmission component, the optical fiber transmission component may include at least the following two types:

[0054] Case 1: The optical fiber transmission component may include an ultra-low loss optical fiber, that is, the optical clock signal source may be connected to the clock signal receiving component via an ultra-low loss optical fiber.

[0055] In this case, the optical clock signal source can send the initial clock signal to the clock signal receiving component through an ultra-low loss optical fiber.

[0056] In this case, the optical fiber transmission component may include a smaller amount of ultra-low-loss optical fibers, which may reduce the consumption of the ultra-low-loss optical fibers and thereby reduce the hardware resource overhead of the signal synchronization system.

[0057] Case 2: The optical fiber transmission assembly may include a main optical fiber and a backup optical fiber. The main optical fiber may include at least one ultra-low-loss optical fiber, and the backup optical fiber may include at least one ultra-low-loss optical fiber. In other words, the optical fiber transmission assembly may include multiple ultra-low-loss optical fibers, wherein the multiple ultra-low-loss optical fibers may include at least one main optical fiber and at least one backup optical fiber. In this case, the optical fiber clock signal source may be connected to the clock signal receiving assembly via the multiple ultra-low-loss optical fibers.

[0058] In this case, if the main optical fiber is not faulty, the optical clock signal source sends the initial clock signal to the clock signal interface component through the main optical fiber; if the main optical fiber fails, the optical clock signal source sends the initial clock signal to the clock signal interface component through the backup optical fiber.

[0059] In this case, when the main optical fiber fails, the initial clock signal can be transmitted through the backup optical fiber, so that the reliability and stability of the optical fiber transmission component are higher, and thus the reliability and stability of the clock synchronization system are higher.

[0060] In this embodiment, the clock signal receiving component is used to convert the initial clock signal into a target clock signal, and the target clock signal is an electrical signal.

[0061] The clock signal receiving component may include a photoelectric conversion unit and a signal processing unit, wherein the photoelectric conversion unit is used to convert the initial clock signal into an analog electrical signal; the signal processing unit is used to convert the analog electrical signal into a digital signal and perform noise reduction processing on the digital signal to obtain a target clock signal.

[0062] The optical fiber conversion unit may be an APD or the like.

[0063] The following combination Figure 4 , describes the clock signal receiving component.

[0064] Figure 1 Schematic diagram of the structure of the clock signal receiving component provided in the embodiment of the present application Figure 4 See Figure 5 The clock signal receiving component may include a photoelectric conversion unit and a signal processing unit, and the signal processing unit may include an analog-to-digital converter, a filter, and a digital signal processor.

[0065] The photoelectric conversion unit can be used to convert the initial clock signal into an analog electrical signal. In other words, the photoelectric conversion unit can be used to convert an optical signal into an electrical signal.

[0066] An analog-to-digital converter (ADC) converts analog electrical signals into digital signals. For example, the ADC can be a high-speed ADC (Analog-to-Digital Converter), ensuring a sufficiently high sampling rate to capture signal details and maintain high signal integrity.

[0067] The filter is used to filter the digital signal to obtain a filtered digital signal, so that the signal-to-noise ratio of the filtered digital signal is high. For example, the filter can be a low-pass filter, a band-pass filter, or a high-pass filter.

[0068] A digital signal processor (DSP) is used to perform noise reduction and enhancement processing on the filtered digital signal to obtain a target clock signal. Specifically, the DSP can execute a digital signal processing algorithm to achieve noise reduction and enhancement of the filtered digital signal. For example, the digital signal processing algorithm can include fast Fourier transform (FFT), digital filtering, signal denoising, and feature extraction.

[0069] In some embodiments, the clock signal receiving component may further include a controller. Figure 5 , further explaining the clock signal receiving component.

[0070] Figure 2 Schematic diagram of the structure of the clock signal receiving component provided in the embodiment of the present application Figure 5 See Figure 4 ,exist Figure 6 On the basis of, the clock signal receiving component may further include a controller, and the controller may be connected to the signal processing unit.

[0071] The controller may be a microcontroller unit (MCU), a field-programmable gate array (FPGA), or the like.

[0072] The controller is used to obtain a reference clock signal and adjust filtering parameters of the filter according to the reference clock signal.

[0073] The reference clock signal may be a clock signal obtained by the controller from a network, or the reference clock signal may be a clock signal obtained by the controller from an electronic device. The electronic device may be an electronic device other than a server where the controller is deployed.

[0074] During specific implementation, the controller can dynamically adjust the filtering parameters of the filter according to the reference clock signal, so that the reliability and stability of the clock synchronization system are better.

[0075] In this embodiment, the clock signal receiving component can convert the initial clock signal into an analog electrical signal through APD, so that the clock signal receiving component has high sensitivity, can accurately receive the optical signal and convert it into an electrical signal, thereby making the clock synchronization system have high sensitivity and high reliability.

[0076] In this embodiment, the clock signal synchronization component may include a time measurement unit and a time adjustment unit, wherein the time measurement unit is used to measure the target clock signal to obtain the time information of the target clock signal, and the time information includes a timestamp, a clock period, and a phase difference; the time adjustment unit is used to perform error calculation on the time information and adjust the target clock signal according to the result of the error calculation.

[0077] The time measurement unit may be, for example, a high-precision time counter or a clock signal receiver.

[0078] The time adjustment unit may be a device that can perform error calculation on time information using a Kalman filter algorithm, for example, a controller.

[0079] Specifically, the time measurement unit measures the target clock signal to obtain time information. The time adjustment unit performs error calculation on the time information using a Kalman filter algorithm to obtain an error calculation result, and can optimize and adjust the target clock signal based on the error calculation result to achieve higher accuracy of the target clock signal.

[0080] In the clock synchronization system provided in this embodiment, an optical clock signal source can be used to generate an optical signal serving as an initial clock signal, and the initial clock signal can be transmitted via optical fiber. In this clock synchronization system, clock synchronization is not performed over a network, and the clock synchronization process is unaffected by jitter, such as network delays, thereby improving clock synchronization accuracy.

[0081] Furthermore, optical signals are less susceptible to electromagnetic interference. Therefore, the clock synchronization system provided by this embodiment can improve the stability and reliability of clock synchronization. For servers operating in complex electromagnetic environments, the clock synchronization system provided by this embodiment can ensure high reliability and stability of server clock synchronization. This clock synchronization system provided by this embodiment can be widely used in scenarios requiring high clock synchronization accuracy, such as data centers, high-frequency trading systems, and cloud computing platforms, effectively resolving the technical issue of poor clock synchronization accuracy in related technologies.

[0082] On the basis of any of the above embodiments, the clock synchronization system provided in the embodiment of the present application may further include a display interface. Figure 6 , further illustrating the clock synchronization system provided in the embodiment of the present application.

[0083] Figure 2 Schematic diagram of the clock synchronization system provided in this embodiment Figure 6 See Figure 3 ,exist Figure 7 On the basis of, the clock synchronization system may further include a display interface, and the display interface may be connected to the clock signal synchronization component.

[0084] In this embodiment, the display interface may include a status display area, an alarm display area, and a query area, wherein the status display area is used to display the operating parameters of the clock synchronization system; the alarm display area is used to display alarm information when the preset conditions are triggered; and the query area is used to display the historical operating parameters of the clock synchronization system based on the query request.

[0085] The operating parameters of the clock synchronization system may include clock synchronization frequency, time deviation, etc.

[0086] The preset conditions may include at least one of the following: the power of the initial clock signal exceeds a preset power range; a fiber optic transmission component fails; or the temperature of the first electronic device exceeds a preset temperature. In other words, if the power of the initial clock signal exceeds the preset power range or the fiber optic transmission component fails, the alarm display area may display an alarm signal.

[0087] The historical operation parameters may include historical clock signals of the clock synchronization system, operation logs of the clock synchronization system, synchronization records of the clock synchronization system, and historical alarm information of the clock synchronization system.

[0088] In the clock synchronization system provided in this embodiment, the clock synchronization system may further include a display interface, which may display operating parameters of the clock synchronization system in real time, so as to facilitate users to monitor and manage the clock synchronization system in real time.

[0089] Based on any of the above embodiments, Figure 7 , through specific examples, the clock synchronization system provided in the embodiment of the present application is described in detail.

[0090] Figure 3 Schematic diagram of the clock synchronization system provided in this embodiment Figure 7 See Figure 7 The clock synchronization system may include an optical clock signal source, a clock signal receiving component, a clock signal synchronization component, and a display interface. The optical clock signal source may be connected to the clock signal receiving component via a primary optical fiber and a backup optical fiber. The clock signal receiving component may also be connected to the clock signal synchronization component. The clock signal synchronization component may also be connected to the display interface.

[0091] like Figure 8As shown, the optical clock signal source may include a laser generator and a calibration component. The clock signal receiving component may include a photoelectric conversion unit, a signal processing unit, and a controller. The signal processing unit may include an analog-to-digital converter, a filter, and a digital signal processor. The clock signal synchronization component may include a time measurement unit and a time adjustment unit. The display interface may include a status display area, an alarm display area, and a query area.

[0092] The clock synchronization system provided in this embodiment can synchronize clocks using optical signals, and can transmit clock signals via optical fibers. Clock signal transmission is unaffected by network delays, jitter, and packet loss, thereby improving clock signal accuracy. This makes the clock synchronization system provided in this embodiment suitable for applications requiring high real-time performance. Furthermore, optical signals are not susceptible to electromagnetic interference, resulting in a highly stable and reliable clock synchronization system.

[0093] Based on any of the above embodiments, an embodiment of the present application further provides a computer cluster, which is deployed with the clock synchronization system provided by any of the above embodiments.

[0094] The following combination Figure 8 , describes the computer cluster provided in the embodiments of the present application.

[0095] Figure 1 Schematic diagram of a computer cluster provided in an embodiment of the present application Figure 8 See Figure 8 , the computer cluster may include a clock server, server 1, server 2, ... and server N, where N may be an integer greater than or equal to 1. It should be noted that this embodiment does not limit the number of servers in the computer cluster. Figure 9 This is merely an illustrative description and does not constitute a limitation on the technical solutions provided in the embodiments of the present application.

[0096] Computer clusters can be high-performance computing (HPC) clusters, web server clusters, artificial intelligence (AI) training clusters, etc.

[0097] The server can be a computing server, storage server, database server, application server, network server, virtualization server, etc.

[0098] An optical clock signal source may be deployed in the clock server in the above-mentioned computer cluster.

[0099] A clock signal receiving component, a clock signal synchronization component, and a display interface can be deployed in any server in the computer cluster. For example, the server can be Server 1 or Server 2. The optical clock signal source can be connected to the clock signal receiving component via an optical fiber transmission component.

[0100] It should be noted that the description of the optical clock signal source, the clock signal receiving component, the clock signal synchronization component, and the display interface can be found in any of the above embodiments and will not be repeated here.

[0101] The computer cluster provided in this embodiment can deploy the clock synchronization system shown in any of the above embodiments, so that the clock synchronization accuracy of the computer cluster is higher and the clock synchronization reliability and stability are higher.

[0102] On the basis of any of the above embodiments, the computer cluster provided by the embodiment of the present application may also only be deployed with the clock signal receiving component, clock signal synchronization component, and display interface in the clock synchronization system provided by any of the above embodiments. Figure 9 , further illustrating the computer cluster provided in the embodiments of the present application.

[0103] Figure 2 Schematic diagram of a computer cluster provided in an embodiment of the present application Figure 9 See ​ The computer cluster may include server 1, server 2, ... and server N, where N may be an integer greater than or equal to 1.

[0104] For any server, a clock signal receiving component, a clock signal synchronization component, and a display interface can be deployed in the server. For example, the server can be server 1 or server 2.

[0105] A clock server can be set up outside the computer cluster, and an optical clock signal source can be deployed in the clock server. The optical clock signal source can be connected to the clock signal receiving component via an optical fiber transmission component.

[0106] It should be noted that the description of the optical clock signal source, the clock signal receiving component, the clock signal synchronization component, and the display interface can be found in any of the above embodiments and will not be repeated here.

[0107] The computer cluster provided in this embodiment can achieve clock synchronization through optical signals, so that the clock synchronization accuracy of the computer cluster is higher and the clock synchronization reliability and stability are higher.

[0108] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0109] The clock synchronization system and computer cluster provided by this application are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of this application. The description of the above embodiments is only intended to help understand the method and core concept of this application. It should be noted that, for those skilled in the art, without departing from the principles of this application, various improvements and modifications may be made to this application, and such improvements and modifications also fall within the scope of protection of the claims of this application.

Claims

1. A clock synchronization system, characterized in that: The clock synchronization system includes: an optical clock signal source deployed in a clock server, an optical fiber transmission component deployed in a computer cluster, a clock signal receiving component and a clock signal synchronization component deployed in each server in the computer cluster; wherein, The clock signal receiving component is connected to the clock signal synchronization component, and the clock signal receiving component is also connected to the optical clock signal source through the optical fiber transmission component; The optical clock signal source is used to generate an initial clock signal and send the initial clock signal to the clock signal receiving component through the optical fiber transmission component, wherein the initial clock signal is an optical signal; the optical fiber transmission component is an ultra-low loss optical fiber; The clock signal receiving component is used to convert the initial clock signal into a target clock signal at least through an avalanche photodiode APD, and the target clock signal is an electrical signal; The clock signal synchronization component is used to perform clock synchronization according to the target clock signal; Wherein, the optical clock signal source includes a laser generator and a calibration component; The laser generator is used to generate an optical clock pulse signal; the calibration component is used to calibrate the clock pulse signal to obtain the initial clock signal; Wherein, the clock signal synchronization component includes a time measurement unit and a time adjustment unit; The time measurement unit is used to measure the target clock signal to obtain time information of the target clock signal, where the time information includes a timestamp, a clock period, and a phase difference; The time adjustment unit is configured to perform error calculation on the time information using a Kalman filter algorithm, and adjust the target clock signal according to a result of the error calculation.

2. The clock synchronization system according to claim 1, wherein: The clock signal receiving component includes a photoelectric conversion unit and a signal processing unit, wherein: The photoelectric conversion unit is used to convert the initial clock signal into an analog electrical signal; The signal processing unit is used to convert the analog electrical signal into a digital signal, and perform noise reduction processing on the digital signal to obtain the target clock signal.

3. The clock synchronization system according to claim 2, wherein: The signal processing unit includes an analog-to-digital converter, a filter, and a digital signal processor, wherein: The analog-to-digital converter is used to convert the analog electrical signal into the digital signal; The filter is used to filter the digital signal to obtain a filtered digital signal; The digital signal processor is used to perform noise reduction and enhancement processing on the filtered digital signal to obtain the target clock signal.

4. The clock synchronization system according to claim 3, wherein: The clock signal receiving component further includes a controller, which is used to obtain a reference clock signal and adjust the filtering parameters of the filter according to the reference clock signal.

5. The clock synchronization system according to claim 1, wherein: The optical fiber transmission component includes a main optical fiber and a backup optical fiber, wherein: When the main optical fiber is not faulty, the optical clock signal source sends the initial clock signal to the clock signal interface component through the main optical fiber; In the event of a failure of the main optical fiber, the optical clock signal source sends the initial clock signal to the clock signal interface component through the backup optical fiber.

6. The clock synchronization system according to claim 1, wherein: The clock synchronization system further includes a display interface, which includes a status display area, an alarm display area, and a query area, wherein: The status display area is used to display the operating parameters of the clock synchronization system; The alarm display area is used to display alarm information when a preset condition is triggered; The query area is used to display historical operating parameters of the clock synchronization system based on a query request.

7. The clock synchronization system according to claim 6, characterized in that: The preset conditions include at least one of the following: The power of the initial clock signal exceeds a preset power range; The optical fiber transmission component fails.

8. A computer cluster, characterized in that: The computer cluster is deployed with the clock synchronization system according to any one of claims 1 to 6.

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