Thin film transistor and display device including the same

Abstract

The invention relates to a thin film transistor and a display device including the same. Disclosed is a thin film transistor in which a carrier mobility of a first active layer connected to a first electrode is lower than a carrier mobility of a second active layer connected to a second electrode. Accordingly, the occurrence of hot carrier stress in the first active layer is reduced even when the second active layer is made of a high carrier mobility material. Further, a display device including the thin film transistor is disclosed.

Description

Technical Field

[0001] The present disclosure relates to a thin film transistor and a display device including the same, and more particularly, for example but not limited to, to a thin film transistor having high brightness and a display device including the same. Background Art

[0002] Display devices are used in various devices such as televisions, monitors, smartphones, tablet PCs, laptop computers, and wearable devices.

[0003] The display device may display an image through a plurality of pixels included in a display area.

[0004] In this case, each pixel may include at least one thin film transistor that can individually control each pixel.

[0005] Recently, consumer demand for ultra-high-resolution display devices has been increasing, and thus a display area is required to include a greater number of pixels.

[0006] When the area or size occupied by each pixel included in the display area is reduced, the size of elements such as thin film transistors included in the pixels may be reduced.

[0007] It should not be assumed that the descriptions provided in the discussion of the related art section are prior art simply because they are mentioned in or related to that section. The discussion of the related art section may include information describing one or more aspects of the subject technology, and the descriptions in this section do not limit the present disclosure. Summary of the Invention

[0008] As the specifications of display devices increase, there is also a need to apply a high current to a thin film transistor that operates to control each pixel.

[0009] In one of the schemes for applying high current to a thin film transistor, an active layer of the thin film transistor may be made of a high carrier mobility oxide semiconductor material.

[0010] However, when the active layer is made of a high carrier mobility oxide semiconductor material, hot carrier stress (HCS) may occur in a channel region adjacent to a drain of a thin film transistor.

[0011] Hot carrier stress can be described as follows.

[0012] When the drain voltage applied to the thin film transistor increases beyond a certain value, electrons migrating through the channel region have strong migration energy, resulting in strong collision of electrons in the channel region near the drain region.

[0013] Due to such strong collision of electrons, defects may occur in the channel region near the drain region, or a hot carrier stress phenomenon in which electrons are trapped may occur.

[0014] When hot carrier stress occurs, the current characteristics of the thin film transistor element are degraded, which may cause a pixel in the display panel to fail to operate normally.

[0015] In particular, when the active layer is made of a high carrier mobility oxide semiconductor material, the possibility of hot carrier stress occurring may increase due to high carrier concentration.

[0016] Thus, when the active layer of the thin film transistor is made of a high carrier mobility oxide semiconductor material, high current may be given to the thin film transistor, and the occurrence of the hot carrier stress phenomenon may cause degraded current characteristics of the transistor or defects of the transistor.

[0017] Therefore, through various experiments, the inventors of the present disclosure have invented a thin film transistor that can reduce the occurrence of a hot carrier stress phenomenon while including a high carrier mobility active layer, and a display device including the thin film transistor.

[0018] An object according to exemplary embodiments of the present disclosure is to provide a thin film transistor that can reduce the occurrence of a hot carrier stress phenomenon and a display device including the thin film transistor.

[0019] Furthermore, an object of exemplary embodiments according to the present disclosure is to provide a thin film transistor having high brightness and a display device including the same.

[0020] Furthermore, an object of exemplary embodiments according to the present disclosure is to provide a thin film transistor that can facilitate control of a threshold voltage and a display device including the thin film transistor.

[0021] Furthermore, an object of exemplary embodiments according to the present disclosure is to provide a thin film transistor and a display device including the same, which can improve productivity and reliability of an active layer through process optimization and achieve energy-saving production.

[0022] Furthermore, an object of exemplary embodiments according to the present disclosure is to provide a thin film transistor advantageous in grayscale expression and a display device including the thin film transistor.

[0023] The objects according to the present disclosure are not limited to the above-mentioned objects. Other objects and advantages according to the present disclosure that are not mentioned can be understood based on the following description and can be more clearly understood based on the embodiments according to the present disclosure. In addition, it will be easily understood that the objects and advantages according to the present disclosure can be achieved using the devices shown in the claims or their combinations.

[0024] A thin film transistor according to an exemplary embodiment of the present disclosure includes an active layer, a first electrode connected to one side of the active layer, a second electrode connected to an opposite side of the active layer, and a gate disposed on top of the active layer.

[0025] In this case, the active layer includes a first active layer connected to the first electrode and a second active layer connected to the second electrode, and carrier mobility of the first active layer is lower than that of the second active layer.

[0026] Furthermore, a display device according to an exemplary embodiment of the present disclosure includes: a light emitting element; and a driving thin film transistor including an active layer, a first electrode, a second electrode, and a gate electrode and configured to drive the light emitting element.

[0027] In this case, carrier mobility of a first region of the active layer connected to the first electrode is lower than carrier mobility of a second region of the active layer connected to the second electrode.

[0028] According to an exemplary embodiment of the present disclosure, the carrier mobility of the first active layer connected to the first electrode is lower than the carrier mobility of the second active layer connected to the second electrode. Therefore, even when the second active layer is made of a high-carrier-mobility material, the occurrence of hot carrier stress in the first active layer can be reduced.

[0029] Furthermore, according to exemplary embodiments of the present disclosure, the large effective channel region of the active layer constituting the main channel can be made of a relatively high carrier mobility material, thereby allowing high current to flow through the thin film transistor, thereby realizing a display device with high brightness.

[0030] Furthermore, according to the exemplary embodiment of the present disclosure, since the active layer is formed as a stack of a plurality of layers having different carrier mobilities, it is easier to control a threshold voltage in the active layer based on high current characteristics.

[0031] Furthermore, according to exemplary embodiments of the present disclosure, since the active layer is formed as a stack of multiple layers having different carrier mobilities, a limited range of process conditions required in forming the active layer can be expanded compared to forming the active layer as a single layer.

[0032] Therefore, not only can the productivity and reliability of the active layer be improved, but also energy saving in production can be achieved through process optimization.

[0033] Furthermore, according to exemplary embodiments of the present disclosure, the S factor value can be increased by electrically connecting a light shielding layer disposed below a thin film transistor to the source electrode of the thin film transistor. Therefore, the display device can exhibit sufficient grayscale, which can be advantageous in terms of grayscale expression.

[0034] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects that are not mentioned will be clearly understood by those skilled in the art from the following description.

[0035] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0037] Figure 1 is a schematic plan view of a display device according to an exemplary embodiment of the present disclosure.

[0038] Figure 2 is a circuit diagram of one sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0039] Figure 3 is a cross-sectional view of a thin film transistor according to a first exemplary embodiment of the present disclosure.

[0040] Figure 4 is a cross-sectional view of a thin film transistor according to a second exemplary embodiment of the present disclosure.

[0041] Figure 5 is a cross-sectional view of a thin film transistor according to a third exemplary embodiment of the present disclosure.

[0042] Figure 6 is a cross-sectional view of a thin film transistor according to a fourth exemplary embodiment of the present disclosure.

[0043] Figure 7 is a cross-sectional view of a thin film transistor according to a fifth exemplary embodiment of the present disclosure.

[0044] Figure 8 is a cross-sectional view of a thin film transistor according to a sixth exemplary embodiment of the present disclosure.

[0045] Figure 9 is a cross-sectional view of a thin film transistor according to a seventh exemplary embodiment of the present disclosure.

[0046] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The relative sizes and depictions of these elements may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0047] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. The described progression of processing steps and / or operations is an example; however, the order of the steps and / or operations is not limited to that set forth herein and may be varied as is known in the art, except that steps and / or operations must occur in a specific order. The names of the various elements used in the following description may have been selected solely for convenience in writing the description and, therefore, may differ from the names used in the actual product.

[0048] The advantages and features of the present disclosure, as well as methods for achieving the advantages and features, will become apparent with reference to the exemplary embodiments described in detail later in conjunction with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed below, but may be embodied in a variety of different forms. Therefore, these exemplary embodiments are provided only to make this disclosure complete and to fully inform those skilled in the art of the present disclosure of its scope, and the present disclosure is limited only by the scope of the claims.

[0049] The shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings for illustrating exemplary embodiments of the present disclosure are illustrative, and the present disclosure is not limited thereto. For simplicity and clarity of explanation, the elements in the drawings are not necessarily drawn to scale. The same reference numerals in different drawings represent the same or similar elements and therefore perform similar functions. In addition, in order to simplify the description, descriptions and details of well-known steps and elements are omitted. In addition, in the following detailed description of the present disclosure, many specific details are proposed in order to provide a thorough understanding of the present disclosure. However, it will be understood that the present disclosure can be practiced without these specific details. In other examples, well-known methods, processes, components and circuits are not described in detail to avoid unnecessarily obscuring aspects of the present disclosure. The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular constructions "one" and "an" are intended to also include plural constructions unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "comprises", "including", "includes", "contains", "composes", "made of", "formed of", etc. specify the presence of stated features, integers, operations, elements and / or parts, but do not preclude the presence or addition of one or more other features, integers, operations, elements, parts and / or parts thereof.

[0050] When interpreting numerical values, the values are interpreted as including the error range unless expressly stated otherwise.Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0051] Furthermore, as used herein, when a layer, film, region, panel area, etc. is disposed “on,” “on top of,” “above,” “upper,” or “over” another layer, film, region, panel area, etc., the former may be in direct contact with the latter, or another layer, film, region, panel area, etc. may be disposed between the former and the latter. For example, when one element or layer is disposed “on” another element or layer, a third layer or element may be interposed therebetween. As used herein, when a layer, film, region, panel area, etc. is disposed directly “on” or “above” another layer, film, region, panel area, etc., the former is in direct contact with the latter, and no further layer, film, region, panel area, etc. is disposed therebetween. Furthermore, as used herein, when a layer, film, region, panel area, etc. is disposed “under” or “below” another layer, film, region, panel area, etc., the former may be in direct contact with the latter, or another layer, film, region, panel area, etc. may be disposed therebetween. As used herein, when a layer, film, region, panel area, etc. is disposed directly “under” or “beneath” another layer, film, region, panel area, etc., the former is in direct contact with the latter and no further layer, film, region, panel area, etc. is disposed between the former and the latter.

[0052] In descriptions of temporal relationships (for example, temporal precedence relationships between two events such as "after," "subsequently," "before," etc.), unless "directly after," "directly subsequent," or "directly before" is indicated, another event may occur in between.

[0053] It will be understood that although the terms "first," "second," "third," "A," "B," "(A)," or "(B)," etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion described below could be termed a second element, component, region, layer, or portion without departing from the spirit and scope of the present disclosure.

[0054] The features of the various exemplary embodiments of the present disclosure may be partially or completely combined with each other, and may be technically associated with each other or operate with each other. The embodiments may be embodied independently of each other, and may be embodied together in an associated relationship.

[0055] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of a first element, a second element, and a third element" encompasses all combinations of the three listed elements, any two of the three elements, and each individual element, the first element, the second element, or the third element.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments belong. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein. For example, the term "part" or "unit" may apply to, for example, a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure that is configured to perform the described function as would be understood by one of ordinary skill in the art.

[0057] The features of the various embodiments of the present disclosure may be combined in part or in whole, and may be technically related to or interoperable with each other. The embodiments may be implemented independently of each other, or may be implemented together in a related relationship.

[0058] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. For the sake of convenience, the components shown in the drawings have a different scale from that of the actual components, and are therefore not limited to the scale shown in the drawings.

[0059] Below, we will refer to Figures 1 to 2 A display device according to an exemplary embodiment of the present disclosure is described in detail.

[0060] Figure 1 is a schematic plan view of a display device according to an exemplary embodiment of the present disclosure.

[0061] The following describes an example in which the display device 1 is embodied as an organic electroluminescent display device (eg, an organic light emitting diode display device). However, embodiments of the present disclosure are not limited thereto.

[0062] The display device 1 may include a substrate 10 including a display area AA and a non-display area NA surrounding the display area AA.

[0063] In the display area AA of the substrate 10 , a plurality of data lines DL extending in a first direction and a plurality of gate lines GL extending in a second direction intersecting the first direction may be arranged.

[0064] Each of a plurality of sub-pixels, such as sub-pixels SP1 , SP2 , and SP3 , may be disposed in each intersection of the data line DL and the gate line GL.

[0065] The sub-pixels SP1 , SP2 , and SP3 may emit light of the same color, for example, white (W) light or red (R), green (G), or blue (B) light, or may emit light beams of different colors.

[0066] The combination of the plurality of sub-pixels SP1 , SP2 and SP3 described above may constitute a pixel P, but the present invention is not limited thereto. More or fewer sub-pixels may constitute a pixel P.

[0067] The plurality of sub-pixels SP1 , SP2 , and SP3 may be arranged in a plurality of rows and columns in a matrix format.

[0068] As used herein, the first direction may be a column or vertical direction and may be defined as a Y-axis direction, and the second direction may be a row or horizontal direction and may be defined as an X-axis direction, but is not limited thereto. In another example, the first direction may be a row or horizontal direction, and the second direction may be a column or vertical direction.

[0069] A plurality of lines and pads for supplying various signals and power to the pixels may be disposed on the non-display area NA of the substrate 10 , but is not limited thereto.

[0070] The data driver circuit (D-IC) 20 may be disposed in one side region of the non-display area NA.

[0071] The data driver circuit 20 may be a circuit for driving a plurality of data lines and may apply data signals to the data lines DL and may apply a driving voltage such as a high potential voltage VDD or a low potential voltage VSS to the pixels P.

[0072] The power line 30 may extend along the edge of the display area AA and in a side area of the non-display area NA except for a side area where the data driver circuit 20 is disposed, but is not limited thereto.

[0073] For example, a gate driver 40 that applies a gate signal to the gate line GL may be provided in the non-display area NA and located on each of two opposite sides of the display area AA. For example, the gate driver 40 may be a circuit for driving a plurality of gate lines. A power supply line 30 that can apply a voltage to an anode or cathode in a pixel P may extend along an outer edge of the gate driver 40 and in the non-display area NA.

[0074] The power line 30 may include a low-potential voltage line capable of applying a low-potential voltage VSS to the cathode of the pixel P. However, the embodiments of the present disclosure are not limited thereto. For example, the power line 30 may also include a high-potential voltage line capable of applying a high-potential voltage VDD to the thin film transistor of the pixel P.

[0075] Multiple power connection lines 31 can be set in the display area AA and can electrically connect the power line 30 to multiple sub-pixels SP1, SP2 and SP3, and can be set between the power line 30 and multiple sub-pixels SP1, SP2 and SP3, and can apply a low potential voltage to the multiple sub-pixels SP1, SP2 and SP3.

[0076] For example, the plurality of power connection lines 31 may extend to equal lengths in the first direction in which the plurality of data lines DL extend, but is not limited thereto.

[0077] Figure 2 is a circuit diagram of one sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0078] The following describes an example of implementing a subpixel based on a 4T (transistor) 2C (capacitor) structure. However, embodiments of the present disclosure are not limited thereto. For example, 3T1C, 4T1C, 5T1C, 3T2C, 5T2C, 6T2C, 7T1C, 7T2C, 8T2C structures, etc. are also possible. Furthermore, more or fewer transistors and capacitors may be included.

[0079] For example, a sub-pixel includes a first storage capacitor Cst1, a second storage capacitor Cst2, a switching transistor SW, a light emitting control transistor ET, a sensing transistor ST, a driving transistor DR and a light emitting element OLED. Figure 2 However, the embodiments of the present disclosure are not limited thereto. More or fewer elements are also possible.

[0080] Each of the switching transistor SW, the light emission control transistor ET, and the sensing transistor ST may function as a switch.

[0081] The first scan signal SCAN1 , the second scan signal SCAN2 , and the third scan signal EM may be supplied to the sub-pixels through the gate lines GL, and the data voltage Vdata may be supplied to the sub-pixels through the data lines DL.

[0082] The switching transistor SW may be used to apply the voltage of the data line DL to the node A. For example, when the switching transistor SW is turned on in response to the first scan signal SCAN1 , the voltage of the data line DL is applied to the node A.

[0083] The switching transistor SW may be turned on or off based on the first scan signal SCAN1 .

[0084] The node A may be connected to the gate of the driving transistor DR. That is, the node A may be located between the switching transistor SW and the driving transistor DR.

[0085] The sensing transistor ST may be used to apply an initialization voltage Vini to the node B to initialize the circuit when performing a compensation operation. For example, when the sensing transistor ST is turned on in response to the second scan signal SCAN2 , the initialization voltage Vini is applied to the node B.

[0086] The sensing transistor ST may be turned on or off based on the second scan signal SCAN2 .

[0087] The light emission control transistor ET may be turned on or off based on the third scan signal EM.

[0088] The driving transistor DR may be turned on or off based on the data voltage.

[0089] The switching transistor SW may perform a switching operation in response to the first scan signal SCAN1 to store the data voltage Vdata in the first capacitor Cst1. The first capacitor Cst1 may be disposed between the node A and the node B.

[0090] The driving transistor DR may operate to allow a driving current to flow between the high potential power line VDDEL and the low potential power line VSSEL based on the data voltage stored in the first capacitor Cst1 .

[0091] The driving transistor DR may be turned on based on the data voltage to control current flowing through the light emitting element OLED to display an image.

[0092] The light emitting element OLED may emit light based on the current of the high potential voltage transmitted through the driving transistor DR.

[0093] One side of the light emitting element OLED can be connected to the node B, and the other side thereof can be connected to the low potential power line VSSEL. For example, the anode of the light emitting element OLED can be connected to the node B, and the cathode thereof can be connected to the low potential power line VSSEL.

[0094] In the present disclosure, the light emitting element OLED may be embodied as an organic light emitting diode. However, the embodiments of the present disclosure are not limited thereto. Various types of light emitting elements may be used as the light emitting element.

[0095] The second capacitor Cst2 may be a compensation capacitor and, for example, may compensate for a threshold voltage of the driving transistor DR.

[0096] One side of the second capacitor Cst2 may be connected to one side of the driving transistor DR, and the other side thereof may be connected to the other side of the light emission control transistor ET. The other side of the driving transistor DR may be connected to one side of the light emission control transistor ET.

[0097] Each of the switching transistor SW and the sensing transistor ST may have a double-gate structure in which gates are respectively located on top of and below one active layer.

[0098] Since each of the switching transistor SW and the sensing transistor ST has a double-gate structure, switching performance may be improved by improving on / off characteristics of the transistors.

[0099] Below, we will refer to Figure 3A thin film transistor according to a first exemplary embodiment of the present disclosure is described in detail.

[0100] The thin film transistor described in the present disclosure may be a driving thin film transistor as the driving transistor DR. However, the embodiments of the present disclosure are not limited thereto.

[0101] Reference Figure 3 , a substrate 10 may be provided, and the substrate 10 may be referred to as a thin film transistor substrate.

[0102] Glass, plastic such as polyimide, or a flexible polymer film may be used as the material of the substrate 10. However, the embodiments of the present disclosure are not limited thereto.

[0103] The light shielding layer 210 may be provided on the substrate 10. Specifically, the light shielding layer 210 may be provided on a portion of the substrate 10.

[0104] The light shielding layer 210 may protect the active layer 220 of the thin film transistor by blocking light incident from the outside.

[0105] Therefore, the light shielding layer 210 may be disposed to overlap the active layer 220 in a vertical direction.

[0106] Figure 3 The vertical direction in may represent the Z-axis direction, but is not limited thereto.

[0107] The light shielding layer 210 may be formed to have an area larger than that of the active layer 220 , and thus may effectively protect the active layer 220 of the thin film transistor by blocking light incident from a position below the active layer 220 .

[0108] The buffer layer 150 may be disposed on the light shielding layer 210. Specifically, the buffer layer 150 may be disposed on the light shielding layer 210 and on a portion of the substrate 10 exposed by the light shielding layer 210.

[0109] The buffer layer 150 may be composed of a single layer or a double layer made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the embodiments of the present disclosure are not limited thereto.

[0110] The buffer layer 150 may protect the active layer 220 by blocking air and moisture.

[0111] The active layer 220 may be disposed on the buffer layer 150. Specifically, the active layer 220 may be disposed on a portion of the buffer layer 150.

[0112] The active layer 220 may include a first active layer 221 and a second active layer 222 having different carrier mobilities, but is not limited thereto.

[0113] The first active layer 221 and the second active layer 222 may be arranged side by side and may be disposed in the same plane, but are not limited thereto.

[0114] For example, the first active layer 221 and the second active layer 222 may be arranged side by side and may be disposed on the buffer layer 150 , but is not limited thereto.

[0115] Each of the first active layer 221 and the second active layer 222 may be formed as a single layer, but is not limited thereto. In another example, the active layer 220 may be formed as a double-layer stack consisting of two layers, ie, a lower layer and an upper layer, such as Figure 4 shown.

[0116] like Figure 3 As shown, the length of the second active layer 222 in the left-right direction may be greater than the length of the first active layer 221 in the left-right direction.

[0117] like Figure 3 The left and right directions shown may refer to the X-axis direction.

[0118] Each of the first active layer 221 and the second active layer 222 may include an oxide semiconductor material, but is not limited thereto.

[0119] As an example, the first active layer 221 may have carrier mobility lower than that of the second active layer 222 .

[0120] Therefore, the first active layer 221 may be made of an oxide semiconductor material having a first carrier mobility, and the second active layer 222 may be made of an oxide semiconductor material having a second carrier mobility higher than the first carrier mobility. For example, the first active layer 221 may be made of an oxide semiconductor material having a low carrier mobility, and the second active layer 222 may be made of an oxide semiconductor material having a high carrier mobility.

[0121] As used herein, low carrier mobility and high carrier mobility are relative concepts. Comparing the mobility values of the first active layer 221 and the second active layer 222 with each other, a relatively low carrier mobility value can be referred to as low carrier mobility, and a relatively high carrier mobility value can be referred to as high carrier mobility.

[0122] In one example, the first active layer 221 with low carrier mobility may include at least one of an IGZO (InGaZnO)-based oxide semiconductor material [Ga concentration ≥ In concentration], a GZO (GaZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, and a GZTO (GaZnSnO)-based oxide semiconductor material. However, embodiments of the present disclosure are not limited thereto.

[0123] For example, the first active layer 221 may have a thickness ranging from about 5 cm 2 / V·s to 12cm 2 However, the embodiments of the present disclosure are not limited thereto.

[0124] In one example, the second active layer 222 with high carrier mobility may include at least one of an IGZO (InGaZnO)-based oxide semiconductor material [In concentration>Ga concentration], an IZO (InZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material, a FIZO (FeInZnO)-based oxide semiconductor material, a ZnO-based oxide semiconductor material, a SIZO (SiInZnO)-based oxide semiconductor material, and a ZnON (Zn-oxynitride)-based oxide semiconductor material. However, embodiments of the present disclosure are not limited thereto.

[0125] For example, the second active layer 222 may have a thickness ranging from about 20 cm 2 / V·s to 50cm 2 However, the embodiments of the present disclosure are not limited thereto.

[0126] The gate insulating layer 160 may be disposed on the active layer 220. Specifically, the gate insulating layer 160 may be disposed on the active layer 220 and a portion of the buffer layer 150 exposed by the active layer 220. The gate insulating layer 160 may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx). However, embodiments of the present disclosure are not limited thereto.

[0127] The gate 230 may be disposed on the gate insulating layer 160. Specifically, the gate 230 may be disposed on a portion of the gate insulating layer 160.

[0128] The gate electrode 230 may be disposed to overlap the active layer 220 in a vertical direction.

[0129] The gate 230 may be formed to have an area smaller than that of the active layer 220 , but is not limited thereto.

[0130] The interlayer insulating layer 170 may be disposed on the gate 230. Specifically, the interlayer insulating layer 170 may be disposed on the gate 230 and a portion of the gate insulating layer 160 exposed by the gate 230.

[0131] The interlayer insulating layer 170 may be formed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx). However, the embodiments of the present disclosure are not limited thereto.

[0132] The first electrode 241 and the second electrode 242 may be disposed on the interlayer insulating layer 170. Specifically, the first electrode 241 and the second electrode 242 may be disposed on a portion of the interlayer insulating layer 170.

[0133] The first electrode 241 may be connected to the first active layer 221 , which is a portion of the active layer 220 , via a first contact hole 241 h extending through the interlayer insulating layer 170 and the gate insulating layer 160 .

[0134] A region where the first active layer 221 of the active layer 220 is located may be defined as a first region. That is, the first electrode 241 may be connected to the first region via a first contact hole 241 h extending through the interlayer insulating layer 170 and the gate insulating layer 160 .

[0135] In addition, the second electrode 242 may be connected to the second active layer 222 , which is another portion of the active layer 220 , via a second contact hole 242 h extending through the interlayer insulating layer 170 and the gate insulating layer 160 .

[0136] Another region of the active layer 220 where the second active layer 222 is located may be defined as a second region. That is, the second electrode 242 may be connected to the second region via a second contact hole 242 h extending through the interlayer insulating layer 170 and the gate insulating layer 160 .

[0137] In addition, the second electrode 242 may be connected to the light shielding layer 210 via a third contact hole 243 h extending through the interlayer insulating layer 170 , the gate insulating layer 160 , and the buffer layer 150 , but is not limited thereto.

[0138] Therefore, the active layer 220 and the light shielding layer 210 may be electrically connected to each other via the second electrode 242 .

[0139] Therefore, the light shielding layer 210 according to the exemplary embodiment of the present disclosure can be electrically connected to the second electrode 242. However, the embodiment of the present disclosure is not limited thereto. In another embodiment, the light shielding layer 210 may not be in contact with the second electrode 242, but may be connected to another electrode or line, thereby connecting to the ground electrode.

[0140] According to an exemplary embodiment of the present disclosure, electrically connecting the second electrode 242 and the light shielding layer 210 disposed under the thin film transistor can increase the S factor value. Therefore, the display device can express sufficient grayscale, which can be advantageous in terms of grayscale expression.

[0141] The S factor is called a "subthreshold slope" and indicates the voltage required when the current increases 10 times. In a graph (IV curve) showing the drain current versus gate voltage characteristics, the S factor value is the reciprocal value of the slope of the graph (IV curve) in the range below the threshold voltage.

[0142] A small S factor value means that the slope of the drain current versus gate voltage characteristic graph IV is large.

[0143] Therefore, the thin film transistor can be turned on even at a small voltage, and the switching characteristics of the thin film transistor can be improved.

[0144] On the other hand, since the voltage reaches the threshold voltage in a short time, it may be difficult to express a sufficient gray scale.

[0145] In contrast, a large S-factor value means that the slope of the drain current versus gate voltage characteristic graph IV is small.

[0146] Therefore, the switching characteristics of the thin film transistor may be degraded due to a decrease in the on / off response speed of the thin film transistor, but since the voltage reaches the threshold voltage in a relatively long period of time, sufficient grayscale expression may be achieved.

[0147] When the light shielding layer 210 disposed under the active layer 220 is not connected to the second electrode 242 , the light shielding layer 210 plays the same role as a gate, thereby improving the switching characteristics of the transistor.

[0148] However, as described above, when the switching characteristics are improved, the voltage reaches the threshold voltage in a short time, making it difficult to express sufficient grayscale. Therefore, the light shielding layer 210 according to the exemplary embodiment of the present disclosure can be electrically connected to the second electrode 242 so that the thin film transistor can provide sufficient grayscale expression.

[0149] In another embodiment, the light shielding layer 210 may not be in contact with the second electrode 242 but may be connected to another electrode or line so as to be connected to a ground electrode.

[0150] The first electrode 241 may be a drain electrode, and the second electrode 242 may be a source electrode. However, the embodiments of the present disclosure are not limited thereto. In another embodiment, the first electrode 241 may be a source electrode, and the second electrode 242 may be a drain electrode.

[0151] The thin film transistor may include the active layer 220 , the gate electrode 230 , the first electrode 241 , and the second electrode 242 formed in this manner.

[0152] The thin film transistor according to an exemplary embodiment of the present disclosure is configured such that the first electrode 241 and the second electrode 242 have asymmetric structures with each other and can be configured as a unidirectional element in which current flows only in a direction from the second electrode 242 to the first electrode 241. However, the embodiments of the present disclosure are not limited thereto.

[0153] like Figure 3 As shown, a region of the active layer 220 that overlaps the gate 230 in a vertical direction may be a channel region CA.

[0154] Thus, a region of each of the first and second active layers 221 and 222 constituting the active layer 220 that vertically overlaps the gate 230 may be a channel region CA. For example, the channel region CA may include a first channel region CA1 and a second channel region CA2.

[0155] As discussed above, the length of the second active layer 222 in the left-right direction may be greater than that of the first active layer 221. For example, the length of the second channel region CA2 may be greater than that of the first channel region CA1.

[0156] For example, a region where the first active layer 221 of the active layer 220 and the gate 230 vertically overlap each other may be a first channel region CA1 , and a region where the second active layer 222 of the active layer 220 and the gate 230 vertically overlap each other may be a second channel region CA2 .

[0157] Regions of the active layer 220 that do not overlap the gate 230 in a vertical direction may be the conductive regions CDA1 and CDA2. For example, the channel region CA may be disposed between the conductive regions CDA1 and CDA2.

[0158] For example, the channel region CA and the conductive regions CDA1 and CDA2 may be formed in the active layer 220 through plasma treatment or hydrogen treatment using the gate electrode 230 as a mask.

[0159] The first active layer 221 connected to the first electrode 241 may function as a first conductive region CDA1 in a region not overlapping the gate 230. The first active layer 221 connected to the first electrode 241 may function as a first channel region CA1 in a region overlapping the gate 230.

[0160] The first active layer 221 may be positioned so that a portion thereof vertically overlaps the gate 230 to function as a first channel region CA1. The first active layer 221 may be positioned so that a portion thereof vertically does not overlap the gate 230 to function as a first conductive region CDA1.

[0161] The second active layer 222 connected to the second electrode 242 may function as a second conductive region CDA2 in a region not overlapping the gate 230. The second active layer 222 connected to the second electrode 242 may function as a second channel region CA2 in a region overlapping the gate 230.

[0162] The second active layer 222 may be positioned so that a portion thereof vertically overlaps the gate 230 to function as the second channel region CA2. The second active layer 222 may be positioned so that a portion thereof vertically does not overlap the gate 23 to function as the second conductive region CDA2.

[0163] In this case, the second active layer 222 may be formed to have a larger overlapping area with the gate 230 than an area of the first active layer 221 overlapping with the gate 230. That is, an area of the second channel region CA2 may be larger than an area of the first channel region CA1.

[0164] Therefore, the length of the second channel region CA2 of high carrier mobility may be greater than the length of the first channel region CA1 of low carrier mobility.

[0165] A main portion of the channel region CA through which a larger number of carriers migrate may be referred to as a main channel region, and a portion of the channel region CA through which a smaller number of carriers migrate may be referred to as a sub-channel region.

[0166] However, depending on the stacking type of the active layer 220 , the channel region may further include a sub-channel region in addition to the main channel region.

[0167] Carriers may migrate in the sub-channel region. However, a smaller number of carriers may migrate in the sub-channel region than in the main channel region.

[0168] When the active layer 220 is formed as a single layer, both the second channel region CA2 and the first channel region CA1 , which are arranged side by side and disposed in the same plane, may be main channel regions.

[0169] The first channel region CA1 and the second channel region CA2 may be arranged not to overlap each other in a vertical direction, but are not limited thereto.

[0170] Therefore, the flowing main current MC may flow from the second electrode 242 to the first electrode 241 via the second channel region CA2 and the first channel region CA1. For example, the flowing main current MC may flow from the source to the drain via the second channel region CA2 and the first channel region CA1, but is not limited thereto.

[0171] In this case, since the length of the second channel region CA2 with high carrier mobility is greater than the length of the first channel region CA1 with low carrier mobility, the second channel region CA2 with high carrier mobility may occupy most of the main channel region.

[0172] According to an exemplary embodiment of the present disclosure, most of the main channel region in the channel region CA of the active layer 220 can be made of a relatively high carrier mobility material, thereby allowing high current to flow through the thin film transistor.

[0173] The first and second boundary regions ΔL1 and ΔL2 may be disposed at one side of the channel region CA adjacent to the first conductive region CDA1 and the other side of the channel region CA adjacent to the second conductive region CDA2, respectively.

[0174] As previously described, each of the first conductive region CDA1 and the second conductive region CDA2 may be formed by conductively conducting a region excluding the channel region CA of the active layer 220. For example, the first conductive region CDA1 may be formed by conductively conducting a region excluding the channel region CA of the first active layer 221, and the second conductive region CDA2 may be formed by conductively conducting a region excluding the channel region CA of the second active layer 222.

[0175] However, in conducting the portion of the active layer 220 into the conductive portion, a portion of the channel area CA adjacent to each of the first and second conductive regions CDA1 and CDA2 may partially undergo the conducting process to become the conductive portion.

[0176] Therefore, a portion of the channel area CA adjacent to the first conductive region CDA1 may partially undergo a conductive process to become a conductive portion, and thus may become the first boundary region ΔL1 .

[0177] The first boundary region ΔL1 may be disposed in the first channel region CA1 of the first active layer 221. The first channel region CA1 may be adjacent to the first conductive region CDA1.

[0178] Furthermore, a portion of the channel area CA adjacent to the second conductive area CDA2 may partially undergo a conductive process to become a conductive portion, and thus may become a second boundary area ΔL2 .

[0179] The second boundary region ΔL2 may be disposed in the second channel region CA2 of the second active layer 222. The second channel region CA2 may be adjacent to the second conductive region CDA2.

[0180] Each of the first boundary region ΔL1 and the second boundary region ΔL2 may have a higher carrier concentration than that of the channel region CA. However, embodiments of the present disclosure are not limited thereto.

[0181] The Fermi levels of the first and second boundary regions ΔL1 and ΔL2 may be similar to those of the first and second conductive regions CDA1 and CDA2, respectively. However, embodiments of the present disclosure are not limited thereto.

[0182] In this manner, conductivity of the first and second boundary regions ΔL1 and ΔL2 , which are two opposite edges of the channel region CA, may be increased while a portion of the active layer 220 is converted into the first and second conductive regions CDA1 and CDA2 .

[0183] The lengths of the first boundary region ΔL1 and the second boundary region ΔL2 may be referred to as a first conductive penetration length ΔL1 and a second conductive penetration length ΔL2 , respectively.

[0184] A region corresponding to a portion of the channel region CA excluding the first conductive penetration length ΔL1 and the second conductive penetration length ΔL2 from among the total length of the channel region CA may be defined as an effective channel region.

[0185] The length of the first channel region CA1 may at least exceed the first conductive penetration length ΔL1.

[0186] Therefore, in the first active layer 221, a region corresponding to the length of the first channel region CA1 excluding the first conductive penetration length ΔL1 in the total length may become a first effective channel region.

[0187] Similarly, in the second active layer 222, the area corresponding to the length of the second channel region CA2 excluding the second conductive penetration length ΔL2 in the total length can become a second effective channel region. Therefore, in the second active layer 222, an effective channel region with high carrier mobility can be ensured.

[0188] In this manner, an effective channel region having a low carrier concentration and thus a low carrier mobility can be ensured in the first active layer 221. Therefore, even when current flows from the second electrode 242 to the first electrode 241, the possibility of hot carrier stress occurring can be greatly reduced.

[0189] In this way, in the second active layer 222 , an effective channel region having a high carrier concentration and thus a high carrier mobility can be ensured.

[0190] According to the exemplary embodiment of the present disclosure as described above, the carrier mobility of the first active layer 221 connected to the first electrode 241 is lower than the carrier mobility of the second active layer 222 connected to the second electrode 242. Therefore, even when the second active layer 222 is made of a high carrier mobility material, the occurrence of hot carrier stress in the first active layer 221 can be reduced.

[0191] That is, the first active layer 221 connected to the first electrode 241 can be formed to have low carrier mobility, which can reduce the carrier concentration in the first channel region CA1. Even when current flows unidirectionally from the second electrode 242 to the first electrode 241, the occurrence of hot carrier stress in the first active layer 221 near the first channel region CA1 can be reduced.

[0192] Furthermore, according to an exemplary embodiment of the present disclosure, the first active layer 221 and the second active layer 222 having different carrier mobilities can be arranged side by side and can be provided in the same layer, and each can be formed as a single layer, but is not limited thereto. Specifically, the carrier mobility of the first active layer 221 connected to the first electrode 241 is lower than the carrier mobility of the second active layer 222 connected to the second electrode 242. Therefore, it is possible to reduce the degradation of the step coverage of the gate insulating layer 160 formed on the first active layer 221 and the second active layer 222.

[0193] As the degradation of the step coverage of the gate insulating layer 160 is reduced, a stabilization effect of device characteristics can be obtained.

[0194] In the following, we will refer to Figures 4 to 9 Thin film transistors according to some further embodiments of the present disclosure are described.

[0195] However, in the second to seventh embodiments described below, the descriptions of the embodiments described above will be omitted or briefly given. Figure 3 The following description will focus on the configuration different from that of the thin film transistor according to the first exemplary embodiment.

[0196] Reference Figure 4 In the thin film transistor according to the second exemplary embodiment, the first active layer 221 may extend toward the second electrode 242 such that the first active layer 221 covers the top surface of the second active layer 222, but is not limited thereto. Figure 3 In the first exemplary embodiment, the first active layer 221 and the second active layer 222 may be arranged side by side and may be disposed in the same plane.

[0197] Therefore, the active layer 220 may be formed as a double-layer stack consisting of two layers, ie, a lower layer and an upper layer, but is not limited thereto. Figure 3 In the first exemplary embodiment, each of the first active layer 221 and the second active layer 222 may be formed as a single layer.

[0198] For example, a portion of the first active layer 221 and the second active layer 222 may be disposed in a stacked lower layer. Another portion of the first active layer 221 may extend from the first active layer 221 of the lower layer and may be disposed in a stacked upper layer. That is, another portion of the first active layer 221 of the upper layer may cover the top surface of the second active layer 222 of the lower layer.

[0199] In this case, the first channel region CA1 of the first active layer 221 may become larger by a length by which the first active layer 221 extends from the first active layer 221 of the lower layer to be disposed in the stacked upper layer.

[0200] Since the first active layer 221 is disposed to cover the top surface of the second active layer 222 , the top surface of the first active layer 221 may be closer to the gate than the top surface of the second active layer 222 .

[0201] Since the first active layer 221 of the upper layer is located closer to the gate 230 than the second active layer 222 , a gate field may be strongly applied to the first active layer 221 so that the first channel region CA1 of the first active layer 221 may serve as a main channel region.

[0202] In this manner, when the first channel region CA1 of low carrier mobility becomes the main channel region, it may be difficult to achieve the high current characteristic effect of the thin film transistor.

[0203] Therefore, according to an exemplary embodiment of the present disclosure, the difference between the carrier mobility of the second active layer 222 and the carrier mobility of the first active layer 221 can be set to be larger, and thus, the second channel region CA2 of the second active layer 222 relatively farther from the gate 230 can be used as a main channel region. However, the embodiments of the present disclosure are not limited thereto. As another example, the thickness d2 of the second active layer 222 can be set to be greater than the thickness d1 of the first active layer 221, as shown in FIG. Figure 5 shown.

[0204] As an example, the carrier mobility of the second active layer 222 may be set to be at least about 10 cm higher than the carrier mobility of the first active layer 221. 2 / V·s. However, the embodiments of the present disclosure are not limited thereto.

[0205] Therefore, instead of the first channel region CA1 of the first active layer 221 closer to the gate 230 than the second active layer 222, the second channel region CA2 of the second active layer 222 relatively far from the gate 230 can be used as the main channel region.

[0206] Therefore, refer to Figure 4 , the main current MC flowing from the second electrode 242 may flow through the second channel region CA2 and the first channel region CA1 in the stacked lower layer, and then may flow toward the first electrode 241 .

[0207] In one example, the first channel region CA1 located in the upper level layer may serve as a protective cover layer that protects the second channel region CA2 located in the lower level layer, and thus, reliability of the thin film transistor may be improved.

[0208] In the process of forming the thin film transistor, the active layer 220 constituting the channel area CA may be damaged in many processes for forming the thin film transistor.

[0209] In this case, a portion of the first channel region CA1 of the first active layer 221 in the upper layer that does not constitute the main channel region covers the upper portion of the second channel region CA2. Therefore, the first channel region CA1 of the first active layer 221 of the upper layer can be used to prevent damage to the second channel region CA2 of the lower layer serving as the main channel region.

[0210] Since damage to the second channel region CA2 serving as the main channel region can be reduced, reliability of the thin film transistor can be improved.

[0211] Further, refer to Figure 5 In the thin film transistor according to the third exemplary embodiment of the present disclosure, the thickness d2 of the second active layer 222 can be greater than the thickness d1 of the first active layer 221. Therefore, the second channel region CA2 in the second active layer 222, which is relatively farther from the gate 230, can function as a main channel region. Thus, a high current characteristic effect of the thin film transistor can be achieved.

[0212] When the thickness d2 of the second active layer 222 is greater than the thickness d1 of the first active layer 221, even if the difference between the carrier mobility of the second active layer 222 and the carrier mobility of the first active layer 221 is not set to be large, the second channel region CA2 of the second active layer 222 disposed below the first channel region CA1 of the first active layer 221 can also serve as the main channel region. However, the embodiments of the present disclosure are not limited to this. As another example, the thickness d2 of the second active layer 222 can be set to be greater than the thickness d1 of the first active layer 221, and the difference between the carrier mobility of the second active layer 222 and the carrier mobility of the first active layer 221 can be set to be large, thereby further achieving the high current characteristic effect of the thin film transistor.

[0213] Since the thickness of the second channel region CA2 of the second active layer 222 increases, a stronger gate field may be applied to the second channel region CA2.

[0214] Therefore, instead of the first channel region CA1 of the first active layer 221 closer to the gate 230 than the second active layer 222, the second channel region CA2 of the second active layer 222 relatively far from the gate 230 can be used as the main channel region, thereby achieving high current characteristics of the thin film transistor.

[0215] Therefore, refer to Figure 5 , the main current MC flowing from the second electrode 242 may flow through the second channel region CA2 of the lower-level layer and the first channel region CA1 of the lower-level layer, and then may flow toward the first electrode 241 .

[0216] Reference Figure 6 , the thin film transistor according to the fourth exemplary embodiment of the present disclosure may include a multi-layer active layer 220 consisting of a stack of three layers.

[0217] The second active layer 222 may include a second lower active layer 222b and a second upper active layer 222t, the second lower active layer 222b being disposed so that a portion thereof is covered by the first active layer 221, and the second upper active layer 222t extending from the second lower active layer 222b to cover at least a portion of the first active layer 221 that covers the second lower active layer 222b. That is, a portion of the first active layer 221 may be disposed between the second lower active layer 222b and the second upper active layer 222t, but is not limited thereto.

[0218] For example, the first active layer 221 and the second active layer 222 may be provided in a lower layer, the first active layer 221 may be provided in an intermediate layer, and the second active layer 222 may be provided in an upper layer. Specifically, a portion of the first active layer 221 and the second lower active layer 222b may be provided in the lower layer, another portion of the first active layer 221 may be provided in an intermediate layer, and the second upper active layer 222t may be provided in the upper layer, but is not limited thereto.

[0219] The lower first active layer 221 and the middle first active layer 221 may be connected to each other along the side of the lower second active layer 222. The lower second active layer 222 and the upper second active layer 222 may be connected to each other along the side of the middle first active layer 221.

[0220] In this case, the second upper active layer 222t and the second lower active layer 222b may be formed to have the same carrier mobility. However, embodiments of the present disclosure are not limited thereto.

[0221] For example, the first active layer 221 may be made of an oxide semiconductor material having low carrier mobility, and the second active layer 222 may be made of an oxide semiconductor material having high carrier mobility.

[0222] In addition, the second upper active layer 222 t and the second lower active layer 222 b may be formed in different processes.

[0223] For example, after forming the second lower active layer 222 b and forming the first active layer 221 , the second upper active layer 222 t may be additionally formed.

[0224] The second upper active layer 222 t may not cover a partial region of the first channel region CA1 of the first active layer 221 , so that the partial region of the first channel region CA1 of the first active layer 221 may be directly exposed to the gate 230 , but is not limited thereto.

[0225] For example, the second upper active layer 222 t may extend as much as possible so that the end portion thereof may not intrude into the first boundary region ΔL1 .

[0226] The active layer 220 is constructed such that the first active layer 221 with low carrier mobility is surrounded by the second active layer 222 with high carrier mobility in a sandwich manner, and the first active layer 221 with low carrier mobility separates the upper and lower portions of the second active layer 222 with high carrier mobility from each other.

[0227] That is, the active layer 220 may be configured such that active layers having different carrier mobility are alternately stacked on each other in a vertical direction.

[0228] Since the second upper active layer 222t is located closest to the gate electrode 230 and has high carrier mobility, the second upper active layer 222t may constitute a main channel region, thereby achieving high current characteristics of the thin film transistor.

[0229] Therefore, refer to Figure 6 , the main current MC flowing from the second electrode 242 can flow through a partial area of the second channel area CA2 of the second lower active layer 222b of the lower layer, and then can flow through the second channel area CA2 of the second upper active layer 222t of the upper layer, and can flow through the first channel area CA1 of the first active layer 221 of the intermediate layer and the lower layer, and then can flow to the first electrode 241.

[0230] The second lower active layer 222 b positioned in the lower level may serve as a carrier support layer that supplements carriers into the second upper active layer 222 t .

[0231] In order to increase the intensity of the current passing through the second channel region CA2 of the second upper active layer 222t, the carrier mobility of the second upper active layer 222t may be further increased or its thickness may be increased. Due to the increase in the thickness of the second upper active layer 222t, a stronger gate field may be applied to the second channel region CA2 of the second upper active layer 222t.

[0232] However, when the carrier mobility of the second upper active layer 222 t excessively increases, the influence of the main channel region adjacent to the gate 230 may become too large.

[0233] Therefore, the threshold voltage of the thin film transistor may vary, and it may be difficult to control the interface between the second upper active layer 222 t constituting the main channel region and the gate insulating layer 160 .

[0234] Therefore, instead of directly increasing the carrier mobility of the second upper active layer 222t, a method of indirectly increasing the carrier mobility of the second upper active layer 222t (for example, by transferring carriers from the second lower active layer 222b to the second upper active layer 222t) can be applied to the thin film transistor according to the present disclosure. That is, the second lower active layer 222b located in the lower layer can play the role of a carrier support layer that replenishes carriers into the second upper active layer 222t.

[0235] For example, a strong gate field acts in a region where the voltage applied to the gate 230 is high. Therefore, the gate field is affected by the second lower active layer 222b of the lower layer. Therefore, as the carriers in the second lower active layer 222b migrate to the second upper active layer 222t, the carriers can be replenished to the second upper active layer 222t.

[0236] As carriers are added to the second upper active layer 222t, the carrier mobility of the second upper active layer 222t is indirectly increased. Therefore, the intensity of the current passing through the second channel region CA2 of the second upper active layer 222t can be increased while maintaining the stability of the threshold voltage of the thin film transistor.

[0237] Thus, a portion of the first active layer 221 between the second upper active layer 222 t and the second lower active layer 222 b may serve as an isolation layer that structurally isolates the second upper active layer 222 t and the second lower active layer 222 b from each other.

[0238] Since the first active layer 221 structurally isolates the second upper active layer 222 t and the second lower active layer 222 b from each other, it is possible to prevent the thickness of the second upper active layer 222 t from being significantly increased directly.

[0239] According to the exemplary embodiment of the present disclosure as described above, the active layer 220 is embodied as a stack of a plurality of layers having different carrier mobilities, thereby allowing a threshold voltage to be more easily controlled in the active layer 220 based on high current characteristics.

[0240] Furthermore, according to the exemplary embodiment of the present disclosure, the large effective channel region of the active layer 220 constituting the main channel can be made of a relatively high carrier mobility material. Therefore, high current can be allowed to flow through the thin film transistor, thereby realizing a display device with high brightness.

[0241] Reference Figure 7 In the thin film transistor according to the fifth exemplary embodiment, the second active layer 222 extends toward the first electrode 241 to cover the top surface of the first active layer 221. Specifically, the second active layer 222 covers a portion of the top surface of the first active layer 221.

[0242] Therefore, the active layer 220 may be formed as a double layer consisting of two layers, ie, a lower layer and an upper layer. For example, the active layer 220 includes a first active layer 221 and a second active layer 222 of a lower layer and a second active layer 222 of an upper layer.

[0243] For example, the first active layer 221 and the second active layer 222 may be provided in the lower layer, and the second active layer 222 may be provided in the upper layer. Specifically, a portion of the second active layer 222 and the first active layer 221 may be provided in the lower layer, and another portion of the second active layer 222 may be provided in the upper layer.

[0244] In this case, the length of the first channel region CA1 of the first active layer 221 disposed in the lower level layer is greater than the length of the second channel region CA2 of the second active layer 222 disposed in the lower level layer.

[0245] However, since the second channel region CA2 of the second active layer 222 disposed in the upper level extends toward the first electrode 241 , the total length of the second active layer 222 may increase.

[0246] The second active layer 222 extends so as not to cover a partial region of the first channel region CA1 of the first active layer 221. Therefore, a partial region of the first channel region CA1 of the first active layer 221 may be directly exposed to the gate 230, but is not limited thereto.

[0247] For example, the second active layer 222 in the upper layer may extend as much as possible so that the end portion thereof does not intrude into the first boundary region ΔL1 .

[0248] Since the second active layer 222 in the upper layer is disposed to cover the top surface of the first active layer 221 , the top surface of the second active layer 222 may be closer to the gate 230 than the top surface of the first active layer 221 .

[0249] Since the second active layer 222 with high carrier mobility is located closer to the gate 230 than the first active layer 221 with low carrier mobility, a strong gate field is applied to the second active layer 222. Therefore, the second channel region CA2 of the second active layer 222 of the upper layer can be used as a main channel region. Therefore, a high current characteristic effect of the thin film transistor can be achieved.

[0250] Therefore, refer to Figure 7 , the main current MC flowing from the second electrode 242 may flow through the second channel region CA2 of the lower layer, then flow through the second channel region CA2 of the upper layer, and then may flow to the first electrode 241 through the first channel region CA1 of the lower layer.

[0251] Reference Figure 8 , the thin film transistor according to the sixth embodiment of the present disclosure may include a multi-layer active layer 220 consisting of a stack of three layers.

[0252] The first active layer 221 is constructed to include a first lower active layer 221b, a partial area of the first lower active layer 221b is covered by the second active layer 222, and a first upper active layer 221t extends from the first lower active layer 221b to cover at least a partial area of the second active layer 222 covering the first lower active layer 221b.

[0253] For example, the first active layer 221 and the second active layer 222 may be provided in a lower-level layer, the second active layer 222 may be provided in an intermediate-level layer, and the first active layer 221 may be provided in an upper-level layer.

[0254] Since the first upper active layer 221 t is disposed to cover the top surface of the second active layer 222 , the top surface of the first upper active layer 221 t may be closer to the gate 230 than the top surface of the second active layer 222 .

[0255] Since the first upper active layer 221t is located closer to the gate 230 than the second active layer 222, a strong gate field is applied to the first active layer 221. Therefore, the first channel region CA1 of the first active layer 221 may serve as a main channel region.

[0256] When the first channel region CA1 of low carrier mobility is used as the main channel region, it may be difficult to achieve the high current characteristic effect of the thin film transistor.

[0257] Therefore, according to an exemplary embodiment of the present disclosure, the difference between the carrier mobility of the second active layer 222 and the carrier mobility of the first active layer 221 can be set to be larger, so that the second channel region CA2 of the second active layer 222 relatively farther from the gate 230 can be used as a main channel region. However, the embodiments of the present disclosure are not limited thereto.

[0258] In this case, the carrier mobility of the second active layer 222 may be set to be higher by about 10 cm⁻¹ than that of the first active layer 221. 2 / V·s. However, the embodiments of the present disclosure are not limited thereto.

[0259] Therefore, instead of the first channel region CA1 of the first upper active layer 221t closer to the gate 230 than the second active layer 222, the second channel region CA2 of the second active layer 222 relatively farther from the gate 230 can be used as the main channel region. Therefore, a high current characteristic effect of the thin film transistor can be achieved.

[0260] Therefore, refer to Figure 8 , the main current MC flowing from the second electrode 242 may flow through the second active layer 222 of the lower level layer, then flow through the first channel area CA1 of the intermediate level layer, then flow through the first active layer 221 of the lower level layer, and then may flow to the first electrode 241 .

[0261] The first channel region CA1 of the first upper active layer 221t in the upper level and the first lower active layer 221b in the lower level may function as protective capping layers for protecting the second channel region CA2 in the middle level, thereby improving reliability of the thin film transistor.

[0262] In the process of forming the thin film transistor, the active layer 220 constituting the channel area CA may be damaged in the process.

[0263] In this case, the first channel region CA1 of the first upper active layer 221t located in the upper layer that does not constitute the main channel region and the first channel region CA1 of the first lower active layer 221b located in the lower layer that does not constitute the main channel region can respectively cover the upper surface and the lower surface of the second channel region CA2, thereby preventing damage to the second channel region CA2 of the intermediate layer that constitutes the main channel region.

[0264] The active layer 220 is constructed such that the high carrier mobility second active layer 222 is surrounded by the low carrier mobility first active layer 221 in a sandwich manner, and the high carrier mobility second active layer 222 separates the upper and lower portions of the low carrier mobility first active layer 221 from each other.

[0265] Since damage to the second channel region CA2 constituting the main channel region is reduced, reliability of the thin film transistor can be improved.

[0266] Further, refer to Figure 9 The thin film transistor according to the seventh embodiment of the present disclosure has Figure 8 The stacked structure also has a structure in which the thickness d2 of the second active layer 222 is greater than the thickness d1 of the first upper active layer 221t.

[0267] Therefore, when the thickness d2 of the second active layer 222 is greater than the thickness d1 of the first active layer 221t, even if the difference between the carrier mobility of the second active layer 222 and the carrier mobility of the first active layer 221t is not set to be large, the second channel region CA2 of the second active layer 222 can also function as a main channel region. However, the embodiments of the present disclosure are not limited to this. As another example, the thickness d2 of the second active layer 222 can be set to be greater than the thickness d1 of the first active layer 221t, and the difference between the carrier mobility of the second active layer 222 and the carrier mobility of the first active layer 221t can be set to be large, thereby further achieving the high current characteristics effect of the thin film transistor.

[0268] Since the thickness of the second channel region CA2 of the second active layer 222 is increased, a stronger gate field can be applied to the second channel region CA2. Therefore, instead of the first channel region CA1 of the first upper active layer 221t closer to the gate 230, the second channel region CA2 of the second active layer 222, which is relatively far from the gate 230, can be used as the main channel region. As a result, a high current characteristic effect of the thin film transistor can be achieved.

[0269] Therefore, refer to Figure 9 , the main current MC flowing from the second electrode 242 may flow through the second channel region CA2 of the upper layer and the first channel region CA1 of the lower layer, and then may flow toward the first electrode 241 .

[0270] A thin film transistor and a display device according to various aspects and embodiments of the present disclosure can be described as follows.

[0271] One aspect of the present disclosure provides a thin film transistor comprising: an active layer; a first electrode connected to one side of the active layer; a second electrode connected to an opposite side of the active layer opposite to the one side of the active layer; and a gate disposed above the active layer, wherein the active layer comprises a first active layer connected to the first electrode and a second active layer connected to the second electrode, wherein the carrier mobility of the first active layer is lower than the carrier mobility of the second active layer.

[0272] According to some embodiments of the thin film transistor, the active layer includes a channel region formed in an area thereof overlapping with the gate in a vertical direction, wherein the first active layer and the second active layer respectively include a first channel region and a second channel region, wherein each of the first channel region and the second channel region is located in the channel region, wherein at least a portion of the first channel region does not overlap with the second channel region in the vertical direction.

[0273] According to some embodiments of the thin film transistor, the first active layer and the second active layer are located in the same layer.

[0274] According to some embodiments of the thin film transistor, a length of the second channel region is greater than a length of the first channel region.

[0275] According to some embodiments of the thin film transistor, the first active layer extends to cover a portion of an upper surface of the second active layer.

[0276] According to some embodiments of the thin film transistor, a top surface of the first active layer covering a portion of an upper surface of the second active layer is closer to the gate than a top surface of the second active layer.

[0277] According to some embodiments of the thin film transistor, a thickness of the second active layer is greater than a thickness of the first active layer.

[0278] According to some embodiments of the thin film transistor, the second active layer includes: a second lower active layer, a portion of the second lower active layer is covered by the first active layer; and a second upper active layer, the second upper active layer extending from the second lower active layer to cover at least a portion of the second lower active layer covering the first active layer.

[0279] According to some embodiments of the thin film transistor, the second lower active layer is used as a carrier supporting layer that replenishes carriers into the second upper active layer.

[0280] According to some embodiments of the thin film transistor, a portion of the first active layer between the second upper active layer and the second lower active layer is used as an isolation layer that structurally isolates the second upper active layer and the second lower active layer from each other.

[0281] According to some embodiments of the thin film transistor, a top surface of the second upper active layer is closer to the gate electrode than a top surface of the first active layer.

[0282] According to some embodiments of the thin film transistor, the second active layer extends to cover an upper surface of the first active layer.

[0283] According to some embodiments of the thin film transistor, a top surface of the second active layer is closer to the gate electrode than a top surface of the first active layer.

[0284] According to some embodiments of the thin film transistor, the first active layer includes: a first lower active layer, a portion of the first lower active layer being covered by the second active layer; and a first upper active layer, the first upper active layer extending from the first lower active layer to cover at least a portion of the first lower active layer covering the second active layer.

[0285] According to some embodiments of the thin film transistor, a top surface of the first upper active layer is closer to the gate electrode than a top surface of the second upper active layer.

[0286] According to some embodiments of the thin film transistor, a thickness of the second active layer is greater than a thickness of the first active layer.

[0287] According to some embodiments of the thin film transistor, the first electrode functions as a drain electrode, and the second electrode functions as a source electrode.

[0288] According to some embodiments of the thin film transistor, the active layer includes an oxide semiconductor material.

[0289] According to some embodiments of the thin film transistor, a light shielding layer is disposed below the active layer, wherein the light shielding layer is electrically connected to the second electrode.

[0290] According to some embodiments of the thin film transistor, the thin film transistor is used as a driving thin film transistor.

[0291] According to some embodiments of the thin film transistor, the carrier mobility of the second active layer is set to be at least 10 cm higher than the carrier mobility of the first active layer. 2 / V·s.

[0292] According to some embodiments of the thin film transistor, the thin film transistor is configured to allow current to flow through the thin film transistor in a unidirectional manner.

[0293] Another aspect of the present disclosure provides a display device comprising: a light-emitting element; and a driving thin film transistor comprising an active layer, a first electrode, a second electrode, and a gate, and configured to drive the light-emitting element, wherein a carrier mobility of a first region of the active layer connected to the first electrode is lower than a carrier mobility of a second region of the active layer connected to the second electrode.

[0294] According to some embodiments of the display device, the first channel region and the second channel region are disposed between the first area and the second area, wherein carrier mobility of the first channel region is lower than carrier mobility of the second channel region.

[0295] According to some embodiments of the display device, the first channel region includes a region overlapping with the gate electrode in a vertical direction and not overlapping with the second channel region in the vertical direction.

[0296] According to some embodiments of the display device, the active layer consists of a single layer.

[0297] According to some embodiments of the display device, the active layer is composed of a stack of a plurality of active layers.

[0298] According to some embodiments of the display device, a plurality of active layers having different carrier mobilities are alternately stacked in at least a portion of a region overlapping the gate.

[0299] According to some embodiments of the display device, the driving thin film transistor is configured to allow current to flow through the driving thin film transistor in a unidirectional manner.

[0300] Another aspect of the present disclosure provides a thin film transistor, comprising: an active layer; a first electrode connected to one side of the active layer; a second electrode connected to an opposite side of the active layer opposite to the one side of the active layer; and a gate arranged above the active layer, wherein the active layer comprises a first active layer connected to the first electrode and a second active layer connected to the second electrode, wherein the thickness of the second active layer is greater than the thickness of the first active layer.

[0301] Although the exemplary embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above-described embodiments, but can be implemented in various different forms. It will be understood by those skilled in the art that the present disclosure can be practiced in other specific forms without changing the technical spirit or basic features of the present disclosure. Therefore, it should be understood that the embodiments described above are not restrictive, but illustrative in all aspects.

Claims

1. A thin film transistor, comprising: active layer; a first electrode connected to one side of the active layer; a second electrode connected to an opposite side of the active layer opposite to the one side of the active layer; as well as a gate, the gate being disposed above the active layer, The active layer includes a first active layer connected to the first electrode and a second active layer connected to the second electrode. The carrier mobility of the first active layer is smaller than the carrier mobility of the second active layer.

2. The thin film transistor according to claim 1, wherein The active layer includes a channel region in a region of the active layer that vertically overlaps with the gate. The first active layer and the second active layer include a first channel region and a second channel region, respectively, wherein each of the first channel region and the second channel region is located in the channel region. Wherein, at least a portion of the first channel region does not overlap with the second channel region in the vertical direction.

3. The thin film transistor according to claim 2, wherein: The first active layer and the second active layer are located in the same layer. The thin film transistor according to claim 3 , wherein: The length of the second channel region is greater than the length of the first channel region.

5. The thin film transistor according to claim 2, wherein The first active layer covers a portion of an upper surface of the second active layer. The thin film transistor according to claim 5 , wherein: A top surface of the portion of the first active layer covering the upper surface of the second active layer is closer to the gate than a top surface of the second active layer.

7. The thin film transistor according to claim 5, wherein The thickness of the second active layer is greater than that of the first active layer.

8. The thin film transistor according to claim 5, wherein The second active layer includes: a second lower active layer, the second lower active layer including a partial region covered by the first active layer; and a second upper active layer extending from the second lower active layer and covering at least a portion of a region of the first active layer covering the second lower active layer.

9. The thin film transistor according to claim 8, wherein The second lower active layer serves as a carrier supporting layer for replenishing the carriers into the second upper active layer.

10. The thin film transistor according to claim 8, wherein A portion of the first active layer located between the second upper active layer and the second lower active layer serves as an isolation layer that structurally isolates the second upper active layer and the second lower active layer from each other.

11. The thin film transistor according to claim 8, wherein A top surface of the second upper active layer is closer to the gate than a top surface of the first upper active layer.

12. The thin film transistor according to claim 2, wherein: The second active layer covers an upper surface of the first active layer.

13. The thin film transistor according to claim 12, wherein: A top surface of the second active layer is closer to the gate than a top surface of the first active layer.

14. The thin film transistor according to claim 12, wherein: The first active layer includes: a first lower active layer, the first lower active layer including a partial region covered by the second active layer; and A first upper active layer extends from the first lower active layer and covers at least a portion of the second active layer covering the first lower active layer.

15. The thin film transistor according to claim 14, wherein A top surface of the first upper active layer is closer to the gate than a top surface of the second upper active layer.

16. The thin film transistor according to claim 14, wherein: The thickness of the second active layer is greater than that of the first active layer.

17. The thin film transistor according to claim 1, wherein The first electrode is a drain electrode, and the second electrode is a source electrode.

18. The thin film transistor according to claim 1, wherein The active layer includes an oxide semiconductor material.

19. The thin film transistor according to claim 1, wherein A light shielding layer is under the active layer and electrically connected to the second electrode.

20. The thin film transistor according to claim 1, wherein The thin film transistor is a driving thin film transistor.

21. The thin film transistor according to claim 1, wherein The carrier mobility of the second active layer is set to be at least 10 cm higher than the carrier mobility of the first active layer. 2 / V·s.

22. The thin film transistor according to claim 1, wherein The thin film transistor is configured to allow current to flow through the thin film transistor in a unidirectional manner.

23. A display device, comprising: Light-emitting element; as well as a driving thin film transistor including an active layer, a first electrode, a second electrode, and a gate electrode and configured to drive the light emitting element, The carrier mobility of a first region of the active layer connected to the first electrode is smaller than the carrier mobility of a second region of the active layer connected to the second electrode.

24. The display device according to claim 23, wherein The first channel region and the second channel region are between the first region and the second region, The carrier mobility of the first channel region is smaller than the carrier mobility of the second channel region.

25. The display device according to claim 24, wherein The first channel region includes a region that overlaps with the gate in a vertical direction and does not overlap with the second channel region in the vertical direction.

26. The display device according to claim 23, wherein The active layer includes a single layer.

27. The display device according to claim 23, wherein The active layer includes a stack of multiple active layers.

28. The display device according to claim 27, wherein: The plurality of active layers having different carrier mobilities in the stack are alternately stacked in at least a portion of a region overlapping the gate.

29. The display device according to claim 23, wherein The driving thin film transistor is configured to allow current to flow through the driving thin film transistor in a unidirectional manner.

30. A thin film transistor, comprising: active layer; a first electrode connected to one side of the active layer; a second electrode connected to an opposite side of the active layer opposite to the one side of the active layer; as well as a gate, the gate being disposed above the active layer, The active layer includes a first active layer connected to the first electrode and a second active layer connected to the second electrode. The thickness of the second active layer is greater than the thickness of the first active layer.

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