Display device

Abstract

A display device is provided. The display device includes: a substrate including a light emitting area and a non-light emitting area; at least one transistor disposed on the substrate and disposed to overlap the light emitting region; a line disposed on the substrate and connected to the at least one transistor; at least one light emitting diode disposed on the at least one transistor and including a first electrode, a light emitting layer, and a second electrode; and an optical member disposed on the at least one light emitting diode and disposed to overlap the non-light emitting region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0023288 filed on February 19, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present specification relates to a display device, and more particularly, to a display device capable of stably performing a repair process while achieving a high aperture ratio. Background Art

[0004] Recently, with the full entry into the information age, display devices that visually display electrical information signals are rapidly developing. Various studies are being continuously conducted to develop various display devices that are thin and lightweight, have low power consumption, and have improved performance.

[0005] As representative display devices, there may be a liquid crystal display device (LCD), a field emission display device (FED), an electrowetting display device (EWD), an organic light emitting display device (OLED), and the like.

[0006] Among display devices, organic light-emitting display devices refer to self-luminous display devices. Unlike liquid crystal display devices, organic light-emitting display devices do not require a separate light source and can therefore be manufactured as lightweight and thin display devices. In addition, organic light-emitting display devices are advantageous in terms of power consumption because electroluminescent display devices operate at low voltages. In addition, because organic light-emitting display devices are also excellent in color realization, response speed, viewing angle, and contrast ratio (CR), organic light-emitting display devices are expected to be adopted in various fields. Summary of the Invention

[0007] An object to be achieved by this specification is to provide a display device capable of repairing defective sub-pixels without losing the aperture ratio.

[0008] Another object to be achieved by the present specification is to provide a display device capable of repairing a defective sub-pixel by cutting lines in repair regions provided at different positions.

[0009] The objects of the present disclosure are not limited to the above-mentioned objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0010] According to aspects of the present disclosure, a display device is provided. The display device includes: a substrate including a light-emitting region and a non-light-emitting region; at least one transistor disposed on the substrate and arranged to overlap with the light-emitting region; a line disposed on the substrate and connected to the at least one transistor; at least one light-emitting diode disposed on the at least one transistor and including a first electrode, a light-emitting layer, and a second electrode; and an optical member disposed on the at least one light-emitting diode and arranged to overlap with the non-light-emitting region.

[0011] Additional details of exemplary embodiments are included in the detailed description and accompanying drawings.

[0012] According to an embodiment of the present disclosure, a defective sub-pixel is repaired by using an optical member disposed under a color filter, which can ensure a maximum aperture ratio of the sub-pixel.

[0013] According to an embodiment of the present specification, a defective sub-pixel may be repaired by cutting lines in the repair region disposed at different positions using a grating member disposed between the optical member and the repair region.

[0014] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 is a block diagram of a display device according to an embodiment of the present specification;

[0017] Figure 2 It shows Figure 1 A circuit diagram of an example of a sub-pixel circuit included in a display device;

[0018] Figure 3 is an enlarged top plan view of a display device according to an embodiment of the present specification;

[0019] Figure 4 is shown along Figure 3 A cross-sectional view of an example cut along line II';

[0020] Figure 5 is shown along Figure 3 A cross-sectional view of an example cut along line II-II';

[0021] Figure 6A and Figure 6B Is used to illustrate Figure 3 A view showing an example of an optical member included in a display device;

[0022] Figure 7 is an enlarged top plan view of a display device according to another embodiment of the present specification;

[0023] Figure 8 is shown along Figure 7 A cross-sectional view of an example cut along line III-III';

[0024] Figure 9A and Figure 9B Is used to illustrate Figure 7 A diagram showing an example of a grating member included in a display device;

[0025] Figure 10 is shown along Figure 7 A cross-sectional view of another example of a cut along line III-III';

[0026] Figure 11 is shown along Figure 7 A cross-sectional view of another example cut along line III-III'; and

[0027] Figure 12 is shown along Figure 7 A cross-sectional view of another example cut along line III-III'. DETAILED DESCRIPTION

[0028] The advantages and features of the present disclosure and methods for achieving these advantages and features will be apparent by reference to the exemplary embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure and scope of the present disclosure.

[0029] The shapes, sizes, ratios, angles, numbers, etc. used to describe the exemplary embodiments of the present disclosure shown in the accompanying drawings are merely examples, and the present disclosure is not limited thereto. Throughout the specification, similar reference numerals generally represent similar elements. In addition, in the following description of the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including," "having," and "consisting of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only." Unless otherwise expressly stated, any reference to the singular may include the plural.

[0030] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0031] When terms such as "on," "above," "below," and "beside" are used to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used together with the terms "immediately" or "directly."

[0032] When an element or layer is referred to as being “on” another element or layer, the other layer or element can be directly on the other element or interposed therebetween.

[0033] Although the terms "first," "second," and the like are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component mentioned below may be the second component in the technical concept of the present disclosure.

[0034] Like reference numerals generally refer to like elements throughout the specification.

[0035] The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the size and thickness of the illustrated components.

[0036] The features of the various embodiments of the present disclosure may be partially or completely dependent on or combined with each other, and may be technically interlocked and operated in various ways, and the embodiments may be performed independently of each other or in association with each other.

[0037] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0038] Figure 1 is a block diagram of a display device according to an embodiment of this specification.

[0039] An electroluminescent display device may be used as the display device according to the embodiment of the present specification. An organic light emitting diode display device, a quantum dot light emitting diode display device, or an inorganic light emitting diode display device may be used as the electroluminescent display device.

[0040] Reference Figure 1 , the display device 100 may include a display panel PN, a gate driver GD, a data driver DD, and a timing controller TD.

[0041] The display panel PN may generate an image to be provided to a user. The display panel PN may include a display area and a non-display area configured to surround the display area.

[0042] The display area of the display panel PN may include a plurality of pixels PX arranged in row and column directions. For example, the plurality of pixels PX may be arranged in an area where a plurality of data lines DL and a plurality of gate lines GL intersect.

[0043] The non-display area of the display panel PN may be provided along the periphery of the display area. Various components for operating the pixel circuits provided in the pixel area PX may be provided in the non-display area. For example, various types of signal lines, pads, at least a portion of the gate driver GD, etc. may be provided in the non-display area. The non-display area may be referred to as a frame area.

[0044] The display panel PN may be implemented as a display panel for various display devices. Hereinafter, a configuration in which the display panel PN is a panel for an organic light-emitting display device will be described. However, the present specification is not limited thereto.

[0045] The data driver DD, the gate driver GD, and the timing controller TD may provide signals for operating the pixels PX through signal lines. For example, the signal lines for providing signals for operating the pixels PX may include a plurality of data lines DL and a plurality of gate lines GL.

[0046] The plurality of data lines DL may include a plurality of lines arranged in a column direction and connected to the pixels PX arranged in one column direction. The plurality of gate lines GL may include a plurality of lines arranged in a row direction and connected to the pixels PX arranged in one row direction.

[0047] In some cases, the display device 100 may further include a power supply unit. In this case, a signal for operating the pixel PX may be provided via a power line connecting the power supply unit and the display panel PN. Depending on the embodiment, the power supply unit may provide power to the data driver DD and the gate driver GD. The data driver DD and the gate driver GD may operate based on the power provided by the power supply unit.

[0048] The timing controller TD can control the data driver DD and the gate driver GD. For example, the timing controller TD can realign digital video data input from the outside to adapt to the resolution of the display panel PN and supply the video data to the data driver DD. In addition, the timing controller TD can generate timing control signals for controlling the data driver DD and the gate driver GD by using control signals input from the outside, and provide the timing control signals to the data driver DD and the gate driver GD.

[0049] The data driver DD may convert digital video data input from the timing controller TD into analog data voltages based on the data control signal and supply the analog data voltages to the plurality of data lines DL.

[0050] The gate driver GD may generate a gate signal based on the gate control signal. For example, the gate driver GD may generate a gate signal for operating at least one gate line connected to each pixel row in a row-sequential manner and supply the gate signal to the gate line.

[0051] According to an embodiment, the gate driver GD may be provided on the display panel PN in a gate-driver-in-panel (GIP) manner. For example, the gate driver GD may be divided into a plurality of gate drivers and respectively provided on at least two side surfaces of the display panel PN. However, the present invention is not limited thereto.

[0052] Each of the plurality of pixels PX included in the display panel PN may include a plurality of sub-pixels SP. The plurality of sub-pixels SP included in one pixel PX may emit light beams having different colors. For example, the plurality of sub-pixels SP included in one pixel PX may include a first sub-pixel configured to emit red light, a second sub-pixel configured to emit white light, a third sub-pixel configured to emit blue light, and a fourth sub-pixel configured to emit green light. However, the present invention is not limited thereto. The plurality of sub-pixels SP may constitute a pixel PX.

[0053] Meanwhile, in this specification, the first subpixel may be referred to as a red subpixel, the second subpixel may be referred to as a white subpixel, the third subpixel may be referred to as a blue subpixel, and the fourth subpixel may be referred to as a green subpixel.

[0054] In the following, reference will be made to Figure 2 A sub-pixel circuit for operating one pixel SP is described in more detail.

[0055] Figure 2 It shows Figure 1 A circuit diagram of an example of a sub-pixel circuit included in a display device.

[0056] at the same time, Figure 2 The sub-pixel circuit SPC shown is the same as the reference Figure 1 The display device 100 includes a plurality of sub-pixels SP including a corresponding sub-pixel circuit.

[0057] Reference Figure 2 The sub-pixel circuit SPC may include a driving transistor DT, a switching transistor SWT, a sensing transistor SET, a storage capacitor SC, and a light emitting diode ED.

[0058] The light emitting diode ED may include a first electrode, a light emitting layer, and a second electrode. For example, the first electrode of the light emitting diode ED is an anode electrode and may be connected to a second node N2 corresponding to the second electrode of the driving transistor DT. For example, the second electrode of the light emitting diode ED is a cathode electrode and may be connected to a low potential power line VSSL configured to supply a low potential power voltage VSS. For example, the light emitting layer of the light emitting diode ED is an organic layer and may include various organic layers, such as a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, and an electron injection layer. At the same time, Figure 2 The light emitting diode ED is shown to be an organic light emitting diode. However, the present invention is not limited thereto. An inorganic light emitting diode may also be used as the light emitting diode ED.

[0059] The driving transistor DT can supply a driving current from a high-potential power line VDDL configured to supply a high-potential power voltage VDD, so that the driving current passes through the light-emitting diode ED and flows to a low-potential power line VSSL configured to supply a low-potential power voltage VSS. The light-emitting diode ED can emit light based on the driving current supplied from the driving transistor DT.

[0060] The driving transistor DT may include a gate electrode connected between the second node N2 and the third node N3 and connected to the first node N1. For example, the driving transistor DT may include a first electrode connected to the third node N3 and a second electrode connected to the second node N2.

[0061] The switching transistor SWT may supply the data voltage DATA supplied from the data line DL to a first node N1 corresponding to the gate electrode of the driving transistor DT.

[0062] The switching transistor SWT may include a gate electrode connected between the data line DL and the first node N1 and connected to the gate line GL. For example, the switching transistor SWT may include a first electrode connected to the data line DL and a second electrode connected to the first node N1. The switching transistor SWT may be turned on or off by a scan signal SCAN supplied via the gate line GL. Therefore, the switching transistor SWT may be turned on when the scan signal SCAN having a turn-on level is supplied to the gate line GL, and the switching transistor SWT may transmit the data voltage DATA supplied via the data line DL to the first node N1 corresponding to the gate electrode of the driving transistor DT.

[0063] The storage capacitor SC can maintain a voltage corresponding to the data voltage DATA for one frame. The storage capacitor SC can be connected between a first node N1 and a second node N2, where the first node N1 corresponds to the gate electrode of the drive transistor DT and the second node N2 corresponds to the second electrode of the drive transistor DT. For example, one electrode of the storage capacitor SC can be connected to the first node N1. The other electrode of the storage capacitor SC can be connected to the second node N2.

[0064] Meanwhile, in the case of the display device 100, circuit elements such as the drive transistor DT may degrade as the operating time of each sub-pixel SP increases. Therefore, the inherent characteristic values of the circuit elements such as the drive transistor DT may change. In this case, the inherent characteristic values of the circuit elements may include the threshold voltage Vth of the drive transistor DT, the mobility α of the drive transistor DT, etc. The change in the characteristic value of the circuit element may cause the luminance of the corresponding sub-pixel SP to change. Therefore, the change in the characteristic value of the circuit element can be used in the same way as the change in the luminance of the sub-pixel SP.

[0065] Furthermore, the degree of variation in characteristic values between the circuit elements of each sub-pixel SP may vary depending on the difference in the degree of degradation between the circuit elements. The difference in the degree of variation in characteristic values between the circuit elements may result in luminance deviation between the sub-pixels SP. Therefore, the deviation in characteristic values between the circuit elements may be used as the same concept as the luminance deviation between the sub-pixels SP. The variation in characteristic values of the circuit elements (i.e., the luminance variation of the sub-pixels SP and the deviation between characteristic values between the circuit elements) (i.e., luminance deviation between the sub-pixels SP) may result in problems such as degradation in the accuracy of the luminance representation of the sub-pixels SP or image anomalies.

[0066] Therefore, the subpixel SP of the display device 100 according to the embodiment of this specification may be provided with a sensing function of sensing a characteristic value of the subpixel SP and a compensation function of compensating the characteristic value of the subpixel SP by using the sensing result.

[0067] Therefore, like the switching transistor SWT, the driving transistor DT, the storage capacitor SC, and the light emitting diode ED, the sub-pixel SP may further include a sensing transistor SET for effectively controlling a voltage state of the second electrode of the driving transistor DT.

[0068] Reference Figure 2The sensing transistor SET may include a gate electrode connected between the second electrode N2 and a reference voltage line RL configured to supply a reference voltage Vref, and the gate electrode is connected to a gate line GL configured to supply a sensing signal SENSE. For example, the sensing transistor SET may include a first electrode connected to the reference voltage line RL via a reference voltage connection line 140, and a second electrode connected to a second node N2 corresponding to the second electrode of the driving transistor DT. The sensing transistor SET can be turned on or off by the sensing signal SENSE supplied via the gate line GL. Therefore, the sensing transistor SET can be turned on when the sensing signal SENSE having an on level is supplied to the gate line GL, and the sensing transistor SET can transmit the reference voltage Vref supplied via the reference voltage line RL to the second node N2 corresponding to the second electrode of the driving transistor DT.

[0069] In addition, the sensing transistor SET may be used as one of voltage sensing paths of the second electrode of the driving transistor DT.

[0070] Reference Figure 2 , the switching transistor SWT and the sensing transistor SET of the sub-pixel SP can share a single gate line GL. That is, the switching transistor SWT and the sensing transistor SET can be connected to the same gate line GL and receive the same gate signal. However, for ease of description, the voltage applied to the gate electrode of the switching transistor SWT is referred to as the scanning signal SCAN, and the voltage applied to the gate electrode of the sensing transistor SET is referred to as the sensing signal SENSE. However, the scanning signal SCAN and the sensing signal SENSE applied to a single sub-pixel SP can be the same signal transmitted from the same gate line GL. For example, the scanning signal SCAN and the sensing signal SENSE applied to one sub-pixel SP can be referred to as gate signals.

[0071] However, the present specification is not limited thereto. Only the switching transistor SWT may be connected to the gate line GL configured to supply the scan signal SCAN, and the sensing transistor SET may be connected to a separate sensing line configured to supply the sensing signal SENSE.

[0072] Therefore, the reference voltage Vref can be applied to the second electrode of the drive transistor DT via the sensing transistor SET. Furthermore, a voltage for sensing the threshold voltage Vth of the drive transistor DT or the mobility α of the drive transistor DT can be detected via the reference voltage line RL. Furthermore, the data driver DD can compensate the data voltage DATA based on a detected change in the threshold voltage Vth of the drive transistor DT or a detected change in the mobility α of the drive transistor DT.

[0073] According to the embodiment, Figure 2The plurality of transistors DT, SWT, and SET may include at least one of an oxide semiconductor such as amorphous silicon, polycrystalline silicon, and IGZO. The first electrode or the second electrode of the transistor may be a source electrode or a drain electrode. For example, the first electrode may be a source electrode, or the second electrode may be a drain electrode. As another example, the first electrode may be a drain electrode, and the second electrode may be a source electrode.

[0074] Meanwhile, in the display device 100 according to an embodiment of the present specification, if some of the plurality of sub-pixels SP are defective, the reference voltage connection line 140 provided in the repair area LCA can be cut using a laser. When the reference voltage connection line 140 of the defective sub-pixel SP is cut as described above, the sensing transistor SET is electrically separated from the reference voltage line RL configured to provide the reference voltage Vref, so that the reference voltage Vref supplied by the reference voltage line RL is not supplied to the sensing transistor SET. Therefore, since the driving transistor DT cannot be supplied with the reference voltage Vref from the sensing transistor SET, the driving transistor DT does not operate, and thus, the light-emitting diode ED does not emit light. In other words, the sub-pixel SP including the defective circuit element may become a dark spot through the repair process.

[0075] However, the repair area LCA subjected to laser cutting is not limited thereto. The repair area LCA can be provided in various configurations. For example, the repair area LCA can be provided on various lines, such as a data line DL configured to supply a data voltage DATA or a connection line configured to connect a drive transistor DT and a light-emitting diode ED. In such cases, when the corresponding line is laser cut, the drive transistor DT does not operate and / or the light-emitting diode ED does not emit light. Below, for ease of explanation, a configuration in which the repair area LCA is provided on the reference voltage connection line 140 will be described.

[0076] Figure 3 It is an enlarged top plan view of a display device according to an embodiment of this specification. Figure 4 is shown along Figure 3 A cross-sectional view of the example cut along line II'. Figure 5 is shown along Figure 3 A cross-sectional view of the example cut along line II-II'.

[0077] Meanwhile, for ease of explanation, hereinafter, the first direction X is illustrated as a horizontal direction in a plan view, and the second direction Y is illustrated as a vertical direction in a plan view. In addition, a normal direction of a plane defined by the first direction X and the second direction Y (e.g., a thickness direction of the display device 100) may be defined as a third direction Z.

[0078] at the same time, Figure 4 and Figure 5 An example of a cross-sectional structure of the display device 100 according to an embodiment of this specification is shown.

[0079] Reference Figure 3 The display device 100 according to the embodiment of this specification may include a plurality of sub-pixels SP disposed in one pixel area PXA, and each sub-pixel includes a corresponding sub-pixel circuit SPC.

[0080] The plurality of sub-pixels SP may include: a first sub-pixel SP1, which is configured to emit red light and includes a first sub-pixel circuit SPC1; a second sub-pixel SP2, which is configured to emit white light and includes a second sub-pixel circuit SPC2; a third sub-pixel SP3, which is configured to emit blue light and includes a third sub-pixel circuit SPC3; and a fourth sub-pixel SP4, which is configured to emit green light and includes a fourth sub-pixel circuit SPC4.

[0081] The plurality of sub-pixels SP disposed in one pixel area PXA may be sequentially arranged in the first direction X. For example, the second sub-pixel SP2 may be disposed on one side of the first sub-pixel SP1 based on the first direction X, the third sub-pixel SP3 may be disposed on one side of the second sub-pixel SP2 based on the first direction X, and the fourth sub-pixel SP4 may be disposed on one side of the third sub-pixel SP3 based on the first direction X. However, the present specification is not limited thereto. The arrangement of the sub-pixels SP may be modified and implemented in various ways.

[0082] For example, the first subpixel SP1 may include a first emission area EA1, the second subpixel SP2 may include a second emission area EA2, the third subpixel SP3 may include a third emission area EA3, and the fourth subpixel SP4 may include a fourth emission area EA4.

[0083] Each of the plurality of sub-pixels SP includes an emission area EA that can independently emit light of a single color. A light-emitting diode ED corresponding to the corresponding sub-pixel SP can be provided in the emission area EA. For example, red light can be emitted from the first emission area EA1, white light can be emitted from the second emission area EA2, blue light can be emitted from the third emission area EA3, and green light can be emitted from the fourth emission area EA4.

[0084] The sub-pixel circuits SPC respectively included in the plurality of sub-pixels SP may have substantially the same or similar structures, and the plurality of sub-pixels SP disposed in one pixel area PXA may share at least one signal line. Figure 3As shown, the first subpixel SP1 , the second subpixel SP2 , the third subpixel SP3 , and the fourth subpixel SP4 disposed in one pixel area PXA may share one reference voltage line RL.

[0085] At the same time, although Figure 3 Although not shown, at least some of the plurality of sub-pixels SP disposed in one pixel area PXA may share a high potential power line VDDL supplied with the high potential voltage VDD and extending in the second direction Y. However, the present specification is not limited thereto.

[0086] A reference voltage line RL configured to supply a reference voltage Vref may be provided between the plurality of sub-pixels SP. For example, the reference voltage line RL may be provided between the second sub-pixel SP2 and the third sub-pixel SP3 and extend in the second direction Y.

[0087] In addition, a connection line 130 may be connected to the reference voltage line RL, the connection line 130 being disposed to pass through the corresponding pixel area PXA in the first direction X. For example, the connection line 130 may extend in the first direction X to pass through the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, and the fourth subpixel SP4, and a central portion of the connection line 130 may be connected to the reference voltage line RL through the first contact hole CH1.

[0088] In addition, a reference voltage connection line 140 disposed between the plurality of sub-pixels SP may be connected to the connection line 130. For example, the reference voltage connection line 140 may include a first reference voltage connection line 141 disposed between the first sub-pixel SP1 and the second sub-pixel SP2, and a second reference voltage connection line 142 disposed between the third sub-pixel SP3 and the fourth sub-pixel SP4.

[0089] The first reference voltage connection line 141 may include a first main portion extending in the second direction Y, and the first main portion of the first reference voltage connection line 141 and the connection line 130 may be connected via a second contact hole CH2 in the center portion of the first main portion of the first reference voltage connection line 141. Furthermore, the first reference voltage connection line 141 may include a first auxiliary portion extending from one end of the first main portion in a direction opposite to the first direction X and connected to the first sub-pixel circuit SPC1; and a second auxiliary portion extending from the other end of the first main portion in the first direction X and connected to the second sub-pixel circuit SPC2. Therefore, the reference voltage Vref may be supplied to the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 via the first reference voltage connection line 141 connected to the reference voltage line RL via the connection line 130.

[0090] Furthermore, the second reference voltage connection line 142 may include a second main portion extending in the second direction Y, and the second main portion of the second reference voltage connection line 142 and the connection line 130 may be connected via a third contact hole CH3 in the center portion of the second main portion of the second reference voltage connection line 142. Furthermore, the second reference voltage connection line 142 may include a third auxiliary portion extending from one end of the second main portion in a direction opposite to the first direction X and connected to the third sub-pixel circuit SPC3; and a fourth auxiliary portion extending from the other end of the second main portion in the first direction X and connected to the fourth sub-pixel circuit SPC4. Therefore, the reference voltage Vref can be supplied to the third and fourth sub-pixel circuits SPC3 and SPC4 via the second reference voltage connection line 142 connected to the reference voltage line RL via the connection line 130.

[0091] At the same time, although Figure 3 Although not shown in the figure, a corresponding data line DL can be connected to each of the plurality of sub-pixel circuits SPC. For example, a data line DL extending in the second direction Y and configured to provide a data voltage DATA for red light can be connected to a first sub-pixel circuit SPC1. A data line DL extending in the second direction Y and configured to provide a data voltage DATA for white light can be connected to a second sub-pixel circuit SPC2. A data line DL extending in the second direction Y and configured to provide a data voltage DATA for blue light can be connected to a third sub-pixel circuit SPC3. A data line DL extending in the second direction Y and configured to provide a data voltage DATA for green light can be connected to a fourth sub-pixel circuit SPC4.

[0092] In addition, although Figure 3 Although not shown, a corresponding gate line GL may be connected to each of the plurality of sub-pixel circuits SPC. For example, a gate line GL extending in the first direction X and configured to provide a scan signal SCAN and / or a sense signal SENSE may be connected to each of the plurality of sub-pixel circuits SPC. Sub-pixels SPC arranged in the same pixel row are connected to the same gate line GL, so that a plurality of sub-pixel circuits SPC arranged in one pixel area PXA may be connected to the same gate line GL.

[0093] At the same time, as reference Figure 2 As described above, the plurality of repair areas LCA may be provided on the reference voltage connection line 140 of each sub-pixel circuit in the sub-pixel circuit SPC. The plurality of repair areas LCA may be arranged so as not to overlap with the emission area EA of each sub-pixel in the plurality of sub-pixels SP. For example, the plurality of repair areas LCA may overlap with the non-emission areas of the plurality of sub-pixels SP.

[0094] A plurality of optical members 170 may be provided in the plurality of repair areas LCA.

[0095] For example, the plurality of repair areas LCA may include: a first repair area LCA1 in the first main portion of the first reference voltage connection line 141, which is adjacent to the first auxiliary portion connected to the first sub-pixel circuit SPC1; and a second repair area LCA2 in the first main portion of the first reference voltage connection line 141, which is adjacent to the second auxiliary portion connected to the second sub-pixel circuit SPC2. The first optical member 171 may be disposed to overlap the first repair area LCA1, and the second optical member 172 may be disposed to overlap the second repair area LCA2.

[0096] In addition, the plurality of repair areas LCA may further include: a third repair area LCA3 in the second main portion of the second reference voltage connection line 142, adjacent to the third auxiliary portion connected to the third sub-pixel circuit SPC3; and a fourth repair area LCA4 in the second main portion of the second reference voltage connection line 142, adjacent to the fourth auxiliary portion connected to the fourth sub-pixel circuit SPC4. The third optical member 173 may be disposed to overlap the third repair area LCA3, and the fourth optical member 174 may be disposed to overlap the fourth repair area LCA4.

[0097] Each of the plurality of optical members 170 may focus the laser light and provide the laser light to the reference voltage connection line 140 disposed in the corresponding repair area LCA. Thus, the reference voltage connection line 140 disposed in the corresponding repair area LCA may be cut.

[0098] Will refer to Figure 4 The arrangement of components included in the plurality of sub-pixels SP included in the display device 100 is described in more detail. The display device 100 may include a first substrate 111, a buffer layer BF, a gate insulating layer GI, an interlayer insulating layer ILD, a passivation layer PAS, a reference voltage line RL, a driving transistor DT, a sensing transistor SET, a reference voltage connection line 140, a light blocking layer LS, a data line DL, an overcoat layer OC, a light emitting diode ED, a bank 150, an encapsulation member 160, at least one color filter CF1 or CF2, an optical member 170, and a second substrate 112.

[0099] The first substrate 111 and the second substrate 112 may each include an insulating material. The first substrate 111 and the second substrate 112 may each include a transparent material. For example, the first substrate 111 and the second substrate 112 may each include glass or plastic.

[0100] The first substrate 111 may be disposed below the display device 100 and support components of the display device 100. The second substrate 112 may be disposed above the display device 100 and protect components of the display device 100. For example, the first substrate 111 and the second substrate 112 may be disposed facing each other, the first substrate 111 may be a lower substrate, and the second substrate 112 may be an upper substrate. However, the present specification is not limited thereto.

[0101] A light blocking layer LS may be provided on the first substrate 111. The light blocking layer LS may be provided to overlap the driving transistor DT (e.g., the first semiconductor layer ACT1 of the driving transistor DT). The light blocking layer LS may serve to block external light from entering the first semiconductor layer ACT1 in the region where the driving transistor DT is formed.

[0102] The light blocking layer LS may be configured as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof. However, the present invention is not limited thereto.

[0103] The reference voltage connection line 140 and the reference voltage line RL may be provided on the first substrate 111. The reference voltage connection line 140 and the reference voltage line RL may be provided on the same layer as the light blocking layer LS. For example, the reference voltage connection line 140 and the reference voltage line RL may be formed simultaneously through the same process and include the same material as the light blocking layer LS. However, the present invention is not limited thereto.

[0104] The buffer layer BF may be disposed on the first substrate 111. For example, the buffer layer BF may be disposed on the first substrate 111 and cover the light blocking layer LS, the reference voltage link line 140, and the reference voltage line RL.

[0105] The buffer layer BF can protect the transistor from moisture penetrating into the first substrate 111, which is susceptible to moisture penetration. The buffer layer BF may include an insulating material. For example, the buffer layer BF may be made of an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx), or may be configured as a multilayer made of silicon oxide (SiOx) and silicon nitride (SiNx).

[0106] Semiconductor layers of transistors may be disposed on the buffer layer BF. For example, a first semiconductor layer ACT1 of the drive transistor DT and a second semiconductor layer ACT2 of the sense transistor SET may be disposed on the buffer layer BF. The first semiconductor layer ACT1 and the second semiconductor layer ACT2 may each be made of a silicon-based semiconductor material or an oxide-based semiconductor material. However, the present disclosure is not limited thereto.

[0107] A gate insulating layer GI may be provided on the buffer layer BF. For example, the gate insulating layer GI may be provided on the buffer layer BF and cover the first semiconductor layer ACT1 and the second semiconductor layer ACT2. The gate insulating layer GI may insulate the semiconductor layers and gate electrodes of the transistors. For example, the gate insulating layer GI may insulate the first semiconductor layer ACT1 and the first gate electrode GE1 of the drive transistor DT, and insulate the second semiconductor layer ACT2 and the second gate electrode GE2 of the sensing transistor SET.

[0108] The gate insulating layer GI may include an insulating material. For example, the gate insulating layer GI may be made of an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx), or may be configured as a multilayer made of silicon oxide (SiOx) and silicon nitride (SiNx). The gate insulating layer GI may include a material having a high dielectric constant. For example, the gate insulating layer GI may include a high-k material such as hafnium oxide (HfO).

[0109] The gate electrodes of the transistors may be disposed on the gate insulating layer GI. For example, the first gate electrode GE1 of the driving transistor DT and the second gate electrode GE2 of the sensing transistor SET may be disposed on the gate insulating layer GI.

[0110] The gate electrode of each of the transistors may be arranged to overlap with the channel region of the semiconductor layer of the corresponding transistor. For example, the first gate electrode GE1 of the drive transistor DT may overlap with the channel region of the first semiconductor layer ACT1, and the second gate electrode GE2 of the sense transistor SET may overlap with the channel region of the second semiconductor layer ACT2.

[0111] The first gate electrode GE1 and the second gate electrode GE2 may each be configured as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, the present specification is not limited thereto.

[0112] At the same time, despite Figure 4 Although not shown in the figure, according to an embodiment, the gate line GL connected to each of the plurality of sub-pixels SP may be provided on the same layer as the gate electrode of the transistor (e.g., the first gate electrode GE1 and the second gate electrode GE2). For example, the gate line GL may be formed simultaneously through the same process and include the same material as the first gate electrode GE1 and the second gate electrode GE2. However, the present specification is not limited thereto.

[0113] Reference Figure 5, a connection line 130 may be further provided on the gate insulating layer GI. The connection line 130 may be provided on the same layer as the gate electrodes of the transistor (e.g., the first gate electrode GE1 and the second gate electrode GE2). For example, the connection line 130 may be formed simultaneously through the same process and include the same material as the first gate electrode GE1 and the second gate electrode GE2. However, the present specification is not limited thereto.

[0114] One end of the connection line 130 may contact the reference voltage connection line 140 via a second contact hole CH2 formed through the gate insulating layer GI and the buffer layer BF. The other end of the connection line 130 may contact the reference voltage line RL via a first contact hole CH1 formed through the gate insulating layer GI and the buffer layer BF. Therefore, the reference voltage connection line 140 may be supplied with the reference voltage Vref from the reference voltage line RL via the connection line 130.

[0115] Return to reference Figure 4 The interlayer insulating layer ILD may be disposed on the gate insulating layer GI. For example, the interlayer insulating layer ILD may be disposed on the gate insulating layer GI and cover the first gate electrode GE1, the second gate electrode GE2, and the connection line 130. The interlayer insulating layer ILD may insulate the gate, source, and drain electrodes of the transistors. For example, the interlayer insulating layer ILD may insulate the first gate electrode GE1 of the drive transistor DT from the first source electrode SE1 and the first drain electrode DE1, and insulate the second gate electrode GE2 of the sensing transistor SET from the second source electrode SE2 and the second drain electrode DE2.

[0116] The interlayer insulating layer ILD may include an insulating material. For example, the interlayer insulating layer ILD may be made of an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx), or may be configured as a multilayer made of silicon oxide (SiOx) and silicon nitride (SiNx).

[0117] The source and drain electrodes of the transistors may be disposed on the interlayer insulating layer ILD. For example, the first source electrode SE1 and the first drain electrode DE1 of the driving transistor DT and the second source electrode SE2 and the second drain electrode DE2 of the sensing transistor SET may be disposed on the interlayer insulating layer ILD.

[0118] The source and drain electrodes of the transistors can contact the gate electrodes of the corresponding transistors through contact holes formed through the interlayer insulating layer ILD and the gate insulating layer GI. For example, the first source electrode SE1 and the first drain electrode DE1 of the drive transistor DT can be connected to the first semiconductor layer ACT1 through the fourth contact hole CH4 and the fifth contact hole CH5 formed through the interlayer insulating layer ILD and the gate insulating layer GI. The second source electrode SE2 and the second drain electrode DE2 of the sensing transistor SET can be connected to the second semiconductor layer ACT2 through the sixth contact hole CH6 and the seventh contact hole CH7 formed through the interlayer insulating layer ILD and the gate insulating layer GI.

[0119] The first source electrode SE1, the second source electrode SE2, the first drain electrode DE1, and the second drain electrode DE2 can each be configured as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0120] The data line DL may be disposed on the interlayer insulating layer ILD. For example, the data line DL may be disposed on the same layer as the first source electrode SE1, the second source electrode SE2, the first drain electrode DE1, and the second drain electrode DE2. For example, the data line DL may be formed simultaneously through the same process and include the same material as the first source electrode SE1, the second source electrode SE2, the first drain electrode DE1, and the second drain electrode DE2. However, the present invention is not limited thereto.

[0121] At the same time, despite Figure 4 Although not shown, according to an embodiment, the high-potential power line VDDL and the low-potential power line VSSL connected to each of the plurality of sub-pixels SP may be provided on the same layer as the source and drain electrodes of the transistor (e.g., the first source electrode SE1, the second source electrode SE2, the first drain electrode DE1, and the second drain electrode DE2). For example, the high-potential power line VDDL and the low-potential power line VSSL may be formed simultaneously through the same process and include the same material as the first source electrode SE1, the second source electrode SE2, the first drain electrode DE1, and the second drain electrode DE2. However, the present specification is not limited thereto.

[0122] The passivation layer PAS may be disposed on the interlayer insulating layer ILD. For example, the passivation layer PAS may be disposed on the interlayer insulating layer ILD and cover the first source electrode SE1, the second source electrode SE2, the first drain electrode DE1, the second drain electrode DE2, and the data line DL.

[0123] The passivation layer PAS may suppress damage to the transistor caused by external moisture and impact. For example, the passivation layer PAS may extend along the surface of the transistor (eg, the surface of the driving transistor DT and the surface of the sensing transistor SET).

[0124] The passivation layer PAS may include an insulating material. For example, the passivation layer PAS may be made of an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx), or may be configured as a multilayer made of silicon oxide (SiOx) and silicon nitride (SiNx).

[0125] The overcoat layer OC may be disposed on the passivation layer PAS. The overcoat layer OC may include an insulating material. The overcoat layer OC may include a material different from that of the passivation layer PAS. For example, the overcoat layer OC may include an organic insulating material. For example, the overcoat layer OC may include an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin.

[0126] The overcoat layer OC can remove the level difference caused by the transistors (eg, the driving transistor DT and the sensing transistor SET), for example, flatten the transistors (eg, the driving transistor DT and the sensing transistor SET). For example, the top surface of the overcoat layer OC opposite to the first substrate 111 can be a flat surface.

[0127] The light emitting diode ED may be disposed on the overcoat layer OC. For example, the light emitting diode ED may include a first electrode AND, a light emitting layer EML, and a second electrode CAT disposed on the overcoat layer OC.

[0128] The first electrode AND may be disposed on the overcoat layer OC. The first electrode AND may be connected to the first source electrode SE1 or the first drain electrode DE1 of the driving transistor DT through a ninth contact hole CH9 formed through the overcoat layer OC and the passivation layer PAS. Thus, the first electrode AND of the light emitting diode ED may be electrically connected to the driving transistor DT.

[0129] The first electrode AND may include a conductive material. For example, the first electrode AND may include a material having a high reflectivity. For example, the first electrode AND may include a metal, such as aluminum (Al) and silver (Ag). The first electrode AND may have a multilayer structure. For example, the first electrode AND may have a structure in which a reflective electrode made of a metal is positioned between transparent electrodes made of a transparent conductive material such as ITO and IZO. The first electrode AND may be an anode electrode of a light-emitting diode ED.

[0130] The bank 150 may be provided on the overcoat layer OC. The bank 150 may be formed to cover the edge of each of the first electrodes AND included in the plurality of sub-pixels SP and to expose a portion of each of the first electrodes AND. Therefore, the bank 150 can suppress the problem of current accumulation at the ends of the first electrodes AND and deterioration of luminous efficiency.

[0131] The bank 150 may be disposed between the first electrodes AND included in the plurality of sub-pixels SP and expose at least a portion of the first electrodes AND, thereby defining the emission areas EA of the sub-pixels SP. For example, the emission areas EA of each of the plurality of sub-pixels SP (e.g., the first emission area EA1, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4) may each define a region in which the first electrode AND, the emission layer EML, and the second electrode CAT are sequentially stacked, and positive holes from the first electrode AND and electrons from the second electrode CAT are coupled to each other in the emission layer EML to emit light. In this case, since the region in which the bank 150 is formed does not emit light, the region may be defined as a non-emission area NEA. The region in which the bank 150 is not formed and the first electrode AND is exposed may be defined as the emission area EA.

[0132] In addition, the bank 150 may be provided between the first electrodes AND included in the plurality of sub-pixels SP and insulate the first electrodes AND provided in the sub-pixels SP.

[0133] The bank 150 may be configured as an organic film made of acrylic resin, epoxy resin, phenol resin, polyamide resin, and polyimide resin. However, the present specification is not limited thereto.

[0134] The light emitting layer EML may be disposed on the first electrode AND. For example, the light emitting layer EML may be disposed on the bank 150 and the first electrode AND exposed by the bank 150.

[0135] The light emitting layer EML may generate light having a brightness corresponding to the voltage difference between the first electrode AND and the second electrode CAT. For example, the light emitting layer EML may include a light emitting material layer (EML) including a light emitting material. The light emitting material may include an organic material, an inorganic material, or a mixed material.

[0136] The emission layer EML may have a multi-layer structure. For example, the emission layer EML may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0137] According to an embodiment, a light-emitting layer EML may be formed for each of the plurality of sub-pixels SP. For example, a red light-emitting layer configured to emit red light may be formed in the first sub-pixel SP1, a white light-emitting layer configured to emit white light may be formed in the second sub-pixel SP2, a blue light-emitting layer configured to emit blue light may be formed in the third sub-pixel SP3, and a green light-emitting layer configured to emit green light may be formed in the fourth sub-pixel SP4.

[0138] However, this is provided for illustrative purposes only, and the present specification is not limited thereto. The light emitting layer EML may be a common layer commonly formed in a plurality of sub-pixels SP. In this case, the light emitting layer EML may be a white light emitting layer configured to emit white light.

[0139] The second electrode CAT may be disposed on the emission layer EML and the bank 150. The second electrode CAT may be disposed not only in the emission area EA but also in the non-emission area NEA. However, the present specification is not limited thereto.

[0140] The second electrode CAT may include a conductive material. The second electrode CAT may include a material different from that of the first electrode AND. The transmittance of the second electrode CAT may be higher than the transmittance of the first electrode AND. For example, the second electrode CAT may be configured as a transparent electrode made of a transparent conductive material such as ITO and IZO. Therefore, in the display device 100 according to the embodiment of this specification, light generated by the light-emitting layer EML can be emitted through the second electrode CAT.

[0141] The second electrodes CAT included in the plurality of sub-pixels SP may be electrically connected to each other. For example, the second electrode CAT may be a common layer commonly formed in the plurality of sub-pixels SP and supplied with the same voltage. The second electrode CAT may be a cathode electrode of the light emitting diode ED.

[0142] The encapsulation member 160 may be disposed on the light-emitting diode ED. The encapsulation member 160 may be formed to cover the second electrode CAT. The encapsulation member 160 may suppress damage to the light-emitting diode ED caused by external moisture and impact. The encapsulation member 160 may have a multilayer structure. For example, the encapsulation member 160 may include at least one inorganic film and at least one organic film.

[0143] The color filter CF may be provided on the encapsulation member 160. The color filter CF may be provided on one surface (e.g., the bottom surface of the second substrate 112 facing the first substrate 111). In this case, the first substrate 111 having the encapsulation member 160 and the second substrate 112 having the color filter CF may be bonded by a separate bonding layer (not shown). In this case, the bonding layer (not shown) may be an optically clear resin layer (OCR) or an optically clear adhesive film (OCA). However, the present specification is not limited thereto.

[0144] The color filter CF can be patterned for each of the multiple sub-pixels SP. For example, the color filter CF may include: a first color filter CF1, which is arranged to correspond to the first emission area EA1 of the first sub-pixel SP1; a second color filter CF2, which is arranged to correspond to the second emission area EA2 of the second sub-pixel SP2; a third color filter, which is arranged to correspond to the third emission area EA3 of the third sub-pixel SP3; and a fourth color filter, which is arranged to correspond to the fourth emission area EA4 of the fourth sub-pixel SP4. For example, the first color filter CF1 may be a red color filter configured to transmit red light, the second color filter CF2 may be a white color filter configured to transmit white light, the third color filter may be a blue color filter configured to transmit blue light, and the fourth color filter may be a green color filter configured to transmit green light. At the same time, the second color filter CF2, which is a white color filter, may be made of a transparent organic material that transmits white light. However, this specification is not limited to this.

[0145] Meanwhile, the configuration in which the second color filter CF2, which is a white color filter, is disposed to correspond to the second emission area EA2 of the second sub-pixel SP2 has been described above. However, this is provided for illustrative purposes only, and the present specification is not limited thereto. For example, the color filter may not be disposed to correspond to the second emission area EA2 of the second sub-pixel SP2.

[0146] According to an embodiment, the display device 100 may further include a black matrix disposed between the plurality of color filters CF. The black matrix may be disposed between the plurality of sub-pixels SP and suppress the occurrence of color mixing between adjacent sub-pixels SP. In addition, the black matrix may suppress reflection or leakage of light from lines disposed below the black matrix.

[0147] Meanwhile, as described above, some of the circuit elements provided in the plurality of sub-pixels SP may be defective. For example, if the drive transistor DT is defective, the light-emitting diode ED connected to the defective drive transistor DT may not emit light or may emit light with high brightness. For this reason, the defective sub-pixel can be visually identified by the user.

[0148] In the case where some of the multiple sub-pixels SP are defective as described above, the reference voltage connection line 140 set in the repair area LCA of the display device 100 according to the embodiment of the present specification is cut by the laser L, and the reference voltage connection line 140 is electrically separated from the defective circuit elements of the sub-pixel circuit SPC, so that the defective sub-pixels SP can be repaired.

[0149] Specifically, when laser light L emitted from above the display device 100 is supplied to the reference voltage connection line 140 located in the repair area LCA, the reference voltage connection line 140 located in the corresponding repair area LCA may be cut. When the reference voltage connection line 140 located in the repair area LCA is cut by the laser light L, the sensing transistor SET is electrically separated from the reference voltage line RL, so that the reference voltage Vref supplied from the reference voltage line RL is not applied to the sub-pixel circuit SPC, for example, the sensing transistor SET of the corresponding sub-pixel SP. Therefore, since the reference voltage Vref is not supplied from the sensing transistor SET to the drive transistor DT, the drive transistor DT does not operate, and therefore, the light-emitting diode ED does not emit light. As described above, the sub-pixel SP including the defective circuit element may become a dark spot through the repair process.

[0150] In order to perform a repair process using the laser light L, the light-emitting layer EML does not need to be provided on the propagation path of the laser light L, and the light-emitting layer EML needs to be turned on. That is, because the laser light L needs to be emitted from the area overlapping the non-light-emitting area NEA, the light-emitting area EA may be reduced, that is, the aperture ratio of the sub-pixel SP may be reduced to the extent of the area where the laser light L is emitted.

[0151] In order to suppress the reduction in aperture ratio, the display device 100 according to the embodiment of the present specification focuses the laser light L emitted to the repair area LCA by using an optical member 170 arranged on the bottom surface of the color filter CF and overlapping with the non-luminous area NEA, which can ensure the maximum aperture ratio of the luminous area EA (i.e., the sub-pixel SP).

[0152] More specifically, the optical member 170 may be disposed to overlap the bank 150 disposed in the non-emission area NEA, and the optical member 170 may be disposed on the bottom surface of the color filter CF. For example, the optical member 170 may be disposed to overlap the repair area LCA located in the non-emission area NEA.

[0153] Furthermore, optical member 170 can be used to focus incident light. For example, optical member 170 can include a Fresnel zone plate. In this case, optical member 170 includes multiple closed-loop annular patterns. Light incident on optical member 170 can be diffracted by the annular patterns, and the diffracted waves can constructively interfere, allowing light exiting optical member 170 to be focused at a focal point of optical member 170.

[0154] Therefore, if Figure 4 As shown, in a case where a second subpixel SP is defective and a repair process is performed by emitting laser light L to cut a repair area LCA (e.g., second repair area LCA2 of first reference voltage connection line 141) connected to the second subpixel SP, the laser light L that enters and exits the optical member 170 (e.g., second optical member 172) can be focused by the second optical member 172 and then provided to the repair area LCA. In this case, because the focused laser light L propagates to the repair area LCA, the width of the propagation path of the laser light L in the first direction X and / or the second direction Y can be reduced, and the area of the propagation path of the laser light L on the layer where the light emitting layer EML is provided on the propagation path of the laser light L can be minimized, thereby minimizing the degree to which the light emitting layer EML needs to be opened. Consequently, a reduction in the aperture ratio of the subpixel SP can be minimized.

[0155] Meanwhile, as described above, light entering the optical member 170 may be focused on the focal point of the optical member 170. To this end, the focal length of the optical member 170 may correspond to the distance from the optical member 170 to the reference voltage connection line 140 positioned in the repair area LCA. Figure 6A and Figure 6B The focal length of the optical member 170 is described in detail.

[0156] Figure 6A and Figure 6B Is used to illustrate Figure 3 FIG. 1 is a diagram illustrating an example of an optical member included in a display device.

[0157] Reference Figure 6A and Figure 6BThe optical component 170, including the Fresnel zone plate described above, can be used to focus incident laser light L. For example, the optical component 170 can include multiple closed-loop annular patterns, such as multiple closed annular patterns FZP arranged in a concentric circular shape and spaced apart from each other. Using the aforementioned optical component 170, the incident laser light L is diffracted by the transparent regions spaced apart from each other between the multiple closed annular patterns FZP formed in a concentric circular shape and spaced apart from each other. Furthermore, the diffracted waves constructively interfere, allowing the laser light L exiting the optical component 170 to be focused at the focal point of the optical component 170. As described above, when the laser light L passes through the multiple closed annular patterns FZP of the optical component 170, the laser light L is diffracted between the multiple closed annular patterns FZP and then emitted, so that the multiple closed annular patterns FZP are not damaged by the laser light L.

[0158] The plurality of closed ring patterns FZP included in the optical member 170 may be made of a light-blocking metal. For example, the light-blocking metal may be configured as a single layer made of Cu, Mo, Al, Ag, and Ti, or a combination thereof.

[0159] In this case, an opaque region in which a plurality of closed ring patterns FZP are provided and a transparent region in which no closed ring pattern FZP is provided are formed on the optical member 170. Diffraction of the incident laser light L occurs at each boundary between the opaque region and the transparent region, so that the corresponding laser light L can be focused on the focal point of the optical member 170.

[0160] In this case, among the distances R1, R2, R3, . . . Rn from the center point of the optical member 170 to the boundaries between the opaque area and the transparent area, the distance Rn to the nth (here, n is a natural number) boundary may be calculated based on the following Formula 1.

[0161] [Formula 1]

[0162]

[0163] In Formula 1, Rn represents the distance Rn to the nth boundary among the distances R1, R2, R3, . . . Rn from the center point of the optical member 170 to the boundary between the opaque area and the transparent area, λ represents the wavelength of the laser L, and f represents the focal length f of the optical member 170 .

[0164] As described above, the focal length f of the optical member 170 can be designed by adjusting the widths of the plurality of closed annular patterns FZP included in the optical member 170 and adjusting the intervals between the plurality of closed annular patterns FZP. Figure 5As described above, when the focal length f of the optical member 170 is designed based on the distance from the point where the optical member 170 is set to the reference voltage connection line 140 set in the repair area LCA, the laser L entering the optical member 170 can be focused during the process of repairing the defective sub-pixel, and the focused laser L can be provided to the reference voltage connection line 140 set in the repair area LCA.

[0165] Figure 7 is an enlarged top plan view of a display device according to another embodiment of the present specification. Figure 8 is shown along Figure 7 A cross-sectional view of the example cut along line III-III'.

[0166] at the same time, Figure 7 and Figure 8 The grating member 280 is shown and is related to Figure 3 and Figure 4 Therefore, refer to Figure 7 and Figure 8 , the description will focus on Figure 3 and Figure 4 The differences between the embodiments described above are omitted to avoid repeated description.

[0167] at the same time, Figure 8 An example of a cross-sectional structure of a display device 200 according to another embodiment of the present specification is shown.

[0168] Reference Figure 7 , a display device 200 according to another embodiment of the present specification may include a plurality of sub-pixels SP disposed in one pixel area PXA, and each sub-pixel includes a corresponding sub-pixel circuit SPC.

[0169] The reference voltage connection line 240 disposed between the plurality of sub-pixels SP may be connected to the connection line 130 disposed to pass through the corresponding pixel area PXA in the first direction X. For example, the reference voltage connection line 240 may include a first reference voltage connection line 241 disposed to overlap the second light emitting area EA2 of the second sub-pixel SP2, and a second reference voltage connection line 242 disposed to overlap the third light emitting area EA3 of the third sub-pixel SP3.

[0170] The first reference voltage connection line 241 may include a first main portion extending in the second direction Y and arranged to overlap at least the second light emitting area EA2. The first main portion of the first reference voltage connection line 241 and the connection line 130 may be connected via a second contact hole CH2 in the center portion of the first main portion of the first reference voltage connection line 241. Furthermore, the first reference voltage connection line 241 may include a first auxiliary portion extending from one end of the first main portion in a direction opposite to the first direction X and connected to the first sub-pixel circuit SPC1; and a second auxiliary portion extending from the other end of the first main portion in the first direction X and connected to the second sub-pixel circuit SPC2. Therefore, the reference voltage Vref can be supplied to the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 via the first reference voltage connection line 241 connected to the reference voltage line RL via the connection line 130.

[0171] The second reference voltage connection line 242 may include a second main portion extending in the second direction Y and arranged to overlap at least the third light emitting area EA3. The second main portion of the second reference voltage connection line 242 and the connection line 130 may be connected via a third contact hole CH3 in the center portion of the second main portion of the second reference voltage connection line 242. Furthermore, the second reference voltage connection line 242 may include a third auxiliary portion extending from one end of the second main portion in a direction opposite to the first direction X and connected to the third sub-pixel circuit SPC3; and a fourth auxiliary portion extending from the other end of the second main portion in the first direction X and connected to the fourth sub-pixel circuit SPC4. Therefore, the reference voltage Vref can be supplied to the third sub-pixel circuit SPC3 and the fourth sub-pixel circuit SPC4 via the second reference voltage connection line 242 connected to the reference voltage line RL via the connection line 130.

[0172] At the same time, multiple repair areas LCA may be provided on the reference voltage connection line 240 of each sub-pixel circuit in the sub-pixel circuit SPC. In this case, because the reference voltage connection line 240 is provided to at least partially overlap the emission area EA, the multiple repair areas LCA may be provided to overlap the emission areas EA of the multiple sub-pixels SP. For example, the multiple repair areas LCA may include: a first repair area LCA1 in the first main portion of the first reference voltage connection line 241, which is configured to overlap the second emission area EA2 and is provided adjacent to the first auxiliary portion connected to the first sub-pixel circuit SPC1; and a second repair area LCA2 in the first main portion of the first reference voltage connection line 241, which is configured to overlap the second emission area EA2 and is provided adjacent to the second auxiliary portion connected to the second sub-pixel circuit SPC2. In addition, the multiple repair areas LCA may include: a third repair area LCA3 in the second main portion of the second reference voltage connection line 242, which is configured to overlap with the third light-emitting area EA3 and is set to be adjacent to the third auxiliary portion connected to the third sub-pixel circuit SPC3; and a fourth repair area LCA4 in the second main portion of the second reference voltage connection line 242, which is configured to overlap with the third light-emitting area EA3 and is set to be adjacent to the fourth auxiliary portion connected to the fourth sub-pixel circuit SPC4.

[0173] In addition, a plurality of optical members 270 may be disposed in the non-emission area NEA of the corresponding pixel area PXA. For example, a plurality of optical members 270 may be disposed between a plurality of sub-pixels SP. Therefore, the area in which the optical members 270 are disposed does not overlap with the repair area LCA.

[0174] Specifically, the plurality of optical components 270 may include: a first optical component 271, which is disposed between the first sub-pixel SP1 and the second sub-pixel SP2 and is disposed at one side of the first repair area LCA1 based on the first direction X; a second optical component 272, which is disposed between the first sub-pixel SP1 and the second sub-pixel SP2 and is disposed at one side of the second repair area LCA2 based on the first direction X; a third optical component 273, which is disposed between the third sub-pixel SP3 and the fourth sub-pixel SP4 and is disposed at one side of the third repair area LCA3 based on the first direction X; and a fourth optical component 274, which is disposed between the third sub-pixel SP3 and the fourth sub-pixel SP4 and is disposed at one side of the fourth repair area LCA4 based on the first direction X.

[0175] A plurality of optical members 270 may be used to focus the laser light L. In this case, since the region where the optical members 270 are provided and the repair region LCA do not overlap with each other as described above, the laser light L may be supplied to a region other than the repair region LCA while being supplied in a complete manner to the line to be repaired when the laser light L is focused while passing through the optical members 270.

[0176] Therefore, the display device 200 according to another embodiment of the present specification may further include a grating member disposed to overlap with the plurality of optical members 270 and configured to diffuse the laser light L provided from the plurality of optical members 270 .

[0177] Refer to it together Figure 8 To describe the above configuration in detail, the grating member 280 may be disposed on the interlayer insulating layer ILD. In addition, the grating member 280 may be disposed in the non-emission area NEA. For example, the grating member 280 may be disposed on the interlayer insulating layer ILD and overlap with the optical member 270.

[0178] However, the arrangement of the grating member 280 is not limited thereto, and the grating member 280 may be disposed over any one of the passivation layer PAS, the gate insulating layer GI, and the buffer layer BF instead of the interlayer insulating layer ILD, and overlap the optical member 270 .

[0179] The grating member 280 may include a metal material. For example, the grating member 280 may be configured as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof. According to an embodiment, the grating member 280 may be formed simultaneously through the same process and include the same material as at least one of the first source electrode SE1, the second source electrode SE2, the first drain electrode DE1, and the second drain electrode DE2 provided on the same layer. However, the present specification is not limited thereto.

[0180] The grating member 280 can be used to diffuse the laser light L provided from the optical member 270. For example, the grating member 280 may include a diffraction grating. In this case, the laser light L entering the grating member 280 has a diffraction effect. Parts of the laser light L that pass through the diffraction grating included in the grating member 280 interfere with each other during diffraction, so that the laser light L that has passed through the grating member 280 can be diffused and provided.

[0181] In this case, as described above, since the area irradiated with the laser light L (i.e., the area in which the optical member 270 is provided) does not overlap with the repair area LCA, the laser light L emitted from the optical member 270 and then focused is diffused and provided by the grating member 280. Therefore, at least a portion of the diffused laser light L can be provided to the reference voltage connection line 240 provided in the repair area LCA. Therefore, the reference voltage connection line 240 provided in the repair area LCA can be cut.

[0182] In this case, because the grating member 280 for diffusing the laser light L is positioned below the light-emitting diode ED, even if the light entering the grating member 280 is diffused and emitted, the laser light L exiting the optical member 270 is focused while propagating toward the grating member 280. The grating member 280 does not affect the size and area of the light-emitting layer EML. Therefore, the maximum aperture ratio of the light-emitting area EA (i.e., the sub-pixel SP) can be ensured.

[0183] Meanwhile, the optical member 270 may be designed by setting the focal length f to a point at which the laser light L leaving the optical member 270 is focused and the grating member 280 is positioned. Figure 6A and Figure 6B As described above, the focal length f of the optical member 270 can be designed by adjusting the widths of the multiple closed annular patterns FZP included in the optical member 270 and adjusting the intervals between the multiple closed annular patterns FZP. However, this is provided for illustrative purposes only. The focal length f of the optical member 270 can be designed in various ways.

[0184] Meanwhile, as described above, the laser light L entering the grating member 280 is diffracted and diffused by the diffraction grating included in the grating member 280. The degree of diffusion (e.g., angle) of the laser light L diffused from the grating member 280 may be determined based on the horizontal distance between the region where the grating member 280 is provided and the repair area LCA. Figure 9A and Figure 9B Describe the configuration in detail.

[0185] Figure 9A and Figure 9B Is used to illustrate Figure 7 A view of an example of a grating member included in a display device.

[0186] Reference Figure 9A and Figure 9BGrating member 280 may include a plurality of diffraction gratings and diffract and diffuse incident laser light L. For example, incident laser light L may be diffracted m times (where m is a natural number) by grating member 280 and diffused. Thus, laser light L entering grating member 280 may be distributed as follows: 0th laser light L0, which propagates along a path substantially identical to that of incident laser light L without being diffracted and diffused by grating member 280; first laser light L1, which is diffracted once by grating member 280 and diffused at a first angle θ1; ...; and mth laser light Lm, which is diffracted m times by grating member 280 and diffused at an mth angle θm.

[0187] In this case, the repair area LCA is designed to be positioned on the optical path of the corresponding laser by using a laser beam diffracted and diffused by the grating member 280 (for example, the first laser L1 diffracted once and diffused,..., the mth laser Lm diffracted m times and diffused, in addition to the 0th laser L0 that is not diffracted and diffused), so that the line set in the repair area LCA can be cut.

[0188] For example, the m-th angle θm, which is the diffusion angle at which the m-th laser light Lm is diffracted m times and diffused, can be calculated based on the following formula 2.

[0189] [Formula 2]

[0190] mλ=dsinθm

[0191] In Formula 2, λ represents the wavelength of the laser light L, d represents the spacing distance d between the plurality of diffraction gratings included in the grating member 280 and spaced apart from each other, and θm represents the mth angle θm which is the diffusion angle of the mth laser light Lm.

[0192] In addition, refer to Figure 9B Assuming a right triangle having a first point P1 corresponding to the center point of the grating member 280, a second point P2 corresponding to the repair area LCA, a line segment connecting the first point P1 and the second point P2 (i.e., a hypotenuse), and a third point P3, the grating member 280 may be disposed in the interlayer insulating layer ILD, and an m-th angle θm, which is a diffusion angle of the m-th laser light Lm, may be determined based on a vertical distance between the first point P1 where the grating member 280 is disposed and the second point P2 where the repair area LCA is disposed (i.e., a first distance w1 between the first point P1 and the third point P3) and a horizontal distance between the first point P1 where the grating member 280 is disposed and the second point P2 where the repair area LCA is disposed (i.e., a second distance w2 between the second point P2 and the third point P3). The m-th angle θm can be designed by adjusting the spacing distance d between the plurality of diffraction gratings included in the grating member 280 and adjusting the wavelength of the laser light L to design the diffusion angle to be the m-th angle θm determined based on the first distance w1 and the second distance w2.

[0193] At the same time, if Figure 9B As shown, as the first distance w1 between the first point P1 and the third point P3 (i.e., the vertical distance between the grating member 280 and the repair area LCA) increases, even if the diffusion angle remains the same, the horizontal distance between the grating member 280 and the repair area LCA (e.g., the second distance w2 between the second point P2 and the third point P3) can be sufficiently ensured. To this end, according to embodiments, the thickness of the insulating layer (e.g., at least one of the buffer layer BF, the gate insulating layer GI, and the interlayer insulating layer ILD) disposed between the grating member 280 and the reference voltage connection line 240 disposed in the repair area LCA can be adjusted, and / or at least one of the buffer layer BF, the gate insulating layer GI, and the interlayer insulating layer ILD can be formed into multiple layers.

[0194] Figure 10 is shown along Figure 7 Another example of a cross-sectional view taken along line III-III'.

[0195] at the same time, Figure 10 The reference voltage connection line 340 is shown and is based on Figure 8 Therefore, refer to Figure 10 , the description will focus on Figure 8 The differences between the embodiments described above are omitted to avoid repeated description.

[0196] at the same time, Figure 10 An example of a cross-sectional structure of a display device 300 according to still another embodiment of the present specification is shown.

[0197] Reference Figure 10 A display device 300 according to another embodiment of the present disclosure may include a plurality of sub-pixels SP disposed in one pixel area PXA, and each sub-pixel includes a corresponding sub-pixel circuit SPC.

[0198] As described above, the reference voltage connection line 340 , the light blocking layer LS, and the reference voltage line RL disposed on the first substrate 111 may be disposed on the same layer.

[0199] In this case, the reference voltage connection line 340 may be formed by a half-tone mask process, disposed in the repair area LCA, and cut by the laser light L when performing a repair process on a corresponding sub-pixel SP of a sub-pixel determined to be defective. Therefore, the reference voltage connection line 340 may have a height lower than that of the light blocking layer LS and the reference voltage line RL disposed on the same layer. Therefore, the reference voltage connection line 340 disposed in the repair area LCA may be more easily cut by the laser light L during the repair process.

[0200] Figure 11 is shown along Figure 7 A cross-sectional view of yet another example cut along line III-III'.

[0201] at the same time, Figure 11 Shown is a diagram related to the grating member 480 and according to Figure 8 Therefore, refer to Figure 11 , the description will focus on Figure 8 The differences between the embodiments described above are omitted to avoid repeated description.

[0202] at the same time, Figure 11 An example of a cross-sectional structure of a display device 400 according to still another embodiment of this specification is shown.

[0203] Reference Figure 11 A display device 400 according to another embodiment of the present disclosure may include a plurality of sub-pixels SP disposed in a pixel area PXA, and each sub-pixel includes a corresponding sub-pixel circuit SPC. The plurality of sub-pixels SP may each include a grating pattern DG formed on an overcoat layer OC, and a grating member 480 disposed to correspond to the grating pattern DG.

[0204] The overcoat layer OC may include a grating pattern DG formed in at least a portion of the area. For example, the grating pattern DG may be formed by patterning the top surface of the overcoat layer OC that overlaps with the non-light emitting area NEA, for example, the area in which the optical member 470 is disposed. For example, the grating pattern DG may be formed by patterning the top surface of the overcoat layer OC in a portion corresponding to the interface between the overcoat layer OC and the bank 150.

[0205] The grating member 480 may be disposed on the overcoat layer OC. Furthermore, the grating member 480 may be disposed in the non-emission area NEA. For example, the grating member 480 may be disposed above the grating pattern DG of the overcoat layer OC. In this case, at least a portion of the grating member 480 may fill the space patterned by the grating pattern DG of the overcoat layer OC.

[0206] The grating member 480 may include an insulating material. For example, the grating member 480 may include an insulating material having a different refractive index than the overcoat layer OC.

[0207] In this case, the laser light L provided from the optical member 470 by the shape of the grating pattern DG can be diffused by the grating member 480 according to the difference in refractive index between the grating member 480 and the overcoat layer OC. That is, the grating pattern DG of the overcoat layer OC and the grating member 480 in which the space patterned by the grating pattern DG is filled can function as a diffraction grating, so that the laser light L having passed through the grating member 480 can be diffused and provided.

[0208] Meanwhile, the optical member 470 can be designed by setting the focal length f to a point where the laser light L leaving the optical member 470 is focused and the grating member 480 is positioned. Figure 6A and Figure 6B As described, the focal length f of the optical member 470 can be designed by adjusting the widths of the multiple closed annular patterns FZP included in the optical member 470 and adjusting the intervals between the multiple closed annular patterns FZP. However, this is provided for illustrative purposes only. The focal length f of the optical member 470 can be designed in various ways.

[0209] In addition, the diffusion angle can be designed so that the light diffracted and diffused from the grating member 480 reaches the reference voltage connection line 240 provided in the repair area LCA. Figure 9A and Figure 9B As described, the diffusion angle may be designed by adjusting the spacing distance d between the plurality of diffraction gratings included in the grating member 480 and spaced apart from each other (eg, the spacing distance between the grating patterns DG of the overcoat layer OC).

[0210] In addition, the grating member 480 may be formed to cover edges of the first electrodes AND included in the plurality of sub-pixels SP and to be higher than the first electrodes AND. Therefore, the first electrodes AND included in adjacent sub-pixels SP may be suppressed from being electrically connected to each other.

[0211] In addition, a residual film used to form the first electrode AND may be formed in a region between the first electrodes AND included in adjacent sub-pixels SP (for example, a non-emission area NEA when the first electrode AND is formed). When a patterning process is performed to form the grating pattern DG on the overcoat layer OC, the residual film of the grating pattern DG and the first electrode AND may inhibit the first electrodes AND included in adjacent sub-pixels SP from being electrically connected.

[0212] Figure 12 is shown along Figure 7 A cross-sectional view of yet another example cut along line III-III'.

[0213] at the same time, Figure 12 The refractive member 590 is shown and Figure 11Therefore, refer to Figure 12 , the description will focus on Figure 11 The differences between the embodiments described above are omitted to avoid repeated description.

[0214] at the same time, Figure 12 An example of a cross-sectional structure of a display device 500 according to still another embodiment of this specification is shown.

[0215] Reference Figure 12 A display device 500 according to another embodiment of the present disclosure may include a plurality of sub-pixels SP disposed in one pixel area PXA, each of which includes a corresponding sub-pixel circuit SPC. The plurality of sub-pixels SP may each include a refractive member 590 disposed on the passivation layer PAS.

[0216] The passivation layer PAS may include a groove HM formed in at least a portion of its area. For example, the groove HM may be formed by patterning the top surface of the passivation layer PAS that overlaps with the non-light emitting area NEA (for example, at least a portion of the area in which the grating member 480 is provided in the passivation layer PAS). For example, the groove HM formed by patterning the top surface of the passivation layer PAS may have a triangular pyramid shape. Therefore, in a plan view, the groove HM formed by patterning the top surface of the passivation layer PAS may have a triangular shape, as shown in FIG. Figure 12 shown.

[0217] The refractive member 590 may be disposed on the passivation layer PAS. In addition, the refractive member 590 may be disposed on the non-light emitting area NEA. For example, the refractive member 590 may be disposed to fill the patterned groove HM of the passivation layer PAS. Therefore, the refractive member 590 may have a triangular pyramid shape. Therefore, in a plan view, the refractive member 590 may have a triangular shape, such as Figure 12 shown.

[0218] The refractive member 590 may include an insulating material. For example, the refractive member 590 may include an insulating material having a higher refractive index than the passivation layer PAS.

[0219] Therefore, due to the difference in refractive index between the refractive member 590 and the passivation layer PAS, the laser light L that has traveled along a path substantially the same as the path of the laser light L entering the grating member 480 without being diffracted and diffused among the portions of the laser light L that have exited the grating member 480 may be refracted by the refractive member 590 in the optical path and may travel to the repair area LCA. For example, Figure 9A Like the 0th laser L0 in FIG, the laser light L propagating in a direction parallel to the third direction Z instead of toward the repair area LCA can be refracted by the refractive member 590 in the optical path and can propagate to the repair area LCA.

[0220] Therefore, not only the laser light L diffracted and diffused by the grating member 480 but also the laser light L not diffracted and diffused is refracted by the refractive member 590 and provided to the reference voltage connection line 240 provided in the repair area LCA. Therefore, the reference voltage connection line 240 provided in the repair area LCA can be cut more easily during the repair process.

[0221] Exemplary embodiments of the present disclosure may also be described as follows:

[0222] According to aspects of the present disclosure, a display device is provided. The display device may include: a substrate including a light-emitting region and a non-light-emitting region; at least one transistor disposed on the substrate and arranged to overlap with the light-emitting region; a line disposed on the substrate and connected to the at least one transistor; at least one light-emitting diode disposed on the at least one transistor and including a first electrode, a light-emitting layer, and a second electrode; and an optical member disposed on the at least one light-emitting diode and arranged to overlap with the non-light-emitting region.

[0223] The line may include a repair area, and the optical member is disposed to overlap the repair area.

[0224] Laser light entering the optical component may be focused and provided to the repair area of the wire.

[0225] The optical member may include a plurality of closed ring-shaped patterns, each of the closed ring-shaped patterns having a closed loop shape and including a metal material.

[0226] The display device may further include a color filter disposed on the at least one light emitting diode, wherein the optical member is disposed on a bottom surface of the color filter.

[0227] The line may include at least one of: a reference voltage connection line connected to at least one transistor and configured to provide a reference voltage; a data line configured to provide a data voltage; a high potential power line configured to provide a high potential power voltage; and a low potential power line configured to provide a low potential power voltage.

[0228] The line includes a repair area, and the optical member is disposed so as not to overlap with the repair area.

[0229] The display device may further include a grating member disposed between the wires and the optical member.

[0230] The grating member may be arranged to overlap with the optical member.

[0231] The grating member may be positioned below the at least one light emitting diode.

[0232] The grating member may comprise a metallic material.

[0233] The grating member may be provided on the same layer as the first electrode of the at least one light emitting diode.

[0234] The display device may further include an overcoat layer disposed between the at least one transistor and the at least one light emitting diode, wherein the overcoat layer includes an at least partially patterned grating pattern.

[0235] The grating member may be disposed on the overcoat layer and formed to fill a space patterned by the grating pattern of the overcoat layer.

[0236] The height of the grating member may be higher than that of the first electrode.

[0237] The grating member may comprise an insulating material having a different refractive index than the outer coating.

[0238] The display device may further include a refractive member disposed between the wires and the grating member.

[0239] The refractive member includes an insulating material.

[0240] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: a substrate comprising a light-emitting region and a non-light-emitting region; at least one transistor disposed on the substrate and arranged to overlap the light emitting region; a line disposed on the substrate and connected to the at least one transistor; at least one light emitting diode disposed on the at least one transistor and comprising a first electrode, a light emitting layer, and a second electrode; as well as An optical member is disposed on the at least one light emitting diode and is disposed to overlap the non-light emitting area.

2. The display device according to claim 1, wherein The line includes a repair area, and the optical member is disposed to overlap the repair area.

3. The display device according to claim 2, wherein: Laser light entering the optical member is focused and provided to the repair area of the wire.

4. The display device according to claim 1, wherein The optical member includes a plurality of closed annular patterns, each of which has a closed loop shape and includes a metal material.

5. The display device according to claim 4, wherein In the optical member, a region where the plurality of closed annular patterns are concentrically arranged is opaque, and regions between the plurality of closed annular patterns that are spaced apart from each other are transparent.

6. The display device according to claim 1, further comprising: a color filter disposed on the at least one light emitting diode, Wherein, the optical member is disposed on the bottom surface of the color filter.

7. The display device according to claim 1, wherein The line includes at least one of: a reference voltage connection line connected to the at least one transistor and configured to provide a reference voltage; a data line configured to provide a data voltage; a high potential power line configured to provide a high potential power voltage; and a low potential power line configured to provide a low potential power voltage.

8. The display device according to claim 1, wherein The line includes a repair area, and the optical member is disposed so as not to overlap with the repair area.

9. The display device according to claim 8, further comprising: A grating member is disposed between the wire and the optical member.

10. The display device according to claim 9, wherein The grating member is disposed to overlap with the optical member.

11. The device according to claim 9, wherein The grating member is positioned below the at least one light emitting diode.

12. The display device according to claim 11, wherein The grating member includes a metal material.

13. The display device according to claim 9, wherein: The grating member is disposed on the same layer as the first electrode of the at least one light emitting diode.

14. The display device according to claim 13, further comprising: an outer coating disposed between the at least one transistor and the at least one light emitting diode, Wherein, the outer coating comprises an at least partially patterned grating pattern.

15. The display device according to claim 14, wherein The grating member is disposed on the overcoat layer and formed to fill a space patterned by the grating pattern of the overcoat layer.

16. The display device according to claim 13, wherein The height of the grating member is higher than that of the first electrode.

17. The display device according to claim 14, wherein: The grating member includes an insulating material having a different refractive index than the outer coating.

18. The display device according to claim 13, further comprising: A refractive member is disposed between the wire and the grating member.

19. The display device according to claim 18, wherein The refractive member includes an insulating material.

20. The display device according to claim 9, wherein The grating member includes a diffraction grating.

21. The display device according to claim 1, wherein The optical component includes a Fresnel zone plate.

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