Display device and electronic device including the same

Abstract

The invention relates to a display device and an electronic device including the same. The display device includes: a first sub-pixel including a first pixel circuit; a second sub-pixel including a second pixel circuit and extending from the first sub-pixel in the first direction; a first power line that overlaps the first pixel circuit and extends in a second direction intersecting the first direction; a 22th power line overlapping the second pixel circuit and extending in the second direction; a first power supply line connecting the second power supply line and the second sub-pixel and extending in the first direction; and a 21st power supply line connecting the 22nd power supply line and the first sub-pixel and extending in the first direction.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0023717 filed in the Korean Intellectual Property Office on February 19, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a display device and an electronic device including the display device. Background Art

[0003] With the development of information technology, the importance of display devices as a connecting medium between users and information is becoming increasingly apparent.

[0004] The display device includes a plurality of pixels. Each of the pixels includes a plurality of transistors, a light-emitting element electrically connected to the transistors, and a capacitor. The transistors can be turned on in response to a signal provided by a line, and thus, a drive current (e.g., a predetermined drive current) can be generated. The light-emitting element can emit light in response to the drive current.

[0005] Recently, as the number of pixels and pixel circuits in display devices has been miniaturized, the distance between the wires included in the pixels and pixel circuits has tended to narrow. Accordingly, the resistance of the wires included in the pixels and pixel circuits may increase, and thus, power consumption may increase due to heat generation.

[0006] The above content is merely intended to help understand the background technology of the technical idea of the present disclosure, and therefore, it should not necessarily be understood as content corresponding to the existing technology known to those skilled in the art in the field of the present disclosure. Summary of the Invention

[0007] Embodiments of the present disclosure may provide a display device that can be driven while consuming relatively small power and an electronic device including the display device.

[0008] According to an embodiment of the present disclosure, a display device includes: a first sub-pixel, including a first pixel circuit; a second sub-pixel, including a second pixel circuit and extending from the first sub-pixel in a first direction; a 1_2th power line, overlapping with the first pixel circuit and extending in a second direction intersecting the first direction; a 2_2th power line, overlapping with the second pixel circuit and extending in the second direction; a 1_1th power line, connecting the 1_2th power line and the second sub-pixel and extending in the first direction; and a 2_1th power line, connecting the 2_2th power line and the first sub-pixel and extending in the first direction.

[0009] The display device may further include: a first data line overlapping the first pixel circuit and extending in the second direction; and a second data line overlapping the second pixel circuit and extending in the second direction, wherein the 1_2 th power line is between the first data line and the second data line.

[0010] The second data line may be between the 1_2 th power line and the 2_2 th power line.

[0011] The resistance of the 1_2 th power line and the resistance of the 2_2 th power line may be substantially equal.

[0012] The display device may include: a base layer; a semiconductor layer on the base layer; an interlayer insulating layer on the semiconductor layer and defining a first through hole exposing at least a portion of the semiconductor layer overlapping with a first pixel circuit; a first conductive layer on the interlayer insulating layer; a through hole layer on the first conductive layer and defining a second through hole exposing at least a portion of the first conductive layer overlapping with the first pixel circuit; and a second conductive layer on the through hole layer.

[0013] The through-hole layer may not expose a portion of the first conductive layer overlapping the second pixel circuit.

[0014] The 1_2 power line of the second conductive layer may overlap with the first pixel circuit, wherein the 1_2 power line contacts the connection electrode of the first conductive layer through the second through hole, and wherein the connection electrode contacts at least a portion of the semiconductor layer overlapping with the first pixel circuit through the first through hole.

[0015] The interlayer insulating layer may further define a third through hole exposing at least a portion of the semiconductor layer overlapping with the second pixel circuit, wherein the connecting electrode extends from the first pixel circuit to the area overlapping with the second pixel circuit in the first direction, and wherein the connecting electrode contacts at least a portion of the semiconductor layer overlapping with the second pixel circuit through the third through hole in the second pixel circuit.

[0016] The display device may further include: a gate layer between the semiconductor layer and the interlayer insulating layer, wherein the interlayer insulating layer further defines a fourth through hole exposing at least a portion of the gate layer overlapping the second pixel circuit.

[0017] The via layer may further define a fifth via hole exposing at least a portion of the first conductive layer overlapping the first pixel circuit.

[0018] The first subpixel and the second subpixel may each include: a light-emitting element; a driving transistor connected between the 1_1 power line and the second node, the second node being used to control the driving current supplied to the light-emitting element in response to the voltage of the first node connected to the gate electrode of the driving transistor; a first capacitor including an electrode connected to the first node and another electrode connected to the third node; a second transistor connected between the third node and the first data line or the second data line and configured to be turned on by the first scan signal; a third transistor connected between the first node and the second node and configured to be turned on by the second scan signal; a fourth transistor connected between the first node and the initialization power supply and configured to be turned on by the third scan signal; and a fifth transistor connected between the 2_1 power line and the third node and configured to be turned on by the second scan signal.

[0019] The first subpixel and the second subpixel may each further include: a sixth transistor connected between the second node and a fourth node connected to an electrode of the light-emitting element, and configured to be turned on by the first emission control signal; a seventh transistor connected between the fourth node and the anode initialization power supply, and configured to be turned on by the fourth scan signal; and a second capacitor including one electrode connected to the 1_1th power line and another electrode connected to the third node.

[0020] The first subpixel and the second subpixel may each further include: a sixth transistor, connected between the 1_1 power line and a fifth node connected to an electrode of the driving transistor, and configured to be turned on by the first emission control signal; a seventh transistor, connected between the second node and a fourth node connected to an electrode of the light-emitting element, and configured to be turned on by the second emission control signal; an eighth transistor, connected between the fourth node and the anode initialization power supply, and configured to be turned on by the fourth scan signal; and a ninth transistor, connected between the fifth node and the bias power supply, and configured to be turned on by the fourth scan signal.

[0021] The driving transistor and the second to ninth transistors may include P-type transistors.

[0022] The second transistor, the third transistor, the fourth transistor, and the fifth transistor may include N-type transistors, wherein the driving transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor include P-type transistors.

[0023] Each of the first subpixel and the second subpixel may further include a tenth transistor connected between the 1_1th power line and the fifth node and configured to be turned on by the second scan signal.

[0024] The first subpixel and the second subpixel may each include: a light-emitting element; a driving transistor connected between the second node and a fifth node, the fifth node being used to control a driving current supplied to the light-emitting element in response to a voltage of a first node connected to a gate electrode of the driving transistor; a second transistor connected between the third node and the first data line or the second data line, and configured to be turned on by a first scan signal; a first capacitor including an electrode connected to the third node and another electrode connected to the first node; a third transistor connected between the first node and a second node connected to an electrode of the driving transistor, and configured to be turned on by a second scan signal; a fourth transistor connected between the third node and the 2_1 power line, and configured to be turned on by the second scan signal; and a fifth transistor connected between the 1_1 power line and the fifth node, and configured to be turned on by a first emission control signal.

[0025] The display device may further include: a second capacitor including an electrode connected to the 1_1th power line and another electrode connected to the third node; a sixth transistor connected between the second node and a fourth node connected to an electrode of the light-emitting element, and configured to be turned on by the second emission control signal; a seventh transistor connected between the fourth node and the anode initialization power supply, and configured to be turned on by the first emission control signal; and an eighth transistor connected between the fifth node and the bias power supply, and configured to be turned on by the fourth scan signal.

[0026] Another aspect of the present disclosure can be implemented by an electronic device. According to an embodiment of the present disclosure, an electronic device includes: a processor configured to provide input image data; and a display device configured to display an image based on the input image data, and including: a first subpixel including a first pixel circuit; a second subpixel including a second pixel circuit spaced apart from the first subpixel in a first direction; a 1_2 power line overlapping the first pixel circuit and extending in a second direction intersecting the first direction; a 2_2 power line overlapping the second pixel circuit and extending in the second direction; a 1_1 power line connecting the 1_2 power line and the second subpixel and extending in the first direction; and a 2_1 power line connecting the 2_2 power line and the first subpixel and extending in the first direction.

[0027] The electronic device may further include: a first data line overlapping the first pixel circuit and extending in the second direction; and a second data line overlapping the second pixel circuit and extending in the second direction, wherein the 1_2 th power line is between the first data line and the second data line.

[0028] A display device and an electronic device including the same according to an embodiment of the present disclosure may be driven while consuming relatively little power.

[0029] Aspects according to the embodiments are not limited to the above-exemplified contents, and include other various aspects in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects of the present disclosure will become more apparent by describing embodiments of the present disclosure in more detail with reference to the accompanying drawings, in which:

[0031] Figure 1A is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0032] Figure 1B A detailed diagram Figure 1A A block diagram of one or more embodiments of a display device;

[0033] Figure 2 It is an icon Figure 1A and / or Figure 1B A block diagram of one or more embodiments of a sub-pixel of a sub-pixel;

[0034] Figure 3A is a circuit diagram illustrating a sub-pixel according to one or more embodiments of the present disclosure;

[0035] Figure 3B is a circuit diagram illustrating a sub-pixel according to one or more other embodiments of the present disclosure;

[0036] Figure 3C is a circuit diagram illustrating a sub-pixel according to yet one or more other embodiments of the present disclosure;

[0037] Figure 3D is a circuit diagram illustrating a sub-pixel according to one or more other embodiments of the present disclosure;

[0038] Figure 3E is a circuit diagram illustrating a sub-pixel according to one or more other embodiments of the present disclosure;

[0039] Figure 4 The diagram is based on Figure 3E A waveform diagram showing the operation of one or more embodiments of the pixel shown in FIG. 1 during a display scan period;

[0040] Figure 5 Observed from above Figure 2 A schematic plan view of a display panel;

[0041] Figure 6 The diagram is included in the Figure 5 A plan view of an example of a semiconductor layer in a pixel in a display panel;

[0042] Figure 7The diagram is included in the Figure 5 A plan view of an example of a first conductive layer in a pixel in a display panel of FIG.

[0043] Figure 8 The diagram is included in the Figure 5 A plan view of an example of a second conductive layer in a pixel in a display panel of FIG.

[0044] Figure 9 The diagram is included in the Figure 5 A plan view of an example of a third conductive layer in a pixel in a display panel of FIG.

[0045] Figure 10 The diagram is included in the Figure 5 A plan view of an example of a fourth conductive layer in a pixel in a display panel of FIG.

[0046] Figure 11 The diagram is included in the Figure 5 A plan view of an example of a fifth conductive layer in a pixel in a display panel of FIG.

[0047] Figure 12 The diagram is along Figure 5 A cross-sectional view of the stacked structure of the display panel taken along line II';

[0048] Figure 13 The diagram is along Figure 5 A cross-sectional view of the stacked structure of the display panel taken along line II-II';

[0049] Figure 14 is a block diagram illustrating an electronic device including a display device according to an embodiment of the present disclosure;

[0050] Figure 15 It is shown in the figure Figure 14 A perspective view of an example in which the electronic device is implemented as a smart phone; and

[0051] Figure 16 It is shown in the figure Figure 14 A perspective view of an example in which the electronic device is implemented as a tablet PC. DETAILED DESCRIPTION

[0052] By referring to the detailed description and drawings of the embodiments, it is easier to understand various aspects of some embodiments of the present disclosure and the methods for realizing them. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and the described embodiments will fully convey various aspects of the present disclosure to those skilled in the art. Accordingly, processes, elements and techniques that are redundant, irrelevant or unrelated to the description of the embodiments, or are not necessary for a complete understanding of various aspects of the present disclosure by those of ordinary skill in the art may be omitted. Unless otherwise stated, throughout the drawings and written descriptions, the same reference numerals, characters or combinations thereof represent the same elements, and therefore, repeated descriptions thereof may be omitted.

[0053] The described embodiments may have various modifications and may be implemented in different forms and should not be construed as limited to the embodiments illustrated herein. When describing embodiments, the use of "can," "may," or "may not" corresponds to one or more embodiments of the present disclosure.

[0054] In view of the entire content of the present disclosure, those skilled in the art will understand that the present disclosure covers all modifications, equivalents and replacements within the scope of the ideas and technology of the present disclosure, and that each of the features of the embodiments of the present disclosure may be combined with each other in part or in whole and that various technical interlocking and operations are possible, and that unless otherwise specified or implied, each embodiment may be implemented independently of each other or may be implemented together in an associated manner.

[0055] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify boundaries between adjacent elements. Therefore, unless otherwise indicated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between illustrated elements, and / or any other characteristics, attributes, properties, etc.

[0056] Various embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances are contemplated. Furthermore, descriptions of specific structures or functions disclosed herein are merely illustrative, for purposes of describing embodiments according to the concepts of the present disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes of the illustrated elements, layers, or regions, but are intended to include deviations in shapes resulting from, for example, manufacturing.

[0057] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0058] For ease of explanation, spatial relative terms such as "below", "below", "lower", "downside", "beneath", "above", "upper", "above", "higher", "upper side" and "side" (e.g., as in "sidewall") may be used herein to describe the relationship between an element or feature and another (some) element or feature as illustrated in the figures. It will be understood that, in addition to the orientation depicted in the figures, spatial relative terms are intended to include different orientations of the device in use or in operation. For example, if the device in the figure is turned over, the elements described as being "below", "below" or "below" other elements or features will then be oriented "above" the other elements or features. Therefore, the example terms "below" and "below" can include both the orientations of above and below. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used in this article should be interpreted accordingly. Similarly, when a first component is described as being arranged "on" a second component, this means that the first component is arranged on the upper or lower side of the second component, and is not limited to its upper side based on the direction of gravity.

[0059] Further, the phrase "in a plan view" means when the object portion is viewed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-section taken by vertically cutting the object portion is viewed from the side. The term "overlapping" or "overlapping" means that the first object can be above or below or to the side of the second object, and vice versa. In addition, the term "overlapping" can include stacking, facing or facing, extending above, covering or partially covering, or any other suitable term as will be recognized and understood by a person of ordinary skill in the art. The expression "non-overlapping" can include terms such as "separated from..." or "set to the side of..." or "deviating from..." and any other suitable equivalent meanings as will be recognized and understood by a person of ordinary skill in the art. The terms "facing" and "facing" can mean that the first object can be directly or indirectly opposite to the second object. In the case where a third object is interposed between the first and second objects, the first and second objects can be understood to be indirectly opposite to each other, although still facing each other.

[0060] It will be understood that when an element, layer, region, or component is referred to as being formed “on,” “on,” “connected to,” or “(operably or communicatively) coupled to” another element, layer, region, or component, it may be directly formed on, directly on, directly connected to, or directly coupled to another element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or coupled to another element, layer, region, or component such that there may be one or more intervening elements, layers, regions, or components. Additionally, this may collectively mean directly or indirectly coupled or connected, as well as integrally or non-integrally coupled or connected. For example, when a layer, region, or component is referred to as being “electrically connected” or “electrically coupled” to another layer, region, or component, it may be directly electrically connected or directly electrically coupled to another layer, region, and / or component, or there may be one or more intervening layers, regions, or components. One or more intervening components may include switches, resistors, and / or capacitors, etc. In describing the embodiments, unless explicitly described as directly connected, the expression "connected" indicates an electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or coupled to another component or is directly on another component without intervening components.

[0061] In addition, in this specification, when a part of a layer, film, area or plate, etc. is formed on another part, the formation direction is not limited to the upward direction, but includes forming the part on the side surface or in the downward direction. On the contrary, when a part of a layer, film, area or plate, etc. is formed "under" another part, this includes not only the case where the part is "directly under" the other part, but also the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between parts (such as "between", "immediately between" or "adjacent to" and "directly adjacent to") can be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0062] For purposes of this disclosure, expressions such as “at least one of” or “any one of” or “one or more of” when following a list of elements modify the entire list of elements without modifying the individual elements of the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z, such as with XYZ, XYY, YZ, and ZZ, or any variation thereof. Similarly, the expression “at least one of A and B” may include A, B, or A and B. As used herein, “or” generally means “and / or,” and the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” may include A, B, or A and B. Similarly, expressions such as “at least one of,” “a plurality of,” “one of,” and other prepositional phrases when preceding or following a list of elements modify the entire list of elements without modifying the individual elements of the list. Unless otherwise specified, when "C to D" is stated, it means C or more and D or less.

[0063] It will be understood that although the terms "first", "second", "third", etc. can be used to describe various elements, components, regions, layers and / or sections in this article, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or advantage, and are only used to distinguish an element, member, component, region, area, layer, section or part from another element, member, component, region, area, layer, section or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or section described below can be referred to as the second element, component, region, layer or section. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used to distinguish different categories or element groups in this article. For the sake of simplicity, the terms "first", "second", etc. can respectively represent "first class (or first group)", "second class (or second group)", etc.

[0064] In the examples, the x-axis, y-axis, and / or z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broad sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0065] The terms used in this document are used only for the purpose of describing the embodiments and are not intended to limit the present disclosure. As used herein, the singular form "a" and "an" are intended to include the plural form as well, and the plural form is intended to include the singular form, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "comprises," "having," and "comprising" and their variations specify the presence of stated features, wholes, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts, and / or groups thereof.

[0066] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as approximate terms rather than as terms of degree, and are intended to take into account the inherent deviations in measured or calculated values that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / - 5% of the corresponding value. Taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein include the stated value and mean within an acceptable deviation range for that particular value as determined by those of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value. Further, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0067] In some embodiments, well-known structures and devices related to one or more functional blocks (e.g., block diagrams), units and / or modules may be described in the accompanying drawings to avoid unnecessary ambiguity of various embodiments. Those skilled in the art will understand that such blocks, units and / or modules are physically implemented by logic circuits, separate components, microprocessors, hard-wired circuits, memory elements, line connections and other electronic circuits. This can be formed using semiconductor-based manufacturing technology or other manufacturing technology. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, optionally, can be driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by a combination of dedicated hardware or dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and related circuits) that performs functions different from the functions of the dedicated hardware. In addition, in some embodiments, without departing from the scope of this disclosure, blocks, units and / or modules can be physically divided into two or more interacting separate blocks, units and / or modules. Additionally, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0068] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0069] Figure 1A is a block diagram illustrating a display device according to an embodiment of the present disclosure. Figure 1B A detailed diagram Figure 1A A block diagram of one or more embodiments of a display device.

[0070] refer to Figure 1A , the display device 1000 may include a display panel 100 , a scan driver 200 , an emission driver 300 , a data driver 400 , and a timing controller 500 .

[0071] The display panel 100 may include a display area where pixels PX are located and a non-display area located in a peripheral area (eg, an edge area) of the display area. One or more pixels PX may be located in the display area.

[0072] Each pixel PX may include a plurality of sub-pixels SP. Each of the plurality of sub-pixels SP may emit light of a single color. For example, a pixel PX may include a red sub-pixel SP that emits red light (e.g., a first color light), a green sub-pixel SP that emits green light (e.g., a second color light), and a blue sub-pixel SP that emits blue light (e.g., a third color light). However, the colors of light emitted by the sub-pixels SP and the types and / or numbers of the sub-pixels SP are not limited thereto.

[0073] According to one or more embodiments, the sub-pixel SP may be configured in a striped or Layout structure ( is a registered trademark of Samsung Display Co., Ltd. of Korea), but is not limited thereto, and various embodiments may be applied to the present disclosure.

[0074] refer to Figure 1A and Figure 1B , the scan driver 200 can be divided into the configuration and operation of the first scan driver 210, the second scan driver 220, the third scan driver 230, and the fourth scan driver 240. The emission driver 300 can be divided into the configuration and operation of the first emission driver 310 and the second emission driver 320. However, the division of the scan driver and the emission driver is for convenience of description, and according to design, at least a portion of the scan driver and the emission driver can be integrated into one driving circuit or module, etc.

[0075] In one or more embodiments, the display device 1000 may further include a power supply for supplying a voltage of a first power supply VDD, a voltage of a second power supply VSS, and a third power supply VREF (or a reference power supply VREF), a fourth power supply VINT (or an initialization power supply VINT), a fifth power supply VAINT (or an anode initialization power supply VAINT), and a sixth power supply VBS (or a bias power supply VBS) to the display panel 100. The power supply may supply a low power supply and a high power supply that determine a gate-on level and a gate-off level of a scan signal, a control signal, and / or an emission control signal to the scan driver 200 and / or the emission driver 300. The low power supply may have a voltage level lower than that of the high power supply.

[0076] According to one or more embodiments, a first power supply VDD and a second power supply VSS may generate a voltage for driving a light-emitting element. In one or more embodiments, the voltage level of the second power supply VSS may be lower than the voltage level of the first power supply VDD. For example, the voltage of the first power supply VDD may be a positive voltage, and the voltage of the second power supply VSS may be a ground voltage or a negative voltage.

[0077] The third power supply VREF may be a power supply for initializing the sub-pixel SP. For example, the capacitor and / or transistor included in the sub-pixel SP may be initialized by the voltage of the third power supply VREF. The third power supply VREF may be a positive voltage.

[0078] The fourth power source VINT may be a power source for initializing the sub-pixel SP. For example, the driving transistor included in the sub-pixel SP may be initialized by the voltage of the fourth power source VINT. The fourth power source VINT may be a ground voltage or a negative voltage.

[0079] The anode initialization power supply VAINT may be a power supply for initializing the sub-pixel SP. For example, the anode of the light-emitting element included in the sub-pixel SP may be initialized by the voltage of the anode initialization power supply VAINT. The anode initialization power supply VAINT may be a ground voltage or a negative voltage.

[0080] The bias power supply VBS may be a power supply for supplying a conduction bias voltage (e.g., a predetermined conduction bias voltage) to the source electrode of the driving transistor included in the subpixel SP. The bias power supply VBS may be a positive voltage. In one or more embodiments, the voltage of the bias power supply VBS may be at a level similar to that of the data voltage of the black grayscale.

[0081] The display panel 100 may include sub-pixels SP respectively connected to the first to n-th scan lines SL1, ... and SLn (n is an integer equal to or greater than 2), the first to m-th data lines DL1, ... and DLm (m is an integer equal to or greater than 2), and the first to n-th emission control lines EL1, ... and ELn.

[0082] Each of the first to n-th scan lines SL1, ..., and SLn may include first to p-th sub-scan lines (p is an integer equal to or greater than 2). For example, the first scan line SL1 may include a first sub-scan line SL11, a second sub-scan line SL12, a third sub-scan line SL13, and a fourth sub-scan line SL14 connected to the first to fourth scan drivers 210, 220, 230, and 240, respectively.

[0083] Each of the first to n-th emission control lines EL1, ..., and ELn may include first to q-th sub-emission control lines (q is an integer equal to or greater than 2). For example, the first emission control line EL1 may include a first sub-emission control line EL11 and a second sub-emission control line EL21 connected to the first emission driver 310 and the second emission driver 320, respectively.

[0084] The sub-pixel SP may receive voltages of a first power supply VDD, a second power supply VSS, a third power supply VREF, a fourth power supply VINT, a fifth power supply VAINT, and a sixth power supply VBS from the outside. In one or more embodiments, the sub-pixel SPij located in the i-th (i is an integer equal to or greater than 2 and equal to or less than n) row and the j-th (j is an integer equal to or greater than 2 and equal to or less than m) column may be connected to the sub-scan lines SL1i, SL2i, SL3i, and SL4i corresponding to the i-th pixel row, the sub-emission control lines EL1i and EL2i corresponding to the i-th pixel row, and the data line DLj corresponding to the j-th pixel column.

[0085] The timing controller 500 may generate a first emission drive signal CS1, a second emission drive signal CS2, and a third emission drive signal CS3 in response to a synchronization signal supplied from an external source (e.g., from a processor, etc.). For example, the first emission drive signal CS1 may include a first scan control signal SCS1, a second scan control signal SCS2, a third scan control signal SCS3, and a fourth scan control signal SCS4. Furthermore, the second emission drive signal CS2 may include a first emission control signal ECS1 and a second emission control signal ECS2. The third emission drive signal CS3 may include a data control signal DCS.

[0086] The timing controller 500 may generate a first scan control signal SCS1 , a second scan control signal SCS2 , a third scan control signal SCS3 , a fourth scan control signal SCS4 , a first emission control signal ECS1 , a second emission control signal ECS2 , and a data control signal DCS.

[0087] The first scan control signal SCS1 may be supplied to the first scan driver 210 , the second scan control signal SCS2 may be supplied to the second scan driver 220 , the third scan control signal SCS3 may be supplied to the third scan driver 230 , and the fourth scan control signal SCS4 may be supplied to the fourth scan driver 240 .

[0088] The first emission control signal ECS1 may be supplied to the first emission driver 310 , and the second emission control signal ECS2 may be supplied to the second emission driver 320 .

[0089] The data control signal DCS may be supplied to the data driver 400 .

[0090] In addition, the timing controller 500 may rearrange input image data supplied from the outside (eg, from a processor, etc.) into image data RGB and may supply the image data RGB to the data driver 400 .

[0091] The first scan control signal SCS1 may include a first scan start pulse and a clock signal. The first scan start pulse may control a first timing of a scan signal output from the first scan driver 210. The clock signal may be used to shift the first scan start pulse.

[0092] The second scan control signal SCS2 may include a second scan start pulse and a clock signal. The second scan start pulse may control a first timing of a scan signal output from the second scan driver 220. The clock signal may be used to shift the second scan start pulse.

[0093] The third scan control signal SCS3 may include a third scan start pulse and a clock signal. The third scan start pulse may control the first timing of the scan signal output from the third scan driver 230. The clock signal may be used to shift the third scan start pulse.

[0094] The fourth scan control signal SCS4 may include a fourth scan start pulse and a clock signal. The fourth scan start pulse may control a first timing of a scan signal output from the fourth scan driver 240. The clock signal may be used to shift the fourth scan start pulse.

[0095] The first emission control signal ECS1 may include a first emission control start pulse and a clock signal. The first emission control start pulse may control a first timing of the emission control signal output from the first emission driver 310. The clock signal may be used to shift the first emission control start pulse.

[0096] The second emission control signal ECS2 may include a second emission control start pulse and a clock signal. The second emission control start pulse may control the first timing of the emission control signal output from the second emission driver 320. The clock signal may be used to shift the second emission control start pulse.

[0097] The data control signal DCS may include a source start pulse and a clock signal. The source start pulse may control the start time of data sampling. The clock signal may be used to control the sampling operation.

[0098] The first scan driver 210 may receive a first scan control signal SCS1 from the timing controller 500 and may supply a scan signal (e.g., a first scan signal) to the first sub-scan lines SL11 to SL1n based on the first scan control signal SCS1. For example, the first scan driver 210 may sequentially supply the first scan signal to the first scan line SL1. When the first scan signal is sequentially supplied, the sub-pixels SP may be selected in units of horizontal lines (or pixel rows), and data signals may be supplied to the sub-pixels SP. In other words, the first scan signal may be a signal for writing data.

[0099] The first scan signal may be set to a gate-on level (eg, a low voltage). When the first scan signal is supplied, a transistor included in the subpixel SP and receiving the first scan signal may be set to a turn-on state.

[0100] The first scan driver 210 may supply a scan signal to the first scan line SL1 during a display scan period of one frame. For example, the first scan driver 210 may supply at least one scan signal to each first scan line SL1 during the display scan period.

[0101] The second scan driver 220 may receive a second scan control signal SCS2 from the timing controller 500 and may supply a scan signal (e.g., a second scan signal) to the second sub-scan lines SL21 to SL2n based on the second scan control signal SCS2. For example, the second scan driver 220 may sequentially supply the second scan signal to the second scan line SL2. The second scan signal may be supplied for initialization and / or threshold voltage (Vth) compensation of transistors and capacitors included in the sub-pixel SP. When the second scan signal is supplied, the sub-pixel SP may perform a threshold voltage compensation operation and / or an initialization operation. The second scan signal may be set to a gate-on level (e.g., a low voltage). When the second scan signal is supplied, the transistor included in the sub-pixel SP and receiving the second scan signal may be set to an on state.

[0102] The second scan driver 220 may supply a scan signal to the second scan line SL2 during a display scan period of one frame. For example, the second scan driver 220 may supply at least one scan signal to each second scan line SL2 during the display scan period.

[0103] The third scan driver 230 may receive a third scan control signal SCS3 from the timing controller 500 and may supply a scan signal (e.g., a third scan signal) to the third sub-scan line SL3 based on the third scan control signal SCS3. For example, the third scan driver 230 may supply a scan signal (e.g., a third scan signal) to the third sub-scan lines SL31 to SL3n. The third scan signal may be supplied to initialize the drive transistor included in the sub-pixel SP and / or to initialize the capacitor included in the sub-pixel SP. When the third scan signal is supplied, the sub-pixel SP may perform an initialization operation on the drive transistor and / or an initialization operation on the capacitor.

[0104] The third scan signal may be set to a gate-on level (eg, a low voltage). When the third scan signal is supplied, a transistor included in the subpixel SP and receiving the third scan signal may be set to a turn-on state.

[0105] The fourth scan driver 240 may receive a fourth scan control signal SCS4 from the timing controller 500 and may supply a scan signal (e.g., a fourth scan signal) to the fourth scan control signal. For example, the fourth scan driver 240 may supply a scan signal (e.g., a fourth scan signal) to the fourth sub-scan lines SL41 to SL4n.

[0106] The fourth scan signal may be supplied to initialize the light-emitting element included in the sub-pixel SP. Furthermore, the fourth scan signal may be supplied to supply a bias voltage (e.g., a turn-on bias voltage) to the source electrode of the driving transistor included in the sub-pixel SP. Accordingly, when the fourth scan signal is supplied, the sub-pixel SP may perform an initialization operation for the light-emitting element and / or a bias voltage supply operation.

[0107] The fourth scan signal may be set to a gate-on level (eg, a low voltage). When the fourth scan signal is supplied, a transistor included in the subpixel SP and receiving the fourth scan signal may be set to a turn-on state.

[0108] The first emission driver 310 may receive the first emission control signal ECS1 from the timing controller 500 and may supply an emission control signal (e.g., a first emission control signal) to the first emission control line EL1 based on the first emission control signal ECS1. For example, the first emission driver 310 may sequentially supply the first emission control signal to the first first sub-emission control line EL11 to the nth first sub-emission control line EL1n.

[0109] The second emission driver 320 may receive the second emission control signal ECS2 from the timing controller 500 and may supply an emission control signal (e.g., a second emission control signal) to the first emission control line EL1 based on the second emission control signal ECS2. For example, the second emission driver 320 may sequentially supply the second emission control signal to the first second sub-emission control line EL21 to the nth second sub-emission control line EL2n.

[0110] When the first emission control signal and / or the second emission control signal are supplied, the sub-pixel SP may not emit light in units of horizontal lines (or pixel rows). To this end, the first emission control signal and the second emission control signal may be set to a gate-off level (e.g., a high voltage) so that the transistor included in the sub-pixel SP is turned off. When the first emission control signal and / or the second emission control signal are supplied, the transistor included in the sub-pixel SP and receiving the first emission control signal and / or the second emission control signal may be turned off, and otherwise may be set to an on state.

[0111] The first emission control signal and the second emission control signal may be used to control the emission time of the sub-pixel SP. To this end, the first emission control signal and the second emission control signal may be set to a width wider than that of the scan signal.

[0112] In one or more embodiments, the first emission control signal and / or the second emission control signal may have multiple gate-off level periods (e.g., high voltage periods) during one frame period. For example, the first emission control signal and / or the second emission control signal may include multiple gate-on periods and multiple gate-off periods for initialization and threshold voltage compensation, etc.

[0113] The data driver 400 may receive a data control signal DCS and image data RGB from the timing controller 500. The data driver 400 may supply a data signal to the data line DL in response to the data control signal DCS. The data signal supplied to the data line DL may be supplied to a sub-pixel SP selected by a scan signal (e.g., a first scan signal). In other words, the data driver 400 may supply the data signal to the data line DL in synchronization with the scan signal.

[0114] Figure 2 It is an icon Figure 1A and / or Figure 1B A block diagram of one or more embodiments of a sub-pixel in a sub-pixel. Figure 2 In the Figure 1A and / or Figure 1B The sub-pixel SPij arranged in the i-th row and j-th column among the sub-pixels SP is taken as an example.

[0115] refer to Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0116] The light-emitting element LD may be connected between a first power supply VDD and a second power supply VSS. The anode AE electrode of the light-emitting element LD may be connected to the first power supply VDD via a sub-pixel circuit SPC, and the cathode CE electrode of the light-emitting element LD may be connected to the second power supply VSS. For example, the anode AE electrode of the light-emitting element LD may be connected to the first power supply VDD via one or more transistors included in the sub-pixel circuit SPC.

[0117] The sub-pixel circuit SPC can be connected to Figure 1B The sub-pixel circuit SPC is configured to control the light emitting element LD according to the signal received through these signal lines. Figures 3A to 3E Describe the details.

[0118] Figure 3A is a circuit diagram illustrating a sub-pixel according to one or more embodiments of the present disclosure. Figure 3B is a circuit diagram illustrating a sub-pixel according to one or more other embodiments of the present disclosure. Figure 3Cis a circuit diagram illustrating a sub-pixel according to yet one or more other embodiments of the present disclosure. Figure 3D is a circuit diagram illustrating a sub-pixel according to still one or more other embodiments of the present disclosure. Figure 3E is a circuit diagram illustrating a sub-pixel according to still one or more other embodiments of the present disclosure.

[0119] For ease of description, Figures 3A to 3E A sub-pixel SPij located at an i-th horizontal line (or i-th pixel row) and contacting a j-th data line DLj is shown.

[0120] refer to Figure 3A , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0121] The sub-pixel circuit SPC may include first to seventh transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 , and first and second capacitors C1 and C2 .

[0122] exist Figure 3A , the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 are shown as P-type transistors, but are not limited thereto. For example, the third transistor T3 and the fourth transistor T4 may be N-type transistors.

[0123] At the same time, the P-type transistor can be turned on by a low-level scan signal and turned off by a high-level scan signal. In addition, the N-type transistor can be turned on by a high-level scan signal and turned off by a low-level scan signal.

[0124] A first electrode (or anode) of the light emitting element LD may be connected to the sixth transistor T6 , and a second electrode (or cathode) of the light emitting element LD may be connected to the second power supply VSS.

[0125] A first electrode (e.g., source electrode) of the first transistor T1 may be connected to a first power supply VDD, and a second electrode (e.g., drain electrode) of the first transistor T1 may contact a first electrode of the light-emitting element LD. The first transistor T1 may generate a drive current and may provide the drive current to the light-emitting element LD. A gate electrode of the first transistor T1 may be connected to a first node N1. The first transistor T1 may function as a drive transistor for the sub-pixel SPij. The first transistor T1 may control the amount of current flowing from the first power supply VDD to the second power supply VSS via the light-emitting element LD in response to a voltage applied to the first node N1.

[0126] The first capacitor C1 may be connected between the third node N3 and the first node N1 corresponding to the gate electrode of the first transistor T1. The first capacitor C1 may store a voltage corresponding to a voltage difference between the first node N1 and the third node N3.

[0127] The second capacitor C2 can be connected between the first power supply VDD and the third node N3. The second capacitor C2 can store a voltage corresponding to the voltage difference between the first power supply VDD and the third node N3. Since one electrode of the second capacitor C2 is connected to the first power supply VDD, which is a constant voltage source, and the other electrode is connected to the third node N3, during the self-scan period in which the data signal is not written, the second capacitor C2 can maintain the data signal (or data voltage) written to the third node N3 by the second transistor T2 during the display scan period. In other words, the second capacitor C2 can stabilize the voltage of the third node N3.

[0128] The second transistor T2 may be connected between the data line DLj and the third node N3. According to one or more embodiments, the second transistor T2 may include a 2_1th transistor and a 2_2th transistor connected in series. The second transistor T2 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the second transistor T2 may be connected to the first sub-scan line SL1i to receive the first scan signal. When the first scan signal is supplied to the first sub-scan line SL1i, the second transistor T2 may be turned on to electrically connect the data line DLj and the third node N3. Accordingly, the data signal (or data voltage) may be transmitted to the third node N3.

[0129] The third transistor T3 may be connected between the first node N1 and the second node N2. According to one or more embodiments, the third transistor T3 may include a 3_1 transistor and a 3_2 transistor connected in series. The third transistor T3 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the third transistor T3 may be connected to the second sub-scan line SL2i to receive the second scan signal. When the second scan signal is supplied to the second sub-scan line SL2i, the third transistor T3 may be turned on to electrically connect the first node N1 and the second node N2. By turning on the third transistor T3, the first transistor T1 may have a diode connection. When the first transistor T1 has a diode connection, changes in the threshold voltage of the first transistor T1 may be compensated.

[0130] The fourth transistor T4 can be connected between the fourth power supply VINT and the first node N1. The fourth transistor T4 according to one or more embodiments may include a 4_1th transistor and a 4_2th transistor connected in series. The fourth transistor T4 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the fourth transistor T4 may be connected to the third sub-scan line SL3i to receive the third scan signal. When the third scan signal is supplied to the third sub-scan line SL3i, the fourth transistor T4 may be turned on to electrically connect the fourth power supply VINT and the first node N1. Accordingly, the voltage of the fourth power supply VINT may be supplied to the first node N1. Therefore, the voltage of the first node N1 may be initialized to the voltage of the fourth power supply VINT.

[0131] The fifth transistor T5 may be connected between the third power supply VREF and the third node N3. According to one or more embodiments, the fifth transistor T5 may include a 5_1th transistor and a 5_2th transistor connected in series. The fifth transistor T5 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the fifth transistor T5 may be connected to the second sub-scan line SL2i to receive the second scan signal. When the second scan signal is supplied to the second sub-scan line SL2i, the fifth transistor T5 may be turned on to electrically connect the third power supply VREF and the third node N3. Accordingly, the voltage of the third power supply VREF may be supplied to the third node N3. Therefore, the voltage of the third node N3 may be initialized to the voltage of the third power supply VREF.

[0132] Meanwhile, since the gate electrodes of the third and fifth transistors T3 and T5 are connected to the same scan line (ie, the second sub-scan line SL2i), the third and fifth transistors T3 and T5 may be turned off or turned on concurrently or substantially simultaneously.

[0133] The sixth transistor T6 may be connected between the second node N2 and the fourth node N4. The sixth transistor T6 may include a gate electrode for receiving an emission control signal. For example, the gate electrode of the sixth transistor T6 may be connected to the first sub-emission control line EL1i to receive the first emission control signal. When the first emission control signal is supplied to the first sub-emission control line EL1i, the sixth transistor T6 may be turned off, and otherwise may be turned on. The sixth transistor T6 in the on state may electrically connect the second node N2 and the fourth node N4.

[0134] When the sixth transistor T6 is turned on, the light emitting element LD may emit light having brightness corresponding to the voltage of the first node N1.

[0135] The seventh transistor T7 can be connected between the fourth node N4 and the anode initialization power supply VAINT. The seventh transistor T7 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the seventh transistor T7 may be connected to the fourth sub-scan line SL4i to receive the fourth scan signal. When the fourth scan signal is supplied to the fourth sub-scan line SL4i, the seventh transistor T7 may be turned on to electrically connect the anode initialization power supply VAINT and the fourth node N4. Accordingly, the voltage of the fourth node N4 may be initialized to the voltage of the anode initialization power supply VAINT. When the voltage of the anode initialization power supply VAINT is supplied to the anode of the light-emitting element LD, the parasitic capacitor of the light-emitting element LD may be discharged. As the residual voltage charged in the parasitic capacitor is discharged (removed), undesirable micro-emissions may be reduced or prevented. Therefore, the black rendering capability of the sub-pixel SPij may be improved. At the same time, by separating the initialization operation of the gate electrode (or the first node N1) of the first transistor T1 and the initialization operation of the anode (or the fourth node N4) of the light-emitting element LD, the possibility of the light-emitting element LD inadvertently emitting light during the initialization operation of the gate electrode (or the first node N1) of the first transistor T1 can be reduced or prevented.

[0136] refer to Figure 3B , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0137] The sub-pixel circuit SPC may include first to eighth transistors T1 , T2 , T3 , T4 , T5 , T6 , T7 , and T8 , and first and second capacitors C1 and C2 .

[0138] A first electrode (or anode) of the light emitting element LD may be connected to the second node N2 (eg, via the fourth node N4 and the sixth transistor T6 ), and a second electrode (or cathode) of the light emitting element LD may be connected to the second power supply VSS.

[0139] A first electrode (e.g., source electrode) of the first transistor T1 may be connected to a first power supply VDD, and a second electrode (e.g., drain electrode) of the first transistor T1 may be connected to a first electrode of the light-emitting element LD. The first transistor T1 may generate a drive current and may provide the drive current to the light-emitting element LD. A gate electrode of the first transistor T1 may be connected to a first node N1. The first transistor T1 may function as a drive transistor for the sub-pixel SPij. The first transistor T1 may control the amount of current flowing from the first power supply VDD to the second power supply VSS via the light-emitting element LD in response to a voltage applied to the first node N1.

[0140] The first capacitor C1 may be connected between the first node N1 and the third node N3. The first capacitor C1 may store a voltage corresponding to a voltage difference between the first node N1 and the third node N3.

[0141] The second capacitor C2 can be connected between the first power supply VDD and the third node N3. The second capacitor C2 can store a voltage corresponding to the voltage difference between the first power supply VDD and the third node N3. Since one electrode of the second capacitor C2 is connected to the first power supply VDD, which is a constant voltage source, and the other electrode of the second capacitor C2 is connected to the third node N3, during the self-scan period in which the data signal is not written, the second capacitor C2 can maintain the data signal (or data voltage) written to the third node N3 by the second transistor T2 during the display scan period. In other words, the second capacitor C2 can stabilize the voltage of the third node N3.

[0142] The second transistor T2 may be connected between the data line DLj and the third node N3. According to one or more embodiments, the second transistor T2 may include a 2_1th transistor and a 2_2th transistor connected in series. The second transistor T2 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the second transistor T2 may be connected to the first sub-scan line SL1i to receive the first scan signal. When the first scan signal is supplied to the first sub-scan line SL1i, the second transistor T2 may be turned on to electrically connect the data line DLj and the third node N3. Accordingly, the data signal (or data voltage) may be transmitted to the third node N3.

[0143] The third transistor T3 may be connected between the first node N1 and the second node N2. According to one or more embodiments, the third transistor T3 may include a 3_1 transistor and a 3_2 transistor connected in series. The third transistor T3 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the third transistor T3 may be connected to the second sub-scan line SL2i to receive the second scan signal. When the second scan signal is supplied to the second sub-scan line SL2i, the third transistor T3 may be turned on to electrically connect the first node N1 and the second node N2. By turning on the third transistor T3, the first transistor T1 may have a diode connection. When the first transistor T1 has a diode connection, the threshold voltage of the first transistor T1 may be compensated.

[0144] The fourth transistor T4 may be connected between the third power supply VREF and the third node N3. According to one or more embodiments, the fourth transistor T4 may include a 4_1th transistor and a 4_2th transistor connected in series. The fourth transistor T4 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the fourth transistor T4 may be connected to the second sub-scan line SL2i to receive the second scan signal. When the second scan signal is supplied to the second sub-scan line SL2i, the fourth transistor T4 may be turned on to electrically connect the third power supply VREF and the third node N3. Accordingly, the voltage of the third power supply VREF may be supplied to the third node N3. Therefore, the voltage of the third node N3 may be initialized to the voltage of the third power supply VREF.

[0145] Meanwhile, since the gate electrodes of the third and fourth transistors T3 and T4 are connected to the same scan line (ie, the second sub-scan line SL2i), the third and fourth transistors T3 and T4 may be turned off or turned on concurrently or substantially simultaneously.

[0146] The fifth transistor T5 may be connected between the first power supply VDD and the fifth node N5. The fifth transistor T5 may include a gate electrode for receiving an emission control signal. For example, the gate electrode of the fifth transistor T5 may be connected to the first sub-emission control line EL1i to receive the first emission control signal. When the first emission control signal is supplied to the first sub-emission control line EL1i, the fifth transistor T5 may be turned off, and otherwise may be turned on. The fifth transistor T5 in the on state may connect the first electrode of the first transistor T1 to the first power supply VDD.

[0147] The sixth transistor T6 can be connected between the anode of the light-emitting element LD (or the fourth node N4) and the second node N2 corresponding to the second electrode of the first transistor T1. The sixth transistor T6 may include a gate electrode for receiving an emission control signal. For example, the gate electrode of the sixth transistor T6 may be connected to the second sub-emission control line EL2i to receive the second emission control signal. When the second emission control signal is supplied to the second sub-emission control line EL2i, the sixth transistor T6 may be turned off, and otherwise may be turned on. The sixth transistor T6 in the on state may electrically connect the second node N2 and the fourth node N4.

[0148] When both the fifth transistor T5 and the sixth transistor T6 are turned on, the light emitting element LD may emit light having brightness corresponding to the voltage of the first node N1.

[0149] In one or more embodiments, when the fifth transistor T5 is turned on and the sixth transistor T6 is turned off, threshold voltage compensation of the first transistor T1 may be performed.

[0150] The seventh transistor T7 can be connected between the first electrode (or fourth node N4) of the light-emitting element LD and the anode initialization power supply VAINT. The seventh transistor T7 may include a gate electrode for receiving an emission control signal. For example, the gate electrode of the seventh transistor T7 may be connected to the first sub-emission control line EL1i to receive the first emission control signal. When the first emission control signal is supplied to the first sub-emission control line EL1i, the seventh transistor T7 may be turned on to electrically connect the fourth power supply VINT and the fourth node N4. Accordingly, the voltage of the fourth node N4 (or the anode of the light-emitting element LD) may be initialized to the voltage of the fourth power supply VINT.

[0151] The eighth transistor T8 can be connected between the first electrode (or fifth node N5) of the first transistor T1 and the bias power supply VBS. The eighth transistor T8 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the eighth transistor T8 may be connected to the fourth sub-scan line SL4i to receive the fourth scan signal. When the fourth scan signal is supplied to the fourth sub-scan line SL4i, the eighth transistor T8 may be turned on to electrically connect the fifth node N5 and the bias power supply VBS. Using the eighth transistor T8, a bias can be periodically applied to the source electrode of the driving transistor (e.g., the first transistor T1) at a constant voltage. Therefore, the hysteresis deviation caused by the grayscale difference between adjacent pixels can be eliminated, and the screen dragging caused by this can be reduced (eliminated).

[0152] refer to Figure 3B , the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be implemented as N-type transistors. However, the embodiments of the present disclosure are not limited thereto. For example, at least one of the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be implemented as a P-type transistor, and at least one of the fifth transistor T5 and the sixth transistor T6 may be implemented as an N-type transistor.

[0153] refer to Figure 3C and Figure 3D , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0154] The sub-pixel circuit SPC may include first to ninth transistors T1 , T2 , T3 , T4 , T5 , T6 , T7 , T8 , and T9 , and first and second capacitors C1 and C2 .

[0155] Can be respectively Figure 3A The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the first capacitor C1, the second capacitor C2 and the light emitting element LD are similarly described. Figure 3C and Figure 3D The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the first capacitor C1, the second capacitor C2 and the light emitting element LD are shown in FIG.

[0156] The sixth transistor T6 can be connected between the first power supply VDD and the first electrode (or fifth node N5) of the first transistor T1. The sixth transistor T6 may include a gate electrode for receiving an emission control signal. For example, the gate electrode of the sixth transistor T6 may be connected to the first sub-emission control line EL1i to receive the first emission control signal. When the first emission control signal is supplied to the first sub-emission control line EL1i, the sixth transistor T6 may be turned off, and otherwise may be turned on. The sixth transistor T6 in the on state may connect the first electrode of the first transistor T1 to the first power supply VDD.

[0157] The seventh transistor T7 can be connected between the anode of the light-emitting element LD (or the fourth node N4) and the second node N2 corresponding to the second electrode of the first transistor T1. The seventh transistor T7 may include a gate electrode for receiving an emission control signal. For example, the gate electrode of the seventh transistor T7 may be connected to the second sub-emission control line EL2i to receive the second emission control signal. When the second emission control signal is supplied to the second sub-emission control line EL2i, the seventh transistor T7 may be turned off, and otherwise may be turned on. The seventh transistor T7 in the on state may electrically connect the second node N2 and the fourth node N4.

[0158] The ninth transistor T9 can be connected between the first electrode (or fifth node N5) of the first transistor T1 and the bias power supply VBS. The ninth transistor T9 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the ninth transistor T9 may be connected to the fourth sub-scan line SL4i to receive the fourth scan signal. When the fourth scan signal is supplied to the fourth sub-scan line SL4i, the ninth transistor T9 may be turned on to electrically connect the fifth node N5 and the bias power supply VBS. Using the ninth transistor T9, a bias may be periodically applied to the source electrode of the first transistor T1 at a constant voltage.

[0159] refer to Figure 3D , the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be implemented as N-type transistors. However, the embodiments of the present disclosure are not limited thereto. For example, at least one of the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be implemented as a P-type transistor.

[0160] According to one or more embodiments of the present disclosure, the third transistor T3 and the fourth transistor T4 of the sub-pixel SPij can be configured as N-type transistors, and thus, the first transistor T1 can be driven with improved reliability. For example, the third transistor T3 and the fourth transistor T4 of the sub-pixel SPij can be configured as N-type transistors, and thus, leakage current flowing through the first node N1 to which the gate electrode of the first transistor T1 is connected can be reduced or prevented. Accordingly, the voltage of the first node N1 can be kept relatively constant, and the reliability of driving the sub-pixel SPij can be improved.

[0161] refer to Figure 3E , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0162] The sub-pixel circuit SPC may include first to tenth transistors T1 , T2 , T3 , T4 , T5 , T6 , T7 , T8 , T9 , and T10 , and first and second capacitors C1 and C2 .

[0163] Can be respectively Figure 3C The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the first capacitor C1, the second capacitor C2 and the light emitting element LD are similarly described. Figure 3E a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, a second capacitor C2 and a light emitting element LD.

[0164] The seventh transistor T7 can be connected between the anode of the light-emitting element LD (or the fourth node N4) and the second node N2 corresponding to the second electrode of the first transistor T1. The seventh transistor T7 may include a gate electrode for receiving an emission control signal. For example, the gate electrode of the seventh transistor T7 may be connected to the first sub-emission control line EL1i to receive the first emission control signal. When the first emission control signal is supplied to the first sub-emission control line EL1i, the seventh transistor T7 may be turned off, and otherwise may be turned on. The seventh transistor T7 in the on state may electrically connect the second node N2 and the fourth node N4. However, embodiments of the present disclosure are not limited thereto. For example, the gate electrode of the seventh transistor T7 may be connected to the second sub-emission control line EL2i to receive the second emission control signal.

[0165] The tenth transistor T10 may be connected between the first power supply VDD and the fifth node N5. The tenth transistor T10 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the tenth transistor T10 may be connected to the second sub-scan line SL2i to receive the second scan signal. When the second scan signal is supplied to the second sub-scan line SL2i, the tenth transistor T10 may be turned on to electrically connect the fifth node N5 to the first power supply VDD.

[0166] at the same time, Figures 3A to 3E Each of the first to tenth transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, and T10 may include an amorphous silicon semiconductor, a single crystal silicon semiconductor, a polycrystalline silicon semiconductor, an oxide semiconductor, or the like.

[0167] For example, a transistor including an N-type semiconductor layer may include a polysilicon semiconductor. However, the embodiments of the present disclosure are not limited thereto.

[0168] For example, a transistor including a P-type semiconductor layer may include an oxide semiconductor. The oxide semiconductor may include, for example, a metal oxide semiconductor. However, the embodiments of the present disclosure are not limited thereto.

[0169] In one or more embodiments in which a subpixel includes both a transistor including an N-type semiconductor layer and a transistor including a P-type semiconductor layer, the P-type semiconductor layer and the N-type semiconductor layer may be formed in different layers. For example, the N-type semiconductor layer may be formed first, and the P-type semiconductor layer may be formed in a subsequent process. However, embodiments of the present disclosure are not limited thereto.

[0170] Figure 4 The diagram is based on Figure 3E The waveform diagram of the operation of the display scan period of one or more embodiments of the pixel shown in FIG. Figure 3E The present disclosure is described with reference to the pixels shown in FIG. However, the present disclosure is not limited thereto.

[0171] refer to Figure 3E and Figure 4 , the sub-pixel SPij can receive a signal for image display during a display scan period DSP. The display scan period DSP may include a period in which a data signal DV corresponding to an output image is written. For example, the sub-pixel SPij located in the i-th row and the j-th column can receive a data signal DV from the data line DLj.

[0172] The first emission control signal EM1[i] may be supplied to the first sub-emission control line EL1i, and the first to fourth scan signals GW[i], GC[i], GI[i], and GB[i] may be supplied to the first to fourth sub-scan lines SL1i, SL2i, SL3i, and SL4i, respectively.

[0173] At the first time point tm1, the first emission control signal EM1[i] may be changed from a gate-on level to a gate-off level. Accordingly, the sixth transistor T6 and the seventh transistor T7 may be turned off.

[0174] In the first period P1 (e.g., between the second time point tm2 and the third time point tm3), the third scan signal GI[i] may be changed from a gate-off level to a gate-on level. Accordingly, the fourth transistor T4 may be turned on. Accordingly, the voltage of the fourth power supply VINT may be supplied to the first node N1 (or the gate electrode of the first transistor T1), and the first node N1 may be initialized to the voltage of the fourth power supply VINT.

[0175] In the second period P2 (e.g., between the third time point tm3 and the fourth time point tm4), the second scan signal GC[i] may be changed from the gate-off level to the gate-on level. Accordingly, the third transistor T3 may be turned on. However, because the first emission control signal EM1[i] maintains the gate-off level and the seventh transistor T7 remains in the off state, the possibility of the fourth power supply VINT supplied to the first node N1 also being supplied to the fourth node N4 can be reduced or prevented, thereby reducing or preventing the possibility of the light-emitting element LD accidentally emitting light.

[0176] In addition, the fifth transistor T5 may be turned on by the second scan signal GC[i] of the gate-on level in the second period P2. Accordingly, the voltage of the third power supply VREF may be supplied to the third node N3 and initialized to the voltage of the third power supply VREF.

[0177] In the second period P2, the tenth transistor T10 may be turned on by the second scan signal GC[i] of the gate-on level. Accordingly, the voltage of the first power supply VDD may be supplied to the fifth node N5. However, because the first emission control signal EM1[i] is at the gate-off level and the seventh transistor T7 is in the off state, the light-emitting element LD may not emit light.

[0178] In the third period P3 (e.g., between the fourth time point tm4 and the fifth time point tm5), the third scan signal GI[i] may be changed from the gate-off level to the gate-on level. Accordingly, the fourth transistor T4 may be turned on. Accordingly, the voltage of the fourth power supply VINT may be supplied to the first node N1 (or the gate electrode of the first transistor T1), and the first node N1 may be initialized to the voltage of the fourth power supply VINT.

[0179] In the fourth period P4 (e.g., between the fifth time point tm5 and the sixth time point tm6), the second scan signal GC[i] may be changed from the gate-off level to the gate-on level. Accordingly, the third transistor T3 may be turned on. However, because the first emission control signal EM1[i] maintains the gate-off level, the seventh transistor T7 remains in the off state, thereby reducing or preventing the voltage of the fourth power supply VINT supplied to the first node N1 from being supplied to the fourth node N4, thereby reducing or preventing the light-emitting element LD from unintentionally emitting light.

[0180] In addition, the fifth transistor T5 may be turned on by the second scan signal GC[i] of the gate-on level in the fourth period P4. Accordingly, the voltage of the third power supply VREF may be supplied to the third node N3 and initialized to the voltage of the third power supply VREF.

[0181] In the fourth period P4, the tenth transistor T10 may be turned on by the second scan signal GC[i] of the gate-on level. Accordingly, the voltage of the first power supply VDD may be supplied to the fifth node N5. However, because the first emission control signal EM1[i] is at the gate-off level, the seventh transistor T7 is in the off state, and the light-emitting element LD may not emit light.

[0182] At the sixth time point tm6, the second scan signal GC[i] may be changed from the gate-on level to the gate-off level. Accordingly, the third transistor T3, the fifth transistor T5, and the tenth transistor T10 may be turned off.

[0183] At the seventh time point tm7, the first scan signal GW[i] may be changed from the gate-off level to the gate-on level. Accordingly, the second transistor T2 may be turned on. The second transistor T2 may remain in the on state during the fifth period P5. Accordingly, the i-th data signal DV[i] may be supplied to the third node N3 during the fifth period P5. Between the sixth time point tm6 and the seventh time point tm7, the data signal DV[i-1] written to the i-1-th pixel row may be supplied to the data line DLj.

[0184] The change in the voltage of the third node N3 (i.e., "DATA-VREF") can be reflected in the first node N1 through the first capacitor C1. Therefore, the voltage of the first node N1 can become "VDD-Vth+(DATA-VREF)". Here, DATA may be a voltage corresponding to the data signal DV[i], VREF may be a voltage of the third power supply, VDD may be a voltage of the first power supply, and Vth may be a threshold voltage of the first transistor T1.

[0185] Accordingly, the data signal DV[i] can be Figure 4 The data is written into the sub-pixel SPij during the fifth period P5 from the seventh time point tm7 to the eighth time point tm8 shown in FIG. That is, the fifth period P5 may be a data writing period.

[0186] In one or more embodiments, the length of the fifth period P5 (i.e., the length (pulse width) of the first scanning signal GW[i]) may be one horizontal period (1H). However, the length of the first scanning signal GW[i] is not limited thereto. For example, the length of the first scanning signal GW[i] may be two horizontal periods (2H) or more.

[0187] At the eighth time point tm8, the first scan signal GW[i] may be changed from the gate-on level to the gate-off level, and accordingly, the second transistor T2 may be turned off.

[0188] Between the eighth time point tm8 and the ninth time point tm9, the fourth scan signal GB[i] may transition from the gate-off level to the gate-on level. In other words, the fourth scan signal GB[i] may transition from the gate-off level to the gate-on level during the sixth period P6. Accordingly, the eighth transistor T8 may be turned on, and thus, the voltage of the anode initialization power supply VAINT may be supplied to the fourth node N4. In other words, the anode initialization of the light-emitting element LD may be performed during the sixth period P6.

[0189] In addition, the ninth transistor T9 may be turned on, and thus the voltage of the bias power supply VBS may be supplied to the fifth node N5 (or the source electrode of the first transistor T1). Therefore, the voltage of the bias power supply VBS may be supplied to the first electrode (or source electrode) of the first transistor T1.

[0190] Accordingly, the on-bias can be Figure 4 The sixth period P6 from the eighth time point tm8 to the ninth time point tm9 shown in FIG is applied to the first transistor T1. That is, the sixth period P6 may be a conduction bias period.

[0191] At the ninth time point tm9, the fourth scan signal GB[i] may be changed from the gate-on level to the gate-off level. Accordingly, the eighth transistor T8 and the ninth transistor T9 may be turned off.

[0192] By applying the on-bias to the first transistor T1 in the sixth period P6 , the hysteresis characteristic (ie, the variation of the threshold voltage) of the first transistor T1 may be improved.

[0193] At the ninth time point tm9, the first emission control signal EM1[i] may be changed from the gate-off level to the gate-on level. Accordingly, the sixth transistor T6 may be turned on, and thus, the first electrode (e.g., source electrode) of the first transistor T1 may be connected to the first power supply VDD. In addition, since the seventh transistor T7 may be turned on, the sub-pixel SPij may be turned on. Figure 4 The CMOS device emits light in a seventh period P7 after the ninth time point tm9 shown in FIG. That is, the seventh period P7 may be an emission period.

[0194] Figure 5 Observed from above Figure 2 Schematic plan view of a display panel. Figure 6 The diagram is included in the Figure 5 A plan view of an example of a semiconductor layer in a pixel in a display panel. Figure 7 The diagram is included in the Figure 5 A plan view of an example of a first conductive layer in a pixel in a display panel. Figure 8 The diagram is included in the Figure 5 A plan view of an example of a second conductive layer in a pixel in a display panel. Figure 9 The diagram is included in the Figure 5 A plan view of an example of a third conductive layer in a pixel in a display panel. Figure 10 The diagram is included in the Figure 5 A plan view of an example of a fourth conductive layer in a pixel in a display panel. Figure 11 The diagram is included in the Figure 5 A plan view of an example of a fifth conductive layer in a pixel in a display panel of FIG.

[0195] refer to Figure 5 The display panel 100 may include a first sub-pixel SPa (or a first sub-pixel region SPAa), a second sub-pixel SPb (or a second sub-pixel region SPAb), and a third sub-pixel SPc (or a third sub-pixel region SPAc). The first sub-pixel SPa, the second sub-pixel SPb, and the third sub-pixel SPc may form a unit pixel.

[0196] According to one or more embodiments, the first to third sub-pixels SPa, SPb and SPc may emit light of different colors. For example, the first sub-pixel SPa may be a red pixel that emits red light, the second sub-pixel SPb may be a green pixel that emits green light, and the third sub-pixel SPc may be a blue pixel that emits blue light. However, the color, type and / or number of sub-pixels constituting a unit pixel are not particularly limited, and for example, the color of light emitted by each of the sub-pixels may be variously changed. According to one or more embodiments, the first to third sub-pixels SPa, SPb and SPc may generate light of the same wavelength band, and may be configured to emit light of various wavelengths through external configuration (e.g., a color filter, etc.).

[0197] The first to third sub-pixels SPa, SPb, and SPc (or the pixel driving circuits of the first to third sub-pixels SPa, SPb, and SPc) may be formed to be substantially identical or similar to each other. Hereinafter, the present disclosure will be described based on the first sub-pixel SPa, and the description of the first sub-pixel SPa may also be applied to the second and third sub-pixels SPb and SPc. Repeated descriptions will be omitted.

[0198] The first subpixel SPa (or the subpixel circuit of the first subpixel SPa) may include a semiconductor layer ACT, a first conductive layer GAT1 (or a first gate layer), a second conductive layer GAT2 (or a second gate layer), a third conductive layer GAT3 (or a third gate layer), a fourth conductive layer SD1, and a fifth conductive layer SD2. The semiconductor layer ACT, the first conductive layer GAT1, the second conductive layer GAT2, the third conductive layer GAT3, the fourth conductive layer SD1, and the fifth conductive layer SD2 may be formed in different layers through different processes.

[0199] The semiconductor layer ACT, the first conductive layer GAT1, the second conductive layer GAT2, the third conductive layer GAT3, the fourth conductive layer SD1 and the fifth conductive layer SD2 may constitute the above-mentioned sub-pixel circuit SPC (refer to Figure 3E ).

[0200] refer to Figure 5 and Figure 6The semiconductor layer ACT may be an active layer that forms channels of the first to tenth transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, and T10. The semiconductor layer ACT may include a source region (or first region) that contacts a first electrode (e.g., a source electrode) of each of the first to tenth transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, and T10, and a drain region (or second region) that contacts a second electrode (e.g., a drain electrode). The region between the source region and the drain region may be a channel region. The channel region of the semiconductor layer ACT may be a semiconductor pattern that is not doped with impurities and may be an intrinsic semiconductor. The source region and the drain region may be semiconductor patterns doped with impurities.

[0201] The semiconductor layer ACT may include a first semiconductor pattern group ACT1 and a second semiconductor pattern group ACT2 .

[0202] refer to Figure 6 The first semiconductor pattern group ACT1 may include a first dummy portion ACT_DM1, a second semiconductor pattern ACT_T2, and a fifth semiconductor pattern ACT_T5. The second semiconductor pattern ACT_T2 may constitute a channel of the second transistor T2, and the fifth semiconductor pattern ACT_T5 may constitute a channel of the fifth transistor T5.

[0203] The first dummy portion ACT_DM1 may extend in the first direction DR1 and may be positioned adjacent to one side of the first sub-pixel area SPAa. The first dummy portion ACT_DM1 may extend continuously in the first sub-pixel area SPAa, the second sub-pixel area SPAb, and the third sub-pixel area SPAc. The first dummy portion ACT_DM1 may connect the first semiconductor pattern group ACT1 of each of the first sub-pixel SPa, the second sub-pixel SPb, and the third sub-pixel SPc to each other in the first direction DR1.

[0204] The second semiconductor pattern group ACT2 may include a second dummy portion ACT_DM2 , first, third, fourth, sixth, seventh, eighth, ninth, and tenth semiconductor patterns ACT_T10 .

[0205] The second dummy portion ACT_DM2 may extend in the first direction DR1 and may be positioned adjacent to the other side of the first sub-pixel area SPAa. The second dummy portion ACT_DM2 may extend continuously in the first sub-pixel area SPAa, the second sub-pixel area SPAb, and the third sub-pixel area SPAc. The second dummy portion ACT_DM2 may connect the second semiconductor pattern group ACT2 of each of the first sub-pixel SPa, the second sub-pixel SPb, and the third sub-pixel SPc to each other in the first direction DR1.

[0206] The first semiconductor pattern ACT_T1 may constitute a channel of the first transistor T1. The third semiconductor pattern ACT_T3 may constitute a channel of the third transistor T3. The fourth semiconductor pattern ACT_T4 may constitute a channel of the fourth transistor T4. The sixth semiconductor pattern ACT_T6 may constitute a channel of the sixth transistor T6. The seventh semiconductor pattern ACT_T7 may constitute a channel of the seventh transistor T7. The eighth semiconductor pattern ACT_T8 may constitute a channel of the eighth transistor T8. The ninth semiconductor pattern ACT_T9 may constitute a channel of the ninth transistor T9. The tenth semiconductor pattern ACT_T10 may constitute a channel of the tenth transistor T10.

[0207] refer to Figure 3E 、 Figure 5 and Figure 6 , a portion at which the first semiconductor pattern ACT_T1, the third semiconductor pattern ACT_T3, and the seventh semiconductor pattern ACT_T7 are connected may be configured as a second node N2. A portion at which the seventh semiconductor pattern ACT_T7 and the eighth semiconductor pattern ACT_T8 are connected may be configured as a fourth node N4. A portion at which the first semiconductor pattern ACT_T1, the sixth semiconductor pattern ACT_T6, and the ninth semiconductor pattern ACT_T9 are connected may be configured as a fifth node N5.

[0208] refer to Figures 5 to 7 , the first conductive layer GAT1 may include a 1_1th capacitor electrode C1_E1, gate patterns GE_T2, GE_T3, GE_T4, GE_T5, GE_T6, GE_T7, GE_T8, GE_T9, and GE_T10 of the second to tenth transistors T2 to T10, and a fourth sub-scan line SL4i.

[0209] The 1_1th capacitor electrode C1_E1 may have a corresponding area, may be located approximately at the center of the first sub-pixel area SPAa, and may overlap the first semiconductor pattern ACT_T1. According to one or more embodiments, the 1_1th capacitor electrode C1_E1 may constitute the gate pattern GE_T1 of the first transistor T1.

[0210] The gate pattern GE_T2 of the second transistor T2 may extend in the first direction DR1, may branch in the second direction DR2, and may overlap with a channel region formed in the second semiconductor pattern ACT_T2. For example, a portion of the gate pattern GE_T2 of the second transistor T2 extending in the first direction DR1 may overlap with a channel region formed in the second semiconductor pattern ACT_T2 to constitute a gate electrode of the second transistor T2.

[0211] The gate pattern GE_T3 of the third transistor T3 may extend in the first direction DR1, may branch in the second direction DR2, and may overlap with a channel region formed in the third semiconductor pattern ACT_T3. For example, a portion of the gate pattern GE_T3 of the third transistor T3 that branches in the second direction DR2 may overlap with a channel region formed in the third semiconductor pattern ACT_T3 to constitute a gate electrode of the third transistor T3.

[0212] The gate pattern GE_T4 of the fourth transistor T4 may extend in a direction opposite to the first direction DR1, may branch in the second direction DR2, and may overlap with a channel region formed in the fourth semiconductor pattern ACT_T4. For example, a portion of the gate pattern GE_T4 of the fourth transistor T4 that branches in the second direction DR2 may overlap with a channel region formed in the fourth semiconductor pattern ACT_T4 to constitute a gate electrode of the fourth transistor T4.

[0213] like Figure 7 As shown in FIG, the gate pattern GE_T5 of the fifth transistor T5 and the gate pattern GE_T10 of the tenth transistor T10 may be integrally formed. However, the present disclosure is not limited thereto.

[0214] The gate pattern GE_T5 of the fifth transistor T5 may extend in the first direction DR1, may branch in the second direction DR2, and may overlap with the channel region formed in the fifth semiconductor pattern ACT_T5. For example, a portion of the gate pattern GE_T5 of the fifth transistor T5 that branches in the second direction DR2 may overlap with the channel region formed in the fifth semiconductor pattern ACT_T5 to constitute the gate electrode of the fifth transistor T5.

[0215] The gate pattern GE_T10 of the tenth transistor T10 may extend in the first direction DR1, may branch in a direction opposite to the second direction DR2, and may overlap with a channel region formed in the tenth semiconductor pattern ACT_T10. For example, a portion of the gate pattern GE_T10 of the tenth transistor T10 that branches in a direction opposite to the second direction DR2 may overlap with the channel region formed in the tenth semiconductor pattern ACT_T10 to constitute a gate electrode of the tenth transistor T10.

[0216] like Figure 7 As shown in FIG, the gate pattern GE_T6 of the sixth transistor T6 and the gate pattern GE_T7 of the seventh transistor T7 may be integrally formed. However, the present disclosure is not limited thereto.

[0217] The gate pattern GE_T6 of the sixth transistor T6 may extend in the first direction DR1 and may overlap with the channel region formed in the sixth semiconductor pattern ACT_T6. For example, one end of the gate pattern GE_T6 of the sixth transistor T6 extending in the first direction DR1 may overlap with the channel region formed in the sixth semiconductor pattern ACT_T6 to constitute the gate electrode of the sixth transistor T6.

[0218] The gate pattern GE_T7 of the seventh transistor T7 may extend from the gate pattern GE_T6 of the sixth transistor T6 in a direction opposite to the first direction DR1 and may overlap with a channel region formed in the seventh semiconductor pattern ACT_T7. For example, the other end of the gate pattern GE_T7 of the seventh transistor T7 extending in a direction opposite to the first direction DR1 may overlap with a channel region formed in the seventh semiconductor pattern ACT_T7 to constitute a gate electrode of the seventh transistor T7.

[0219] like Figure 7 As shown in FIG, the gate pattern GE_T8 of the eighth transistor T8 and the gate pattern GE_T9 of the ninth transistor T9 may be integrally formed. However, the present disclosure is not limited thereto.

[0220] The gate pattern GE_T8 of the eighth transistor T8 may extend in a direction opposite to the first direction DR1 and may overlap with a channel region formed in the eighth semiconductor pattern ACT_T8. For example, one end of the gate pattern GE_T8 of the eighth transistor T8 extending in a direction opposite to the first direction DR1 may overlap with a channel region formed in the eighth semiconductor pattern ACT_T8 to constitute a gate electrode of the eighth transistor T8.

[0221] The gate pattern GE_T9 of the ninth transistor T9 may extend in the first direction DR1 and may overlap with the channel region formed in the ninth semiconductor pattern ACT_T9. For example, one end of the gate pattern GE_T9 of the ninth transistor T9 extending from the gate pattern GE_T8 of the eighth transistor T8 in the first direction DR1 may overlap with the channel region formed in the ninth semiconductor pattern ACT_T9 to constitute the gate electrode of the ninth transistor T9.

[0222] The fourth sub-scan line SL4i may extend in the first direction DR1. The fourth sub-scan line SL4i may be integrally formed with the gate pattern GE_T8 of the eighth transistor T8 and the gate pattern GE_T9 of the ninth transistor T9. However, the fourth sub-scan line SL4i is not limited to the present disclosure. Accordingly, refer to Figure 3E The gate electrode of the eighth transistor T8 may receive the fourth scan signal GB[i] from the fourth sub-scan line SL4i. In addition, the gate electrode of the ninth transistor T9 may receive the fourth scan signal GB[i] from the fourth sub-scan line SL4i.

[0223] The first conductive layer GAT1 may include one or more metals selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer GAT1 may have a single-layer or multi-layer structure, and for example, the first conductive layer GAT1 may have a single-layer structure including molybdenum (Mo).

[0224] refer to Figures 5 to 8 The second conductive layer GAT2 may include a 1_2nd capacitor electrode C1_E2, a 2_1st capacitor electrode C2_E1, a fifth power line PL5a, and a repair line RP. The 1_2nd capacitor electrode C1_E2 and the 2_1st capacitor electrode C2_E1 may be integrally configured, but are not limited thereto.

[0225] The 1_2 th capacitor electrode C1_E2 may overlap with the 1_1 th capacitor electrode C1_E1 and may constitute the first capacitor C1 together with the 1_1 th capacitor electrode C1_E1 (refer to Figure 3E The 2_1st capacitor electrode C2_E1 may constitute a second capacitor C2 (refer to Figure 3E ) an electrode.

[0226] The 1_2nd capacitor electrode C1_E2 and / or the 2_1st capacitor electrode C2_E1 may include or define a first opening OP1. Accordingly, the fourth bridge pattern BRP4 (to be described later) and the 1_1st capacitor electrode C1_E1 or the gate pattern GE_T1 of the first transistor T1 may contact each other through the first opening OP1. Figure 10 This is described in detail.

[0227] The fifth power line PL5a may extend in the first direction DR1. The fifth power line PL5a may be connected to one electrode of the ninth transistor T9 through a contact hole. Accordingly, the voltage of the bias power supply VBS may be supplied to the ninth transistor T9 through the fifth power line PL5a.

[0228] The repair line RP may extend in the first direction DR1. The repair line RP may be connected to each of the plurality of sub-pixels SP (refer to FIG. 1 ). For example, the repair line RP may extend in the first direction DR1 and may be connected to the light emitting element LD of each of the first sub-pixel SPa, the second sub-pixel SPb, and the third sub-pixel SPc (refer to FIG. 1 ). Figure 3E ). Accordingly, even if an abnormality occurs in a circuit of one of the plurality of sub-pixels SP (for example, the first sub-pixel SPa) (for example, a short circuit of the 1_1th power line PL1a), the repair line RP can apply a voltage (for example, a predetermined voltage) to the anode electrode of the light-emitting element LD of the first sub-pixel SPa, so that the light-emitting element LD of the first sub-pixel SPa emits light.

[0229] refer to Figures 5 to 9 The third conductive layer GAT3 may include a 1_1st power line PL1a, a third power line PL3a, and a 2_2nd capacitor electrode C2_E2. The 1_1st power line PL1a and the 2_2nd capacitor electrode C2_E2 may be integrally configured, but are not limited thereto.

[0230] The 1_1st power line PL1a may extend in the first direction DR1. The 1_1st power line PL1a may overlap with the 2_1st capacitor electrode C2_E1 and constitute the second capacitor C2 together with the 2_1st capacitor electrode C2_E1 (refer to FIG. 1 ). Figure 3E The area of the 1_1st power line PL1a may be larger than the areas of the 1_2nd capacitor electrode C1_E2 and the 2_1st capacitor electrode C2_E1, and may cover the 1_2nd capacitor electrode C1_E2 and the 2_1st capacitor electrode C2_E1.

[0231] Meanwhile, the 1_1st power line PL1a may include / define a second opening OP2 overlapping the first opening OP1. Accordingly, the fourth bridge pattern BRP4 (to be described later) and the 1_1st capacitor electrode C1_E1 or the gate pattern GE_T1 of the first transistor T1 may contact each other through the first opening OP1 and the second opening OP2. Figure 10 This is described in detail.

[0232] In addition, the 1_1th power line PL1a may include / define the third opening OP3. Accordingly, the second bridge pattern BRP2 and the 2_1th capacitor electrode C2_E1, which will be described later, may be in contact. Figure 10 This is described in detail.

[0233] The 2_2nd capacitor electrode C2_E2 may overlap with the 2_1st capacitor electrode C2_E1 and may constitute a second capacitor C2 together with the 2_1st capacitor electrode C2_E1 (refer to Figure 3E ).

[0234] The third power line PL3a may extend in the first direction DR1 and may be connected to one electrode of the fourth transistor T4 through a contact hole. Accordingly, the fourth transistor T4 may be supplied with the voltage of the fourth power source VINT through the third power line PL3a.

[0235] refer to Figures 5 to 10 The fourth conductive layer SD1 may include first to third sub-scan lines SL1i, SL2i and SL3i, first and second sub-emission control lines EL1i and EL2i, 2_1st power lines PL2a, 4_1st power lines PL4a, first to fifth bridge patterns BRP1, BRP2, BRP3, BRP4 and BRP5, and a connecting electrode CGE.

[0236] The first sub-scan line SL1i may extend in the first direction DR1. The first sub-scan line SL1i may be connected to the gate pattern GE_T2 of the second transistor T2 through a contact hole. Figure 3E , the gate electrode of the second transistor T2 may receive the first scan signal GW[i] from the first sub-scan line SL1i. In other words, the gate electrode of the second transistor T2, at which the semiconductor pattern ACT_T2 of the second transistor T2 and the gate pattern GE_T2 of the second transistor T2 overlap, may contact the first sub-scan line SL1i extending in the first direction DR1, and the second transistor T2 may receive the first scan signal GW[i].

[0237] The second sub-scan line SL2i may extend in the first direction DR1. The second sub-scan line SL2i may be connected to the gate pattern GE_T3 of the third transistor T3 through a contact hole, and may be connected to the gate pattern GE_T5 of the fifth transistor T5 through a contact hole. Figure 3E, the gate electrode of the third transistor T3 may receive the second scan signal GC[i] from the second sub-scan line SL2i. In other words, the gate electrode of the third transistor T3, at which the semiconductor pattern ACT_T3 of the third transistor T3 and the gate pattern GE_T3 of the third transistor T3 overlap, may contact the second sub-scan line SL2i extending in the first direction DR1 and may be located in the lower end portion of the display panel 100, and the third transistor T3 may receive the second scan signal GC[i]. In addition, the gate electrode of the fifth transistor T5 may receive the second scan signal GC[i] from the second sub-scan line SL2i. In other words, the gate electrode of the fifth transistor T5, at which the semiconductor pattern ACT_T5 of the fifth transistor T5 and the gate pattern GE_T5 of the fifth transistor T5 overlap, may contact the second sub-scan line SL2i extending in the first direction DR1 and may be located in the upper end portion of the display panel 100, and the fifth transistor T5 may receive the second scan signal GC[i].

[0238] The third sub-scan line SL3i may extend in the first direction DR1. The third sub-scan line SL3i may be connected to the gate pattern GE_T4 of the fourth transistor T4 through the contact hole. Figure 3E , the gate electrode of the fourth transistor T4 may receive the third scan signal GI[i] from the third sub-scan line SL3i. In other words, the gate electrode of the fourth transistor T4, at which the semiconductor pattern ACT_T4 of the fourth transistor T4 and the gate pattern GE_T4 of the fourth transistor T4 overlap, may contact the third sub-scan line SL3i extending in the first direction DR1, and the fourth transistor T4 may receive the third scan signal GI[i].

[0239] The first sub-emission control line EL1i may extend in the first direction DR1. The first sub-emission control line EL1i may be connected to each of the gate pattern GE_T6 of the sixth transistor T6 and the gate pattern GE_T7 of the seventh transistor T7 through a contact hole. Figure 3E , the gate electrode of the sixth transistor T6 may receive the first emission control signal EM1[i] from the first sub-emission control line EL1i. In other words, the gate electrode of the sixth transistor T6, at which the semiconductor pattern ACT_T6 of the sixth transistor T6 and the gate pattern GE_T6 of the sixth transistor T6 overlap, may contact the first sub-emission control line EL1i extending in the first direction DR1, and the sixth transistor T6 may receive the first sub-emission control signal EM1[i].

[0240] In addition, the gate electrode of the seventh transistor T7 can receive the first emission control signal EM1[i] from the first sub-emission control line EL1i. In other words, the gate electrode of the seventh transistor T7, where the semiconductor pattern ACT_T7 of the seventh transistor T7 and the gate pattern GE_T7 of the seventh transistor T7 overlap, extends in the first direction DR1. The seventh transistor T7 is in contact with the first sub-emission control line EL1i and can receive the first emission control signal EM1[i].

[0241] The 2_1st power line PL2a may extend in the first direction DR1 and may be connected to one electrode of the fifth transistor T5 through a contact hole.

[0242] The 4_1st power line PL4a may extend in the first direction DR1. The 4_1st power line PL4a may be connected to one electrode of the eighth transistor T8 through a contact hole. Accordingly, the voltage of the anode initialization power supply VAINT may be supplied to the eighth transistor T8 through the 4_1st power line PL4a.

[0243] The first bridge pattern BRP1 may overlap with one electrode of the second transistor T2 and may contact one electrode of the second transistor T2 through a contact hole. Furthermore, the first bridge pattern BRP1 may contact a data line DLj formed of the fourth conductive layer SD2 through a contact hole. In other words, the first bridge pattern BRP1 may connect one electrode of the second transistor T2 and the data line DLj.

[0244] The second bridge pattern BRP2 may extend in the second direction DR2 and may overlap with a portion of the first semiconductor pattern group ACT1, each of the 1_2 capacitor electrode C1_E2, and the 2_1 capacitor electrode C2_E1. The second bridge pattern BRP2 may contact a portion of the first semiconductor pattern group ACT1 through the contact hole and may be connected to each of one electrode of the second transistor T2 and one electrode of the fifth transistor T5. In addition, the second bridge pattern BRP2 may contact each of the 1_2 capacitor electrode C1_E2 and the 2_1 capacitor electrode C2_E1 exposed by the third opening OP3 formed in the 1_1 power line PL1a. That is, the second bridge pattern BRP2 may constitute Figure 3E The third node N3.

[0245] The third bridge pattern BRP3 may overlap each of the 1_1th power line PL1a and one electrode of the third transistor T3. For example, the third bridge pattern BRP3 may include a 3_1th bridge pattern BRP3_1 located at the right end of the first subpixel SPa and a 3_2th bridge pattern BRP3_2 located at the left end of the first subpixel SPa. In this case, the 3_1th bridge pattern BRP3_1 may overlap with the 1_1th power line PL1a through a contact hole, and the 3_2nd bridge pattern BRP3_2 may overlap with one electrode of the third transistor T3 through a contact hole.

[0246] The fourth bridge pattern BRP4 can connect the gate electrode (or gate pattern GE_T1) of the first transistor T1, the 1_1 capacitor electrode C1_E1, the third transistor T3, and one electrode of the fourth transistor T4. For example, one end of the fourth bridge pattern BRP4 can contact the gate pattern GE_T1 of the first transistor T1 through the first opening OP1 of the second conductive layer GAT2 and the second opening OP2 of the third conductive layer GAT3. In addition, the other end extending from one end of the fourth bridge pattern BRP4 in a direction opposite to the second direction DR2 can contact the semiconductor pattern ACT_T3 of the third transistor T3 and the semiconductor pattern ACT_T4 of the fourth transistor T4. Accordingly, the fourth bridge pattern BRP4 can connect the gate electrode of the first transistor T1, one electrode of the first capacitor C1, and one electrode of the third transistor T3 and the fourth transistor T4. That is, the fourth bridge pattern BRP4 can constitute Figure 3E The first node N1.

[0247] The fifth bridge pattern BRP5 can connect one electrode of the seventh transistor T7 and the anode of the light emitting element LD. For example, the fifth bridge pattern BRP5 can contact the active pattern ACT_T7 of the seventh transistor T7 and can connect the anode of the light emitting element LD. That is, the fifth bridge pattern BRP5 can constitute Figure 3E The fourth node N4.

[0248] The connection electrode CGE may extend in the first direction DR1 to overlap with the second sub-pixel SPb and the third sub-pixel SPc. The connection electrode CGE may extend in the first direction DR1 and may contact the sixth semiconductor pattern ACT_T6 of each of the second sub-pixel SPb and the third sub-pixel SPc through a contact hole. For example, one end of the connection electrode CGE may contact the sixth semiconductor pattern ACT_T6 of the second sub-pixel SPb, and the other end extending from the one end of the connection electrode CGE in the first direction DR1 may contact the sixth semiconductor pattern ACT_T6 of the third sub-pixel SPc. At this time, one end of the connection electrode CGE may contact the second portion PL1b of the 1_2 power line PL1b (see Figure 11 ), and the sixth transistor T6 of the second sub-pixel SPb can receive the voltage of the first power supply VDD through the connection electrode CGE. Correspondingly, the sixth transistor T6 of the third sub-pixel SPc can receive the voltage of the first power supply VDD through the other end of the connection electrode CGE.

[0249] refer to Figures 5 to 11 The fifth conductive layer SD2 may include a sixth bridge pattern BRP6, first to third data lines DLj, DLj+1, and DLj+2, a 1_2nd power line PL1b, a 2_2nd power line PL2b, and a 4_2nd power line PL4b.

[0250] refer to Figure 10 and Figure 11 The fourth conductive layer SD1 and the fifth conductive layer SD2 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The fourth conductive layer SD1 and the fifth conductive layer SD2 may have a single-layer or multi-layer structure, and for example, the fourth conductive layer SD1 and the fifth conductive layer SD2 may have a multi-layer structure including Ti / Al / Ti.

[0251] The sixth bridge pattern BRP6 may overlap with the fifth bridge pattern BRP5 and may contact the fifth bridge pattern BRP5 through a contact hole. The sixth bridge pattern BRP6 may be connected to one electrode of the seventh transistor T7 through the fifth bridge pattern BRP5. Furthermore, the sixth bridge pattern BRP6 may be connected to the anode of the light-emitting element LD through a contact hole. In other words, the sixth bridge pattern BRP6, together with the fifth bridge pattern BRP5, may connect one electrode of the seventh transistor T7 to the anode of the light-emitting element LD.

[0252] The data lines DL may include a first data line DLj, a second data line DLj+1, and a third data line DLj+2, each extending in the second direction DR2. The data line DLj may be located on one side of each of the sub-pixels SP (see FIG. 1 ) in the first direction DR1. For example, the first data line DLj may be located on one side of the first sub-pixel area SPAa in the first direction DR1 and may overlap with the first bridge pattern BRP1. The first data line DLj may contact the first bridge pattern BRP1 through a contact hole and may be connected to one electrode of the second transistor T2 through the first bridge pattern BRP1.

[0253] The 1_2nd power line PL1b may be located at the other side of each of the sub-pixels SP in the first direction DR1. The 1_2nd power line PL1b may include a first portion PL1b′ of the 1_2nd power line overlapping the first sub-pixel SPa and a second portion PL1b″ of the 1_2nd power line overlapping the second sub-pixel SPb. The 1_2nd power line PL1b may be connected to the 1_1st power line PL1a through a third bridge pattern BRP3 and a contact hole.

[0254] The 2_2nd power line PL2b may extend in the second direction DR2 and may be located on the other side of the third sub-pixel SPc in the first direction DR1. The 2_2nd power line PL2b may overlap with the 2_1st power line PL2a. The 2_2nd power line PL2b may contact the 2_1st power line PL2a through a contact hole and may be connected to one electrode of the fifth transistor T5 through the contact hole. Accordingly, the fifth transistor T5 may receive the voltage of the third power supply VREF (or reference power supply). Figure 5 and Figure 11 In the embodiment, the 2_2nd power line PL2b may overlap with the third subpixel SPc or the pixel circuit SPC of the third subpixel SPc, but the present disclosure is not limited thereto. For example, the 2_2nd power line PL2b may overlap with the first subpixel SPa or the second subpixel SPb. Alternatively, the 2_2nd power line PL2b may alternately overlap with the first subpixel SPa and the third subpixel SPc.

[0255] According to one or more embodiments of the present disclosure, the number of lines extending in one direction (eg, the second direction DR2) of the fifth conductive layer SD2 may be relatively small. The resistance of the fifth conductive layer SD2 may be relatively small. For example, Figure 11 As shown in , unlike the first subpixel SPa or the second subpixel SPb, the third subpixel SPc may include a 2_2nd power line PL2b extending in the second direction DR2. In other words, the third subpixel SPc may have a structure in which the 1_2nd power line PL1b of the first subpixel SPa or the second subpixel SPb is replaced by the 2_2nd power line PL2b.

[0256] In the comparative example, when each of the plurality of sub-pixels SPa, SPb, and SPc overlaps with portions PL1b' and PL1b" of the 1_2nd power line PL1b extending in the second direction DR2, and when each of the sub-pixels SPa, SPb, and SPc overlaps with the plurality of 2_2nd power lines PL2b, the width of each of the 1_2nd power line PL1b and the 2_2nd power line PL2b becomes relatively very narrow. Accordingly, the resistance of the fifth conductive layer SD2 constituting each of the 1_2nd power line PL1b and the 2_2nd power line PL2b may be relatively increased. In this comparative example, a problem may occur in which power consumption increases due to heat.

[0257] However, in the display panel 100 according to one or more embodiments of the present disclosure, one pixel may overlap only with the first portion PL1b′ and the second portion PL1b″ of the 1_2nd power line PL1b extending in the second direction DR2 and one 2_2nd power line PL2b. Accordingly, the number of lines formed by the fifth conductive layer SD2 can be reduced, and the resistance of each of the 1_2nd power line PL1b and the 2_2nd power line PL2b formed by the fifth conductive layer SD2 can be reduced. Accordingly, when the display panel 100 (or the display device 1000) including the fifth conductive layer SD2 is driven, power consumption due to heat generation can be relatively reduced.

[0258] The resistance of one of the 1_2nd power line PL1b and the 2_2nd power line PL2b may be substantially the same. For example, the resistance of the second portion PL1b″ of the 1_2nd power line PL1b and the 2_2nd power line PL2b, each formed of the fifth conductive layer SD2, may be substantially the same.

[0259] The 1_1st power line PL1a and the 1_2nd power line PL1b may form a mesh structure. Additionally, the 2_1st power line PL2a and the 2_2nd power line PL2b may form a mesh structure. Accordingly, when the display device 1000 is driven, a relatively small voltage drop (e.g., IR drop) may occur, and patchiness of the display panel 100 may be reduced.

[0260] The 4_2nd power line PL4b may extend in the second direction DR2. For example, the 4_2nd power line PL4b may be located between the first subpixel SPa and the second subpixel SPb and may extend in the second direction DR2. The 4_2nd power line PL4b may be connected to the eighth transistor T8. For example, a portion of the 4_2nd power line PL4b formed from the fifth conductive layer SD2 may contact the 4_1st power line PL4a formed from the fourth conductive layer SD1. In this case, the 4_2nd power line PL4b may be connected to the eighth transistor T8 via the 4_1st power line PL4a. Accordingly, the voltage of the fifth power supply VAINT may be supplied to one electrode of the eighth transistor T8. However, the voltage supplied by the 4_2nd power line PL4b is not limited thereto. For example, according to one or more embodiments, the voltages of the third power supply VREF, the fourth power supply VINT, and the sixth power supply VBS may be applied to the 4_2nd power line PL4b.

[0261] Figure 12 The diagram is along Figure 5 A cross-sectional view of the stacked structure of the display panel taken along line II'. Figure 13 The diagram is along Figure 5 FIG. 1 is a cross-sectional view of the stacked structure of the display panel taken along line II-II′.

[0262] refer to Figure 12 and Figure 13 The display panel 100 may include a base layer BL and a pixel circuit layer PCL. In one or more embodiments, the display panel 100 may further include a display element layer, an encapsulation layer, and / or an optical layer located on / above the pixel circuit layer PCL. However, the embodiments of the present disclosure are not limited thereto.

[0263] For example, the display element layer may be located on the pixel circuit layer PCL (as used herein, "located on" may mean "above"). The display element layer may include an anode electrode AE (refer to Figure 2 ), cathode CE (reference Figure 2 ) and light-emitting layer, etc.

[0264] The base layer BL may be a base substrate or a base member for supporting the display device 1000. The base layer BL may include a substrate SUB. The substrate SUB may be a rigid substrate of a glass material. Alternatively, the substrate SUB may be a flexible substrate that can be bent, folded, or rolled. In this case, the substrate SUB may include an insulating material such as a polymer resin (e.g., polyimide).

[0265] In an embodiment, the substrate SUB may include a silicon wafer substrate formed using a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon germanium. The substrate SUB may be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer. In other embodiments, the substrate SUB may include a glass substrate.

[0266] The pixel circuit layer PCL is located on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and a conductive pattern located between the insulating layers. The conductive pattern of the pixel circuit layer PCL may function as at least a portion of a circuit element or line. The conductive pattern may include copper, but the embodiment is not limited thereto.

[0267] According to one or more embodiments, the base layer BL may further include a barrier layer and a buffer layer, etc. The barrier layer may be disposed between the substrate SUB and the pixel circuit layer PCL to block unnecessary or unwanted components such as moisture or oxygen from entering the light emitting element LD from the outside (refer to FIG. Figure 3E ). The buffer layer may be configured to reduce or prevent the possibility of diffusion of impurity ions and reduce or prevent penetration of moisture or external air.

[0268] The pixel circuit layer PCL may include a semiconductor layer ACT, a first insulating layer GI1 (or a first gate insulating layer), a first conductive layer GAT1, a second insulating layer GI2 (or a second gate insulating layer), a second conductive layer GAT2, a third insulating layer GI3 (or a third gate insulating layer), a third conductive layer GAT3, an interlayer insulating layer ILD, a fourth conductive layer SD1, a first through-hole layer VIA1, a fifth conductive layer SD2, and a second through-hole layer VIA2 sequentially stacked on the base layer BL. Figures 5 to 11 The semiconductor layer ACT, the first conductive layer GAT1, the second conductive layer GAT2, the third conductive layer GAT3, the fourth conductive layer SD1 and the fifth conductive layer SD2 are similarly described. Figure 12 and Figure 13 The semiconductor layer ACT, the first conductive layer GAT1, the second conductive layer GAT2, the third conductive layer GAT3, the fourth conductive layer SD1 and the fifth conductive layer SD2 are shown in FIG.

[0269] refer to Figure 5 、 Figure 6 and Figure 12The semiconductor layer ACT may be located on the base layer BL. For example, the semiconductor layer ACT may be located between the substrate SUB and the first insulating layer GI1. The semiconductor layer ACT may include a sixth semiconductor pattern ACT_T6b constituting the sixth transistor T6 of the second sub-pixel SPb and a ninth semiconductor pattern ACT_T9 constituting the ninth transistor T9. Furthermore, the semiconductor layer ACT may include a sixth semiconductor pattern ACT_T6c constituting the sixth transistor T6 of the third sub-pixel SPc and an eighth semiconductor pattern ACT_T8 constituting the eighth transistor T8.

[0270] The first insulating layer GI1 may be located on the semiconductor layer ACT. The first insulating layer GI1 may be an inorganic insulating layer including an inorganic material. According to one or more embodiments, the first insulating layer GI1 may be formed of an organic insulating layer including an organic material. The first insulating layer GI1 may be provided as a single layer, but may also be provided as a plurality of layers of two or more layers.

[0271] refer to Figure 7 and Figure 12 , the first conductive layer GAT1 may be located on the first insulating layer GI1. The first conductive layer GAT1 may include a gate pattern GE_T8 of the eighth transistor T8.

[0272] The second insulating layer GI2 may be located on the first insulating layer GI1 and the first conductive layer GAT1. The second insulating layer GI2 may be positioned substantially over the entire surface of the substrate SUB. The second insulating layer GI2 may include the same material as the first insulating layer GI1, but is not limited thereto.

[0273] The third insulating layer GI3 may be located on the second insulating layer GI2. The third insulating layer GI3 may be positioned substantially over the entire surface of the substrate SUB. The third insulating layer GI3 may include the same material as the first insulating layer GI1, but is not limited thereto.

[0274] The interlayer insulating layer ILD may be located on the third insulating layer GI3. The interlayer insulating layer ILD may be an inorganic insulating layer including an inorganic material. According to one or more embodiments, the interlayer insulating layer ILD may be formed of an organic insulating layer including an organic material.

[0275] The interlayer insulating layer ILD may include a first through hole VH1 and a third through hole VH3. The first through hole VH1 and the third through hole VH3 may pass through the first insulating layer GI1, the second insulating layer GI2, and the third insulating layer GI3. For example, the first through hole VH1 and the third through hole VH3 may expose the semiconductor layer ACT in the third direction DR3. Accordingly, the fourth conductive layer SD1 may contact the sixth semiconductor pattern ACT_T6b of the sixth transistor T6 constituting the second subpixel SPb through the first through hole VH1. Furthermore, the fourth conductive layer SD1 may contact the sixth semiconductor pattern ACT_T6c of the sixth transistor T6 constituting the third subpixel SPc through the third through hole VH3.

[0276] refer to Figure 10 and Figure 12 The fourth conductive layer SD1 may be located on the interlayer insulating layer ILD. The fourth conductive layer SD1 may include a connection electrode CGE. For example, the fourth conductive layer SD1 may include a connection electrode CGE extending in the first direction DR1 and contacting the semiconductor layer ACT through the first and third through holes VH1 and VH3. The connection electrode CGE may connect the sixth semiconductor pattern ACT_T6b of the second subpixel SPb and the sixth semiconductor pattern ACT_T6c of the third subpixel SPc.

[0277] The first via layer VIA1 may be located on the interlayer insulating layer ILD and the fourth conductive layer SD1. The first via layer VIA1 may be located substantially throughout the entire surface of the substrate SUB.

[0278] The first via layer VIA1 may include an organic insulating material such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB), but is not limited thereto.

[0279] The first via layer VIA1 may include a second via hole VH2. For example, the first via layer VIA1 may include a second via hole VH2 allowing the fifth conductive layer SD2 and the fourth conductive layer SD1 to contact each other.

[0280] refer to Figure 11 and Figure 12 The fifth conductive layer SD2 may be located on the first via layer VIA1. The fifth conductive layer SD2 may include the second portion PL1b″ of the 1_2 th power line, the third data line DLj+2, and the 2_2 th power line PL2b.

[0281] At the same time, the first through-hole layer VIA1 may not expose the fourth conductive layer SD1 of the sixth transistor T6 constituting the third sub-pixel SPc. Accordingly, the fourth conductive layer SD1 of the sixth transistor T6 constituting the third sub-pixel SPc may not contact the fifth conductive layer SD2. At this time, the second portion PL1b" of the 1_2 power line constituted by the fifth conductive layer SD2 may contact the connecting electrode CGE constituted by the fourth conductive layer SD1 through the second through-hole VH2. Accordingly, the sixth transistor T6 of the third sub-pixel SPc may be connected to the sixth transistor of the second sub-pixel SPb through the connecting electrode CGE. The sixth transistor T6 of the second sub-pixel SPb may be connected to the fifth conductive layer SD2. Accordingly, the sixth transistor T6 of the second sub-pixel SPb and the sixth transistor T6 of the third sub-pixel SPc may receive the voltage of the first power supply VDD through the connecting electrode CGE.

[0282] According to one or more embodiments of the present disclosure, the third subpixel SPc may extend in the second direction DR2 and may not include a line to which the voltage of the first power supply VDD is applied, but the third subpixel SPc (or the sixth transistor T6 of the third subpixel SPc) may receive the voltage of the first power supply VDD through the connecting electrode CGE.

[0283] The second via layer VIA2 may be located on the fifth conductive layer SD2. The second via layer VIA2 may be positioned substantially throughout the entire surface of the substrate SUB. The second via layer VIA2 may include the same material as the first via layer VIA1, but is not limited thereto.

[0284] refer to Figure 6 and Figure 13 The semiconductor layer ACT may be located on the base layer BL. The semiconductor layer ACT may include a first semiconductor pattern ACT_T1 constituting the first transistor T1.

[0285] refer to Figure 7 and Figure 13 The first conductive layer GAT1 may be located on the first insulating layer GI1. The first conductive layer GAT1 may include a 1_1 th capacitor electrode C1_E1 of the second sub-pixel SPb and the third sub-pixel SPc.

[0286] refer to Figure 8 and Figure 13 The second conductive layer GAT2 may be located on the second insulating layer GI2. The second conductive layer GAT2 may include a 1_2 th capacitor electrode C1_E2 and / or a 2_1 th capacitor electrode C2_E1.

[0287] refer to Figure 9 and Figure 13The third conductive layer GAT3 may be located on the third insulating layer GI3. The third conductive layer GAT3 may include a 2_2 th capacitor electrode C2_E2.

[0288] The interlayer insulating layer ILD may be located on the third conductive layer GAT3. The interlayer insulating layer ILD may include a fourth through hole VH4. For example, the interlayer insulating layer ILD may include a fourth through hole VH4 exposing the third conductive layer GAT3 overlapping the third subpixel SPc in the third direction DR3.

[0289] refer to Figure 10 and Figure 13 The fourth conductive layer SD1 may be located on the interlayer insulating layer ILD and may include a second bridge pattern BRP2 and a 3_1st bridge pattern BRP3_1.

[0290] According to one or more embodiments of the present disclosure, the fourth conductive layer SD1 overlapping the third sub-pixel SPc may contact the third conductive layer GAT3 overlapping the third sub-pixel SPc. For example, the 3_1st bridge pattern BRP3_1 of the fourth conductive layer SD1 located in the third sub-pixel region SPac may contact the third conductive layer GAT3 located in the third sub-pixel region SPac.

[0291] The first via layer VIA1 may be located on the fourth conductive layer SD1 and the interlayer insulating layer ILD. The first via layer VIA1 may include a fifth via hole VH5 exposing the fourth conductive layer SD1. For example, the first via layer VIA1 may expose the 3_1st bridge pattern BRP3_1 of the fourth conductive layer SD1 overlapping the second subpixel SPb.

[0292] According to one or more embodiments of the present disclosure, the fifth conductive layer SD2 located on the third sub-pixel area SPAc can contact the fourth conductive layer SD1 located on the second sub-pixel area SPAb through the fifth through hole VH5. For example, the second portion PL1b″ of the 1_2 power line PL1b formed by the fifth conductive layer SD2 can contact the 3_1 bridge pattern BRP3_1 formed by the third conductive layer GAT3 through the fifth through hole VH5.

[0293] The second via layer VIA2 may be located on the first via layer VIA1 and the fifth conductive layer SD2. The second via layer VIA2 may be positioned substantially over the entire surface of the substrate SUB. The second via layer VIA2 may include the same material as the first via layer VIA1, but is not limited thereto.

[0294] Figure 14 is a block diagram illustrating an electronic device including a display device according to an embodiment of the present disclosure. Figure 15 It is shown in the figure Figure 14A perspective view of an example in which the electronic device is implemented as a smart phone. Figure 16 It is shown in the figure Figure 14 A perspective view of an example in which the electronic device is implemented as a tablet PC.

[0295] refer to Figures 14 to 16 , the electronic device ED may include a processor PRC, a memory device MEM, a storage device SD, an input / output device IO, a power supply PS, and a display device 1000. In this case, the display device 1000 may be the display device of FIG1 . In addition, the electronic device ED may further include several ports capable of communicating with a video card, a sound card, a memory card, a USB device, or other systems. In one or more embodiments, as Figure 15 As shown in , the electronic device ED can be implemented as a smart phone. In one or more other embodiments, as Figure 16 As shown in FIG, the electronic device ED may be implemented as a tablet PC. However, this is merely an example, and the electronic device ED is not limited thereto. For example, the electronic device ED may be implemented as a mobile phone, a video phone, a smart tablet, a smartwatch, a car navigation device, a computer monitor, a notebook computer, or a head-mounted display device.

[0296] The processor PRC can perform corresponding calculations or tasks. According to one or more embodiments, the processor PRC can be a microprocessor, a central processing unit, or an application processor. The processor PRC can be connected to other components via an address bus, a control bus, or a data bus. According to one or more embodiments, the processor PRC can also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0297] The memory device MEM may store data suitable for the operation of the electronic device ED. For example, the memory device MEM may include non-volatile memory devices such as erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, flash memory devices, phase change random access memory (PRAM) devices, resistive random access memory (RRAM) devices, nano-floating gate memory (NFGM) devices, polymer random access memory (PoRAM) devices, magnetic random access memory (MRAM) devices, and ferroelectric random access memory (FRAM) devices, and / or volatile memory devices such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, and mobile DRAM devices.

[0298] The storage device SD may include a solid-state drive (SSD), a hard disk drive (HDD), an optical disk read-only memory, and the like.

[0299] The input / output device 10 may include input devices such as a keyboard, a keypad, a touch pad, a touch screen, and a mouse, and output devices such as a speaker and a printer. According to one or more embodiments, the display device 1000 may be included in the input / output device 10.

[0300] The power supply PS may supply power suitable for the operation of the electronic device ED. For example, the power supply PS may be a power management integrated circuit (PMIC).

[0301] The display device 1000 can display an image corresponding to the visual information of the electronic device ED. In this case, the display device 1000 can be an organic light-emitting display device or a quantum dot light-emitting display device, but is not limited thereto. The display device 1000 can be connected to other components via a bus or other communication link.

[0302] refer to Figure 15 , the power consumption of the smart phone 1500 including the display device according to the embodiment of the present disclosure can be reduced.

[0303] refer to Figure 16 , the power consumption of the tablet PC 1600 including the display device according to the embodiment of the present disclosure can be reduced.

[0304] Although embodiments and application examples are described herein, other embodiments and modifications can be derived from the above description. Therefore, the spirit of the present disclosure is not limited to such embodiments, and extends to the claims, various obvious modifications and equivalent scopes.

Claims

1. A display device comprising: a first sub-pixel comprising a first pixel circuit; a second sub-pixel including a second pixel circuit and extending from the first sub-pixel in a first direction; a first_2 power line overlapping the first pixel circuit and extending in a second direction intersecting the first direction; a 2_2nd power line, overlapping with the second pixel circuit and extending in the second direction; a 1_1th power line connecting the 1_2th power line and the second sub-pixel and extending in the first direction; as well as The 2_1st power line connects the 2_2nd power line and the first sub-pixel and extends in the first direction.

2. The display device according to claim 1, further comprising: a first data line overlapping the first pixel circuit and extending in the second direction; as well as a second data line, overlapping the second pixel circuit and extending in the second direction; Wherein, the 1_2nd power line is between the first data line and the second data line.

3. The display device according to claim 2, wherein: The second data line is between the 1_2 th power line and the 2_2 th power line.

4. The display device according to any one of claims 1 to 3, wherein: The resistance of the 1_2 th power line is equal to the resistance of the 2_2 th power line.

5. The display device according to claim 1, comprising: basal layer; a semiconductor layer on the base layer; an interlayer insulating layer on the semiconductor layer and defining a first through hole exposing at least a portion of the semiconductor layer overlapping the first pixel circuit; a first conductive layer on the interlayer insulating layer; a via layer on the first conductive layer and defining a second via exposing at least a portion of the first conductive layer overlapping the first pixel circuit; as well as The second conductive layer is above the through-hole layer. The display device according to claim 5 , wherein: The through-hole layer does not expose a portion of the first conductive layer overlapping with the second pixel circuit.

7. The display device according to claim 6, wherein: The first_2 power line of the second conductive layer overlaps with the first pixel circuit, wherein the first_2 power line contacts the connection electrode of the first conductive layer through the second through hole, and The connecting electrode contacts the at least one portion of the semiconductor layer overlapping with the first pixel circuit through the first through hole.

8. The display device according to claim 7, wherein: The interlayer insulating layer further defines a third through hole exposing at least a portion of the semiconductor layer overlapping the second pixel circuit. wherein the connecting electrode extends from the first pixel circuit to a region overlapping with the second pixel circuit in the first direction, and The connecting electrode contacts the at least a portion of the semiconductor layer overlapping with the second pixel circuit through the third through hole in the second pixel circuit.

9. The display device according to claim 5, further comprising: a gate layer, between the semiconductor layer and the interlayer insulating layer, The interlayer insulating layer further defines a fourth through hole exposing at least a portion of the gate layer overlapping with the second pixel circuit.

10. The display device according to claim 9, wherein The via layer further defines a fifth via exposing at least a portion of the first conductive layer overlapping the first pixel circuit.

11. The display device according to claim 2, wherein: The first sub-pixel and the second sub-pixel each include: Light-emitting element; a driving transistor connected between the 1_1th power line and a second node for controlling a driving current supplied to the light emitting element in response to a voltage of a first node connected to a gate electrode of the driving transistor; a first capacitor including one electrode connected to the first node and another electrode connected to a third node; a second transistor connected between the third node and the first data line or the second data line, and configured to be turned on by a first scan signal; a third transistor connected between the first node and the second node and configured to be turned on by a second scan signal; a fourth transistor connected between the first node and an initialization power source and configured to be turned on by a third scan signal; and A fifth transistor is connected between the 2_1st power line and the third node and configured to be turned on by the second scan signal.

12. The display device according to claim 11 , wherein the first sub-pixel and the second sub-pixel each further comprise: a sixth transistor connected between the second node and a fourth node connected to one electrode of the light emitting element and configured to be turned on by a first emission control signal; a seventh transistor connected between the fourth node and an anode initialization power source and configured to be turned on by a fourth scan signal; as well as The second capacitor includes one electrode connected to the 1_1th power line and another electrode connected to the third node.

13. The display device according to claim 11 , wherein the first sub-pixel and the second sub-pixel each further comprise: a sixth transistor connected between the 1_1th power line and a fifth node connected to one electrode of the driving transistor and configured to be turned on by a first emission control signal; a seventh transistor connected between the second node and a fourth node connected to one electrode of the light emitting element and configured to be turned on by a second emission control signal; an eighth transistor connected between the fourth node and an anode initialization power supply and configured to be turned on by a fourth scan signal; as well as The ninth transistor is connected between the fifth node and a bias power supply and is configured to be turned on by the fourth scan signal.

14. The display device according to claim 13, wherein: The driving transistor and the second to ninth transistors include P-type transistors.

15. The display device according to claim 13, wherein The second transistor, the third transistor, the fourth transistor, and the fifth transistor include N-type transistors, and The driving transistor, the sixth transistor, the seventh transistor, the eighth transistor and the ninth transistor include P-type transistors.

16. The display device according to claim 13, wherein the first sub-pixel and the second sub-pixel each further comprise: A tenth transistor is connected between the 1_1th power line and the fifth node and is configured to be turned on by the second scan signal.

17. The display device according to claim 2, wherein: The first sub-pixel and the second sub-pixel each include: Light-emitting element; a driving transistor connected between the second node and a fifth node, the fifth node being configured to control a driving current supplied to the light emitting element in response to a voltage of a first node connected to a gate electrode of the driving transistor; a second transistor connected between the third node and the first data line or the second data line and configured to be turned on by a first scan signal; a first capacitor including one electrode connected to the third node and another electrode connected to the first node; a third transistor connected between the first node and the second node connected to one electrode of the driving transistor and configured to be turned on by a second scan signal; a fourth transistor connected between the third node and the 2_1 th power line and configured to be turned on by the second scan signal; and A fifth transistor is connected between the 1_1th power line and the fifth node and is configured to be turned on by a first emission control signal.

18. The display device according to claim 17, further comprising: a second capacitor including one electrode connected to the 1_1th power line and another electrode connected to the third node; a sixth transistor connected between the second node and a fourth node connected to one electrode of the light emitting element and configured to be turned on by a second emission control signal; a seventh transistor connected between the fourth node and an anode initialization power supply and configured to be turned on by the first emission control signal; as well as The eighth transistor is connected between the fifth node and a bias power supply and is configured to be turned on by a fourth scan signal.

19. An electronic device comprising: a processor configured to provide input image data; as well as The display device according to any one of claims 1 to 18, configured to display an image based on the input image data.

Images