Display panel and electronic equipment

Abstract

The invention relates to a display panel and electronic equipment, the display panel comprises a display area, and the display panel further comprises a substrate; a plurality of pixel circuits arranged on the substrate in an array, wherein the pixel circuits are electrically connected with the first scanning lines and the data lines; one end of the connecting line is electrically connected with the data line, the other end of the connecting line is electrically connected with the data input end, the connecting line comprises a first connecting line extending in the first direction and a second connecting line extending in the second direction, the first connecting line is electrically connected with the second connecting line, and at least part of the connecting line is located in the display area; the first active layer comprises a shielding part, constant voltage is connected to the shielding part, and the shielding part and the first connecting line are at least partially overlapped in the direction perpendicular to the display panel; or in the third direction, the orthographic projection of the shielding part on the substrate is located between the orthographic projection of the first connecting line and the orthographic projection of the first scanning line on the substrate, and the third direction is parallel to the substrate. The display panel can improve the problem of uneven brightness display.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and an electronic device. Background Art

[0002] Organic Light Emitting Diode (OLED) is a hot topic in the current research field of flat panel displays. OLED has the advantages of simple preparation process, low cost, high luminous efficiency, easy formation of flexible structure, low power consumption, high color saturation and wide viewing angle.

[0003] With the continuous development of display technology, there are higher requirements for the narrow bezels of organic light-emitting displays. Currently, narrow-bezel products can be designed based on the fan-out routing in the display area (Fanout In AA, FIAA) solution.

[0004] However, display panels based on the FIAA solution have uneven brightness (mura), which affects the display quality. Summary of the Invention

[0005] Based on this, it is necessary to provide a display panel and an electronic device, aiming to improve the problem of uneven brightness display of the display panel.

[0006] In a first aspect, an embodiment of the present application provides a display panel, the display panel including a display area, and the display panel further including:

[0007] substrate;

[0008] A plurality of pixel circuits arranged in an array on the substrate, the pixel circuits being electrically connected to the first scan line and the data line;

[0009] a connecting line, one end of the connecting line being electrically connected to the data line, the other end of the connecting line being electrically connected to the data input terminal, the connecting line comprising a first connecting line extending along a first direction and a second connecting line extending along a second direction, the first connecting line and the second connecting line being electrically connected, and the connecting line being at least partially located in the display area;

[0010] The first active layer includes a shielding portion, the shielding portion is connected to a constant voltage, and in a direction perpendicular to the display panel, the shielding portion at least partially overlaps with the first connecting line; or along a third direction, the orthographic projection of the shielding portion on the substrate is located between the orthographic projection of the first connecting line and the first scanning line on the substrate, and the third direction is parallel to the substrate.

[0011] In a second aspect, an embodiment of the present application further provides an electronic device, which includes the display panel provided in the first aspect.

[0012] The display panel and electronic device provided in the embodiments of the present application are configured such that a shielding portion is provided on the active layer, the shielding portion is connected to a fixed potential, and in a direction perpendicular to the display panel, the shielding portion at least partially overlaps with the first connecting line, or the shielding portion is located between the first connecting line and the first scanning line. In this way, the first connecting line can be shielded, and the coupling capacitance between the first connecting line and the first scanning line can be weakened, thereby reducing the possibility of generating oblique bright lines, thereby effectively improving the uneven brightness display phenomenon of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a simplified schematic diagram of a display panel according to an embodiment;

[0014] Figure 2 A wiring diagram of a display panel provided in an embodiment of the present application;

[0015] Figure 3 A wiring diagram of another display panel provided in an embodiment of the present application;

[0016] Figure 4 A circuit diagram of a pixel circuit provided in an embodiment of the present application;

[0017] Figure 5 A circuit diagram of another pixel circuit provided in an embodiment of the present application;

[0018] Figure 6 A schematic diagram of local wiring of a display panel provided in an embodiment of the present application;

[0019] Figure 7 A schematic cross-sectional view of a display panel provided in an embodiment of the present application;

[0020] Figure 8 A schematic top view of a first active layer provided in an embodiment of the present application;

[0021] Figure 9 A schematic top view of a first metal layer provided in an embodiment of the present application;

[0022] Figure 10 A schematic top view of a second metal layer provided in an embodiment of the present application;

[0023] Figure 11 A schematic top view of a first drain-source layer provided in an embodiment of the present application;

[0024] Figure 12 A schematic top view of a second drain-source layer provided in an embodiment of the present application;

[0025] Figure 13 A schematic diagram of local wiring of another display panel provided in an embodiment of the present application;

[0026] Figure 14 A schematic cross-sectional view of another display panel provided in an embodiment of the present application;

[0027] Figure 15 A schematic top view of another first active layer provided in an embodiment of the present application;

[0028] Figure 16 A schematic top view of another first metal layer provided in an embodiment of the present application;

[0029] Figure 17 A schematic top view of another second metal layer provided in an embodiment of the present application;

[0030] Figure 18 A schematic top view of a second active layer provided in an embodiment of the present application;

[0031] Figure 19 A schematic top view of a third metal layer MG provided in an embodiment of the present application;

[0032] Figure 20 A schematic top view of another first drain-source layer provided in an embodiment of the present application;

[0033] Figure 21 A schematic top view of another second drain-source layer provided in an embodiment of the present application;

[0034] Figure 22 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the relevant listed items.

[0037] When describing positional relationships, unless otherwise specified, when an element, such as a layer, film, or substrate, is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, when a layer is referred to as being "under" another layer, it can be directly under or one or more intervening elements may also be present. It will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening elements may also be present.

[0038] In the case of using “including,” “having,” and “comprising” described herein, another component may be added unless a clear limiting term such as “only,” “consisting of,” etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as having one number.

[0039] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this application.

[0040] It should also be understood that when interpreting an element, even if not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of the specific value determined by those skilled in the art. For example, "approximately," "approximately," or "substantially" can mean within one or more standard deviations, and is not limited here.

[0041] Furthermore, in the specification, the phrase “planar distribution diagram” refers to a drawing when the target portion is viewed from above, and the phrase “cross-sectional diagram” refers to a drawing when a section taken by vertically cutting the target portion is viewed from the side.

[0042] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples and not necessarily according to the true scale.

[0043] Organic Light Emitting Diode (OLED) is a hot topic in the current research field of flat panel displays. OLED has the advantages of simple preparation process, low cost, high luminous efficiency, easy formation of flexible structure, low power consumption, high color saturation and wide viewing angle.

[0044] With the continuous development of display technology, there are higher requirements for the narrow border of organic light-emitting displays. At present, narrow-border products can be designed based on the fan-out routing in the display area (Fanout In AA, FIAA) solution, such as Figure 1FIG. 1 is a top view of a display panel, which includes a display area AA and a non-display area NA. In the display area AA, the display panel further includes a plurality of first fan-out lines 1 and a plurality of data lines DATA. The data lines DATA extend along the second direction and are arranged along the first direction. Some of the data lines DATA are electrically connected to a driving module (not shown) through the first fan-out lines 1. The first fan-out lines 1 include a first connecting line 2 and a second connecting line 3. The first connecting line 2 extends along the first direction and is located in the display area AA. The second connecting line 3 extends along the second direction and extends from the display area AA to the non-display area NA. The first connecting line 2 includes a first end 21 and a second end 32 that are opposite to each other. The second end 22, the second connection line 3 connected to the first end 21 extends to one end of the non-display area NA and is electrically connected to the data line DATA, the second connection line 3 connected to the second end 22 extends to one end of the non-display area NA and is electrically connected to the binding pad 4, the second connection line 3 connected to the first end 21 of the first connection line 2 is the first sub-fan-out part 31, and the second connection line 3 connected to the second end 22 of the first connection line 2 is the second sub-fan-out part 32, that is, the end of the first sub-fan-out part 31 away from the first connection line 2 is electrically connected to the data line DATA in the non-display area NA, and the end of the second sub-fan-out part 32 away from the first connection line 2 is electrically connected to the binding pad 4 in the non-display area NA.

[0045] However, the display panel based on the FIAA solution has uneven brightness (mura) phenomenon, which affects the display quality. Figure 2 As shown, the display array includes a base substrate (not shown in the figure), which includes a display area and a non-display area; it also includes a first scan line Scan1, a first reference line Vref1, a first connection line (a horizontal FIAA line) FIAA and a signal line DATA. The projection of the first connection line FIAA on the base substrate overlaps with the projection of the first reference line Vref1 on the base substrate. Since the first connection line FIAA is long and the distance between the first connection line FIAA and the first scan line Scan1 is too close, the lateral capacitance between the first scan line Scan1 and the first connection line FIAA is large. The signal fluctuation of the first scan line Scan1 will affect the first connection line FIAA, resulting in unstable potential on the FIAA line, thereby causing uneven brightness of the display panel and the brightness display unevenness (mura) phenomenon.

[0046] To solve the above technical problems, an embodiment of the present application provides a display panel, including a display area, the display panel also including: a substrate; a plurality of pixel circuits arranged in an array on the substrate, the pixel circuits being electrically connected to a first scan line and a data line; a connecting line, one end of the connecting line being electrically connected to the data line, and the other end of the connecting line being electrically connected to a data input end, the connecting line including a first connecting line extending along a first direction and a second connecting line extending along a second direction, the first connecting line and the second connecting line being electrically connected, and the connecting line being at least partially located in the display area; a first active layer, the first active layer including a shielding portion, the shielding portion being connected to a constant voltage, and in a direction perpendicular to the display panel, the shielding portion at least partially overlaps with the first connecting line; or in a third direction, the orthographic projection of the shielding portion on the substrate substrate is located between the first connecting line and the orthographic projection of the first scan line on the substrate substrate, and the third direction is parallel to the substrate substrate.

[0047] The display panel provided by the embodiment of the present application provides a shielding portion on the first active layer, the shielding portion is connected to a fixed potential, and in the direction perpendicular to the display panel, the shielding portion at least partially overlaps with the first connecting line, or the shielding portion is located between the first connecting line and the first scanning line. In this way, the first connecting line can be shielded, and the coupling capacitance between the first connecting line and the first scanning line is weakened, thereby reducing the possibility of generating oblique bright lines, thereby effectively improving the uneven brightness display phenomenon of the display panel.

[0048] The above is the core concept of this application. The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative work are within the scope of protection of this application.

[0049] like Figure 2 and Figure 3 As shown, the embodiment of the present application provides different wiring diagrams of display panels; according to Figure 2As shown, there are shown the areas where multiple pixel driving circuit rows and multiple pixel driving circuit columns are located. The display panel provided by the embodiment of the present application includes a display area, and the display panel also includes: a substrate; multiple pixel circuits arranged in an array on the substrate substrate, the pixel circuits are electrically connected to the first scan line Scan1 and the data line DATA; a connecting line FIAA, one end of the connecting line FIAA is electrically connected to the data line DATA, and the other end of the connecting line FIAA is electrically connected to the data input end, the connecting line FIAA includes a first connecting line extending along a first direction h1 and a second connecting line extending along a second direction h2, the first connecting line and the second connecting line are electrically connected, and the connecting line FIAA is at least partially located in the display area; a first active layer, the first active layer includes a shielding portion, the shielding portion is connected to a constant voltage, and in the direction perpendicular to the display panel, the shielding portion and the first connecting line are at least partially overlapped; or in the third direction, the shielding portion is located between the first connecting line and the first scan line on the substrate substrate. The third direction is parallel to the substrate substrate.

[0050] The first direction h1 and the second direction h2 intersect and are both perpendicular to the thickness direction of the base substrate.

[0051] In one possible implementation, Figure 2 As shown, the shielding portion 51 at least partially overlaps with the first connecting line FIAA in the direction perpendicular to the display panel. It can be understood that when the shielding portion 51 at least partially overlaps with the first connecting line FIAA, the orthographic projection of the shielding portion 51 on the substrate substrate can completely coincide with the orthographic projection of the first connecting line FIAA on the substrate substrate, or, a part of the orthographic projection of the shielding portion 51 on the substrate substrate can coincide with the orthographic projection of the first connecting line FIAA on the substrate substrate.

[0052] In another possible implementation, in a direction parallel to the base substrate, the orthographic projection of the shielding portion 51 in the first active layer on the base substrate may also be located between the orthographic projections of the first connecting line FIAA and the first scanning line Scan1 on the base substrate. It can be understood that in a direction perpendicular to the display panel, the shielding portion 51 does not overlap with the first connecting line FIAA and the first scanning line Scan1.

[0053] Optionally, the shielding portion extends along the first direction.

[0054] like Figure 2As shown, the display panel also includes a power supply voltage signal line PVDD, a bias adjustment signal line DVH, a first reference line Vref1, a second reference line Vref2 and a light-emitting control signal line Emit. The shielding portion 51 can be connected to the power supply voltage signal line PVDD to access a constant voltage, thereby shielding the first connection line and weakening the coupling capacitance between the first connection line and the first scan line. This embodiment of the present application is not limited to this.

[0055] The power voltage line PVDD transmits a first power voltage Vpvdd, the data line DATA transmits a data voltage Vdata, the first reference line Vref1 transmits a first reset voltage, the second reference line Vref2 transmits a second reset voltage, and the bias adjustment signal line DVH transmits a bias adjustment voltage Vdvh.

[0056] Optional, in Figure 2 In the wiring diagram of the display panel shown in FIG. 1 , the circuit diagram of a pixel circuit can be as follows: Figure 4 As shown, a pixel unit includes a pixel driving circuit 401 and a light-emitting element 402, wherein the pixel driving circuit 401 is a 7T1C circuit, which may include a first light-emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, a first reset transistor T5, a second light-emitting control transistor T6 and an initialization reset transistor T7, wherein the active layers of the transistors T1-T7 are polycrystalline silicon.

[0057] Optional, in Figure 3 In the wiring diagram of the display panel shown in FIG. 1 , the circuit diagram of a pixel circuit can be as follows: Figure 5 As shown, the pixel unit includes a pixel driving circuit 501 and a light-emitting element 502, wherein the pixel driving circuit 501 is an 8T1C circuit, which may include a first light-emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, a first reset transistor T5, a second light-emitting control transistor T6, a second reset transistor T7 and a bias adjustment transistor T8, wherein the active layers of the first light-emitting control transistor T1, the data writing transistor T2, the driving transistor T3, the second light-emitting control transistor T6, the second reset transistor T7 and the bias adjustment transistor T8 are polysilicon, and the active layers of the threshold compensation transistor T4 and the first reset transistor T5 are indium gallium zinc oxide.

[0058] Exemplarily, the light emitting element 402 or the light emitting element 502 includes any one of an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), and a micro light emitting diode (Micro-LED).

[0059] The display panel provided in the above embodiment includes a display area, and the display panel further includes: a base substrate; a plurality of pixel circuits arranged in an array on the base substrate, the pixel circuits being electrically connected to a first scan line and a data line; a connecting line, one end of the connecting line being electrically connected to the data line, the other end of the connecting line being electrically connected to a data input terminal, the connecting line including a first connecting line extending along a first direction and a second connecting line extending along a second direction, the first connecting line and the second connecting line being electrically connected, and the connecting line being at least partially located in the display area; a first active layer, the first active layer including a shielding portion, the shielding portion being connected to a constant voltage, and the shielding portion being connected to the first connecting line in a direction perpendicular to the display panel. The lines at least partially overlap; or along the third direction, the orthographic projection of the shielding portion on the substrate substrate is located between the orthographic projections of the first connecting line and the first scanning line on the substrate substrate, and the third direction is parallel to the substrate substrate by providing a shielding portion on the active layer, the shielding portion is connected to a fixed potential, and in the direction perpendicular to the display panel, the shielding portion at least partially overlaps with the first connecting line, or the shielding portion is located between the first connecting line and the first scanning line, so that the first connecting line can be shielded, the coupling capacitance between the first connecting line and the first scanning line is weakened, thereby reducing the possibility of generating oblique bright lines, thereby effectively improving the uneven brightness display of the display panel.

[0060] In an exemplary embodiment, Figure 2 and Figure 3 As shown, the first active layer further includes a first extension portion 52 , and the constant voltage is transmitted to the shielding portion 51 through the first extension portion 52 .

[0061] The following is based on Figure 2 The wiring diagram of the display panel shown introduces the display panel provided in the embodiment of the present application.

[0062] Optional, Figure 6 It is a schematic diagram of the local wiring of the display panel, such as Figure 2 and Figure 6 As shown, the constant voltage connected to the shielding portion is provided by the power voltage signal line PVDD, and the constant voltage is the first power voltage Vpvdd.

[0063] Optional, such as Figure 2 and Figure 7 As shown, Figure 7 This is a schematic cross-sectional view of a display panel provided in an embodiment of the present application. The display panel includes multiple conductive film layers, including a first active layer poly, a first metal layer M1, a second metal layer Mc, and a first source and drain layer M2. In a direction away from the substrate, the first active layer poly, the first metal layer M1, the second metal layer Mc, and the first source and drain layer M2 are stacked in sequence, with adjacent conductive film layers separated by an insulating layer. Figure 6 The corresponding backplane technology of the display panel may be low-temperature polysilicon (LTPS) technology, with low-temperature polysilicon being used as the active layer material.

[0064] Optional, such as Figure 7 As shown, the conductive film layer further includes a second source-drain electrode layer M3 , and the second source-drain electrode layer M3 is located on a side of the first source-drain electrode layer M2 away from the substrate.

[0065] Optional, such as Figure 6 As shown, the shielding portion 51 in the first active layer is punched through the insulating layer to the first source and drain layer M2 and is electrically connected to the power supply voltage signal line PVDD in the first source and drain layer M2, thereby being connected to a fixed potential.

[0066] Exemplarily, the first active layer may include a silicon material, such as amorphous silicon or polycrystalline silicon, and the first metal layer, the second metal layer, the first source and drain layer and the second source and drain layer may include an alloy composed of one or more metal materials, and may form a single-layer or multi-layer structure. For example, the metal material may be aluminum, silver, magnesium, gold, copper or nickel, etc., which is not limited in the embodiments of the present application.

[0067] Combine Figure 2 , Figure 8 A schematic top view of a first active layer provided in an embodiment of the present application, including active wiring, a shielding portion 51 and a first extension portion 52, Figure 9 A schematic top view of a first metal layer M1 provided in an embodiment of the present application, wherein 901 is a first scan line Scan1, 902 is a second scan line Scan2, and 903 is a light-emitting control signal line Emit. The first scan line Scan1, the second scan line Scan2, and the light-emitting control signal line Emit can be arranged in the first metal layer M1 along a first direction. Figure 10 A schematic top view of a second metal layer Mc provided in an embodiment of the present application, wherein 1001 is a second reference line Vref2, 1002 is a first reference line Vref1, and 1003 is a power supply voltage signal line PVDD. The first reference line Vref1, the second reference line Vref2, and the power supply voltage signal line PVDD can be arranged in the second metal layer Mc along a first direction. Figure 11A schematic top view of a first source-drain layer M2 provided in an embodiment of the present application, wherein 1101 is a first connection line FIAA, 1102 is a power supply voltage signal line PVDD, 1103 is a first reference line Vref1, and 1104 is a second reference line Vref2. The first connection line FIAA can be arranged in the first source-drain layer M2 along a first direction, and the first reference line Vref1, the second reference line Vref2, and the power supply voltage signal line PVDD can be arranged in the first source-drain layer M2 along a second direction. Figure 12 A top view schematic diagram of a second drain-source layer M3 provided in an embodiment of the present application, wherein 1201 is a power supply voltage signal line PVDD, 1202 is a data line DATA, 1203 is a second connection line FIAA, 1204 is a first reference line Vref1, and 1205 is a second reference line Vref2. The power supply voltage signal line PVDD, the data line DATA, the second connection line FIAA, the first reference line Vref1 and the second reference line Vref2 can be arranged in the second drain-source layer M3 along the second direction.

[0068] Optional, such as Figure 2 、 Figures 10 to 12 As shown, the first reference line Vref1 and the second reference line Vref2 are of a mesh structure, including a first reference line Vref1 (1002) and a second reference line Vref2 (1001) extending along a first direction in the second metal layer Mc, and including a first reference line Vref1 (1103) and a second reference line Vref2 (1104) extending along a second direction in the first source-drain layer M2. The first reference line Vref1 (1002) in the second metal layer Mc can be connected to the first reference line Vref1 (1103) in the first source-drain layer M2 through the first reference line Vref1 (1204) in the second drain-source layer M3, and the second reference line Vref1 (1001) in the second metal layer Mc can be connected to the second reference line Vref1 (1104) in the first source-drain layer M2 through the second reference line Vref2 (1205) in the second drain-source layer M3.

[0069] like Figure 2 As shown, one end of the power supply voltage signal line PVDD is electrically connected to the second metal layer Mc, and the other end of the power supply voltage signal line PVDD is electrically connected to the shielding portion.

[0070] Among them, such as Figure 2 、 Figure 10 and Figure 11As shown, the power supply voltage signal line PVDD (1102) in the first source-drain layer M2 is electrically connected to the shielding portion 51 to provide a constant voltage for the shielding portion, wherein one end of the power supply voltage signal line PVDD (1102) in the first source-drain layer M2 is electrically connected to the power supply voltage signal line PVDD (1003) in the second metal layer Mc through a via, and the other end of the power supply voltage signal line PVDD (1102) in the first source-drain layer M2 is electrically connected to the shielding portion 51.

[0071] Optional, such as Figure 4 and Figure 8 As shown, the first electrode of the first light emitting control transistor T1 is electrically connected to the shielding portion through the first extending portion.

[0072] Among them, such as Figure 4 and Figure 8 As shown, the pixel driving circuit also includes a first node N1, which is located between the data writing transistor T2 and the first light-emitting control transistor T1. The second electrode of the first light-emitting control transistor T1, the first electrode of the data writing transistor T2 and the first electrode of the driving transistor T3 are all connected to the first node N1, and the first extension portion is located on the side of the first electrode of the first light-emitting control transistor T1 away from the first node along the second direction.

[0073] Among them, such as Figure 4 As shown, the pixel driving circuit further includes a second node N2 and a third node N3, a gate of the first light emitting control transistor T1 is electrically connected to the light emitting control signal line Emit, and a first electrode is electrically connected to the power supply voltage line PVDD; a gate of the data writing transistor T2 is electrically connected to the second scan line Scan2, and a second electrode is electrically connected to the data line DATA; a gate of the driving transistor T3 is electrically connected to the second node N2, and a second electrode is electrically connected to the third node N3; a gate of the threshold compensation transistor T4 is electrically connected to the second scan line Scan2, a first electrode is electrically connected to the third node N3, and a second electrode is electrically connected to the third node N4. The diode is electrically connected to the second node N2; the gate of the first reset transistor T5 is electrically connected to the first scan line Scan1, the first electrode is electrically connected to the first reference line VREF1, and the second electrode is electrically connected to the second node N2; the gate of the second light-emitting control transistor T6 is electrically connected to the light-emitting control signal line Emit, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the light-emitting element 402; the gate of the initialization reset transistor T7 is electrically connected to the first scan line Scan1, the first electrode is electrically connected to the second reference line VREF2, and the second electrode is electrically connected to the light-emitting element 402.

[0074] Optional, such as Figure 2 and Figure 8As shown, there are multiple shielding parts and pixel circuits, two adjacent pixel circuits and one shielding part 51 are correspondingly provided, and the first electrodes of the first light emitting control transistors T1 in the two adjacent pixel circuits are connected to the corresponding same shielding part 51 .

[0075] Optional, such as Figure 2 and Figure 4 As shown, the pixel circuit further includes an initialization reset transistor T7 , and the first scan line Scan1 is electrically connected to the gate of the initialization reset transistor T7 .

[0076] Among them, the first scan line Scan1 electrically connected to the gate of the initialization reset transistor T7 is a scan line close to the first connection line FIAA. By setting a shielding portion on the first active layer and connecting it to a fixed potential, since the shielding portion at least partially overlaps with the first connection line FIAA in the direction perpendicular to the display panel, or the shielding portion is located between the first connection line FIAA and the first scan line Scan1, the first connection line FIAA can be shielded, and the coupling capacitance between the first connection line FIAA and the first scan line Scan1 can be weakened, thereby reducing the possibility of generating oblique bright lines, thereby effectively improving the uneven brightness display of the display panel.

[0077] In an exemplary embodiment, Figure 2 and Figure 6 As shown, the display panel also includes a first reference line Vref1. In the direction perpendicular to the display panel, the first connecting line FIAA and the shielding portion 51 at least partially overlap with the first reference line Vref1. In the direction parallel to the display panel, the orthographic projection of the first reference line Vref1 on the base substrate is at least partially located between the orthographic projections of the first connecting line FIAA and the first scanning line Scan1 on the base substrate.

[0078] Optionally, the orthographic projection of the first reference line Vref1 on the substrate may be a first projection, the orthographic projection of the first connecting line FIAA on the substrate may be a second projection, and the orthographic projection of the first scanning line Scan1 on the substrate may be a third projection. On the substrate, the first projection may partially overlap with the second projection, or the first projection may completely overlap with the second projection, wherein when the first projection and the second projection partially overlap, the first projection may be located between the second projection and the third projection.

[0079] In an exemplary embodiment, Figure 8 As shown, the first active layer further includes active traces, and the distance between one end of the shielding portion 51 and the adjacent active trace along the second direction is not less than 2.1 μm.

[0080] In the first active layer, for a corresponding shielding portion, the shielding portion is not connected to any other active traces in the first active layer except for being electrically connected to the first electrode of the first light-emitting control transistor T1 through the first extension portion. Moreover, since the shielding portion extends along the first direction, the distance d between one end of the shielding portion and the adjacent active trace along the second direction should be greater than or equal to 2.1 μm.

[0081] In this way, in the process design, by setting the distance between a section of the shielding portion 51 and the adjacent active wiring along the second direction to be no less than 2.1 μm, a loop with the active wiring can be avoided. At the same time, one shielding portion can simultaneously serve as a shield for two adjacent pixel circuits, saving wiring space and materials to a certain extent.

[0082] The following is based on Figure 3 The wiring diagram of the display panel shown introduces the display panel provided in the embodiment of the present application.

[0083] Optional, Figure 13 for Figure 3 The local wiring diagram of the corresponding display panel is as follows: Figure 3 and Figure 13 As shown, the constant voltage connected to the shielding portion is provided by the bias adjustment signal line DVH, and the constant voltage is the bias adjustment voltage Vdvh.

[0084] Optional, such as Figure 14 As shown, Figure 3 Corresponding to a cross-sectional schematic diagram of another display panel, the display panel includes multiple conductive film layers, the conductive film layers include a first active layer poly, a first metal layer M1, a second metal layer Mc, a second active layer, a third metal layer MG, a first source-drain layer M2 and a second source-drain layer M3. Along the direction away from the substrate, the first active layer poly, the first metal layer M1, the second metal layer Mc, the second active layer, the third metal layer MG, the first source-drain layer M2 and the second source-drain layer M3 are stacked in sequence, and two adjacent conductive film layers are separated by an insulating layer. The insulating layer is not described in the embodiment of the present application.

[0085] Optionally, the second active layer is an oxide semiconductor layer, and the corresponding backplane technology of the display panel can be a low-temperature polycrystalline oxide (LTPO) technology that combines low-temperature polycrystalline silicon (LTPS) and indium gallium zinc oxide (IGZO). This can enable the display panel to have not only the advantages of high resolution, high response speed, high brightness, and high aperture ratio of the LTPS display panel, but also the advantage of low leakage current of IGZO, which can improve the display effect.

[0086] Optional, such as Figure 13 As shown, the shielding portion 51 in the first active layer is punched through the insulating layer to the second metal layer Mc, and is electrically connected to the bias adjustment signal line DVH in the second metal layer Mc, thereby being connected to a fixed potential.

[0087] Combine Figure 3 The display panel further includes a third scan line S1N and a fourth scan line S2N. Figure 15 This is a schematic top view of a first active layer poly provided in an embodiment of the present application. Figure 16 A schematic top view of a first metal layer M1 provided in an embodiment of the present application, wherein 1601 is the second scan line Scan2, 1602 is the light-emitting control signal line Emit, and 1603 is the first scan line Scan1. The first scan line Scan1, the second scan line Scan2, and the light-emitting control signal line Emit can be arranged in the first metal layer M1 along the first direction. Figure 17 This is a schematic top view of a second metal layer Mc provided in an embodiment of the present application, wherein 1701 is a first reference line Vref1, 1702 is a bias adjustment signal line DVH, 1703 is a power supply voltage line PVDD, 1704 is a third scan line S1N, and 1705 is a fourth scan line S2N. The first reference line Vref1, the bias adjustment signal line DVH, the power supply voltage line PVDD, the third scan line S1N, and the fourth scan line S2N can be arranged along a first direction on the second metal layer Mc. Figure 18 A schematic top view of a second active layer provided in an embodiment of the present application is shown. Figure 19 A top view of a third metal layer MG is provided for an embodiment of the present application, wherein 1901 is a second reference line Vref2, 1902 is a power supply voltage line PVDD, 1903 is a fourth scan line S2N, and 1904 is a third scan line S1N. The second reference line Vref2, the third scan line S1N, and the fourth scan line S2N can be arranged in the third metal layer along the first direction. Figure 20A schematic top view of a first source / drain layer M2 provided in an embodiment of the present application, wherein 2001 is a first connection line FIAA, 2002 is a second reference line Vref2, and the first connection line FIAA and the second reference line Vref2 can be arranged in the first direction on the first source / drain layer M2. Figure 21 A top view schematic diagram of a second drain-source layer M3 provided in an embodiment of the present application, wherein 2101 is a second connecting line FIAA, 2102 is a data line DATA, and 2103 is a power voltage line PVDD. The data line DATA, the second connecting line FIAA, and the power voltage line PVDD can be arranged in the second drain-source layer M3 along the second direction.

[0088] In an exemplary embodiment, Figure 3 and Figure 15 As shown, the first active layer poly further includes a first extension portion 52 , and the bias adjustment signal line DVH and the shielding portion 51 are electrically connected via the first extension portion 52 .

[0089] like Figure 5 and Figure 15 As shown, the pixel circuit includes a bias compensation transistor T8 , and a first electrode of the bias compensation transistor T8 is electrically connected to the shielding portion 51 via a first extension portion.

[0090] Optional, such as Figure 3 and Figure 15 As shown, in the first active layer, the first electrode of the bias compensation transistor T8 is electrically connected to the shielding portion 51 via the first extension portion 52 .

[0091] Optional, such as Figure 5 and Figure 15 As shown, the pixel driving circuit also includes a first node N1, which is located between the first light-emitting control transistor T1 and the driving transistor T3. The second electrode of the first light-emitting control transistor T1, the first electrode of the data writing transistor T2, the first electrode of the driving transistor T3 and the second electrode of the bias compensation transistor T8 are all connected to the first node N1.

[0092] Among them, such as Figure 5 As shown, the pixel driving circuit further includes a second node N2, a third node N3 and a fourth node N4. The gate of the first light-emitting control transistor T1 is electrically connected to the light-emitting control signal line Emit, and the first electrode is electrically connected to the power supply voltage line PVDD; the gate of the data writing transistor T2 is electrically connected to the second scan line Scan2 (in Figure 5The gate of the driving transistor T3 is electrically connected to the second node N2, and the second electrode is electrically connected to the third node N3; the gate of the threshold compensation transistor T4 is electrically connected to the fourth scan control signal line S2N, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the second node N2; the gate of the first reset transistor T5 is electrically connected to the third scan line S1N, the first electrode is electrically connected to the first reference line VREF1, and the second electrode is electrically connected to the second node N2; the gate of the second light emitting control transistor T6 is electrically connected to the light emitting control signal line Emit, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the light emitting element 702; the gate of the second reset transistor T7 is electrically connected to the first scan line Scan1 ( Figure 5 The first electrode is electrically connected to the second reference line VREF2, and the second electrode is electrically connected to the light emitting element 702; the gate of the bias adjustment transistor T8 is electrically connected to the first scan line Scan1 ( Figure 5 The first electrode is electrically connected to the bias adjustment signal line DVH.

[0093] Optional, such as Figure 3 and Figure 15 As shown, the shielding portion 51 is located on a side of the first electrode of the bias compensation transistor T8 away from the first light emission control transistor T1 along the second direction.

[0094] In an exemplary embodiment, Figure 3 and Figure 15 As shown, there are multiple shielding parts and pixel circuits, two adjacent pixel circuits and one shielding part are correspondingly provided, and the first electrodes of the bias compensation transistors in the two adjacent pixel circuits are connected to the corresponding same shielding part.

[0095] Exemplarily, in the pixel circuits of the same row of the first active layer, two pixel circuits in adjacent columns and a shielding portion are arranged correspondingly. Correspondingly, the two pixel circuits in adjacent columns can share the same extension portion and be connected to the same shielding portion, that is, the first poles of the bias compensation transistors in the two pixel circuits in adjacent columns are electrically connected, and the intersection of the first poles of the bias compensation transistors in the two pixel circuits is electrically connected to the first extension portion, and then the connection with the shielding portion can be achieved through the first extension portion.

[0096] The first electrodes of the bias compensation transistors in two adjacent pixel circuits are connected to the corresponding same shielding portion, which can save materials to a certain extent.

[0097] In an exemplary embodiment, Figure 3 and Figure 13As shown, in a direction parallel to the display panel, the orthographic projection of the bias adjustment signal line on the base substrate is at least partially located between the orthographic projections of the first connection line and the first scan line on the base substrate.

[0098] Optionally, the orthographic projection of the bias adjustment signal line DVH on the substrate substrate can be a fourth projection, the orthographic projection of the first connecting line FIAA on the substrate substrate can be a second projection, and the orthographic projection of the first scanning line Scan1 on the substrate substrate can be a third projection. In this way, on the substrate substrate, the fourth projection can partially overlap with the second projection, or the fourth projection can completely overlap with the second projection, wherein when the fourth projection partially overlaps with the second projection, the first projection can be located between the second projection and the third projection.

[0099] Based on the same application concept, an embodiment of the present application also provides an electronic device. Figure 22 This is a schematic diagram of the structure of the electronic device 20 provided in the embodiment of the present application, as shown in FIG. Figure 22 As shown, the electronic device 20 includes the display panel 10 in any of the above embodiments. Figure 22 As shown, the electronic device 20 includes a display panel 10. Therefore, the electronic device 20 also has the beneficial effects of the display panel 10 in the above embodiment. The similarities can be understood by referring to the above explanation of the display panel 10, which will not be repeated below.

[0100] The electronic device 20 provided in the embodiment of the present application can be Figure 22 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, industrial control equipment, medical display screens, touch interactive terminals, etc. The embodiments of this application do not specifically limit this.

[0101] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A display panel, characterized in that: The display panel includes a display area, and the display panel further includes: substrate; A plurality of pixel circuits arranged in an array on the base substrate, wherein the pixel circuits are electrically connected to the first scan line and the data line; a connecting line, one end of the connecting line being electrically connected to the data line, and the other end of the connecting line being electrically connected to the data input terminal, the connecting line comprising a first connecting line extending along a first direction and a second connecting line extending along a second direction, the first connecting line and the second connecting line being electrically connected, and the connecting line being at least partially located in the display area; A first active layer, wherein the first active layer includes a shielding portion, the shielding portion is connected to a constant voltage, and in a direction perpendicular to the display panel, the shielding portion at least partially overlaps with the first connecting line; or in a third direction, the orthographic projection of the shielding portion on the substrate is located between the first connecting line and the orthographic projection of the first scanning line on the substrate, and the third direction is parallel to the substrate.

2. The display panel according to claim 1, wherein: The first active layer further includes a first extending portion, and the constant voltage is transmitted to the shielding portion through the first extending portion.

3. The display panel according to claim 2, wherein: The display panel further includes a power supply voltage signal line, and the constant voltage is provided by the power supply voltage signal line.

4. The display panel according to claim 3, wherein: The display panel further includes a first metal layer, a second metal layer and a first source-drain electrode layer, wherein the first active layer, the first metal layer, the second metal layer and the first source-drain electrode layer are stacked in sequence in a direction away from the base substrate; One end of the power supply voltage signal line is electrically connected to the second metal layer, and the other end of the power supply voltage signal line is electrically connected to the shielding portion.

5. The display panel according to claim 3, wherein: The pixel circuit includes a first light emission control transistor, and a first electrode of the first light emission control transistor is electrically connected to the shielding portion through the first extension portion.

6. The display panel according to claim 5, wherein: There are multiple shielding parts and pixel circuits, two adjacent pixel circuits are corresponding to one shielding part, and the first electrodes of the first light emitting control transistors in the two adjacent pixel circuits are connected to the corresponding same shielding part.

7. The display panel according to claim 2, wherein: The pixel circuit further includes an initialization reset transistor, and the first scan line is electrically connected to a gate of the initialization reset transistor.

8. The display panel according to claim 2, wherein: The display panel also includes a first reference line. In a direction perpendicular to the display panel, the first connecting line, the shielding portion and the first reference line at least partially overlap. In a direction parallel to the display panel, the orthographic projection of the first reference line on the base substrate is at least partially located between the orthographic projection of the first connecting line and the first scanning line on the base substrate.

9. The display panel according to claim 2, wherein: The first active layer further includes active wiring, and a distance between one end of the shielding portion and an adjacent active wiring along the second direction is not less than 2.1 μm.

10. The display panel according to claim 2, wherein: The display panel further includes a bias adjustment signal line, and the constant voltage is provided by the bias adjustment signal line.

11. The display panel according to claim 10, wherein: The first active layer further includes a first extension portion, and the bias adjustment signal line and the shielding portion are electrically connected via the first extension portion.

12. The display panel according to claim 11, wherein: The pixel circuit includes a bias compensation transistor, and a first electrode of the bias compensation transistor is electrically connected to the shielding portion through the first extension portion.

13. The display panel according to claim 12, wherein: The pixel circuit further includes a first light emission control transistor, and the shielding portion is located on a side of the first electrode of the bias compensation transistor that is away from the first light emission control transistor along the second direction.

14. The display panel according to claim 12, wherein: There are multiple shielding parts and pixel circuits, two adjacent pixel circuits are correspondingly provided to one shielding part, and the first electrodes of the bias compensation transistors in the two adjacent pixel circuits are connected to the corresponding same shielding part.

15. The display panel according to claim 12, wherein: The first scan line is electrically connected to the gate of the bias compensation transistor.

16. The display panel according to claim 10, wherein: In a direction parallel to the display panel, an orthographic projection of the bias adjustment signal line on the base substrate is at least partially located between an orthographic projection of the first connection line and the first scan line on the base substrate.

17. An electronic device, characterized in that: The electronic device comprises the display panel according to any one of claims 1 to 16.

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