Display device

Abstract

A display device includes: a display area in which a plurality of first pixels and a plurality of second pixels including a plurality of pixel electrodes spaced apart from each other are disposed; a first light blocking layer disposed in the display area, and the first light blocking layer including a plurality of holes disposed to overlap the plurality of pixel electrodes; a plurality of color filters disposed on the first light blocking layer to correspond to the plurality of holes; and a second light blocking layer disposed on the plurality of color filters and disposed to correspond to the plurality of pixel electrodes of the plurality of second pixels, the first light blocking layer further including a plurality of separation portions disposed around the plurality of holes of the plurality of second pixels and penetrating the first light blocking layer, and a plurality of color filters disposed in the plurality of second pixels are disposed to cover the plurality of holes of the first light blocking layer and the plurality of separation portions disposed to correspond to the plurality of holes.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived therefrom from Korean Patent Application No. 10-2024-0023566, filed on February 19, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] With the development of an information-oriented society, there is an increasing demand for display devices for displaying images in various ways. For example, display devices are used in various electronic devices such as smartphones, digital cameras, laptop computers, navigation devices, and smart televisions, and can be flat panel display devices such as liquid crystal display devices, field emission display devices, and organic light-emitting display devices. Among flat panel display devices, in light-emitting display devices, since each pixel of the display panel includes a light-emitting element that can emit light by itself, it is possible to display images without a backlight unit that provides light to the display panel. Summary of the Invention

[0005] Aspects of the present invention provide a display device including a plurality of light blocking layers disposed in different layers.

[0006] Aspects of the present invention provide a display device capable of providing a privacy protection mode by including a light blocking layer provided in some pixels.

[0007] However, aspects of the present invention are not limited to those described herein. The above and other aspects of the present invention will become more apparent to those skilled in the art by referring to the detailed description of the present invention given below.

[0008] According to one aspect of the present invention, a display device is provided, which includes: a display area, in which a plurality of first pixels and a plurality of second pixels including a plurality of pixel electrodes spaced apart from each other are arranged; a first light blocking layer, arranged in the display area, and the first light blocking layer includes a plurality of holes arranged to overlap with the plurality of pixel electrodes; a plurality of color filters, arranged on the first light blocking layer, and the plurality of color filters are respectively arranged to correspond to the plurality of holes; and a second light blocking layer, arranged on the plurality of color filters, and the second light blocking layer is arranged to correspond to the plurality of pixel electrodes of the plurality of second pixels, wherein the first light blocking layer also includes a plurality of partitioning portions arranged around the plurality of holes arranged in the plurality of second pixels among the plurality of holes and penetrating the first light blocking layer, and among the plurality of color filters, the plurality of color filters arranged in the plurality of second pixels are arranged to cover the plurality of holes of the first light blocking layer and the plurality of partitioning portions arranged to correspond to the plurality of holes.

[0009] In an embodiment, the first light blocking layer includes: a first hole, overlapping with the first pixel electrode of the first pixel among the multiple first pixels; a second hole, overlapping with the second pixel electrode of the first pixel among the multiple first pixels; a third hole, overlapping with the first pixel electrode of the second pixel among the multiple second pixels; and a fourth hole, overlapping with the second pixel electrode of the second pixel among the multiple second pixels, wherein the diameter of the first hole is larger than the diameter of the third hole.

[0010] In an embodiment, a distance between the first hole and the second hole in the first pixel is smaller than a distance between the third hole and the fourth hole in the second pixel.

[0011] In an embodiment, the plurality of partitions include a first partition surrounding the third hole and a second partition surrounding the fourth hole, wherein a diameter of a region surrounded by the first partition is greater than a diameter of a region surrounded by the second partition.

[0012] In an embodiment, the second dividing portion includes a first sub-dividing portion surrounding the fourth hole and a second sub-dividing portion surrounding the first sub-dividing portion.

[0013] In an embodiment, the plurality of partitions are spaced apart from outer sides of the plurality of holes in the plurality of second pixels, and the plurality of partitions have a curved shape along the outer sides.

[0014] In an embodiment, the plurality of partitioning portions are provided between the plurality of holes located in the plurality of second pixels.

[0015] In an embodiment, the pixels among the multiple first pixels and the multiple second pixels include a first pixel electrode and a second pixel electrode having a diameter smaller than the diameter of the first pixel electrode, and wherein the second light blocking layer includes: a first light blocking pattern surrounding the outer side of the first pixel electrode of the second pixel among the multiple second pixels, and the first light blocking pattern forming a first transmission portion overlapping with the first pixel electrode of the second pixel among the multiple second pixels; and a second light blocking pattern surrounding the outer side of the second pixel electrode of the second pixel among the multiple second pixels, and the second light blocking pattern forming a second transmission portion overlapping with the second pixel electrode of the second pixel among the multiple second pixels.

[0016] In an embodiment, a diameter of the first transmissive portion is greater than a diameter of the second transmissive portion.

[0017] In an embodiment, a spacing distance between the outer side of the first pixel electrode and the inner side of the first light-blocking pattern is different from a spacing distance between the outer side of the second pixel electrode and the inner side of the second light-blocking pattern.

[0018] According to one aspect of the present invention, a display device is provided, comprising: a substrate on which a first pixel and a second pixel including a plurality of pixel electrodes are provided; an encapsulation layer provided on the plurality of pixel electrodes; a first light blocking layer provided on the encapsulation layer, the first light blocking layer including a plurality of holes, each of the plurality of holes being provided to correspond to a corresponding one of the plurality of pixel electrodes; a plurality of color filters provided on the first light blocking layer, the plurality of color filters being provided to correspond to the plurality of holes, respectively; a passivation layer provided on the plurality of color filters and the first light blocking layer; a second light blocking layer provided on the passivation layer in the second pixel, the second light blocking layer including a plurality of light-blocking patterns forming a plurality of transmissive portions, the plurality of transmissive portions respectively overlapping with the plurality of pixel electrodes of the second pixel; and an outer coating layer disposed on the second light-blocking layer, wherein the plurality of pixel electrodes include a first pixel electrode and a second pixel electrode disposed in each of the first pixel and the second pixel, the second pixel electrode having a diameter smaller than a diameter of the first pixel electrode, the first light-blocking layer being disposed around a plurality of holes disposed in the second pixel among the plurality of holes, and the first light-blocking layer including a plurality of partition portions penetrating the first light-blocking layer, and, among the color filters, the plurality of color filters disposed in the second pixel being disposed to cover the plurality of partition portions.

[0019] In an embodiment, the passivation layer includes: a first passivation layer disposed on the first light blocking layer and the plurality of color filters; and a second passivation layer disposed on the first passivation layer.

[0020] In an embodiment, the first passivation layer is disposed to cover a plurality of color filters disposed in the first pixel among the plurality of color filters and the first light blocking layer in the first pixel, and the first passivation layer is patterned to partially expose the plurality of color filters in the second pixel.

[0021] In an embodiment, the first passivation layer has a refractive index lower than a refractive index of the second passivation layer.

[0022] In an embodiment, the first passivation layer contacts the second passivation layer disposed on the plurality of color filters disposed in the second pixel and forms an inclined side surface.

[0023] In an embodiment, the first light blocking layer includes: a first hole overlapping with the first pixel electrode of the first pixel; a second hole overlapping with the second pixel electrode of the first pixel; a third hole overlapping with the first pixel electrode of the second pixel; and a fourth hole overlapping with the second pixel electrode of the second pixel, wherein the diameter of the first hole is larger than the diameter of the third hole, and wherein, among the multiple color filters, the thickness of the color filter arranged on the first hole is smaller than the thickness of the color filter arranged on the third hole.

[0024] In an embodiment, among the plurality of color filters, a thickness of a color filter disposed on the second hole is thinner than a thickness of a color filter disposed on the fourth hole.

[0025] In an embodiment, among the plurality of color filters, a thickness difference between the color filter disposed on the first hole and the color filter disposed on the third hole is different from a thickness difference between the color filter disposed on the second hole and the color filter disposed on the fourth hole.

[0026] In an embodiment, the plurality of color filters overlap one another on the first light blocking layer.

[0027] In an embodiment, on the first light blocking layer, the color filter disposed on the second hole among the plurality of color filters is disposed on the color filter disposed on the first hole.

[0028] According to an embodiment, a display device may include a plurality of light blocking layers, wherein the plurality of light blocking layers may have a shape corresponding to and surrounding a pixel electrode. The display device may include a partition formed in the light blocking layer to reduce thickness deviation of a color filter according to the width of the light blocking layer provided in different pixels, thereby reducing transmittance difference.

[0029] However, the effects according to the embodiments of the present invention are not limited to the effects exemplified above, and various other effects are included herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present invention will become more apparent by describing in detail embodiments of the present invention with reference to the accompanying drawings, in which:

[0031] Figure 1 is a schematic perspective view of an electronic device according to an embodiment;

[0032] Figure 2 is a perspective view showing a display device included in an electronic device according to an embodiment;

[0033] Figure 3 According to the embodiment, the embodiment is viewed from the side Figure 2 A cross-sectional view of a display device;

[0034] Figure 4 is a plan view of an arrangement of pixel electrodes in a display area of a display device according to an embodiment;

[0035] Figure 5 is a plan view showing the arrangement of a pixel electrode and a first light blocking layer in a display area of a display device according to an embodiment;

[0036] Figure 6 is a plan view showing the arrangement of a pixel electrode and a second light blocking layer in a display area of a display device according to an embodiment;

[0037] Figure 7 is a schematic diagram illustrating a light-emitting pixel according to an emission mode of a display device according to an embodiment;

[0038] Figure 8 According to the embodiment of the invention Figure 5 and Figure 6 A cross-sectional view taken along line X1-X1';

[0039] Figure 9 According to the embodiment of the invention Figure 5 and Figure 6 A cross-sectional view taken along line X2-X2';

[0040] Figure 10 According to the embodiment of the invention Figure 6 A cross-sectional view taken along line X3-X3' and line X4-X4';

[0041] Figure 11 is a diagram illustrating relative arrangement of a pixel electrode and a first light blocking layer provided in one pixel of a display device according to an embodiment;

[0042] Figure 12 is a diagram showing a cross section of a second pixel of a display device according to another embodiment;

[0043] Figure 13 is a diagram illustrating a cross section of a first pixel and a second pixel of a display device according to another embodiment;

[0044] Figure 14 is a plan view showing the arrangement of a pixel electrode and a first light blocking layer in a display area of a display device according to another embodiment;

[0045] Figure 15 is a plan view showing the arrangement of a pixel electrode and a first light blocking layer in a display area of a display device according to another embodiment;

[0046] Figure 16 is a plan view showing the arrangement of a pixel electrode and a first light blocking layer in a display area of a display device according to another embodiment;

[0047] Figure 17 is a cross-sectional view of a display device according to another embodiment;

[0048] Figure 18 is a cross-sectional view of a display device according to another embodiment;

[0049] Figure 19 is a cross-sectional view of a display device according to yet another embodiment; and

[0050] Figure 20 is a cross-sectional view of a display device according to yet another embodiment. DETAILED DESCRIPTION

[0051] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. However, the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art.

[0052] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like components throughout the specification. In the drawings, the thickness of layers and regions are exaggerated for clarity.

[0053] Although the terms "first", "second" etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms can be used to distinguish an element from another element. Therefore, without departing from the teaching of one or more embodiments, the first element discussed below can be referred to as the second element. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second" etc. can also be used to distinguish different categories or sets of elements in this article. For simplicity, the terms "first", "second" etc. can respectively represent "first category (or first set)", "second category (or second set)" etc.

[0054] It will also be understood that when a layer is referred to as being "connected to" or "coupled to" another element, layer, or substrate, the layer can be directly on the other element, layer, or substrate, or there can be intervening elements, layers, or substrates. Likewise, references to "below," "to the left of," and "to the right of" include instances where the layer is directly adjacent to the other element or where another layer or other material is interposed. For these purposes, the term "connected" can refer to a physical connection, an electrical connection, and / or a fluid connection, with or without intervening elements.

[0055] Unless otherwise indicated, the illustrated embodiments will be understood to provide features of different details that can implement some of the modes of the present disclosure in practice. Therefore, unless otherwise indicated, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged without departing from the scope of the present invention.

[0056] The use of cross-hatching and / or shading in the drawings is generally provided to clarify boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and / or any other characteristics, attributes, properties, etc. of elements.

[0057] In addition, in the accompanying drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. When embodiments can be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0058] In addition, the X-axis (first direction DR1), the Y-axis (second direction DR2), and the Z-axis (third direction DR3) are not limited to the three axes of the rectangular coordinate system, and thus the X-axis (first direction DR1), the Y-axis (second direction DR2), and the Z-axis (third direction DR3) can be interpreted in a broader sense. For example, the X-axis (first direction DR1), the Y-axis (second direction DR2), and the Z-axis (third direction DR3) can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0059] For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XY, YZ, or XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0060] For descriptive purposes, spatially relative terms such as "under," "beneath," "beneath," "down," "over," "up," "across," "high," and "side" (e.g., as in "sidewall") may be used herein and thereby describe the relationship of one element to another element(s) as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the accompanying drawings. For example, if the device in the drawings is turned over, an element described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features. Thus, the term "under" can encompass both the "over" and "under" orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0061] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "one", and "the" are also intended to include the plural forms. In addition, when used in this specification, the terms "comprises / comprising" and / or "includes / including" illustrate the presence of stated features, integral bodies, steps, operations, elements, components, and / or their groups, but do not exclude the presence or addition of one or more other features, integral bodies, steps, operations, elements, components, and / or their groups. It is also noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms rather than terms of degree, and are therefore used to illustrate the inherent deviations of measured values, calculated values, and / or provided values that will be recognized by those of ordinary skill in the art.

[0062] Various embodiments may be described herein with reference to cross-sectional and / or exploded views that are schematic representations of embodiments and / or intervening structures. Thus, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes of the regions shown, but rather include deviations in shape due to, for example, manufacturing. In this manner, the regions shown in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device and are therefore not intended to be limiting.

[0063] According to the convention of the art, some embodiments are described and shown in the form of functional blocks, units, components and / or modules in the accompanying drawings. It will be understood by those skilled in the art that these blocks, units, components and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connections, etc.) that can be formed using semiconductor-based manufacturing technology or other manufacturing technology. When blocks, units, components and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also conceivable that each block, unit, component and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and related circuits) that performs other functions. In addition, without departing from the scope of the present invention, each block, unit, component and / or module of some embodiments can be physically divided into two or more interactive and discrete blocks, units, components and / or modules. Furthermore, the blocks, units, components and / or modules of some embodiments may be physically combined into more complex blocks, units, components and / or modules without departing from the scope of the invention.

[0064] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the relevant art and the context of the present disclosure, and should not be interpreted in an idealized or overly formal sense.

[0065] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0066] Figure 1 is a schematic perspective view of an electronic device according to an embodiment.

[0067] In the examples and with reference to Figure 1 , electronic device 1 displays a moving image or a still image. Electronic device 1 may refer to any electronic device that provides a display screen. Examples of electronic device 1 may include televisions, laptop computers, monitors, billboards, IoT devices, mobile phones, smartphones, tablet personal computers (PCs), electronic watches, smart watches, watch phones, head-mounted displays, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, game consoles, digital cameras, and camcorders that provide a display screen.

[0068] In an embodiment, the electronic device 1 may include a display device 10 (eg, Figure 2 ). Examples of the display device 10 may include an inorganic light emitting diode display device, an organic light emitting display device, a quantum dot light emitting display device, a plasma display device, and a field emission display device. In the following description, the case where an organic light emitting diode display device is applied as the display device will be exemplified, but the present invention is not limited thereto, and other display devices can be applied within the scope of the same technical spirit.

[0069] In the embodiment, the shape of the electronic device 1 in a plan view can be modified in various ways. For example, in a plan view, the electronic device 1 can have a shape such as a horizontally elongated rectangular shape, a vertically elongated rectangular shape, a square shape, a quadrilateral shape with rounded corners (vertices), other polygonal shapes, and a circular shape. In a plan view, the shape of the display area DA of the electronic device 1 can also be similar to the overall shape of the electronic device 1. Figure 1 The electronic device 1 is shown having a rectangular shape elongated in the second direction DR2 in a plan view.

[0070] The electronic device 1 may include a display area DA and a non-display area NDA. The display area DA is an area where an image can be displayed, and the non-display area NDA is an area where an image is not displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DA may generally occupy the center of the electronic device 1.

[0071] In an embodiment, the display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The second display area DA2 and the third display area DA3 are areas in which components for adding various functions to the electronic device 1 are provided, and the second display area DA2 and the third display area DA3 may correspond to component areas.

[0072] Figure 2 is a perspective view illustrating a display device included in an electronic device according to an embodiment.

[0073] In the examples and with reference to Figure 2 , electronic device 1 (see Figure 1) may include a display device 10, wherein the display device 10 can provide a screen displayed in the electronic device 1. The display device 10 may have a planar shape similar to that of the electronic device 1. For example, in a plan view, the display device 10 may have a shape similar to a rectangular shape having short sides in the first direction DR1 and long sides in the second direction DR2. The edge where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be rounded to have a curvature, but is not limited thereto, and may be formed at a right angle. The planar shape of the display device 10 is not limited to a quadrilateral shape, and may be formed in a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0074] In an embodiment, the display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , and a touch driver 400 , wherein the display panel 100 may include a main area MA and a sub-area SBA.

[0075] The main area MA may include a display area DA and a non-display area NDA disposed around the display area DA. The display area DA includes pixels PX1, PX2, PX3, and PX4 that display an image (see FIG. Figure 4 ). The display area DA may be disposed at the center of the main area MA, and the non-display area NDA may surround the display area DA. The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. In an embodiment, the display panel 100 may include: a pixel circuit including a switching element; a pixel defining layer defining an emission area or an opening area; and a self-luminous element.

[0076] For example, the self-luminous element may include at least one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0077] The non-display area NDA may be an area disposed outside the display area DA and may be defined as an edge area of the main area MA of the display panel 100. The non-display area NDA may include a gate driver (not shown) supplying gate signals to the gate lines and a fan-out line (not shown) connecting the display driver 200 to the display area DA.

[0078] In an embodiment, the sub-area SBA may be an area extending from one side of the main area MA and may include a flexible material that can be bent, folded, or curled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (third direction DR3). The sub-area SBA may include a display driver 200 and a pad portion connected to the circuit board 300. In another embodiment, the sub-area SBA may be omitted, and the display driver 200 and the pad portion may be provided in the non-display area NDA.

[0079] In an embodiment, the display driver 200 may output a signal and a voltage for driving the display panel 100, wherein the display driver 200 may supply a data voltage to the data line. The display driver 200 may supply a power supply voltage to the power line and may supply a gate control signal to the gate driver. The display driver 200 may be formed as an integrated circuit (IC) and mounted on the display panel 100 by a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. In an embodiment, the display driver 200 may be disposed in a sub-area SBA and may overlap with the main area MA in a thickness direction by bending the sub-area SBA. In another embodiment, the display driver 200 may be mounted on a circuit board 300.

[0080] In an embodiment, the circuit board 300 may be attached to the pad portion of the display panel 100 using an anisotropic conductive film (ACF). The leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0081] In an embodiment, the touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be connected to the touch sensing unit of the display panel 100. The touch driver 400 may supply a touch drive signal to the multiple touch electrodes of the touch sensing unit and may sense the capacitance change between the multiple touch electrodes. For example, the touch drive signal may be a pulse signal having a predetermined frequency. The touch driver 400 may calculate whether an input has been made and the input coordinates based on the capacitance change between the multiple touch electrodes. The touch driver 400 may be formed as an integrated circuit (IC).

[0082] Figure 3 According to the embodiment, the embodiment is viewed from the side Figure 2 sectional view of a display device. Figure 3 Shown in folded state Figure 2 The sub-area SBA of the display panel 100 in the display device 10 is shown.

[0083] In the examples and with reference to Figure 3The display panel 100 may include a display layer DU, a touch sensing layer TSU, a color filter layer CFL, and a light blocking member layer PML. The display layer DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0084] In an embodiment, the substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or curled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. In another embodiment, the substrate SUB may include a glass material or a metal material.

[0085] In an embodiment, a thin film transistor layer TFTL may be disposed on a substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may also include gate lines, data lines, power lines, gate control lines, fan-out lines connecting the display driver 200 to the data lines, and leads connecting the display driver 200 to a pad portion. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a thin film transistor.

[0086] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistors, gate lines, data lines, and power lines of each pixel of the thin film transistor layer TFTL may be disposed in the display area DA. The gate control lines and fan-out lines of the thin film transistor layer TFTL may be disposed in the non-display area NDA. Lead lines of the thin film transistor layer TFTL may be disposed in the sub-area SBA.

[0087] In embodiments, a light-emitting element layer (EML) may be disposed on the thin film transistor layer (TFTL) and may include: a plurality of light-emitting elements, each including a first electrode, a second electrode, and a light-emitting layer to emit light; and a pixel-defining layer defining pixels. The plurality of light-emitting elements of the light-emitting element layer (EML) may be disposed in the display area (DA).

[0088] In an embodiment, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin film transistor of the thin film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may be respectively transported to the organic light-emitting layer through the hole transport layer and the electron transport layer and may be recombined with each other in the organic light-emitting layer to emit light.

[0089] In another embodiment, the light emitting element may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0090] In an embodiment, the encapsulation layer TFEL may cover the top and side surfaces of the light emitting element layer EML and may protect the light emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer for encapsulating the light emitting element layer EML.

[0091] In an embodiment, the touch sensing layer TSU may be provided on the encapsulation layer TFEL and may include a plurality of touch electrodes for sensing a user's touch in a capacitive manner and touch lines connecting the plurality of touch electrodes to the touch driver 400. For example, the touch sensing layer TSU may sense the user's touch by using a mutual capacitance method or a self-capacitance method.

[0092] In another embodiment, the touch sensing layer TSU may be provided on a separate substrate provided on the display layer DU. In this embodiment, the substrate supporting the touch sensing layer TSU may be a base member encapsulating the display layer DU.

[0093] In an embodiment, a plurality of touch electrodes of the touch sensing layer TSU may be provided in a touch sensor area overlapping the display area DA, and a touch line of the touch sensing layer TSU may be provided in a touch peripheral area overlapping the non-display area NDA.

[0094] In embodiments, a color filter layer (CFL) may be provided on the touch sensing layer (TSU) and may include multiple color filters corresponding to the multiple emission regions. Each color filter may selectively transmit light of a specific wavelength and may block or absorb light of a different wavelength. The color filter layer (CFL) may absorb a portion of light from outside the display device 10 to reduce reflected light caused by external light. Thus, the color filter layer (CFL) may prevent color distortion caused by reflection of external light.

[0095] Since the color filter layer CFL is directly disposed on the touch sensing layer TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively small.

[0096] In an embodiment, a light blocking member layer PML may be disposed on the color filter layer CFL and may include a light blocking pattern disposed to correspond to a specific pixel of the display layer DU. The display device 10 may further include a light blocking member layer PML to control visibility at a specific viewing angle and provide a privacy protection mode for the user.

[0097] In an embodiment, the display device 10 may further include an optical device 500, wherein the optical device 500 may be disposed in the second display area DA2 or the third display area DA3. The optical device 500 may transmit or receive light in the infrared band, the ultraviolet band, and the visible light band. For example, the optical device 500 may be an optical sensor (such as a proximity sensor, an illuminance sensor, a camera sensor, or an image sensor) that detects light incident on the display device 10.

[0098] Figure 4 is a plan view of an arrangement of pixel electrodes in a display area of a display device according to an embodiment. Figure 5 is a plan view illustrating the arrangement of a pixel electrode and a first light blocking layer in a display area of a display device according to an embodiment.

[0099] In the examples and with reference to Figure 4 and Figure 5 , also refer to Figure 1 、 Figure 3 and Figure 6 , the display device 10 may include a plurality of pixels PX1, PX2, PX3, and PX4 arranged in a display area DA. The plurality of pixels PX1, PX2, PX3, and PX4 may be arranged in a fourth direction DR4 and a fifth direction DR5, and the fourth direction DR4 and the fifth direction DR5 are oblique directions pointing between the first direction DR1 and the second direction DR2. The first pixel PX1 and the second pixel PX2 may be arranged adjacent to each other in the fifth direction DR5, and the second pixel PX2 and the third pixel PX3 may be arranged adjacent to each other in the fourth direction DR4. The third pixel PX3 and the fourth pixel PX4 may be arranged adjacent to each other in the fifth direction DR5. The plurality of pixels PX1, PX2, PX3, and PX4 may be arranged throughout the entire display area DA. Figure 4 The arrangement is set repeatedly.

[0100] In an embodiment, each of the plurality of pixels PX1, PX2, PX3, and PX4 may include a plurality of pixel electrodes AE1, AE2, and AE3. For example, each of the plurality of pixels PX1, PX2, PX3, and PX4 may include a first pixel electrode AE1, a second pixel electrode AE2, and a third pixel electrode AE3. One pixel in the plurality of pixels PX1, PX2, PX3, and PX4 may include one first pixel electrode AE1, two second pixel electrodes AE2, and one third pixel electrode AE3. However, the present invention is not limited thereto. The number of pixel electrodes AE1, AE2, and AE3 provided in the pixels PX1, PX2, PX3, and PX4 may be modified in various ways.

[0101] One pixel electrode AE1, AE2 or AE3 may be an anode electrode of a light emitting element included in each of the pixels PX1, PX2, PX3 and PX4. One pixel in the plurality of pixels PX1, PX2, PX3 and PX4 may include one or more light emitting elements ED (see Figure 8 ), and the light-emitting elements may be light-emitting elements that emit light of different colors. For example, the light-emitting element including the first pixel electrode AE1 may emit a red first light. The light-emitting element including the second pixel electrode AE2 may emit a green second light, and the light-emitting element including the third pixel electrode AE3 may emit a blue third light. However, the present invention is not limited thereto. One first pixel electrode AE1, two second pixel electrodes AE2, and one third pixel electrode AE3 may form one pixel among a plurality of pixels PX1, PX2, PX3, and PX4, emit light of different colors, and express a white grayscale. However, the present invention is not limited thereto, and the combination of the pixel electrodes AE1, AE2, and AE3 constituting one pixel among the plurality of pixels PX1, PX2, PX3, and PX4 may be modified in various ways according to the arrangement of the pixel electrodes AE1, AE2, and AE3 and the color of the light emitted by them, etc.

[0102] Each of the pixel electrodes AE1, AE2, and AE3 may form an emission region in each of the pixels PX1, PX2, PX3, and PX4. For example, the first pixel electrode AE1 may form a first emission region that emits light of a first color, the second pixel electrode AE2 may form a second emission region that emits light of a second color, and the third pixel electrode AE3 may form a third emission region that emits light of a third color. In an embodiment, the emission region of the display device 10 may be a region overlapping with the pixel electrodes AE1, AE2, and AE3, and for example, Figure 8 The pixel definition layer PDL shown in FIG Figure 8 ) may correspond to the emission region. For example, the emission region may be formed by a pixel definition layer PDL (see FIG. 1 ) formed in a light emitting element layer EML to be described later. Figure 8 ). The first emission region may be defined by a first opening of the pixel-defining layer overlapping with the first pixel electrode AE1, the second emission region may be defined by a second opening of the pixel-defining layer overlapping with the second pixel electrode AE2, and the third emission region may be defined by a third opening of the pixel-defining layer overlapping with the third pixel electrode AE3.

[0103] The plurality of pixel electrodes AE1, AE2 and AE3 may be arranged as follows: Type (e.g., diamond For example, the first pixel electrode AE1 and the third pixel electrode AE3 may be spaced apart from each other in the second direction DR2, and the first pixel electrode AE1 and the third pixel electrode AE3 may be alternately arranged in the first direction DR1 and the second direction DR2. The second pixel electrode AE2 may be spaced apart from another adjacent second pixel electrode AE2 in the first direction DR1 and the second direction DR2, and may be spaced apart from the adjacent first pixel electrode AE1 and the adjacent third pixel electrode AE3 in the fourth direction DR4 or the fifth direction DR5. A plurality of second pixel electrodes AE2 may be repeatedly arranged along the first direction DR1 and the second direction DR2, and the second pixel electrode AE2 and the first pixel electrode AE1, or the second pixel electrode AE2 and the third pixel electrode AE3 may be alternately arranged in the fourth direction DR4 or the fifth direction DR5.

[0104] In an embodiment, the areas or sizes of the first to third pixel electrodes AE1 to AE3 may be different from each other. Figure 4 In the embodiment of the present invention, the area of the third pixel electrode AE3 may be larger than the area of the first pixel electrode AE1 and the area of the second pixel electrode AE2, and the area of the first pixel electrode AE1 may be larger than the area of the second pixel electrode AE2. The intensity of the emitted light may vary according to the size of the emission area overlapping with the pixel electrodes AE1, AE2 and AE3, and the color displayed on the screen of the display device 10 or the electronic device 1 may be controlled by adjusting the size of the emission area. Figure 4 In the embodiment of the present invention, the third pixel electrode AE3 has the largest area, but is not limited thereto. The sizes of the pixel electrodes AE1, AE2, and AE3 and the areas of the emission regions can be freely adjusted according to the color of the screen required by the display device 10 and the electronic device 1. In addition, the areas of the pixel electrodes AE1, AE2, and AE3 can be adjusted to the same size as the light emitting element ED (see FIG. Figure 8 ) is related to light efficiency and lifespan, and may have a trade-off relation with reflection of external light. The areas of the pixel electrodes AE1, AE2, and AE3 may be adjusted in consideration of the above factors.

[0105] In an embodiment, the display device 10 may include a first light blocking layer BM1 and a plurality of color filters CF1 , CF2 , and CF3 disposed on the pixel electrodes AE1 , AE2 , and AE3 .

[0106] The first light blocking layer BM1 may be provided throughout the entire display area DA and may include a plurality of holes provided to correspond to the plurality of pixel electrodes AE1, AE2, and AE3. Each of the holes of the first light blocking layer BM1 may be provided to correspond to the pixel defining layer PDL (see FIG. Figure 8). The first light blocking layer BM1 may cover the display area DA except for the area where the hole is provided in the display area DA. The hole of the first light blocking layer BM1 may be a region that emits light emitted from the light emitting element including the pixel electrodes AE1, AE2, and AE3.

[0107] In an embodiment, in the first pixel PX1, the plurality of holes may include a first hole OPT1 overlapping the first pixel electrode AE1, a second hole OPT2 overlapping the second pixel electrode AE2, and a third hole OPT3 overlapping the third pixel electrode AE3. One first hole OPT1, two second holes OPT2, and one third hole OPT3 may be formed in the first light blocking layer BM1 within the area occupied by one first pixel PX1.

[0108] In a plan view, each of the multiple apertures may have a larger area than a corresponding one of the pixel electrodes AE1, AE2, and AE3. For example, in a plan view, the first aperture OPT1 of the first pixel PX1 may have a larger area than the first pixel electrode AE1. In a plan view, the areas of the second aperture OPT2 and the third aperture OPT3 may also be larger than the areas of the second pixel electrode AE2 and the third pixel electrode AE3, respectively. Furthermore, in a plan view, the apertures OPT1, OPT2, and OPT3 of the first light-blocking layer BM1 may have different areas. As described above, the areas of the multiple pixel electrodes AE1, AE2, and AE3 may differ from one another, and accordingly, the sizes of the apertures OPT1, OPT2, and OPT3 of the first light-blocking layer BM1 may also differ from one another. For example, the diameter or size of the third aperture OPT3 may be larger than the diameter or size of the first aperture OPT1 and the diameter or size of the second aperture OPT2, and the diameter or size of the first aperture OPT1 may be larger than the diameter or size of the second aperture OPT2. However, the present invention is not limited to this.

[0109] In an embodiment, in pixels PX1 and PX2 of the same type, the difference between the diameters of the pixel electrodes AE1, AE2, and AE3 and the diameters of the holes OPT1, OPT2, OPT3, OPT4, OPT5, and OPT6 of the first light blocking layer BM1, or the spacing distances between the outer sides of the pixel electrodes AE1, AE2, and AE3 and the inner sides of the holes OPT1, OPT2, OPT3, OPT4, OPT5, and OPT6, may be consistent regardless of the type of the pixel electrodes AE1, AE2, and AE3 or the holes OPT1, OPT2, OPT3, OPT4, OPT5, and OPT6. For example, in the first pixel PX1, the spacing distance between the first pixel electrode AE1 and the first hole OPT1 (or the difference between the diameters of the first pixel electrode AE1 and the first hole OPT1) may be equal to the spacing distance between the second pixel electrode AE2 and the second hole OPT2 (or the difference between the diameters of the second pixel electrode AE2 and the second hole OPT2). Similarly, the spacing distance between the first pixel electrode AE1 and the first hole OPT1 (or the difference between the diameter of the first pixel electrode AE1 and the diameter of the first hole OPT1) may also be equal to the spacing distance between the third pixel electrode AE3 and the third hole OPT3 (or the difference between the diameter of the third pixel electrode AE3 and the diameter of the third hole OPT3). As another example, in the second pixel PX2, the spacing distance between the first pixel electrode AE1 and the fourth hole OPT4 (or the difference between the diameter of the first pixel electrode AE1 and the diameter of the fourth hole OPT4) may be equal to the spacing distance between the second pixel electrode AE2 and the fifth hole OPT5 (or the difference between the diameter of the second pixel electrode AE2 and the diameter of the fifth hole OPT5). The spacing distance between the first pixel electrode AE1 and the fourth hole OPT4 (or the difference between the diameter of the first pixel electrode AE1 and the diameter of the fourth hole OPT4) may also be equal to the spacing distance between the third pixel electrode AE3 and the sixth hole OPT6 (or the difference between the diameter of the third pixel electrode AE3 and the diameter of the sixth hole OPT6). However, the present invention is not limited thereto, and in pixels PX1 and PX2 of the same type, the spacing distances between the pixel electrodes AE1, AE2 and AE3 and the holes OPT1, OPT2, OPT3, OPT4, OPT5 and OPT6 of the first light blocking layer BM1 may be different depending on the type of the pixel electrodes AE1, AE2 and AE3.

[0110] According to an embodiment, the display device 10 may include different types of pixels PX1, PX2, PX3, and PX4, wherein the holes of the first light blocking layer BM1 have different sizes. For example, in the first pixel PX1 and the third pixel PX3, the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1 may have the same diameter. In addition, in the second pixel PX2 and the fourth pixel PX4, the holes OPT4, OPT5, and OPT6 of the first light blocking layer BM1 may have the same diameter. However, in the first pixel PX1 and the second pixel PX2, the holes of the same type of the first light blocking layer BM1 (e.g., holes OPT1 and OPT4) may have different diameters.

[0111] For example, in an embodiment, the plurality of holes of the first light blocking layer BM1 may include a fourth hole OPT4 overlapping the first pixel electrode AE1, a fifth hole OPT5 overlapping the second pixel electrode AE2, and a sixth hole OPT6 overlapping the third pixel electrode AE3 in the second pixel PX2. One fourth hole OPT4, two fifth holes OPT5, and one sixth hole OPT6 may be formed in the first light blocking layer BM1 within the area occupied by one second pixel PX2.

[0112] In a plan view, the fourth aperture OPT4 of the second pixel PX2 may have a larger area than the first pixel electrode AE1. In a plan view, the fifth aperture OPT5 and the sixth aperture OPT6 may also have larger areas than the second pixel electrode AE2 and the third pixel electrode AE3, respectively. The diameter or size of the sixth aperture OPT6 may be larger than the diameter or size of the fourth aperture OPT4 and the diameter or size of the fifth aperture OPT5, and the diameter or size of the fourth aperture OPT4 may be larger than the diameter or size of the fifth aperture OPT5. However, the present invention is not limited thereto.

[0113] According to an embodiment, the same type of pixel electrodes AE1, AE2, and AE3 in the first pixel PX1 and the second pixel PX2 may have the same diameter, while the apertures corresponding to the same type of pixel electrodes AE1, AE2, and AE3 in the first pixel PX1 and the second pixel PX2 may have different diameters. For example, the diameter of the first aperture OPT1 corresponding to the first pixel electrode AE1 of the first pixel PX1 may be larger than the diameter of the fourth aperture OPT4 corresponding to the first pixel electrode AE1 of the second pixel PX2. The diameter of the second aperture OPT2 corresponding to the second pixel electrode AE2 of the first pixel PX1 may be larger than the diameter of the fifth aperture OPT5 corresponding to the second pixel electrode AE2 of the second pixel PX2. The diameter of the third aperture OPT3 corresponding to the third pixel electrode AE3 of the first pixel PX1 may be larger than the diameter of the sixth aperture OPT6 corresponding to the third pixel electrode AE3 of the second pixel PX2. In different pixels PX1 and PX2 , the pixel electrodes AE1 , AE2 , and AE3 may have the same diameter, but the holes may have different diameters, and spacing distances between the pixel electrodes AE1 , AE2 , and AE3 and the holes may be different from each other.

[0114] According to an embodiment, the display device 10 may include pixels PX1, PX2, PX3, and PX4, each of which has different spacing distances between the pixel electrodes AE1, AE2, and AE3 and the apertures OPT1, OPT2, and OPT3 of the first light blocking layer BM1. For example, in the first pixel PX1 and the third pixel PX3, the spacing distances between the pixel electrodes AE1, AE2, and AE3 and the apertures OPT1, OPT2, and OPT3 of the first light blocking layer BM1 may be equal to each other. Furthermore, in the second pixel PX2 and the fourth pixel PX4, the spacing distances between the pixel electrodes AE1, AE2, and AE3 and the apertures OPT4, OPT5, and OPT6 of the first light blocking layer BM1 may be equal to each other. However, in the first pixel PX1 and the second pixel PX2, the spacing distances between the pixel electrodes AE1, AE2, and AE3 and the apertures OPT1 to OPT3 and OPT4 to OPT6 of the first light blocking layer BM1 may be different from each other. In an embodiment, a spacing distance between the pixel electrodes AE1, AE2, and AE3 in the first pixel PX1 and the third pixel PX3 and the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1 may be greater than a spacing distance between the pixel electrodes AE1, AE2, and AE3 in the second pixel PX2 and the fourth pixel PX4 and the holes OPT4, OPT5, and OPT6 of the first light blocking layer BM1. In the second pixel PX2 and the fourth pixel PX4, a difference in diameter between the pixel electrodes AE1, AE2, and AE3 and the holes OPT4, OPT5, and OPT6 of the first light blocking layer BM1 may be small, and outer sides of the pixel electrodes AE1, AE2, and AE3 and inner sides of the holes OPT4, OPT5, and OPT6 may be positioned adjacent to each other in a plan view.

[0115] According to an embodiment, the first light-blocking layer BM1 may include a plurality of partitions DBP1, DBP2, and DBP3 disposed in the second-type pixels (e.g., the second pixel PX2 and the fourth pixel PX4). The partitions DBP1, DBP2, and DBP3 may be formed to penetrate the first light-blocking layer BM1 in a manner similar to the holes of the first light-blocking layer BM1. The partitions DBP1, DBP2, and DBP3 may be disposed around the holes OPT4, OPT5, and OPT6 of the first light-blocking layer BM1 located in the second pixel PX2, and in some embodiments, the partitions DBP1, DBP2, and DBP3 may surround the holes OPT4, OPT5, and OPT6 of the first light-blocking layer BM1.

[0116] For example, the partitions DBP1, DBP2, and DBP3 may include a first partition DBP1 disposed around the fourth hole OPT4 in the second pixel PX2, a second partition DBP2 disposed around the fifth hole OPT5, and a third partition DBP3 disposed around the sixth hole OPT6. The plurality of partitions DBP1, DBP2, and DBP3 may have a predetermined width and surround the pixel electrodes AE1, AE2, and AE3 or the holes OPT4, OPT5, and OPT6. The separation pattern of the first light blocking layer BM1 may remain between the holes OPT4, OPT5, and OPT6 and the partitions DBP1, DBP2, and DBP3.

[0117] In an embodiment, since a plurality of partitions DBP1, DBP2, and DBP3 are formed to surround the holes OPT4, OPT5, and OPT6, respectively, the different partitions DBP1, DBP2, and DBP3 may have different sizes. For example, the diameter of the portion surrounded by the first partition DBP1 may be larger than the diameter of the portion surrounded by the second partition DBP2, and may be smaller than the diameter of the portion surrounded by the third partition DBP3. The size relationship of the plurality of partitions DBP1, DBP2, and DBP3 may be the same as the size relationship of the diameters of the holes OPT4, OPT5, and OPT6 (or the diameters of the pixel electrodes AE1, AE2, and AE3).

[0118] In the first light-blocking layer BM1, the diameters of the apertures OPT1, OPT2, and OPT3 disposed in the first pixel PX1 and the diameters of the apertures OPT4, OPT5, and OPT6 disposed in the second pixel PX2 may differ from each other. Therefore, the distance between two adjacent apertures, or the width of the pattern of the first light-blocking layer BM1, may differ between the first pixel PX1 and the second pixel PX2. For example, the distance between the first aperture OPT1 and the second aperture OPT2 in the first pixel PX1 may be smaller than the distance between the fourth aperture OPT4 and the fifth aperture OPT5 in the second pixel PX2. As will be described later, color filters CF1, CF2, and CF3 may be disposed on the first light-blocking layer BM1, and the thickness of the color filters CF1, CF2, and CF3 may vary depending on the width of the pattern of the first light-blocking layer BM1. Since the distance between two adjacent holes OPT1, OPT2 and OPT3 in the first pixel PX1 is smaller than the distance between two adjacent holes OPT4, OPT5 and OPT6 in the second pixel PX2, the thickness of the color filters CF1, CF2 and CF3 set in the first pixel PX1 can be smaller than the thickness of the color filters CF1, CF2 and CF3 set in the second pixel PX2.

[0119] Since the thickness of the color filters CF1, CF2, and CF3 provided in the second pixel PX2 is relatively thick, the transmittance of light may be reduced. In an embodiment, a plurality of partitions DBP1, DBP2, and DBP3 may be provided around the holes OPT4, OPT5, and OPT6 of the second pixel PX2, and may be used to reduce the thickness of the color filters CF1, CF2, and CF3. The color filters CF1, CF2, and CF3 may be provided to cover all of the plurality of holes and the partitions DBP1, DBP2, and DBP3, and may have a reduced thickness by filling the space formed by the plurality of partitions DBP1, DBP2, and DBP3. Accordingly, the thickness difference between the color filters CF1, CF2, and CF3 in the first pixel PX1 and the second pixel PX2 may be reduced, and the transmittance difference between the two pixels may be reduced. A more detailed description will be given later.

[0120] In an embodiment, the display device 10 may include first-type pixels such as first and third pixels PX1 and PX3, and second-type pixels such as second and fourth pixels PX2 and PX4. In addition to the provision of partitions DBP1, DBP2, and DBP3, the first-type pixels and the second-type pixels may be distinguished based on the spacing distance between the pixel electrodes AE1, AE2, and AE3 and the apertures of the first light-blocking layer BM1, or the difference in diameter of the apertures, and the provision of the second light-blocking layer BM2, which will be described later. For example, the second light-blocking layer BM2 may not be provided in the first and third pixels PX1 and PX3, and the second light-blocking layer BM2 may be provided in the second and fourth pixels PX2 and PX4.

[0121] In an embodiment, a plurality of color filters CF1, CF2 and CF3 (see Figure 8 ) may be provided to correspond to the pixel electrodes AE1, AE2, and AE3, respectively. For example, the color filters CF1, CF2, and CF3 may be provided on the first light blocking layer BM1 and may be provided to correspond to the plurality of holes in the first light blocking layer BM1. The holes of the first light blocking layer BM1 may be formed to correspond to the pixel defining layer PDL (see Figure 8 ) overlap with the opening of the first light blocking layer BM1 and may form a light exit area through which light emitted from the emission area is emitted. The color filters CF1, CF2, and CF3 may have an area larger than the area of the hole of the first light blocking layer BM1, and the color filters CF1, CF2, and CF3 may completely cover the light exit area formed by the hole. The color filters CF1, CF2, and CF3 may completely cover the hole of the first light blocking layer BM1, and some of the color filters CF1, CF2, and CF3 may be directly disposed on the first light blocking layer BM1. However, in an embodiment, the color filters CF1, CF2, and CF3 may be omitted.

[0122] In an embodiment, the color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 that are arranged to correspond to different pixel electrodes AE1, AE2, and AE3, respectively. The color filters CF1, CF2, and CF3 may include a colorant such as a dye or pigment that absorbs light in a wavelength band different from the light in the specific wavelength band, and may be arranged to correspond to the color of the light emitted by the light-emitting element including the pixel electrodes AE1, AE2, and AE3. For example, the first color filter CF1 may be a red color filter that is arranged to overlap with the first pixel electrode AE1 and can only transmit red first light. The second color filter CF2 may be a green color filter that is arranged to overlap with the second pixel electrode AE2 and can only transmit green second light, and the third color filter CF3 may be a blue color filter that is arranged to overlap with the third pixel electrode AE3 and can only transmit blue third light.

[0123] Similar to the arrangement of the pixel electrodes AE1, AE2 and AE3, the color filters CF1, CF2 and CF3 may be arranged as follows: Type (e.g., diamond Type). For example, the first color filter CF1 and the third color filter CF3 may be alternately arranged in the first direction DR1 and the second direction DR2. The second color filter CF2 and another adjacent second color filter CF2 may be arranged in the first direction DR1 and the second direction DR2, and the second color filter CF2 and the adjacent first color filter CF1 and the adjacent third color filter CF3 may be arranged in the fourth direction DR4 or the fifth direction DR5. A plurality of second color filters CF2 may be repeatedly arranged along the first direction DR1 and the second direction DR2, and the second color filter CF2 and the first color filter CF1, or the second color filter CF2 and the third color filter CF3 may be alternately arranged along the fourth direction DR4 or the fifth direction DR5.

[0124] According to an embodiment, the multiple color filters CF1, CF2, and CF3 may have different areas in a plan view. As described above, the areas of the multiple pixel electrodes AE1, AE2, and AE3 may differ from one another, and accordingly, the size of the aperture of the first light-blocking layer BM1 and the areas of the color filters CF1, CF2, and CF3 may also differ from one another in a plan view. For example, the area of the first color filter CF1, which is a red color filter, may be larger than the area of the second color filter CF2, which is a green color filter, and the area of the third color filter CF3, which is a blue color filter. In addition, the area of the third color filter CF3 may be larger than the area of the second color filter CF2. The shape of the color filters CF1, CF2, and CF3 in a plan view may be a circular shape similar to the shape of the pixel electrodes AE1, AE2, and AE3. However, the present invention is not limited to this, and the color filters CF1, CF2, and CF3 may have a rectangular or diamond shape in a plan view. The display device 10 according to the embodiment may be designed such that the planar shapes and areas of the color filters CF1 , CF2 , and CF3 allow external light of the display device 10 to have a specific color.

[0125] In an embodiment, the planar area ratio of the first color filter CF1 and the second color filter CF2 may be in a range of about 1:0.3 to about 1:0.7, and the planar area ratio of the first color filter CF1 and the third color filter CF3 may be in a range of about 1:0.4 to about 1:1. For example, the planar area ratio of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be about 1:0.59:0.52 or about 1:0.59:1. However, the planar area ratio of the color filters CF1, CF2, and CF3 is not limited to that described above, and the planar areas of the color filters CF1, CF2, and CF3 may be designed differently so that the reflected light in the display device 10 and the electronic device 1 has a desired color coordinate.

[0126] In an embodiment, the display device 10 may include color filters CF1, CF2, and CF3 disposed on the display layer DU to reduce the intensity of reflected light caused by external light. In addition, the color of the reflected light of the external light can be controlled by adjusting the arrangement, shape, and area of the color filters CF1, CF2, and CF3 in a plan view.

[0127] In an embodiment, the touch electrode TL may be disposed between the pixel electrodes AE1, AE2, and AE3. The touch electrode TL may be disposed to extend in the fourth direction DR4 and the fifth direction DR5 and may be spaced apart from the pixel electrodes AE1, AE2, and AE3. The touch electrode TL may be disposed to extend in the fourth direction DR4 and the fifth direction DR5 and may be spaced apart from the pixel electrodes AE1, AE2, and AE3. Figure 8) overlaps the first light blocking layer BM1. Although the touch electrode TL is briefly shown in the drawings, the touch electrode TL may include a touch driving electrode and a sensing electrode.

[0128] Figure 6 is a plan view illustrating the arrangement of a pixel electrode and a second light blocking layer in a display area of a display device according to an embodiment. Figure 7 is a schematic diagram illustrating light-emitting pixels according to an emission mode of a display device according to an embodiment. Figure 7 The display device 10 (see Figure 3 ) in an emission mode in which the side visibility of the luminous pixel is partially limited.

[0129] In the examples and with reference to Figure 6 and Figure 7 , also refer to Figure 5 , the display device 10 may include a second light blocking layer BM2. The second light blocking layer BM2 may be provided only in some of the plurality of pixels in the display area DA. For example, the second light blocking layer BM2 may be provided in the second type pixels (e.g., the second pixel PX2 and the fourth pixel PX4) among the plurality of pixels. As described above, the plurality of pixels may include two types of pixels in which the pixel electrodes AE1, AE2, and AE3 and the apertures of the first light blocking layer BM1 have different diameters, and the second light blocking layer BM2 may be provided only in the second type pixels.

[0130] In an embodiment, the second light-blocking layer BM2 may include a plurality of light-blocking patterns, and the light-blocking patterns may be arranged to correspond to the plurality of pixel electrodes AE1, AE2, and AE3. For example, the light-blocking patterns may each have a uniform width and may be arranged to surround the pixel electrodes AE1, AE2, and AE3 without overlapping the pixel electrodes AE1, AE2, and AE3 in a plan view. The light-blocking patterns may have a ring shape that surrounds the pixel electrodes AE1, AE2, and AE3 in a plan view without overlapping the pixel electrodes AE1, AE2, and AE3. Similar to the apertures of the first light-blocking layer BM1, the inner sides of the light-blocking patterns may be spaced apart from the outer sides of the pixel electrodes AE1, AE2, and AE3 in a plan view.

[0131] In the display device 10, according to an embodiment, the plurality of pixels may include first-type pixels in which the second light-blocking layer BM2 is not provided and second-type pixels in which the second light-blocking layer BM2 is provided, so that side visibility can be adjusted according to the emission mode. Depending on the viewing angle of the display device 10, the light-blocking pattern of the second light-blocking layer BM2 may partially cover the pixel electrodes AE1, AE2, and AE3, and may block emission of light at a specific viewing angle.

[0132] For example, in an embodiment, in the first emission mode of the display device 10, when side visibility is not restricted, both the first type pixel and the second type pixel can emit light. Figure 6 As shown in , when all pixels PX1, PX2, PX3, and PX4 emit light in the first emission mode, light emitted from at least the first pixel PX1 and the third pixel PX3 can be visually recognized by the user no matter from which direction the user looks at the display device 10.

[0133] On the other hand, in an embodiment, in the second emission mode of the display device 10, when it is necessary to limit the side visibility, only the second type of pixels can emit light. Figure 7 As shown in FIG, when only the second pixel PX2 and the fourth pixel PX4 emit light in the second emission mode, light emitted from the holes OPT4, OPT5, and OPT6 of the first light-blocking layer BM1 can be blocked by the second light-blocking layer BM2 at a specific viewing angle. Since the first pixel PX1 and the third pixel PX3 do not emit light, the screen of the display device 10 in the second emission mode can be visually recognized only by users viewing from the front of the display area DA, and may not be visually recognized by users viewing from a specific viewing angle or from the side. The display device 10 can provide a privacy protection mode for the user.

[0134] In the second emission mode of the display device 10, light leakage of light emitted from the pixel electrodes AE1, AE2, and AE3 of the second pixel PX2 and the fourth pixel PX4 may occur depending on the extent to which the pixel electrodes AE1, AE2, and AE3 of the second pixel PX2 and the fourth pixel PX4 are covered by the second light-blocking layer BM2. However, in the display device 10 according to the embodiment, the light-blocking pattern of the second light-blocking layer BM2 can be provided to surround the pixel electrodes AE1, AE2, and AE3 corresponding to the shape of the pixel electrodes AE1, AE2, and AE3. In the display device 10, the extent to which the pixel electrodes AE1, AE2, and AE3 of the second-type pixels are covered can be uniform at all viewing angles when viewing the display device 10 in the second emission mode, and light leakage of light emitted from the light-emitting elements including the specific pixel electrodes AE1, AE2, and AE3 can be prevented.

[0135] In addition, in the embodiment, in the display device 10, since the light blocking pattern of the second light blocking layer BM2 is arranged to correspond to the pixel electrodes AE1, AE2, and AE3 of the second type pixels, the light blocking pattern of the second light blocking layer BM2 can not interfere with other adjacent pixels (for example, first type pixels), and thus can not cover the pixel electrodes of the first type pixels in the first emission mode. That is, in the display device 10, even in the embodiment of a high-resolution display device, the arrangement of the pixel structure can be freely designed.

[0136] Figure 8 According to the embodiment of the invention Figure 5 and Figure 6 A cross-sectional view taken along line X1-X1'. Figure 9 According to the embodiment of the invention Figure 5 and Figure 6 A cross-sectional view taken along line X2-X2'. Figure 10 According to the embodiment of the invention Figure 6 A cross-sectional view taken along line X3-X3' and line X4-X4'.

[0137] Figure 8 A cross section is shown spanning pixel electrodes AE1 , AE2 , and AE3 in a first pixel PX1 , which is a first-type pixel. Figure 9 A cross section is shown spanning pixel electrodes AE1 , AE2 , and AE3 in a second pixel PX2 , which is a second type pixel. Figure 10 A cross section spanning the first pixel electrode AE1 of a first type pixel and the first pixel electrode AE1 of a second type pixel is shown.

[0138] Will refer to Figures 8 to 10 Description of the display device 10 (see Figure 3 ) cross-sectional structure. In the embodiment, the display panel 100 (see Figure 3 ) may include a display layer DU, a touch sensing layer TSU, a first light blocking layer BM1, a color filter layer CFL, and a second light blocking layer BM2. The display layer DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL. The first light blocking layer BM1 may be disposed on the touch sensing layer TSU of the display panel 100, and the color filters CF1, CF2, and CF3 of the color filter layer CFL may be disposed on the first light blocking layer BM1. The second light blocking layer BM2 may be disposed on the passivation layers PSV1 and PSV2, which are disposed on the color filter layer CFL, and an overcoat layer OC may be disposed on the second light blocking layer BM2.

[0139] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or rolled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. In another embodiment, the substrate SUB may include a glass material or a metal material.

[0140] The thin film transistor layer TFTL may include a first buffer layer BF1, a lower metal layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first protection layer PAS1, a second connection electrode CNE2, and a second protection layer PAS2.

[0141] The first buffer layer BF1 may be disposed on the substrate SUB and may include an inorganic layer capable of preventing air or moisture from penetrating. For example, the first buffer layer BF1 may include a plurality of inorganic layers alternately stacked.

[0142] The lower metal layer BML may be disposed on the first buffer layer BF1. For example, the lower metal layer BML may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0143] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer BML, and may include an inorganic layer capable of preventing air or moisture from penetrating. For example, the second buffer layer BF2 may include a plurality of inorganic layers alternately stacked.

[0144] In an embodiment, a thin film transistor TFT may be disposed on the second buffer layer BF2 and may constitute a pixel circuit of each of the plurality of pixels. For example, the thin film transistor TFT may be a switching transistor or a driving transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0145] The semiconductor layer ACT may be disposed on the second buffer layer BF2 and may overlap the lower metal layer BML and the gate electrode GE in the thickness direction and may be insulated from the gate electrode GE by the gate insulating layer GI. In a portion of the semiconductor layer ACT, the material of the semiconductor layer ACT may be made into a conductor to form the source electrode SE and the drain electrode DE.

[0146] The gate electrode GE may be disposed on the gate insulating layer GI and may overlap with the semiconductor layer ACT with the gate insulating layer GI interposed therebetween.

[0147] The gate insulating layer GI may be disposed on the semiconductor layer ACT and may cover the semiconductor layer ACT and the second buffer layer BF2 to insulate the gate electrode GE from the semiconductor layer ACT. The gate insulating layer GI may include a contact hole through which the first connection electrode CNE1 passes.

[0148] In an embodiment, the first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI and may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0149] In an embodiment, the capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1 and may overlap the gate electrode GE in a thickness direction. The capacitor electrode CPE and the gate electrode GE may form a capacitor.

[0150] In an embodiment, the second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1 and may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer ILD2 may be connected to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0151] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2 and may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into a contact hole provided in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0152] In an embodiment, the first protection layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2 and may protect the thin film transistor TFT. The first protection layer PAS1 may include a contact hole through which the second connection electrode CNE2 passes.

[0153] The second connection electrode CNE2 may be disposed on the first protection layer PAS1 and may electrically connect the first connection electrode CNE1 to the pixel electrode AE of the light emitting element ED. The second connection electrode CNE2 may be inserted into a contact hole formed in the first protection layer PAS1 to contact the first connection electrode CNE1.

[0154] In an embodiment, the second protection layer PAS2 may cover the second connection electrode CNE2 and the first protection layer PAS1 , and may include a contact hole through which the pixel electrode AE of the light emitting element ED passes.

[0155] In an embodiment, the light emitting element layer EML may be disposed on the thin film transistor layer TFTL and may include a light emitting element ED and a pixel defining layer PDL. The light emitting element ED may include pixel electrodes AE1, AE2, and AE3, a light emitting layer EL, and a common electrode CE.

[0156] Pixel electrodes AE1, AE2, and AE3 may be disposed on the second protective layer PAS2. Each of the different pixel electrodes AE1, AE2, and AE3 may be disposed to overlap a corresponding one of the different openings of the pixel defining layer PDL. The pixel electrodes AE1, AE2, and AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT via a first connection electrode CNE1 and a second connection electrode CNE2.

[0157] In embodiments, the light-emitting layer EL may be disposed on the pixel electrodes AE1, AE2, and AE3. For example, the light-emitting layer EL may be an organic light-emitting layer made of an organic material, but is not limited thereto. When an organic light-emitting layer is used as the light-emitting layer EL, the thin film transistor TFT applies a predetermined voltage to the pixel electrodes AE1, AE2, and AE3 of the light-emitting element ED. When the common electrode CE of the light-emitting element ED receives a common voltage or a cathode voltage, holes and electrons may move to the light-emitting layer EL through the hole transport layer and the electron transport layer and recombine to generate light to be emitted by the light-emitting layer EL.

[0158] In an embodiment, the light-emitting layers EL disposed on different pixel electrodes AE1, AE2, and AE3 may emit light of different colors. For example, the light-emitting layer EL disposed on the first pixel electrode AE1 may emit red light of a first color, the light-emitting layer EL disposed on the second pixel electrode AE2 may emit green light of a second color, and the light-emitting layer EL disposed on the third pixel electrode AE3 may emit blue light of a third color. However, the present invention is not limited thereto. In another embodiment, the light-emitting layer EL may be disposed as a single common layer on the different pixel electrodes AE1, AE2, and AE3 and the pixel defining layer PDL, and the light-emitting layers EL disposed on the different pixel electrodes AE1, AE2, and AE3 may emit light of the same color. In this case, the display device 10 may further include a color adjustment layer disposed on the light-emitting element ED.

[0159] In an embodiment, a common electrode CE may be disposed on the light-emitting layer EL. For example, the common electrode CE may be formed as an electrode common to all pixels, rather than as an electrode specific to each pixel. The common electrode CE may be provided on the light-emitting layer EL in the emission region corresponding to the pixel electrodes AE1, AE2, and AE3, and may be provided on the pixel-defining layer PDL in regions other than the emission region corresponding to the pixel electrodes AE1, AE2, and AE3.

[0160] When the pixel electrodes AE receive a voltage corresponding to the data voltage and the common electrode CE receives a low potential voltage, a potential difference is formed between the pixel electrodes AE1, AE2, and AE3 and the common electrode CE, so that the light emitting layer EL can emit light.

[0161] In an embodiment, the pixel defining layer PDL may include a plurality of openings and may be provided on a portion of the pixel electrodes AE1, AE2, and AE3 and the second protective layer PAS2. Each opening of the pixel defining layer PDL may partially expose the pixel electrodes AE1, AE2, and AE3. As described above, the corresponding openings of the pixel defining layer PDL may define the first emission area to the third emission area, and the areas or sizes of the first emission area to the third emission area may be different from each other. The pixel defining layer PDL may separate and insulate the pixel electrodes AE1, AE2, and AE3 of each of the plurality of light-emitting elements ED. The pixel defining layer PDL may include a light absorbing material to prevent light reflection. For example, the pixel defining layer PDL may include a polyimide (PI)-based adhesive and a mixture of red, green, and blue pigments. In another embodiment, the pixel defining layer PDL may include a cardo-based adhesive resin and a mixture of a lactam black pigment and a blue pigment. In yet another embodiment, the pixel defining layer PDL may include carbon black.

[0162] In an embodiment, an encapsulation layer TFEL may be provided on the common electrode CE to cover the plurality of light-emitting elements ED. The encapsulation layer TFEL may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the light-emitting element layer EML. The encapsulation layer TFEL may include at least one organic layer to protect the light-emitting element layer EML from foreign matter such as dust.

[0163] In an embodiment, the encapsulation layer TFEL may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3. The first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be inorganic encapsulation layers, and the second encapsulation layer TFE2 disposed between the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be an organic encapsulation layer.

[0164] Each of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may include one or more inorganic insulating materials, such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0165] The second encapsulation layer TFE2 may include a polymer material. Examples of polymer materials include acrylic resin, epoxy resin, polyimide, and polyethylene. For example, the second encapsulation layer TFE2 may include an acrylic resin, such as polymethyl methacrylate or polyacrylic acid. The second encapsulation layer TFE2 may be formed by curing a monomer or applying a polymer.

[0166] In an embodiment, the touch sensing layer TSU may be disposed on the encapsulation layer TFEL, and may include a first touch insulating layer SIL1, a second touch insulating layer SIL2, a touch electrode TL, and a third touch insulating layer SIL3.

[0167] The first touch insulating layer SIL1 may be disposed on the encapsulation layer TFEL. The first touch insulating layer SIL1 may have an insulating function and an optical function. The first touch insulating layer SIL1 may include at least one inorganic layer. In another embodiment, the first touch insulating layer SIL1 may be omitted.

[0168] The second touch insulating layer SIL2 may cover the first touch insulating layer SIL1. Although not shown in the drawings, another layer of touch electrodes TL may be further provided on the first touch insulating layer SIL1, and the second touch insulating layer SIL2 may cover the touch electrodes TL. The second touch insulating layer SIL2 may have both insulating and optical functions. For example, the second touch insulating layer SIL2 may be an inorganic layer including at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0169] A portion of the touch electrode TL may be disposed on the second touch insulating layer SIL2. The touch electrode TL may not overlap with the pixel electrodes AE1, AE2, and AE3. The touch electrode TL may be formed of a single layer including molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO), or may be formed to have a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an Ag-Pd-Cu (APC) alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO).

[0170] The touch electrode TL of the touch sensing layer TSU can have a constant line width and can be arranged to overlap with the first light blocking layer BM1, which will be described later. The first light blocking layer BM1 can have a width sufficient to completely cover the touch electrode TL and can define a gap between the edge of the first light blocking layer BM1 and the touch electrode TL. In an embodiment, the line width of the touch electrode TL can be in a range of approximately 4 μm to approximately 6 μm, and the gap between the touch electrode TL and the edge of the first light blocking layer BM1 can be in a range of approximately 5 μm to approximately 7 μm. The touch electrode TL can be arranged so that its center is substantially aligned with the center of the first light blocking layer BM1, and the gap from both sides of the touch electrode TL to the edge of the first light blocking layer BM1 can be substantially constant.

[0171] The third touch insulating layer SIL3 may cover the touch electrode TL and the second touch insulating layer SIL2. The third touch insulating layer SIL3 may have an insulating function and an optical function. The third touch insulating layer SIL3 may be made of the materials exemplified in association with the second touch insulating layer SIL2.

[0172] In embodiments, a first light-blocking layer BM1 may be disposed on the third touch insulating layer SIL3 of the touch sensing layer TSU. The first light-blocking layer BM1 may include a plurality of apertures OPT1, OPT2, OPT3, OPT4, OPT5, and OPT6 that overlap with the pixel electrodes AE1, AE2, and AE3, and may be disposed to cover the conductive lines of the touch electrodes TL. For example, the first aperture OPT1 may be disposed to overlap with the first pixel electrode AE1 of the first pixel PX1. The second aperture OPT2 may be disposed to overlap with the second pixel electrode AE2 of the first pixel PX1, and the third aperture OPT3 may be disposed to overlap with the third pixel electrode AE3 of the first pixel PX1. The fourth aperture OPT4 may be disposed to overlap with the first pixel electrode AE1 of the second pixel PX2. The fifth aperture OPT5 may be disposed to overlap with the second pixel electrode AE2 of the second pixel PX2, and the sixth aperture OPT6 may be disposed to overlap with the third pixel electrode AE3 of the second pixel PX2. The area or size of each of the holes OPT1, OPT2, OPT3, OPT4, OPT5, and OPT6 may be larger than the area or size of the corresponding one of the pixel electrodes AE1, AE2, and AE3. In addition, the area or size of each of the holes OPT1, OPT2, and OPT3 may be formed to be larger than the area or size of the corresponding opening of the pixel defining layer PDL, and the light emitted from the light-emitting element ED may be visually recognized by the user not only from the front of the display device 10 but also from the side thereof. However, whether the first pixel PX1 and the second pixel PX2 emit light may vary depending on the emission mode of the display device 10, and the shape of the first light blocking layer BM1 may be designed so that light is not visually recognized at a specific viewing angle in the emission mode in which the side visibility is limited in the second pixel PX2.

[0173] Figure 11 is a diagram illustrating relative arrangement of a pixel electrode and a first light blocking layer provided in one pixel of a display device according to an embodiment. Figure 11 A planar arrangement of the first pixel electrode AE1 and the first hole OPT1 of the first pixel PX1 and the first pixel electrode AE1, the fourth hole OPT4 and the first partition DBP1 of the second pixel PX2 is shown.

[0174] In the Examples and with further reference Figure 11 , also refer to Figures 1 to 10In the display device 10, the sizes of the apertures OPT1, OPT2, and OPT3 provided in the first pixel PX1 may be larger than the sizes of the apertures OPT4, OPT5, and OPT6 provided in the second pixel PX2. For example, the radius RT1 or size of the first aperture OPT1 overlapping with the first pixel electrode AE1 of the first pixel PX1 may be larger than the radius RT2 or size of the fourth aperture OPT4 overlapping with the first pixel electrode AE1 of the second pixel PX2.

[0175] Although not in Figure 11 , but in an embodiment and as described above, the radius or size of the second hole OPT2 in the first pixel PX1 may be greater than the radius or size of the fifth hole OPT5 in the second pixel PX2. The radius or size of the third hole OPT3 in the first pixel PX1 may be greater than the radius or size of the sixth hole OPT6 in the second pixel PX2.

[0176] In the second emission mode of the display device 10, the first-type pixels may not emit light, and only the second-type pixels may emit light. When the second-type pixels emit light, the size of the apertures OPT4, OPT5, and OPT6 of the first light-blocking layer BM1 in the second pixel PX2 may be relatively small to block light from being emitted at a specific viewing angle. In addition, since the second light-blocking layer BM2 is provided in the second-type pixels, the second emission mode of the display device 10 can control the side visibility of light emitted from the second-type pixels.

[0177] In the first emission mode, both the first pixel PX1 and the second pixel PX2 emit light and can be visually recognized from the front and side. Accordingly, in the first pixel PX1, to ensure visibility from the side, the diameters of the pixel electrodes AE1, AE2, and AE3, as well as the diameters of the apertures OPT1, OPT2, and OPT3, can be greater than or equal to a certain level. On the other hand, in the second emission mode, only the second pixel PX2 can emit light, while the first pixel PX1 may not emit light, and side visibility may be limited. In the second emission mode, the light of the second pixel PX2 may not be visually recognized at side viewing angles other than near-front viewing angles. The diameters of the apertures OPT4, OPT5, and OPT6 provided in the second pixel PX2 may be almost identical to the diameters of the pixel electrodes AE1, AE2, and AE3, and visibility may be limited even at small side viewing angles. In addition, a second light-blocking layer BM2, described later, may be provided in the second pixel PX2 to further limit side visibility.

[0178] In an embodiment, in the display device 10, the same type of pixel electrodes AE1, AE2, and AE3 provided in each of the first pixel PX1 and the second pixel PX2 (for example, the first pixel electrode AE1 of the first pixel PX1 and the first pixel electrode AE1 of the second pixel PX2) may have the same diameter, and the first hole OPT1 provided in the first pixel PX1 may have a larger diameter than the fourth hole OPT4 provided in the second pixel PX2. In an embodiment, the diameter difference between the pixel electrodes AE1, AE2, and AE3 of the second pixel PX2 and the holes OPT4, OPT5, and OPT6 may be adjusted according to the patterning process performance of the first light blocking layer BM1, and in addition to the patterning process performance, the diameter difference between the pixel electrodes AE1, AE2, and AE3 of the first pixel PX1 and the holes OPT1, OPT2, and OPT3 may also be adjusted according to the optical distance from the pixel electrodes AE1, AE2, and AE3.

[0179] In an embodiment, the diameter difference between the pixel electrodes AE1, AE2, and AE3 of the second pixel PX2 and the holes OPT4, OPT5, and OPT6 may be about 1.0 μm to about 1.5 μm, or about 1.2 μm, and the diameter difference between the pixel electrodes AE1, AE2, and AE3 of the first pixel PX1 and the holes OPT1, OPT2, and OPT3 may be about 4.5 μm to about 6.5 μm, or about 5 μm. The diameter difference between the pixel electrodes AE1, AE2, and AE3 of the first pixel PX1 and the holes OPT1, OPT2, and OPT3 may be greater than the diameter difference between the pixel electrodes AE1, AE2, and AE3 of the second pixel PX2 and the holes OPT4, OPT5, and OPT6. In another embodiment, the diameter difference DB1 between the holes OPT1, OPT2, and OPT3 of the first pixel PX1 and the opening of the pixel defining layer PDL may be greater than the diameter difference DB2 between the holes OPT4, OPT5, and OPT6 of the second pixel PX2 and the opening of the pixel defining layer PDL. The diameter difference between the holes OPT1, OPT2, and OPT3 of the first pixel PX1 and the holes OPT4, OPT5, and OPT6 of the second pixel PX2 may be a value designed in consideration of the above-mentioned optical distance (e.g., the distance between the pixel electrodes AE1, AE2, and AE3 and the top surface of the second encapsulation layer TFE2). However, the present invention is not limited thereto, and the diameter difference between the hole provided in the first pixel PX1 and the hole provided in the second pixel PX2 may be designed and modified in various ways according to the optical characteristic conditions required by the electronic device 1 or the optical characteristic conditions that may be required by the electronic device 1.

[0180] In an embodiment, the display device 10 may include partitions DBP1, DBP2, and DBP3 disposed around the holes OPT4, OPT5, and OPT6 in the second pixel PX2. The first partition DBP1 may be disposed to surround the fourth hole OPT4. The first light blocking layer BM1 may include a pattern portion located between the fourth hole OPT4 and the first partition DBP1. Although not shown in FIG. Figure 11 , but as described above, the first light blocking layer BM1 may include the second dividing portion DBP2 disposed to surround the fifth hole OPT5 and the third dividing portion DBP3 disposed to surround the sixth hole OPT6.

[0181] Because the plurality of partitions DBP1, DBP2, and DBP3 are provided in the second pixel PX2, the diameters of the apertures OPT4, OPT5, and OPT6 of the second pixel PX2 can be smaller than the diameters of the apertures OPT1, OPT2, and OPT3 of the first pixel PX1, and the gaps between adjacent apertures OPT4, OPT5, and OPT6 can be slightly reduced. For example, if the partitions DBP1, DBP2, and DBP3 were not provided, the distances between adjacent apertures OPT4, OPT5, and OPT6 of the second pixel PX2 could be greater than the distances between adjacent apertures OPT1, OPT2, and OPT3 of the first pixel PX1, and the thickness difference between the color filters CF1, CF2, and CF3 provided on the adjacent apertures OPT4, OPT5, and OPT6 of the second pixel PX2 could be large. However, in the display device 10, the thicknesses of the color filters CF1, CF2, and CF3 provided in the second pixel PX2 can be reduced by the partitions DBP1, DBP2, and DBP3 provided in the second pixel PX2. Therefore, a thickness difference between the color filters CF1 , CF2 , and CF3 disposed in the first pixel PX1 and the color filters CF1 , CF2 , and CF3 disposed in the second pixel PX2 may be reduced, and a transmittance difference between different pixels PX1 and PX2 may also be reduced.

[0182] In an embodiment, the first light-blocking layer BM1 may include a light-absorbing material. For example, the first light-blocking layer BM1 may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but they are not limited thereto. The first light-blocking layer BM1 may prevent visible light penetration and color mixing between the holes OPT1, OPT2, and OPT3, thereby improving the color reproducibility of the display device 10. In an embodiment, the first light-blocking layer BM1 may have a thickness of approximately 1 μm to approximately 3 μm (or approximately 1.5 μm).

[0183] In embodiments, color filters CF1, CF2, and CF3 of the color filter layer CFL may be disposed on the first light-blocking layer BM1. Different color filters CF1, CF2, and CF3 may be disposed to correspond to different pixel electrodes AE1, AE2, and AE3 and apertures OPT1, OPT2, and OPT3 of the first light-blocking layer BM1, respectively. For example, the first color filter CF1 may be disposed to correspond to the first pixel electrode AE1, the second color filter CF2 may be disposed to correspond to the second pixel electrode AE2, and the third color filter CF3 may be disposed to correspond to the third pixel electrode AE3. In the first pixel PX1, the first color filter CF1 may be disposed in the first aperture OPT1 of the first light-blocking layer BM1, the second color filter CF2 may be disposed in the second aperture OPT2 of the first light-blocking layer BM1, and the third color filter CF3 may be disposed in the third aperture OPT3 of the first light-blocking layer BM1. In the second pixel PX2, the first color filter CF1 may be disposed in the fourth hole OPT4 of the first light blocking layer BM1, the second color filter CF2 may be disposed in the fifth hole OPT5 of the first light blocking layer BM1, and the third color filter CF3 may be disposed in the sixth hole OPT6 of the first light blocking layer BM1. Each of the color filters CF1, CF2, and CF3 may be disposed to have a larger area than the corresponding hole OPT1, OPT2, OPT3 of the first light blocking layer BM1 in a plan view, and a portion of the color filters CF1, CF2, and CF3 may be disposed directly on the first light blocking layer BM1.

[0184] In an embodiment, the areas of the plurality of color filters CF1, CF2, and CF3 may vary depending on the sizes of the holes OPT1, OPT2, OPT3, OPT4, OPT5, and OPT6 of the first light blocking layer BM1. For example, the first color filter CF1 may have a larger area than the second color filter CF2 in a plan view, but may have a smaller area than the third color filter CF3 in a plan view. On the other hand, in an embodiment, the first color filter CF1 disposed in the first pixel PX1 may have the same area as the first color filter CF1 disposed in the second pixel PX2 in a plan view. However, the present invention is not limited thereto. In an embodiment, the first color filter CF1 disposed in the first pixel PX1 may have a larger area than the first color filter CF1 disposed in the second pixel PX2 in a plan view.

[0185] According to an embodiment, the thickness of the color filters CF1, CF2, and CF3 disposed in the first pixel PX1 may be different from the thickness of the color filters CF1, CF2, and CF3 disposed in the second pixel PX2. The diameters of the apertures OPT1, OPT2, and OPT3 of the first pixel PX1 may be larger than the diameters of the apertures OPT4, OPT5, and OPT6 of the second pixel PX2, and the color filters CF1, CF2, and CF3 covering the apertures may have different thicknesses in the first pixel PX1 and the second pixel PX2. For example, in an embodiment, the thickness TH1 of the first color filter CF1 covering the first aperture OPT1 of the first pixel PX1 may be less than the thickness TH2 of the first color filter CF1 covering the fourth aperture OPT4 of the second pixel PX2. However, the first color filter CF1 of the second pixel PX2 may be disposed to cover both the fourth aperture OPT4 and the first partition DBP1, and the thickness difference (TH2-TH1) between the first color filter CF1 of the second pixel PX2 and the first color filter CF1 of the first pixel PX1 may be reduced.

[0186] Although not shown in the drawings, the thickness of the second color filter CF2 covering the second hole OPT2 of the first pixel PX1 may be thinner than the thickness of the second color filter CF2 covering the fifth hole OPT5 of the second pixel PX2. The thickness of the third color filter CF3 covering the third hole OPT3 of the first pixel PX1 may be thinner than the thickness of the third color filter CF3 covering the sixth hole OPT6 of the second pixel PX2. However, the second color filter CF2 and the third color filter CF3 of the second pixel PX2 may be arranged to cover all of the fifth hole OPT5 and the second partition DBP2, and the sixth hole OPT6 and the third partition DBP3, respectively, and the difference in thickness between the second color filter CF2 and the third color filter CF3 of the second pixel PX2 and the color filters CF2 and CF3 of the first pixel PX1 may be reduced.

[0187] In the embodiment, due to the thickness difference of the color filters CF1, CF2, and CF3, the transmittance of light emitted from the first pixel PX1 and the transmittance of light emitted from the second pixel PX2 may be different, but the transmittance difference and thickness difference of the color filters CF1, CF2, and CF3 can be reduced by the partitions DBP1, DBP2, and DBP3. Therefore, the brightness difference between the first pixel PX1 and the second pixel PX2 in the first emission mode can be reduced.

[0188] In an embodiment, passivation layers PSV1 and PSV2 may be disposed on the first light-blocking layer BM1 and the color filter layer CFL. The passivation layers PSV1 and PSV2 may be disposed throughout the entire display area DA to flatten the top surface of the display panel 100. The passivation layers PSV1 and PSV2 may include a first passivation layer PSV1 disposed on the color filter layer CFL and the first light-blocking layer BM1, and a second passivation layer PSV2 disposed on the first passivation layer PSV1. The passivation layers PSV1 and PSV2 may be formed of a plurality of layers and flatten a stepped portion caused by the color filter layer CFL and the first light-blocking layer BM1.

[0189] However, the present invention is not limited thereto. In an embodiment, the first passivation layer PSV1 may be patterned to partially expose the holes OPT4, OPT5, and OPT6 in the second pixel PX2. In this case, light emission efficiency may be improved by adjusting the refractive index using the second passivation layer PSV2.

[0190] The passivation layers PSV1 and PSV2 may be colorless light-transmitting layers having no color in the visible light band. For example, the passivation layers PSV1 and PSV2 may include a colorless light-transmitting organic material such as acrylic resin.

[0191] In an embodiment, a second light-blocking layer BM2 may be disposed on the passivation layers PSV1 and PSV2. The second light-blocking layer BM2 may not be disposed in the first-type pixel (or first pixel PX1), but may be disposed only in the second-type pixel (or second pixel PX2). The second light-blocking layer BM2 may be disposed to correspond to the periphery of the pixel electrodes AE1, AE2, and AE3 of the second-type pixel, and may form transmissive portions OPB1, OPB2, and OPB3 that overlap the pixel electrodes AE1, AE2, and AE3. For example, in an embodiment, the second light-blocking layer BM2 may include a first transmissive portion OPB1 that overlaps the first pixel electrode AE1, a second transmissive portion OPB2 that overlaps the second pixel electrode AE2, and a third transmissive portion OPB3 that overlaps the third pixel electrode AE3. The diameter of the first transmissive portion OPB1 is greater than the diameter of the second transmissive portion OPB2. The transmission portions OPB1 , OPB2 , and OPB3 may overlap with the holes OPT4 , OPT5 , and OPT6 of the first light blocking layer BM1 , respectively.

[0192] In an embodiment, the diameter or area of the transmissive portions OPB1, OPB2, and OPB3 of the second light-blocking layer BM2 in a plan view may be larger than the diameter or area of the holes OPT4, OPT5, and OPT6 of the first light-blocking layer BM1 and the pixel electrodes AE1, AE2, and AE3 in a plan view. Light emitted from the light-emitting element ED including the pixel electrodes AE1, AE2, and AE3 may be emitted through the holes OPT4, OPT5, and OPT6 of the first light-blocking layer BM1 and the transmissive portions OPB1, OPB2, and OPB3 of the second light-blocking layer BM2. Light emitted from the second-type pixels is ultimately emitted after passing through the transmissive portions OPB1, OPB2, and OPB3, and much light may be visually recognized at least when the display device 10 is viewed from the front.

[0193] However, when the display device 10 is viewed from the side, even if light emitted from the second-type pixel passes through the holes OPT4, OPT5, and OPT6 of the first light-blocking layer BM1, the light can be blocked by the second light-blocking layer BM2. In other words, the display device 10 can allow only the second pixel PX2 or the second-type pixel in which the second light-blocking layer BM2 is provided to emit light in the second emission mode, thereby controlling visibility at a specific viewing angle and providing a privacy protection mode for the user.

[0194] In an embodiment, the second light-blocking layer BM2 may include a light-absorbing material. For example, the second light-blocking layer BM2 may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but they are not limited thereto. In an embodiment, the second light-blocking layer BM2 may have a thickness of approximately 1 μm to approximately 3 μm (or approximately 1.5 μm).

[0195] In an embodiment, an overcoat layer OC may be disposed on the second light blocking layer BM2 and the passivation layers PSV1 and PSV2. The overcoat layer OC may be disposed throughout the entire display area DA to flatten the top surface of the display panel 100. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. For example, the overcoat layer OC may include a colorless light-transmitting organic material such as an acrylic resin.

[0196] Hereinafter, the display device 10 will be described with reference to other drawings (see Figure 3 ) various embodiments.

[0197] Figure 12 is a diagram illustrating a cross section of a second pixel of a display device according to another embodiment.

[0198] In the examples and with reference to Figure 12 , also refer to Figure 3 and Figure 4In the display device 10, the color filters CF1, CF2, and CF3 provided in the same type of pixels PX1 and PX2 may have different thicknesses. For example, the first color filter CF1, the second color filter CF2, and the third color filter CF3 provided in the second pixel PX2 may have different thicknesses. For example, the thickness of the second color filter CF2 may be greater than the thicknesses of the first color filter CF1 and the third color filter CF3, and the thickness of the third color filter CF3 may be greater than the thickness of the first color filter CF1.

[0199] Although not shown in the drawings, the color filters CF1, CF2, and CF3 of the first pixel PX1 may have the same thickness or different thicknesses. When the color filters CF1, CF2, and CF3 of the first pixel PX1 have different thicknesses, the color filters CF1, CF2, and CF3 disposed in the second pixel PX2 may also have different thicknesses. On the other hand, when the color filters CF1, CF2, and CF3 of the first pixel PX1 have the same thickness, the extent to which the thickness of the color filters CF1, CF2, and CF3 is reduced by the diameter difference of the holes OPT4, OPT5, and OPT6 and the size of the partitions DBP1, DBP2, and DBP3 may vary depending on the materials forming the color filters CF1, CF2, and CF3. For example, even if the first and second color filters CF1 and CF2 of the first pixel PX1 have the same thickness, the first and second color filters CF1 and CF2 of the second pixel PX2 may have different thicknesses. Therefore, in each of the first pixel PX1 and the second pixel PX2 , a thickness difference between the first color filters CF1 may be different from a thickness difference between the second color filters CF2 .

[0200] The thickness variation rate may vary depending on the material forming the color filters CF1, CF2, and CF3. For example, the appropriate thickness of the first color filter CF1, where the transmittance is the highest, may be smaller than the appropriate thickness of the second color filter CF2, where the transmittance is the highest. Furthermore, the appropriate thickness of the third color filter CF3, where the transmittance is the highest, may be smaller than the appropriate thickness of the second color filter CF2, where the transmittance is the highest. Accordingly, the first and third color filters CF1 and CF3 may have thicknesses that are smaller than the thickness of the second color filter CF2. Considering the transmittance variation caused by the color filters CF1, CF2, and CF3 in the second pixel PX2, the thicknesses of the color filters CF1, CF2, and CF3 may be varied differently.

[0201] Figure 13 is a diagram illustrating a cross section of a first pixel and a second pixel of a display device according to another embodiment.

[0202] In the examples and with reference to Figure 13 , also refer to Figure 3 and Figure 12In the display device 10, the first passivation layer PSV1 may be patterned in the second pixel PX2. The first passivation layer PSV1 may be disposed in the first pixel PX1 to completely cover the first light blocking layer BM1 and the color filters CF1, CF2, and CF3, and may be partially patterned in the second pixel PX2. For example, the first passivation layer PSV1 may be patterned to partially expose the plurality of color filters CF1, CF2, and CF3, and may be disposed to partially overlap with the light blocking pattern of the first light blocking layer BM1.

[0203] In an embodiment, since the first passivation layer PSV1 is patterned in the second pixel PX2, the patterned first passivation layer PSV1 may form an inclined side surface on the color filters CF1, CF2, and CF3. The inclined side surface of the first passivation layer PSV1 may contact the second passivation layer PSV2 to form an interface, and light incident on the inclined side surface may be emitted in an upward direction. In an embodiment, the first passivation layer PSV1 may include a material having a refractive index lower than that of the second passivation layer PSV2, and light incident on the side surface of the first passivation layer PSV1 among the light emitted through the color filters CF1, CF2, and CF3 may be emitted in an upward direction.

[0204] Color filters CF1, CF2, and CF3 may be in contact with each of the first passivation layer PSV1 and the second passivation layer PSV2, and light emitted from the light-emitting element ED of the second pixel PX2 may pass through the color filters CF1, CF2, and CF3 and be incident on the first passivation layer PSV1 or the second passivation layer PSV2. Some of the light incident on the second passivation layer PSV2 may be refracted at the side surface of the first passivation layer PSV1 and emitted in an upward direction. Therefore, even if the transmittance is slightly lower due to the thickness of the color filters CF1, CF2, and CF3 disposed in the second pixel PX2 being greater than the thickness of the color filters CF1, CF2, and CF3 disposed in the first pixel PX1, the efficiency difference caused by the transmittance difference can be minimized by improving the light emission efficiency in the upward direction.

[0205] Figures 14 to 16 is a plan view illustrating the arrangement of a pixel electrode and a first light blocking layer in a display area of a display device according to another embodiment.

[0206] In the examples and with reference to Figure 14 , in the display device 10 (see Figure 3), the structure of the partitions DBP1, DBP2, and DBP3 provided in the second pixel PX2 may vary depending on the diameter difference of the holes OPT4, OPT5, and OPT6. In an embodiment, among the partitions DBP1, DBP2, and DBP3 of the first light blocking layer BM1, the second partition DBP2 may include a first sub-partition SDP1 and a second sub-partition SDP2. The first sub-partition SDP1 may surround the fifth hole OPT5, and the second sub-partition SDP2 may surround the first sub-partition SDP1. Unlike the first partition DBP1 and the third partition DBP3, the second partition DBP2 may have a multi-partition structure.

[0207] The second partition portion DBP2, which is formed as a partition portion corresponding to the fifth aperture OPT5 having a relatively small diameter, can have a smaller diameter than other adjacent partition portions (e.g., the first partition portion DBP1 and the third partition portion DBP3). Since the diameter of the fifth aperture OPT5 is small, there can be space around it for multiple partition portions to be arranged. The second partition portion DBP2 can have a multi-partition structure within a range that does not interfere with other adjacent partition portions, and can include multiple sub-partition portions SDP1 and SDP2 to further reduce the thickness of the color filters CF1, CF2, and CF3.

[0208] In the examples and with reference to Figure 15 and Figure 16 , also refer to Figure 3 and Figure 14 In the display device 10, the partition portion DBP may not necessarily have a shape surrounding the holes OPT4, OPT5, and OPT6. In an embodiment, the shape of the partition portion DBP may be variously modified as long as the partition portion DBP is disposed around the plurality of holes OPT4, OPT5, and OPT6 located in the second pixel PX2 to overlap with the color filters CF1, CF2, and CF3.

[0209] For example, in Figure 15 In the display device 10, the partition portion DBP may be provided only around the fifth hole OPT5 (or the second pixel electrode AE2 of the second pixel PX2). The partition portion DBP may be spaced apart from the fifth hole OPT5, have a predetermined width, and have a curved shape along a portion of the outer side of the fifth hole OPT5. The partition portion DBP may have an arched shape corresponding to a circular hole.

[0210] exist Figure 16In the display device 10, the partition portion DBP may be provided between the fourth hole OPT4 and the fifth hole OPT5 and between the sixth hole OPT6 and the fifth hole OPT5. The partition portion DBP may have a curved shape along the outer sides of the plurality of holes OPT4, OPT5, and OPT6, and may be provided so that the light blocking portion of the first light blocking layer BM1 located between the fourth hole OPT4 and the sixth hole OPT6 is discontinuous.

[0211] Figure 17 and Figure 18 is a cross-sectional view of a display device according to another embodiment. Figure 17 shows a cross section of a first pixel PX1, and Figure 18 A cross section of the second pixel PX2 is shown.

[0212] In the examples and with reference to Figure 17 and Figure 18 , also refer to Figure 3 and Figure 14 In the display device 10, the color filters CF1, CF2, and CF3 may be arranged to partially overlap. A plurality of color filters CF1, CF2, and CF3 may overlap different color filters disposed adjacent to each other on the first light blocking layer BM1. For example, the second color filter CF2 may overlap each of the first color filter CF1 and the third color filter CF3 disposed adjacent to each other on the first light blocking layer BM1. Although not shown in the drawings, the first color filter CF1 may overlap the third color filter CF3 on the first light blocking layer BM1, and in various embodiments, all of the first color filters CF1, the second color filters CF2, and the third color filters CF3 may overlap.

[0213] Furthermore, in the second pixel PX2, a plurality of color filters CF1, CF2, and CF3 may overlap with one another. The color filters CF1, CF2, and CF3 may be arranged to cover different apertures OPT4, OPT5, and OPT6, and the color filters CF1, CF2, and CF3 may also respectively cover partitions DBP1, DBP2, and DBP3 of the first light-blocking layer BM1. The color filters CF1, CF2, and CF3 of the second pixel PX2 overlap with one another on the first light-blocking layer BM1 and may therefore have a relatively thick thickness. However, the thickness is slightly reduced by the partitions, so that the difference in thickness between the color filters CF1, CF2, and CF3 of the second pixel PX2 and the color filters CF1, CF2, and CF3 of the first pixel PX1 can be reduced.

[0214] Figure 19 and Figure 20 is a cross-sectional view of a display device according to yet another embodiment. Figure 19 and Figure 20 Each shows a cross section of a second pixel PX2.

[0215] In the examples and with reference to Figure 19 , in the display device 10 (see Figure 3 ), in the first light blocking layer BM1, a partition may be formed at different holes (e.g., the fourth hole OPT4 and the fifth hole OPT5) of the second pixel PX2 to correspond to the different holes, but the partition may not be formed at the sixth hole OPT6. For example, the partition may not be formed at the sixth hole OPT6 of the second pixel PX2 that overlaps with the third pixel electrode AE3. Since the sixth hole OPT6 of the first light blocking layer BM1 has a diameter larger than the diameters of the fourth hole OPT4 and the fifth hole OPT5, even if the partition is not formed, the thickness of the third color filter CF3 may not be significantly different from the thicknesses of the other color filters CF1 and CF2. Accordingly, in the first light blocking layer BM1, the partition may be formed only at the fourth hole OPT4 and the fifth hole OPT5 of the second pixel PX2 to correspond to the fourth hole OPT4 and the fifth hole OPT5, and may not be formed at the sixth hole OPT6.

[0216] In the examples and with reference to Figure 20 , in the display device 10 (see Figure 3 ), the first passivation layer PSV1 may be partially patterned only on the sixth hole OPT6 of the second pixel PX2. In the display device 10, the first passivation layer PSV1 may form an inclined side surface only on the sixth hole OPT6.

[0217] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the present invention without departing substantially from the scope and principles of the present invention. Therefore, the disclosed embodiments of the present invention are used only in a general and descriptive sense, rather than for the purpose of limitation. Each component specifically shown in the embodiments of the present invention may be implemented by modification, and such application-related modifications and differences should be interpreted as being included within the scope of the present invention. In addition, the parts of the embodiments or embodiments may be combined in whole or in part without departing from the scope of the present invention.

Claims

1. A display device, wherein: The display device includes: a display area in which a plurality of first pixels and a plurality of second pixels including a plurality of pixel electrodes spaced apart from each other are provided; a first light blocking layer disposed in the display area, the first light blocking layer including a plurality of holes disposed to overlap with the plurality of pixel electrodes; a plurality of color filters disposed on the first light blocking layer, and the plurality of color filters are disposed to correspond to the plurality of holes; and a second light blocking layer disposed on the plurality of color filters to correspond to the plurality of pixel electrodes of the plurality of second pixels, wherein the first light blocking layer further comprises a plurality of partitioning portions, the plurality of partitioning portions being disposed around the plurality of holes disposed in the plurality of second pixels among the plurality of holes and penetrating the first light blocking layer, and Among the plurality of color filters, the plurality of color filters disposed in the plurality of second pixels are disposed to cover the plurality of holes of the first light blocking layer and the plurality of partition portions disposed to correspond to the plurality of holes.

2. The display device according to claim 1, wherein The first light blocking layer comprises: a first hole overlapping a first pixel electrode of a first pixel among the plurality of first pixels; a second hole overlapping with a second pixel electrode of the first pixel among the plurality of first pixels; a third hole overlapping the first pixel electrode of a second pixel among the plurality of second pixels; and The fourth hole overlaps with the second pixel electrode of the second pixel among the plurality of second pixels, wherein a diameter of the first hole is greater than a diameter of the third hole.

3. The display device according to claim 2, wherein: A distance between the first hole and the second hole in the first pixel is smaller than a distance between the third hole and the fourth hole in the second pixel.

4. The display device according to claim 2, wherein: The plurality of partitions include a first partition surrounding the third hole and a second partition surrounding the fourth hole, and The diameter of the region surrounded by the first partition is larger than the diameter of the region surrounded by the second partition.

5. The display device according to claim 4, wherein The second dividing portion includes a first sub-dividing portion surrounding the fourth hole and a second sub-dividing portion surrounding the first sub-dividing portion. The display device according to claim 1 , wherein: The plurality of partitions are spaced apart from outer sides of the plurality of holes in the plurality of second pixels, and have a curved shape along the outer sides.

7. The display device according to claim 1, wherein: The plurality of partitions are disposed between the plurality of holes in the plurality of second pixels.

8. The display device according to claim 1, wherein A pixel of the plurality of first pixels and the plurality of second pixels includes a first pixel electrode and a second pixel electrode, the second pixel electrode having a diameter smaller than a diameter of the first pixel electrode, and Wherein, the second light blocking layer comprises: a first light-blocking pattern surrounding an outer side of the first pixel electrode of a second pixel among the plurality of second pixels, and forming a first transmissive portion overlapping the first pixel electrode of the second pixel among the plurality of second pixels; and A second light-blocking pattern surrounds an outer side of the second pixel electrode of the second pixel among the plurality of second pixels and forms a second transmissive portion overlapping the second pixel electrode of the second pixel among the plurality of second pixels.

9. The display device according to claim 8, wherein: A diameter of the first transmission portion is greater than a diameter of the second transmission portion.

10. The display device according to claim 8, wherein A spacing distance between the outer side of the first pixel electrode and the inner side of the first light-blocking pattern is different from a spacing distance between the outer side of the second pixel electrode and the inner side of the second light-blocking pattern.

11. A display device, wherein: The display device includes: a substrate on which first and second pixels including a plurality of pixel electrodes are provided; an encapsulation layer, disposed on the plurality of pixel electrodes; a first light blocking layer disposed on the encapsulation layer, wherein the first light blocking layer includes a plurality of holes, each of the plurality of holes being disposed to correspond to a corresponding one of the plurality of pixel electrodes; a plurality of color filters disposed on the first light blocking layer, and the plurality of color filters are disposed to correspond to the plurality of holes; a passivation layer disposed on the plurality of color filters and the first light blocking layer; a second light-blocking layer disposed on the passivation layer in the second pixel, the second light-blocking layer including a plurality of light-blocking patterns forming a plurality of transmission portions respectively overlapping the plurality of pixel electrodes of the second pixel; and an outer coating layer disposed on the second light blocking layer, wherein The plurality of pixel electrodes include a first pixel electrode and a second pixel electrode provided in each of the first pixel and the second pixel, the second pixel electrode having a diameter smaller than a diameter of the first pixel electrode, The first light blocking layer is provided around the plurality of holes provided in the second pixel among the plurality of holes, and the first light blocking layer includes a plurality of partition portions penetrating the first light blocking layer, and Among the plurality of color filters, the plurality of color filters provided in the second pixel are provided to cover the plurality of partition portions.

12. The display device according to claim 11, wherein The passivation layer includes a first passivation layer disposed on the first light blocking layer and the plurality of color filters; and a second passivation layer disposed on the first passivation layer.

13. The display device according to claim 12, wherein: The first passivation layer is disposed to cover a plurality of color filters disposed in the first pixel among the plurality of color filters and the first light blocking layer in the first pixel, and is patterned to partially expose the plurality of color filters in the second pixel.

14. The display device according to claim 12, wherein: The first passivation layer has a refractive index lower than a refractive index of the second passivation layer.

15. The display device according to claim 12, wherein: The first passivation layer contacts the second passivation layer disposed on the plurality of color filters in the second pixel and forms an inclined side surface.

16. The display device according to claim 11, wherein The first light blocking layer comprises: a first hole, overlapping with the first pixel electrode of the first pixel; a second hole, overlapping with the second pixel electrode of the first pixel; a third hole overlapping the first pixel electrode of the second pixel; and a fourth hole, overlapping with the second pixel electrode of the second pixel, wherein the diameter of the first hole is greater than the diameter of the third hole, and Among the plurality of color filters, a thickness of the color filter disposed on the first hole is smaller than a thickness of the color filter disposed on the third hole.

17. The display device according to claim 16, wherein: Among the plurality of color filters, a thickness of a color filter disposed on the second hole is smaller than a thickness of a color filter disposed on the fourth hole.

18. The display device according to claim 16, wherein: Among the plurality of color filters, a thickness difference between the color filter disposed on the first hole and the color filter disposed on the third hole is different from a thickness difference between the color filter disposed on the second hole and the color filter disposed on the fourth hole.

19. The display device according to claim 16, wherein: The plurality of color filters overlap one another on the first light blocking layer.

20. The display device according to claim 19, wherein On the first light blocking layer, a color filter disposed on the second hole among the plurality of color filters is disposed on the color filter disposed on the first hole.

Images