Piezoelectric device preparation process and piezoelectric device

Abstract

According to the piezoelectric device preparation process, a metal bottom electrode layer, a piezoelectric material layer and a metal top electrode layer are prepared on a substrate, then the metal bottom electrode layer, the piezoelectric material layer and the metal top electrode layer are etched, and piezoelectric patterning is achieved. And finally, in the process of releasing the piezoelectric device, firstly etching the bottom silicon layer of the substrate to form a back cavity to release internal stress, and then etching the top silicon layer of the substrate. According to the piezoelectric device preparation process provided by the embodiment of the invention, the bottom silicon layer is etched firstly, and then the top silicon layer is etched, so that stress can be released, the probability of cantilever beam fracture and device falling can be reduced, the stability of the device is guaranteed, and the yield is further improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor device technology, and in particular to a piezoelectric device preparation process and a piezoelectric device. Background Art

[0002] Microelectromechanical systems (MEMS) technology has been widely used in many fields, one of which is piezoelectrically driven MEMS device technology.

[0003] Electrostatic drive, electromagnetic drive, electrothermal drive and piezoelectric drive are the four main driving mechanisms of MEMS devices. Compared with electrostatic drive devices, piezoelectric drive devices can be driven at a lower voltage and there is no pull-in effect, which makes them widely used in portable devices and battery-powered systems. Electrothermal drive devices have high driving voltage, poor reliability and are easily affected by external factors. Compared with electromagnetic drive devices, piezoelectric drive devices do not require complex assembly processes, are simple to assemble and have low costs, which reduces the size of the entire system and is a smaller and more highly integrated MEMS device technology. The working principle of MEMS piezoelectric devices is to use the inverse piezoelectric effect to convert electrical signals into mechanical vibrations, that is, some materials (piezoelectric materials such as PZT and AlN) will deform when they are subjected to voltage.

[0004] Therefore, studying the preparation methods of piezoelectrically driven MEMS devices is an important part of device research that cannot be ignored.

[0005] MEMS devices use single-crystal silicon wafers / SOI as their substrate material. Their material performance advantages include: 1. Stable mechanical properties, coupled with mature, controllable, and low-cost MEMS processing technology; 2. Single-crystal silicon has a high Young's modulus but low density, enabling lightweight devices; 3. High melting point and low thermal expansion coefficient, adaptable to extreme operating conditions; and 4. Low mechanical hysteresis, leading to their widespread use in sensor device manufacturing. Silicon-based MEMS fabrication processes are similar to those used in the IC device industry, enabling photolithography and patterning on silicon substrate wafers, including thin film deposition, dry and wet etching, ion implantation and diffusion doping, and chemical mechanical polishing. MEMS processes primarily involve bulk and surface micromachining on silicon wafers / SOI to create characteristic structures, spawning a host of new MEMS processes, such as sacrificial layer technology, deep reactive ion etching, and LIGA technology to fabricate high-aspect-ratio structures, enabling the conversion of electrical and mechanical signals.

[0006] Typically, piezoelectric MEMS devices utilize a subtractive process, which involves first depositing various thin film layers, then sequentially removing unwanted thin film materials through various dry and wet etching methods, and finally etching the bottom silicon layer to release the piezoelectric MEMS device. However, due to the high internal stress generated during the deposition and etching processes, cantilever beams may break or the device may fall off when the device is released, resulting in low product yield. Therefore, using traditional subtractive processes will make it difficult to improve the manufacturing yield of piezoelectric MEMS devices, becoming a key obstacle to achieving product commercialization. Summary of the Invention

[0007] The present invention aims to solve at least one of the technical problems existing in the prior art or related art.

[0008] To this end, a first aspect of the present invention provides a process for preparing a piezoelectric device.

[0009] A second aspect of the present invention provides a piezoelectric device.

[0010] In view of this, according to a first aspect of an embodiment of the present application, a piezoelectric device manufacturing process is proposed, comprising:

[0011] Providing a substrate, and sequentially preparing a metal bottom electrode layer, a piezoelectric material layer, and a metal top electrode layer on the substrate;

[0012] Etching the metal bottom electrode layer, the piezoelectric material layer and the metal top electrode layer to achieve piezoelectric patterning;

[0013] The bottom silicon layer of the substrate is first etched to form a back cavity to release the internal stress, and then the top silicon layer of the substrate is etched to release the piezoelectric device.

[0014] In a feasible embodiment, the steps of providing a substrate and sequentially preparing a metal bottom electrode layer, a piezoelectric material layer, and a metal top electrode layer on the substrate include:

[0015] The metal bottom electrode layer and the metal top electrode layer are deposited by reactive magnetron sputtering, the target material includes at least one of Pt, Au, Cu, and Ti, and the thickness of the metal bottom electrode layer and the metal top electrode layer is 50 to 200 nm.

[0016] In a feasible embodiment, the steps of providing a substrate and sequentially preparing a metal bottom electrode layer, a piezoelectric material layer, and a metal top electrode layer on the substrate include:

[0017] The piezoelectric material layer is prepared by a sol-gel method and / or a magnetron sputtering method. The piezoelectric material is at least one of lead zirconate titanate, aluminum nitride, zinc oxide and LNO. The thickness of the prepared piezoelectric material layer is 1-5 μm.

[0018] In a feasible embodiment, before the step of first etching the bottom silicon layer of the substrate to form a back cavity to release internal stress, and then etching the top silicon layer of the substrate to release the piezoelectric device, the method further includes:

[0019] preparing an insulating protective layer and a metal lead layer on a piezoelectric device that realizes piezoelectric patterning;

[0020] Wherein, the insulating protective layer is grown by PCVD or PECVD, has a thickness of 300nm-500nm, and the material includes silicon nitride;

[0021] The metal lead layer is grown by magnetron sputtering deposition, has a thickness of 100 nm to 300 nm, and the material includes at least one of Al, Pt, Au, Ag and Cu.

[0022] In a feasible embodiment, the gas source for growing the insulating protection layer includes SiH4 and NH3, and the growth temperature is 200°C-400°C.

[0023] In a feasible embodiment, the step of etching the metal bottom electrode layer, the piezoelectric material layer, and the metal top electrode layer to achieve piezoelectric patterning includes:

[0024] Using an ion beam to etch the metal bottom electrode layer, the metal top electrode layer, and the metal lead layer, patterning the metal electrodes, and etching the useless metal bottom electrode layer, the metal top electrode layer, and the metal lead layer, so that the thickness of the metal bottom electrode layer and the metal top electrode layer is 50 to 100 nm;

[0025] Using wet etching or reactive ion etching to etch the piezoelectric material layer;

[0026] The insulating protection layer is etched by reactive ion etching or inductively coupled plasma etching to pattern the insulating protection layer.

[0027] In a feasible embodiment, the acidic solution used in the wet etching comprises a buffered hydrofluoric acid etching solution and a buffered etching solution;

[0028] Wherein, the buffered hydrofluoric acid etching solution and the buffered etching solution both comprise ammonium fluoride and hydrofluoric acid;

[0029] For PZT media, buffered hydrofluoric acid etching solutions and buffered etching solutions include: pre-etching solutions, main etching solutions, or buffered etching solutions formed by diluting ammonium fluoride and hydrofluoric acid with hydrochloric acid, nitric acid, and water;

[0030] For reactive ion etching of PZT media, the etching gas may be a mixture of sulfur hexafluoride and argon, a mixture of carbon tetrafluoride and argon, or a mixture of trifluoromethane and argon.

[0031] In a feasible embodiment, a first silicon oxide layer is formed on a side of the bottom silicon layer facing away from the top silicon layer;

[0032] A second silicon oxide layer is formed between the bottom silicon layer and the top silicon layer;

[0033] A third silicon oxide layer is formed between the top silicon layer and the metal bottom electrode layer;

[0034] The thickness of the top silicon layer is 5um to 50um, and the thickness of the bottom silicon layer is 100um-500um.

[0035] In a feasible embodiment, the step of first etching the bottom silicon layer of the substrate to form a back cavity to release internal stress, and then etching the top silicon layer of the substrate to release the piezoelectric device includes:

[0036] etching the first silicon oxide using reactive ion etching;

[0037] The bottom silicon layer is first etched by deep reactive ion etching to form a back cavity to release internal stress;

[0038] Reactive ion etching the third silicon oxide layer, then deep reactive ion etching the top silicon layer, and then reactive ion etching the second silicon oxide layer;

[0039] The etching source gas for reactive ion etching may be one or more of CHF3, SF6, and C2F6.

[0040] According to a second aspect of an embodiment of the present application, a piezoelectric device is provided, which is manufactured by the piezoelectric device manufacturing process described in any of the above technical solutions. The piezoelectric device includes:

[0041] substrate;

[0042] A metal bottom electrode, a piezoelectric material layer, a metal top electrode layer and a lead layer are provided on the substrate;

[0043] An insulating protective layer covers the metal bottom electrode, the piezoelectric material layer, and the metal top electrode layer.

[0044] Compared with the prior art, the present invention has at least the following beneficial effects:

[0045] The piezoelectric device preparation process provided in the embodiment of the present application first prepares a metal bottom electrode layer, a piezoelectric material layer and a metal top electrode layer on the substrate, and then etches the metal bottom electrode layer, the piezoelectric material layer and the metal top electrode layer to achieve piezoelectric patterning. Finally, in the process of releasing the piezoelectric device, the bottom silicon layer of the substrate is first etched to form a back cavity to release the internal stress, and then the top silicon layer of the substrate is etched. In the traditional technology, the top silicon of the device layer is first etched, and then the bottom silicon of the support layer is etched, and finally the MEMS device is released. This method will introduce residual stress in the final bottom silicon etching, thereby causing the patterned top silicon and piezoelectric layer to peel off, break, and bend, which is not conducive to the normal use of the piezoelectric MEMS device. The piezoelectric device preparation process provided in the embodiment of the present application first etches the bottom silicon layer and then etches the top silicon layer, which can release the stress, reduce the probability of cantilever beam breakage and device detachment, ensure the stability of the device, and thus improve the yield rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present application. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0047] Figure 1 A schematic flowchart of the steps of a piezoelectric device manufacturing process according to an embodiment of the present application;

[0048] Figure 2 A schematic structural diagram of a step in the process of manufacturing a piezoelectric device according to an embodiment of the present application;

[0049] Figure 3 A schematic structural diagram of another step in the process of manufacturing a piezoelectric device according to an embodiment of the present application;

[0050] Figure 4 A schematic structural diagram of a piezoelectric device according to an embodiment of the present application.

[0051] in, Figures 2 to 4 The corresponding relationship between the reference numerals and component names is as follows:

[0052] 110 substrate, 120 metal bottom electrode layer, 130 piezoelectric material layer, 140 metal top electrode layer, 150 insulating protection layer, 160 metal lead layer;

[0053] 111 bottom silicon layer, 112 top silicon layer, 113 first silicon oxide layer, 114 second silicon oxide layer, 115 third silicon oxide layer. DETAILED DESCRIPTION

[0054] In order to better understand the above technical solution, the technical solution of the embodiment of the present application is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiment of the present application and the specific features in the embodiment are detailed descriptions of the technical solution of the embodiment of the present application, rather than limitations on the technical solution of the present application. In the absence of conflict, the embodiment of the present application and the technical features in the embodiment can be combined with each other.

[0055] like Figure 1 As shown, according to a first aspect of an embodiment of the present application, a piezoelectric device manufacturing process is proposed, comprising:

[0056] Step 101: providing a substrate, and sequentially preparing a metal bottom electrode layer, a piezoelectric material layer, and a metal top electrode layer on the substrate;

[0057] Step 102: etching the metal bottom electrode layer, the piezoelectric material layer, and the metal top electrode layer to achieve piezoelectric patterning;

[0058] Step 103: first, etching the bottom silicon layer of the substrate to form a back cavity to release the internal stress, and then etching the top silicon layer of the substrate to release the piezoelectric device.

[0059] like Figures 2 to 4 As shown, the piezoelectric device preparation process provided in the embodiment of the present application first prepares a metal bottom electrode layer 120, a piezoelectric material layer 130 and a metal top electrode layer 140 on the substrate 110, and then etches the (metal top electrode layer, piezoelectric material layer, metal bottom electrode layer) to achieve piezoelectric patterning. Finally, in the process of releasing the piezoelectric device, the bottom silicon layer 111 of the substrate 110 is first etched to form a back cavity to release internal stress, and then the top silicon layer 112 of the substrate 110 is etched. In the traditional technology, the top silicon of the device layer is first etched, and then the bottom silicon of the support layer is etched, and finally the MEMS device is released. This method will introduce residual stress in the final bottom silicon etching, thereby causing the patterned top silicon and piezoelectric layer to peel off, break, and bend, which is not conducive to the normal use of the piezoelectric MEMS device. The piezoelectric device preparation process provided in the embodiment of the present application first etches the bottom silicon layer 111 and then etches the top silicon layer 112, which can release stress, reduce the probability of cantilever beam breakage and device detachment, ensure the stability of the device, and thus improve the yield rate.

[0060] like Figures 2 to 4 As shown, in a feasible embodiment, a substrate 110 is provided, and the steps of sequentially preparing a metal bottom electrode layer 120, a piezoelectric material layer 130 and a metal top electrode layer 140 on the substrate 110 include: depositing the metal bottom electrode layer 120 and the metal top electrode layer 140 by reactive magnetron sputtering, wherein the target material includes at least one of Pt, Au, Cu, and Ti, and the thickness of the metal bottom electrode layer 120 and the metal top electrode layer 140 is 50 to 200 nm.

[0061] This technical solution further provides a method for forming the metal bottom electrode layer 120 and the metal top electrode layer 140. Reactive magnetron sputtering is used to deposit the metal bottom electrode layer 120 and the metal top electrode layer 140. First, a high deposition rate is achieved: Compared with traditional physical evaporation, reactive magnetron sputtering has a higher deposition rate. This allows thicker films to be obtained in a shorter time, improving production efficiency. Second, low-temperature deposition is possible: Because the substrate temperature is low during reactive magnetron sputtering, deformation or thermal stress caused by high temperatures can be avoided. This has important application value for substrates that are sensitive to high temperatures, further ensuring the yield rate of piezoelectric devices. Third, excellent adhesion is achieved: Thin films deposited by reactive magnetron sputtering have excellent adhesion to the substrate and are not easily detached. This is due to the impact of high-energy particles on the substrate surface during the sputtering process, which strengthens the bonding between the film and the substrate, further improving the strength of the piezoelectric device. Fourth, precise control of film thickness is possible: By controlling parameters such as sputtering time and power, the thickness of the film deposited by reactive magnetron sputtering can be precisely controlled. This helps achieve high-precision thin film preparation, meet various application requirements, and improve the stability of piezoelectric devices.

[0062] In this technical solution, the target material and thickness of the metal bottom electrode layer 120 and the metal top electrode layer 140 are further provided. The target material includes at least one of Pt, Au, Cu, and Ti. The thickness of the metal bottom electrode layer 120 and the metal top electrode layer 140 is 50 to 200 nm. This configuration ensures the carrying current of the piezoelectric device. While being able to carry a larger current, it avoids excessive temperature. If the thickness of the metal bottom electrode layer 120 and the metal top electrode layer 140 is less than 50 nm, the current transmission may be limited due to overheating or excessive resistance. At the same time, by selecting a thickness range of 50 to 200 nm, firstly, mechanical stability is achieved: the thickness of the metal bottom electrode layer 120 and the metal top electrode will also affect their mechanical stability. A thicker metal bottom electrode layer 120 can provide better support and protection, preventing the electrode layer from being damaged by mechanical stress. A thinner metal bottom electrode layer 120 may deform or break due to mechanical stress. Secondly, electrical performance is guaranteed: the thickness of the metal bottom electrode layer 120 and the metal top electrode will also affect their electrical performance. A thicker metal bottom electrode layer 120 has lower resistance, which can improve the efficiency of the circuit. However, a thinner metal bottom electrode layer 120 may increase energy loss due to its higher resistance. Thirdly, thermal conductivity is guaranteed: the thickness of the metal bottom electrode layer 120 and the metal top electrode will also affect their thermal conductivity. A thicker metal bottom electrode layer 120 and the metal top electrode can better dissipate heat and prevent overheating. However, a thinner metal bottom electrode layer 120 and the metal top electrode may easily overheat due to their poor thermal conductivity.

[0063] like Figures 2 to 4 As shown, in a feasible embodiment, a substrate 110 is provided, and the steps of sequentially preparing a metal bottom electrode layer 120, a piezoelectric material layer 130 and a metal top electrode layer 140 on the substrate 110 include: using a sol-gel method and / or a magnetron sputtering method to prepare the piezoelectric material layer 130, the piezoelectric material is at least one of lead zirconate titanate, aluminum nitride, zinc oxide and LNO, and the thickness of the prepared piezoelectric material layer 130 is 1-5um.

[0064] In this technical solution, a preparation method of the piezoelectric material layer 130 is further provided, and the piezoelectric material layer 130 is prepared using a sol-gel method and / or a magnetron sputtering method. The sol-gel method has the advantages of low preparation temperature, high chemical uniformity, easy control of chemical measurement, ability to prepare nanomaterials, wide range of applications and environmental protection, and can ensure the stability of the piezoelectric material layer 130; and the magnetron sputtering method for preparing the piezoelectric material layer 130 has the advantages of high deposition rate, low temperature deposition, good adhesion, precise control of film thickness, wide range of applications, environmental friendliness, and ability to prepare large-area thin films, which can improve the precise control of the thickness of the piezoelectric material layer 130.

[0065] In this technical solution, the material and thickness of the piezoelectric material are provided at the same time, so that the output voltage, operating frequency, electromechanical conversion efficiency, impedance matching and reliability of the piezoelectric material layer 130 are guaranteed.

[0066] like Figures 2 to 4 As shown, in a feasible embodiment, before the step of first etching the bottom silicon layer 111 of the substrate 110 to form a back cavity to release internal stress, and then etching the top silicon layer 112 of the substrate 110 to release the piezoelectric device, the method further includes:

[0067] An insulating protective layer 150 and a metal lead layer 160 are prepared on a piezoelectric device that realizes piezoelectric patterning; wherein, the insulating protective layer 150 is grown by PCVD or PECVD, has a thickness of 300nm-500nm, and the material includes silicon nitride; wherein, the metal lead layer 160 is grown by magnetron sputtering deposition, has a thickness of 100nm-300nm, and the material includes at least one of Al, Pt, Au, Ag and Cu.

[0068] In this technical solution, before releasing the piezoelectric device, it is also necessary to prepare an insulating protective layer 150 and a metal lead layer 160. This arrangement facilitates the connection of the piezoelectric device and facilitates insulation control. The insulating layer is grown by PCVD or PECVD to facilitate the preparation of the insulating protective layer 150. The thickness of the insulating protective layer 150 is 300nm-500nm, and the material includes silicon nitride to ensure the insulation effect. The preparation process, thickness and material selection of the metal lead layer 160 facilitate the preparation of the metal lead layer 160.

[0069] like Figures 2 to 4 As shown, in a feasible embodiment, the gas source for growing the insulating protective layer 150 includes SiH4 and NH3, and the growth temperature is 200° C.-400° C. This configuration ensures that there is sufficient gas source during the growth of the insulating protective layer 150 and facilitates the growth of the insulating protective layer 150.

[0070] like Figures 2 to 4 As shown, in a feasible embodiment, the steps of forming a metal top electrode layer, a piezoelectric material layer, and a metal bottom electrode layer to realize piezoelectric patterning include:

[0071] The metal bottom electrode layer 120, the metal top electrode layer 140 and the metal lead layer 160 are etched by ion beam to pattern the metal electrodes, and the useless metal bottom electrode layer 120, the metal top electrode layer 140 and the metal lead layer 160 are etched to reduce the thickness of the metal bottom electrode layer 120 and the metal top electrode layer 140 to 50 to 100 nm;

[0072] The piezoelectric material layer 130 is etched by wet etching or reactive ion etching;

[0073] The insulating protection layer 150 is etched by reactive ion etching or inductively coupled plasma etching to pattern the insulating protection layer 150 .

[0074] This technical solution further provides a step for etching the metal bottom electrode layer 120, the piezoelectric material layer 130, and the metal top electrode layer 140 to achieve piezoelectric patterning. Ion beam etching of the metal bottom electrode layer 120, the metal top electrode layer 140, and the metal lead layer 160 enables high-precision processing of the metal bottom electrode layer 120, the metal top electrode layer 140, and the metal lead layer 160, with accurate control of the etching depth and etching shape. Furthermore, due to the short wavelength of the ion beam, high-resolution processing can be achieved, making it suitable for the manufacture of high-precision microstructures.

[0075] In this technical solution, wet etching is used to etch the piezoelectric material layer 130, which has the advantages of fast speed, uniform etching depth, effective suppression of dead angles, more uniform surface protection, higher roughness and glossiness of the etching surface, simple process conditions and wide range of applications, and can ensure precise control of the piezoelectric material layer 130.

[0076] In this technical solution, reactive ion etching is used to etch the piezoelectric material layer 130 , which has the advantages of high selectivity and high etching rate, excellent morphology control capability, compatibility with various substrates, flexible process parameter adjustment, high cleanliness, and mature and stable equipment, and can ensure precise control of the piezoelectric material layer 130 .

[0077] In this technical solution, reactive ion etching etches the insulating protective layer 150. Reactive ion etching has the advantages of high selectivity and high etching rate, excellent morphology control ability, compatibility with various substrates, flexible process parameter adjustment, mature and stable equipment, and environmental friendliness, which can ensure the etching accuracy of the insulating protective layer 150.

[0078] In this technical solution, inductively coupled plasma etches the insulating protective layer 150, which has the advantages of high etching rate and anisotropy, excellent morphology control ability, compatibility with various substrates, flexible process parameter adjustment, mature and stable equipment, and environmental friendliness, and can ensure the etching accuracy of the insulating protective layer 150.

[0079] like Figures 2 to 4 As shown, in a feasible embodiment, the acidic solution used in wet etching comprises a buffered hydrofluoric acid etching solution and a buffered etching solution; wherein the buffered hydrofluoric acid etching solution and the buffered etching solution both comprise ammonium fluoride and hydrofluoric acid; for PZT media, the buffered hydrofluoric acid etching solution and the buffered etching solution comprise: a pre-etching solution, a main etching solution, or a buffered etching solution formed by diluting ammonium fluoride and hydrofluoric acid with hydrochloric acid, nitric acid, and water; for reactive ion etching of PZT media, the etching gas can be selected from a mixture of sulfur hexafluoride and argon, a mixture of carbon tetrafluoride and argon, or a mixture of trifluoromethane and argon. Such an arrangement can improve etching efficiency.

[0080] In a feasible embodiment, a first silicon oxide layer 113 is formed on the side of the bottom silicon layer 111 facing away from the top silicon layer 112; a second silicon oxide layer 114 is formed between the bottom silicon layer 111 and the top silicon layer 112; and a third silicon oxide layer 115 is formed between the top silicon layer 112 and the metal bottom electrode layer 120; wherein the thickness of the top silicon layer 112 is 5um to 50um, and the thickness of the bottom silicon layer 111 is 100um-500um.

[0081] In this technical solution, the structural composition of the substrate 110 is further provided, and such a configuration facilitates the clear etching process.

[0082] like Figures 2 to 4 As shown, in a feasible embodiment, the steps of first etching the bottom silicon layer 111 of the substrate 110 to form a back cavity to release the internal stress, and then etching the top silicon layer 112 of the substrate 110 to release the piezoelectric device include:

[0083] etching the first silicon oxide 113 using reactive ion etching;

[0084] The bottom silicon layer 111 is first etched by deep reactive ion etching to form a back cavity and release internal stress;

[0085] Reactive ion etching is performed on the third silicon oxide layer 115, and then deep reactive ion etching is performed on the top silicon layer 112, and then reactive ion etching is performed on the second silicon oxide layer 114;

[0086] The etching source gas for reactive ion etching may be one or more of CHF3, SF6, and C2F6.

[0087] In this technical solution, a step of releasing the piezoelectric device is further provided. Silicon oxide is etched by reactive ion etching, which has the advantages of high selectivity, high precision, high consistency, high cleanliness, high reliability, repeatability and automated operation, and can ensure the etching accuracy of silicon oxide; the bottom silicon layer 111 and the top silicon layer 112 are first etched by deep reactive ion etching. Deep reactive ion etching has the advantages of high aspect ratio, high etching rate, anisotropic etching, wide application range, high precision and environmental protection, and can ensure the etching accuracy of deep reactive ion etching.

[0088] It can be understood that etching the bottom silicon layer 111 through the bottom and etching the top silicon layer 112 through the top fully considers the etching length, which can further ensure the etching accuracy.

[0089] In some examples, the piezoelectric device manufacturing process provided in the embodiments of the present application includes:

[0090] Step 1: Preparation of substrate 110 material. Figure 1 To complete the cross-sectional view with piezoelectric material and electrode layer after the first step, it includes substrate 110, piezoelectric material layer 130 and metal top electrode layer 140. A metal bottom electrode layer 120, a piezoelectric material and a metal top electrode layer 140 are sequentially deposited on SOI. The metal bottom electrode layer 120 and the metal top electrode layer 140 are deposited by reactive magnetron sputtering, and the target material can be Pt metal, or Au, Cu, Ti and other metals can be used as targets to prepare electrodes, and the film thickness of the electrode layer can be 50-200nm. Piezoelectric materials can be prepared using sol-gel method and magnetron sputtering method. The piezoelectric material can be lead zirconate titanate (PZT), aluminum nitride, zinc oxide, LNO, etc., and the prepared film thickness can be 1-5um. You can also use a directly purchased SOI wafer with a metal bottom electrode, piezoelectric material and a metal top electrode.

[0091] Step 2: Patterning of multiple piezoelectric drive layers. Figure 2This is a cross-sectional view after patterning the multi-piezoelectric drive layer in the second step. It includes an insulating protective layer 150 and a metal lead layer 160. The insulating protective layer 150 can be made of silicon nitride, silicon nitride, etc.; the metal lead layer 160 can be made of metals such as Al, Pt, Au, Ag, and Cu. LPCVD or PECVD can be used to grow the insulating protective layer 150, and the thickness of the grown insulating layer can be 300nm-500nm. The metal lead layer 160 can be deposited by magnetron sputtering, and the thickness of the grown metal lead layer 160 can be 100nm-300nm. For the metal bottom electrode layer 120 and the metal top electrode layer 140 or the metal lead layer 160, ion beam etching (IBE) can be used to etch the metal electrodes / metal lead layer 160 to pattern the metal electrodes. The thickness of the useless metal electrode layer / metal lead layer 160 is etched to its film thickness. The film thickness of the electrode layer can be 50-100nm, and the film thickness of the metal lead layer 160 can be 100nm-300nm. The piezoelectric material can be etched by wet etching or reactive ion etching (RIE) to pattern the piezoelectric material. The thickness of the useless piezoelectric material is etched to its film thickness. The thickness of the piezoelectric material can be 1-5um. The insulating protective layer 150 is etched by reactive ion etching (RIE) or inductively coupled plasma etching (ICP) to pattern the insulating protective layer 150. The thickness of the useless insulating protective layer 150 is etched to its thickness. The thickness of the insulating layer can be 300nm-500nm.

[0092] Step 3: Etching of the SOI substrate 110. Reactive ion etching (RIE) is used to etch silicon oxide, and deep reactive ion etching (DRIE) is used to etch the top silicon and bottom silicon. The thickness of silicon oxide is generally 1um, the thickness of the top silicon can be 5um-50um, and the thickness of the bottom silicon can be 100um-500um. In general piezoelectric MEMS device processes, when etching the SOI substrate 110, the top silicon of the device layer is generally etched first, then the bottom silicon of the support layer is etched, and finally the MEMS device is released. However, such a process method will introduce residual stress in the final bottom silicon etching, thereby causing the patterned top silicon and piezoelectric layer to peel off, break, and bend, which is not conducive to the normal use of the piezoelectric MEMS device. Therefore, in order to solve this problem, the embodiment of the present application etches the SOI substrate 110 by first etching the bottom silicon layer 111 of the support layer and then etching the top silicon layer 112 of the device layer to protect the patterning of the multi-piezoelectric drive layer.

[0093] like Figures 2 to 4As shown, according to the second aspect of the embodiment of the present application, a piezoelectric device is proposed, which is prepared by a piezoelectric device preparation process such as any of the above technical solutions, and the piezoelectric device includes: a substrate 110; a metal bottom electrode, a piezoelectric material layer 130, a metal top electrode layer 140 and a lead layer arranged on the substrate 110; and an insulating protective layer 150, the insulating protective layer 150 covering the circumference of the metal bottom electrode, the piezoelectric material layer 130 and the metal top electrode layer 140.

[0094] The piezoelectric device provided in the embodiment of the present application has all the beneficial effects of the above-mentioned technical solutions because the piezoelectric device is prepared by the piezoelectric device preparation process of any of the above-mentioned technical solutions.

[0095] During the preparation process of the piezoelectric device provided in the embodiment of the present application, a metal bottom electrode layer 120, a piezoelectric material layer 130 and a metal top electrode layer 140 are first prepared on the substrate 110, and then the metal bottom electrode layer 120, the piezoelectric material layer 130 and the metal top electrode layer 140 are etched to achieve piezoelectric patterning. Finally, in the process of releasing the piezoelectric device, the bottom silicon layer 111 of the substrate 110 is first etched to form a back cavity to release internal stress, and then the top silicon layer 112 of the substrate 110 is etched. In the traditional technology, the top silicon of the device layer is first etched, and then the bottom silicon of the support layer is etched, and finally the MEMS device is released. This method will introduce residual stress in the final bottom silicon etching, thereby causing the patterned top silicon and piezoelectric layer to peel off, break, and bend, which is not conducive to the normal use of the piezoelectric MEMS device. The piezoelectric device fabrication process provided in the embodiments of the present application first etches the bottom silicon layer 111 and then etches the top silicon layer 112. This can release stress, reduce the probability of cantilever beam breakage and device detachment, ensure device stability, and thus improve product yield. This arrangement ensures the operational stability of the piezoelectric device.

[0096] In some examples, the substrate 110 includes a bottom silicon layer 111 and a top silicon layer 112, a first silicon oxide layer 113 is formed on the side of the bottom silicon layer 111 facing away from the top silicon layer 112; a second silicon oxide layer 114 is formed between the bottom silicon layer 111 and the top silicon layer 112; and a third silicon oxide layer 115 is formed between the top silicon layer 112 and the metal bottom electrode layer 120.

[0097] In the present invention, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "plurality" refers to two or more, unless expressly limited otherwise. Terms such as "installed," "connected," "connected," and "fixed" should be interpreted broadly. For example, "connected" can mean a fixed connection, a detachable connection, or an integral connection; "connected" can mean a direct connection or an indirect connection through an intermediary. Those skilled in the art will understand the specific meanings of these terms in the present invention based on specific circumstances.

[0098] In the description of the present invention, it should be understood that the directions or positional relationships indicated by terms such as "up", "down", "left", "right", "front" and "back" are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or unit referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limiting the present invention.

[0099] Throughout this specification, terms such as "one embodiment," "some embodiments," and "specific embodiments" mean that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, schematic representations of these terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0100] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A piezoelectric device preparation process, characterized in that: include: Providing a substrate, and sequentially preparing a metal bottom electrode layer, a piezoelectric material layer, and a metal top electrode layer on the substrate; Etching the metal bottom electrode layer, the piezoelectric material layer and the metal top electrode layer to achieve piezoelectric patterning; The bottom silicon layer of the substrate is first etched to form a back cavity to release the internal stress, and then the top silicon layer of the substrate is etched to release the piezoelectric device.

2. The piezoelectric device preparation process according to claim 1, characterized in that: The steps of providing a substrate and sequentially preparing a metal bottom electrode layer, a piezoelectric material layer and a metal top electrode layer on the substrate include: The metal bottom electrode layer and the metal top electrode layer are deposited by reactive magnetron sputtering, the target material includes at least one of Pt, Au, Cu, and Ti, and the thickness of the metal bottom electrode layer and the metal top electrode layer is 50 to 200 nm.

3. The piezoelectric device preparation process according to claim 1, characterized in that: The steps of providing a substrate and sequentially preparing a metal bottom electrode layer, a piezoelectric material layer and a metal top electrode layer on the substrate include: The piezoelectric material layer is prepared by a sol-gel method and / or a magnetron sputtering method. The piezoelectric material is at least one of lead zirconate titanate, aluminum nitride, zinc oxide and LNO. The thickness of the prepared piezoelectric material layer is 1-5 μm.

4. The piezoelectric device preparation process according to claim 1, characterized in that: Before the step of first etching the bottom silicon layer of the substrate to form a back cavity to release internal stress, and then etching the top silicon layer of the substrate to release the piezoelectric device, the method further includes: preparing an insulating protective layer and a metal lead layer on a piezoelectric device that realizes piezoelectric patterning; Wherein, the insulating protective layer is grown by PCVD or PECVD, has a thickness of 300nm-500nm, and the material includes silicon nitride; The metal lead layer is grown by magnetron sputtering deposition, has a thickness of 100 nm to 300 nm, and the material includes at least one of Al, Pt, Au, Ag and Cu.

5. The piezoelectric device preparation process according to claim 4, characterized in that: The gas sources for growing the insulating protection layer include SiH4 and NH3, and the growth temperature is 200°C-400°C.

6. The process for preparing a piezoelectric device according to claim 4, wherein: The step of etching the metal bottom electrode layer, the piezoelectric material layer, and the metal top electrode layer to achieve piezoelectric patterning includes: Using an ion beam to etch the metal bottom electrode layer, the metal top electrode layer, and the metal lead layer, patterning the metal electrodes, and etching the useless metal bottom electrode layer, the metal top electrode layer, and the metal lead layer, so that the thickness of the metal bottom electrode layer and the metal top electrode layer is 50 to 100 nm; Using wet etching or reactive ion etching to etch the piezoelectric material layer; The insulating protection layer is etched by reactive ion etching or inductively coupled plasma etching to pattern the insulating protection layer.

7. The process for preparing a piezoelectric device according to claim 6, wherein: The acid solution used in wet etching comprises a buffered hydrofluoric acid etching solution and a buffered etching solution; Wherein, the buffered hydrofluoric acid etching solution and the buffered etching solution both comprise ammonium fluoride and hydrofluoric acid; For PZT media, buffered hydrofluoric acid etching solutions and buffered etching solutions include: pre-etching solutions, main etching solutions, or buffered etching solutions formed by diluting ammonium fluoride and hydrofluoric acid with hydrochloric acid, nitric acid, and water; For reactive ion etching of PZT media, the etching gas may be a mixture of sulfur hexafluoride and argon, a mixture of carbon tetrafluoride and argon, or a mixture of trifluoromethane and argon.

8. The process for preparing a piezoelectric device according to any one of claims 1 to 7, characterized in that: A first silicon oxide layer is formed on a side of the bottom silicon layer facing away from the top silicon layer; A second silicon oxide layer is formed between the bottom silicon layer and the top silicon layer; A third silicon oxide layer is formed between the top silicon layer and the metal bottom electrode layer; The thickness of the top silicon layer is 5um to 50um, and the thickness of the bottom silicon layer is 100um-500um.

9. The process for preparing a piezoelectric device according to claim 8, wherein: The step of first etching the bottom silicon layer of the substrate to form a back cavity to release internal stress, and then etching the top silicon layer of the substrate to release the piezoelectric device includes: etching the first silicon oxide using reactive ion etching; The bottom silicon layer is first etched by deep reactive ion etching to form a back cavity to release internal stress; Reactive ion etching the third silicon oxide layer, then deep reactive ion etching the top silicon layer, and then reactive ion etching the second silicon oxide layer; The etching source gas for reactive ion etching may be one or more of CHF3, SF6, and C2F6.

10. A piezoelectric device, characterized in that: Prepared by the piezoelectric device preparation process according to any one of claims 1 to 9, the piezoelectric device comprises: substrate; A metal bottom electrode, a piezoelectric material layer, a metal top electrode layer and a lead layer are provided on the substrate; An insulating protective layer covers the metal bottom electrode, the piezoelectric material layer, and the metal top electrode layer.

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