Wafer level inertial device test path planning method and system

Abstract

The application provides a wafer-level inertial device test path planning method and system, and relates to the technical field of inertial device detection. The method determines the test point coordinate of the index path and the multi-view probe type, judges whether there is a to-be-tested point that can be tested, determines whether there are bad points in the multiple point coordinates of the neighborhood of the to-be-tested point according to the multi-view probe type, moves the to-be-tested point, determines whether there are bad points in the multiple point coordinates of the neighborhood of the moved to-be-tested point, skips the moved to-be-tested point if there are bad points, and re-determines the to-be-tested point of the index path if there are no bad points. If there are no bad points, a moving instruction is sent to the probe table, the multi-view probe is connected with the to-be-tested point and the multiple points in the neighborhood, and the driving end test and the detection end test are performed. The above method can plan a path, avoid bad points in real time, improve test efficiency, and reduce test cost in the batch test process of wafer-level inertial devices.

Description

Technical Field

[0001] The present invention relates to the technical field of inertial device detection, and in particular to a wafer-level inertial device test path planning method and system. Background Art

[0002] Wafer testing of inertial devices is a critical step in ensuring their performance, reliability, and cost-effectiveness. Early testing and screening can effectively reduce costs, improve yields, and provide data support for design and process optimization, ultimately ensuring high product quality and market competitiveness. Existing batch testing systems use multiple probes to implement batch testing. Due to the presence of bad pixels on the wafer, if a probe connects to a bad pixel on the inertial device wafer during testing, it can cause a short circuit and other problems, potentially damaging the test system and the inertial device wafer. This significantly increases testing costs and hinders improvements in test efficiency. Summary of the Invention

[0003] The purpose of this invention is to provide a wafer-level inertial device test path planning method and system, which aims to perform path planning during batch testing of wafer-level inertial devices, avoid bad points in real time, improve test efficiency, and reduce test costs. The specific technical solution is as follows:

[0004] A wafer-level inertial device test path planning method, the method comprising the following steps:

[0005] S100, input the configuration file, obtain the index path and bad pixel distribution information, determine the test point coordinates of the index path and the multi-eye probe type;

[0006] S200, determine whether there is a test point that can be tested, if yes, jump to step S300, if not, jump to step S600;

[0007] S300, judging whether there are bad points in the coordinates of multiple points in the neighborhood of the point to be measured according to the multi-probe type, if there are bad points, jumping to step S400; if there are no bad points, jumping to step S500;

[0008] S400, moving the test point, determining whether there is a bad point in the coordinates of multiple points in the neighborhood of the moved test point, if there is a bad point, skipping the moved test point, re-determining the test point of the index path, and jumping to step S200; if there is no bad point, jumping to step S500;

[0009] S500, sending a movement instruction to the probe station, connecting the multi-eye probe to the point to be tested and multiple points in the neighborhood, and performing a driving end test and a detection end test; after the test is completed, resetting the label of the tested point to tested as tested, and jumping to step S200;

[0010] S600: Generate a test result report and end the test process.

[0011] Furthermore, in step S100, the index path is vertical or horizontal.

[0012] Furthermore, the multi-mesh probe can be any one of a transverse multi-mesh probe, a longitudinal multi-mesh probe, an oblique multi-mesh probe, an interval multi-mesh probe, and a transverse and longitudinal multi-mesh probe.

[0013] Furthermore, before step S100, the following steps are also included: connecting all hardware serial ports, including the host computer and the probe station interface connection, loading the wafer to be tested on the wafer stage, initializing the host computer, and the probe station probe waiting for instructions to insert the wafer to be tested.

[0014] Furthermore, in step S200, whether there is a point to be tested that can be tested is determined by searching the index path for a point with a tag that can be tested.

[0015] Furthermore, in step S300, multiple points in the neighborhood of the point to be measured are determined according to the multi-eye probe type; and the coordinate information of multiple bad points is obtained according to the bad point distribution information of the configuration file, so as to determine whether there are bad points in the coordinates of multiple points in the neighborhood of the point to be measured.

[0016] Furthermore, in step S400, based on the original test point, one point is moved horizontally or vertically to obtain a point to be tested in which the index path is re-determined.

[0017] Furthermore, in step S500, the multi-eye probe is moved to the position of the coordinate information of the point to be measured by sending the coordinate information of the point to be measured.

[0018] Furthermore, in step S600, the test result report includes key test results of each tested point on the wafer, and the key test results include Q value and resonant frequency.

[0019] The present invention also provides a wafer-level inertial device testing system for implementing the wafer-level inertial device testing path planning method as described above, comprising:

[0020] Wafer stage, used to load the wafer to be tested;

[0021] Probe station, equipped with multiple probes;

[0022] A host computer is connected to the probe station interface.

[0023] The present invention provides a wafer-level inertial device test path planning method and system, which have the following beneficial effects: by providing a multi-eye probe, the present invention can simultaneously batch test multiple points, and during the batch testing process of wafer-level inertial devices, path planning can be performed, thereby avoiding bad points in real time, improving test efficiency, and reducing test costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a flow chart of a wafer-level inertial device test path planning method provided by the present invention;

[0025] Figure 2 is an overall flow chart of an embodiment of the present invention;

[0026] Figure 3 It is an overall flow chart of another embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following will be combined with the accompanying drawings provided by the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions. They are only used to facilitate and clearly illustrate the purpose of the embodiments of the present invention.

[0028] Example 1: This example provides a wafer-level inertial device test path planning method, see Figure 1-3 As shown, the method includes the following steps:

[0029] S100: Input the configuration file, obtain the index path and bad pixel distribution information, and determine the test point coordinates of the index path and the multi-eye probe type.

[0030] Specifically, prior to testing, verification work is performed on the wafers being tested, including static testing. This can filter out some dies (smaller dies within the entire wafer) that are unsuitable for static testing and mark them as bad pixels. Furthermore, some areas that cannot be needled are also marked as bad pixels. The test points are the locations of the dies on the wafer.

[0031] The index path is a path that traverses the entire wafer. The purpose is to test all the dies that need to be tested on the entire wafer. The path is filtered through a column in the die file; the index path is vertical or horizontal.

[0032] The multi-mesh probe can be in various shapes, including horizontal multi-mesh probes, vertical multi-mesh probes, oblique multi-mesh probes, spaced multi-mesh probes, horizontal and vertical multi-mesh probes, etc. In actual use, the type of multi-mesh probe can be set according to the specific application scenario. The number of multi-mesh probes can be multiple, such as 4, 6, 8, 10, etc.

[0033] The test system includes a host computer, a probe station, and a wafer stage. The probe station is equipped with multiple probes. Before step S100, the following steps are also included: connecting all hardware serial ports, including the host computer and probe station interface connections, loading the wafer to be tested on the wafer stage, initializing the host computer, and waiting for the probe station probe to be inserted into the wafer to be tested.

[0034] S200, determine whether there is a test point that can be tested, if yes, jump to step S300, if not, jump to step S600.

[0035] Specifically, during the initial test, all points on the wafer under test are judged; during subsequent tests, based on the original test point, one point is moved horizontally or vertically, and all remaining points on the wafer under test are judged starting from this point.

[0036] Specifically, the presence of a testable point is determined by searching for a point in the index path with a tag indicating that the point is testable. For example, setting the tag to 0 indicates that the point can be tested, setting the tag to 1 indicates that the point cannot be tested, and setting the tag to -1 indicates that the point has been tested.

[0037] S300, judging whether there are bad points in the coordinates of multiple points in the neighborhood of the point to be measured according to the multi-probe type, if there are bad points, jump to step S400; if there are no bad points, jump to step S500.

[0038] Specifically, multiple points in the neighborhood of the point to be measured are determined according to the type of multi-eye probe. For example, for a 4-eye probe in the horizontal and vertical directions, the coordinates of the point to be measured A are (x, y), and the multiple points in the neighborhood of the point to be measured are B(x+1, y), C(x+1, y+1), and D(x, y+1). The coordinate information of multiple bad points is also obtained according to the bad point distribution information in the configuration file, so as to determine whether there are bad points in the coordinates of multiple points in the neighborhood of the point to be measured.

[0039] S400, move the point to be measured, determine whether there is a bad point in the coordinates of multiple points in the neighborhood of the moved point to be measured, if there is a bad point, skip the moved point to be measured, re-determine the point to be measured in the index path, and jump to step S200; if there is no bad point, jump to step S500.

[0040] Specifically, multiple points in the neighborhood of the point to be measured after the move are determined according to the type of multi-eye probe. For example, for a 4-eye probe in the horizontal and vertical directions, the point to be measured after the move is A(x, y-1), and the multiple points in the neighborhood of the point to be measured after the move are B(x+1, y-1), C(x+1, y), and D(x, y).

[0041] Specifically, based on the original test point, one point is moved horizontally or vertically to obtain a point to be tested on a newly determined index path.

[0042] S500, send a movement instruction to the probe station, connect the multi-eye probe to the point to be tested and multiple points in the neighborhood, and perform drive-end test and detection-end test; after the test is completed, reset the label of the tested point to tested as tested, and jump to step S200.

[0043] Specifically, by sending the coordinate information of the point to be measured, the multi-eye probe is moved to the position of the coordinate information of the point to be measured.

[0044] S600: Generate a test result report and end the test process.

[0045] In one embodiment, the test result report includes key test results for each tested point on the wafer, including Q value and resonant frequency. Specifically, the key test results are displayed via a MAP (wafer map), which shows the key test results of each die, such as Q value and resonant frequency.

[0046] The wafer-level inertial device test path planning method provided by the present invention can simultaneously batch test multiple points by setting up multiple probes. In addition, path planning can be performed during the batch testing process of wafer-level inertial devices, thereby avoiding bad points in real time, improving test efficiency, and reducing test costs.

[0047] Embodiment 2: This embodiment provides a wafer-level inertial device testing system for implementing the aforementioned wafer-level inertial device test path planning method, including:

[0048] Wafer stage, used to load the wafer to be tested;

[0049] Probe station, equipped with multiple probes;

[0050] A host computer is connected to the probe station interface.

[0051] Those skilled in the art should understand that the present invention can be implemented in many other specific forms without departing from the spirit and scope of the present invention. Based on the embodiments of the present invention, any changes and modifications made by ordinary technicians in the field of the present invention in accordance with the above disclosure are within the scope of protection of the claims.

Claims

1. A wafer-level inertial device test path planning method, characterized in that: The method comprises the following steps: S100, input the configuration file, obtain the index path and bad pixel distribution information, determine the test point coordinates of the index path and the multi-eye probe type; S200, determine whether there is a test point that can be tested, if yes, jump to step S300, if not, jump to step S600; S300, judging whether there are bad points in the coordinates of multiple points in the neighborhood of the point to be measured according to the multi-probe type, if there are bad points, jumping to step S400; if there are no bad points, jumping to step S500; S400, moving the point to be measured, determining whether there is a bad point in the coordinates of multiple points in the neighborhood of the moved point to be measured, if there is a bad point, skipping the moved point to be measured, and re-determining the point to be measured in the index path, and jumping to step S200; if there is no bad point, jumping to step S500; S500, sending a movement instruction to the probe station, connecting the multi-eye probe to the point to be tested and multiple points in the neighborhood, and performing a driving end test and a detection end test; after the test is completed, resetting the label of the tested point to tested as tested, and jumping to step S200; S600: Generate a test result report and end the test process.

2. The wafer-level inertial device test path planning method according to claim 1, characterized in that: In step S100, the index path is vertical or horizontal.

3. The wafer-level inertial device test path planning method according to claim 1, characterized in that: The multi-mesh probe is any one of a transverse multi-mesh probe, a longitudinal multi-mesh probe, an oblique multi-mesh probe, an interval multi-mesh probe, and a transverse and longitudinal multi-mesh probe.

4. The wafer-level inertial device test path planning method according to claim 1, characterized in that: Before step S100, the following steps are also included: connecting all hardware serial ports, including the host computer and the probe station interface connection, loading the wafer to be tested on the wafer stage, initializing the host computer, and the probe station probe waiting for instructions to insert the wafer to be tested.

5. The wafer-level inertial device test path planning method according to claim 1, characterized in that: In step S200 , it is determined whether there is a point to be tested that can be tested by searching the index path for a point with a tag that can be tested.

6. The wafer-level inertial device test path planning method according to claim 1, characterized in that: In step S300, multiple points in the neighborhood of the point to be measured are determined according to the multi-eye probe type; and coordinate information of multiple bad points is obtained according to the bad point distribution information in the configuration file, so as to determine whether there are bad points in the coordinates of multiple points in the neighborhood of the point to be measured.

7. The wafer-level inertial device test path planning method according to claim 1, characterized in that: In step S400 , based on the original point to be measured, one point is moved horizontally or vertically to obtain a point to be measured with a newly determined index path.

8. The wafer-level inertial device test path planning method according to claim 1, characterized in that: In step S500, the multi-eye probe is moved to the position of the coordinate information of the point to be measured by sending the coordinate information of the point to be measured.

9. The wafer-level inertial device test path planning method according to claim 1, characterized in that: In step S600, the test result report includes key test results of each tested point on the wafer, and the key test results include Q value and resonant frequency.

10. A wafer-level inertial device testing system, configured to implement the wafer-level inertial device testing path planning method according to any one of claims 1 to 9, comprising: Wafer stage, used to load the wafer to be tested; Probe station, equipped with multiple probes; A host computer is connected to the probe station interface.

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